Data distribution method, electronic device, and medium

Abstract

This invention relates to the field of chip technology, and more particularly to a data distribution method, electronic device, and medium. The method includes: S1, acquiring P m The initial data to be sent is stored in P. m Corresponding memory group A m S2, Get P m Sending command data U m , get U m The corresponding instruction number, target Q n Identify, initialize data length, initialize the memory identifier where the data is stored, and add it to U. m Then send to the corresponding target Q. n S3, Get Q n The memory identifier B corresponding to the current instruction data to be dispatched n If the conditions are met, proceed to step S4; S4, Q n Based on the initialization data length corresponding to the current instruction data to be distributed, from B n Read the initialization data from the middle and send the instruction data and the corresponding initialization data to Q. n The corresponding downstream processing engine unit. This invention can improve the efficiency of data distribution without consuming excessive resources.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more particularly to a data distribution method, electronic device, and medium. Background Technology

[0002] In a chip system, upstream instruction data and corresponding initialization data need to be sent to the downstream Processing Engine Unit (PEU). However, the size of the initialization data is variable, and some initialization data is quite large. Sending all initialization data along with the corresponding instruction data would consume a significant amount of chip area, resulting in wasted chip space. To avoid this waste, the initialization data can be cached in memory and then read out of memory one by one before being sent to the PEU. However, when encountering large amounts of initialization data, data distribution can easily become congested, leading to low efficiency. Storing initialization data in multiple memories can improve data distribution efficiency, but since the size of the initialization data is variable, reading it from memory using address addressing would consume a large amount of resources. Therefore, improving data distribution efficiency while avoiding excessive resource consumption is a pressing technical problem. Summary of the Invention

[0003] The purpose of this invention is to provide a data distribution method, electronic device, and medium that can improve the efficiency of data distribution without consuming a large amount of resources.

[0004] According to a first aspect of the present invention, a data distribution method is provided, comprising:

[0005] Step S1: Obtain P m The initial data to be sent is stored in P m Corresponding memory group A m In the middle, P m Let A be the m-th input channel, where m ranges from 1 to M, and M is the total number of input channels. m For P m The corresponding memory bank, each P m It includes at least two memories, with initialization data and instruction data corresponding one-to-one, and each initialization data is stored in one memory.

[0006] Step S2, Obtain P m Sending command data U m , get U m The corresponding instruction number, target Q n Identify, initialize data length, initialize the memory identifier where the data is stored, and add it to U.m And send to the corresponding target Q n Q n This is the nth output processing module, where n ranges from 1 to N. m The corresponding instruction number is according to P m The order in which the sent instruction data is generated;

[0007] Step S3, Obtain Q n The memory identifier B corresponding to the current instruction data to be dispatched n If the current other Q conditions are met n There is no corresponding memory identifier, which is also B. n And the corresponding instruction sequence number is in the instruction data preceding the current instruction data to be dispatched, and there are no other Qs. n Executing from B n If the conditions for the corresponding memory data reading operation are met, then step S4 is executed;

[0008] Step S4, Q n Based on the initialization data length corresponding to the current instruction data to be distributed, from B n Read Q from the corresponding memory n The current pending instruction data corresponds to the initialization data, and the instruction data and the corresponding initialization data are sent to Q. n The corresponding downstream processing engine unit.

[0009] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.

[0011] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the data distribution method, electronic device, and medium provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It possesses at least the following beneficial effects:

[0012] The application sets a memory group for each input channel, stores the initialization data corresponding to each input channel in the memory group, and sets a plurality of output processing modules running in parallel, which distribute the initialization data from the corresponding initialization data in each register according to the storage order according to the instruction requirement, without reading the initialization data in the memory through address addressing, so as to improve the efficiency of data distribution on the basis of avoiding consuming a large amount of resources. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0014] Figure 1 The data distribution method flowchart provided by the embodiments of the present application. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of the present application.

[0016] The embodiments of the present application provide a data distribution method, as shown in Figure 1 , comprising:

[0017] Step S1, obtaining P m The initialization data sent by the upstream device is stored in the P m The corresponding memory group A m , P m is the mth input channel, the value range of m is 1 to M, M is the total number of input channels, A m is the corresponding memory group of P m , each P m includes at least two memories, and the initialization data and the instruction data are one-to-one corresponding, and each initialization data is stored in a memory.

[0018] , P m is used for receiving the initialization data and the instruction data sent by the mth upstream device and sending them to the input processing module, the initialization data and the instruction data are one-to-one corresponding, and the initialization data is sent before the corresponding instruction data, and usually P mInitialization data and instruction data are sent alternately, for example, P m Send initialization data 1, instruction data 1, initialization data 2, instruction data 2, initialization data 3, instruction data 3... in sequence for each P. m Corresponding to an independent memory group A m Each initialization data is stored in one memory location within the corresponding memory group. Each A m The specific number of memories included can be determined based on the chip area and the corresponding P. m The decision is made comprehensively based on factors such as the data transmission situation. As a preferred example, each A m Each chip includes two memories, which avoids data read conflicts during initialization and reduces the chip area occupied. m Initialization data is stored in A in a polling manner. m In the registers, data read conflicts during initialization can be avoided, thus improving data distribution efficiency.

[0019] Step S2, Obtain P m Sending command data U m , get U m The corresponding instruction number, target Q n Identify, initialize data length, initialize the memory identifier where the data is stored, and add it to U. m And send to the corresponding target Q n Q n This is the nth output processing module, where n ranges from 1 to N. m The corresponding instruction number is according to P m The order in which the sent instruction data is generated.

[0020] It should be noted that instruction data can be sent through the instruction transmission channel. During the transmission process, the instruction sequence number and target Q corresponding to the instruction data are obtained. n The identifier, initialization data length, and memory identifier where the initialization data is stored are added to the instruction data to prepare for accurate and fast subsequent reading of the corresponding initialization data from the corresponding memory. N output processing modules run in parallel to improve data distribution efficiency. Each output processing module is connected to a downstream processing engine unit (PEU). Q n The specific quantity can be determined based on the chip area, P m Data transmission status, P m The required downstream devices and other factors are taken into account. As a preferred example, two Qs can be set. nThat is, N=2, which can not only meet the requirement of avoiding initial data reading conflicts and improving data distribution efficiency, but also reduce the area occupied by the chip.

[0021] Step S3, Obtain Q n The memory identifier B corresponding to the current instruction data to be dispatched n If the current other Q conditions are met n There is no corresponding memory identifier, which is also B. n And the corresponding instruction sequence number is in the instruction data preceding the current instruction data to be dispatched, and there are no other Qs. n Executing from B n If the conditions for the corresponding memory data reading operation are met, then step S4 is executed.

[0022] It should be noted that Q n The corresponding currently pending instruction data refers to the instruction data that is currently waiting to be read from the corresponding memory to retrieve initialization data. However, since the same memory can only be accessed based on one Q at a time... n The data read operation is performed, and in this embodiment of the invention, for each memory, the data needs to be read according to the storage order of the initialization data and then according to the length of the initialization data. Therefore, when reading each Q... n Before initializing the corresponding data for the current instruction to be dispatched, a judgment needs to be made first. If the conditions of other Q values ​​are met... n There is no corresponding memory identifier, which is also B. n And the corresponding instruction sequence number is in the instruction data preceding the current instruction data to be dispatched, and there are no other Qs. n Executing from B n The initialization data read operation can only be executed when the corresponding conditions for memory data read operation are met; otherwise, it cannot be executed and must wait until the corresponding conditions are met before execution. During the waiting process, Q... n A new instruction data to be distributed can be determined for judgment.

[0023] Step S4, Q n Based on the initialization data length corresponding to the current instruction data to be distributed, from B n Read Q from the corresponding memory n The current pending instruction data corresponds to the initialization data, and the instruction data and the corresponding initialization data are sent to Q. n The corresponding downstream processing engine unit.

[0024] It should be noted that since the read order and the storage order of the initialization data in each memory are consistent in step S3, the corresponding initialization data can be read from the corresponding memory directly according to the length of the initialization data, without the need to read the initialization data in the memory through address addressing, thereby reducing resource consumption.

[0025] As an embodiment, in step S2, the U m corresponding to the target Q n is obtained.

[0026] Step C21, according to the priority of P m , the sending order of the instruction data corresponding to the same P m , and the load of Q n , one or more factors determine the target Q n corresponding to each initialization data.

[0027] Among them, the output arbitration module can be specifically set in the instruction transmission channel, and the output arbitration module determines the target Q m corresponding to each initialization data according to the priority of P m , the sending order of the instruction data corresponding to the same P n , and the load of Q n , and can also determine the order of transmission to Q n . It should be noted that the existing arbitration method is all within the protection scope of the present application, and will not be described here.

[0028] As an embodiment, step S3 includes:

[0029] Step S31, obtaining the memory identifier B n corresponding to the current to-be-distributed instruction data corresponding to the target Q n .

[0030] It should be noted that since the corresponding memory identifier has been added before the distribution instruction reaches the target Q n , the obtaining in step S31 can be directly performed.

[0031] Step S32, judging whether there is to-be-distributed instruction data with the memory identifier B n in all current Q n , if not, step S36 is executed, otherwise, step S33 is executed.

[0032] It should be noted that Q n can access each other, and each Q n can know the current state of other Q n .

[0033] Step S33, judge whether there is other Q n is executing from B n the corresponding memory reading data operation, if not, execute step S34, otherwise, execute step S35.

[0034] It should be noted that, since the same memory at the same time can only be one Q n read, when there is other Q n is executing from B n the corresponding memory reading data operation, Q n corresponding to the current to be distributed instruction data corresponding to the initialization data can not be read.

[0035] Step S34, judge whether the corresponding memory identifier is also B n and the corresponding instruction sequence number is in the current to be distributed instruction data, if exists, execute step S35, otherwise, execute step S36.

[0036] It should be noted that, in order to avoid reading initialization data based on the address of each initialization data, which consumes a lot of resources, it is necessary to read data from the memory in the same order as the storage order, so that the initialization data length can be accurately read from the corresponding memory, avoiding the situation of data disorder.

[0037] Step S35, re-determine Q n corresponding to the current to be distributed instruction data, return to execute step S31.

[0038] It should be noted that, when Q n corresponding to the current to be distributed instruction data cannot be distributed, Q n corresponding to the current to be distributed instruction data can be re-determined, which improves the data distribution efficiency.

[0039] Step S36, determine that other Q n does not exist, the corresponding memory identifier is also B n and the corresponding instruction sequence number is in the instruction data before the current to be distributed instruction data and other Q n is executing from B n corresponding to the memory reading data operation, execute step S4.

[0040] The instruction sequence number is used to identify the same P m corresponding instruction data sequence, since the initialization data and the instruction data are one-to-one corresponding and alternating sending, the instruction sequence number also identifies the initialization data sequence, as an embodiment, each P m corresponds to a group of instruction sequence number data structure {R1m R2 m},R1 m is P m the first part of the data structure of the instruction sequence number, R2 m is P m the second part of the data structure of the instruction sequence number, R1 m is one of [0, 2], R2 m is one of [0, X], X is the maximum number of instruction data that can be cached by all Q n , R1 m , R2 m The initial values of R1

[0041] In the step S2, the instruction sequence number corresponding to U m is obtained, including:

[0042] In step S21, the current P m corresponding to {R1 m , R2 m} is obtained.

[0043] In step S22, if R2 m X, then update R1 m =R1 m , R2 m =R2 m +1.

[0044] If R2 m =X, and R1 m ≠2, then update R1 m =R1 m +1, R2 m =1.

[0045] If R2 m =X, and R1 m =2, then update R1 m =0, R2 m =1.

[0046] The updated {R1 m , R2 m} is determined as the instruction sequence number corresponding to U m .

[0047] It should be noted that through the above setting, it can avoid the need to increase indefinitely, avoid repetition between sequence numbers, and also clearly identify the order of instruction data corresponding to the same P m .

[0048] As an embodiment, the step S34 includes:

[0049] Step S341, if Q n If the first part of the serial number corresponding to the current to-be-distributed instruction data is 0, it is determined whether there is a memory identifier corresponding to B n If the first part of the serial number corresponding to the current to-be-distributed instruction data is 0, or there is a memory identifier corresponding to B n If the first part of the serial number corresponding to the current to-be-distributed instruction data is 0 and the second part is less than Q n If the second part of the serial number corresponding to the current to-be-distributed instruction data exists, it is determined that there is a memory identifier corresponding to B n If the serial number corresponding to the current to-be-distributed instruction data is in the current to-be-distributed instruction data, otherwise, step S342 is performed.

[0050] Step S342, if Q n If the first part of the serial number corresponding to the current to-be-distributed instruction data is 1, it is determined whether there is a memory identifier corresponding to B n If the first part of the serial number corresponding to the current to-be-distributed instruction data is 0, or there is a memory identifier corresponding to B n If the first part of the serial number corresponding to the current to-be-distributed instruction data is 1 and the second part is less than Q n If the second part of the serial number corresponding to the current to-be-distributed instruction data exists, it is determined that there is a memory identifier corresponding to B n If the serial number corresponding to the current to-be-distributed instruction data is in the current to-be-distributed instruction data, otherwise, step S343 is performed.

[0051] Step S343, if Q n If the first part of the serial number corresponding to the current to-be-distributed instruction data is 2, it is determined whether there is a memory identifier corresponding to B n If the first part of the serial number corresponding to the current to-be-distributed instruction data is 1, or there is a memory identifier corresponding to B n If the first part of the serial number corresponding to the current to-be-distributed instruction data is 2 and the second part is less than Q n If the second part of the serial number corresponding to the current to-be-distributed instruction data exists, it is determined that there is a memory identifier corresponding to B n If the serial number corresponding to the current to-be-distributed instruction data is in the current to-be-distributed instruction data, otherwise, it is determined that there is no memory identifier corresponding to B n If the serial number corresponding to the current to-be-distributed instruction data is in the current to-be-distributed instruction data.

[0052] As an embodiment, Q n The g(n) cache units {C1 n , C2 n ,..., C i n ,..., C g(n)n}, C i n For Q n The i-th cache unit is set in Q, where i ranges from 1 to g(n), and g(n) is Q. n The number of cache units set in Q; n Obtain the memory identifier corresponding to the received instruction data, and store the received instruction data and the corresponding memory identifier into the free C memory. i n In the middle, Q n Select one of the non-idle C i n The instruction data is determined to be Q. n The corresponding memory identifier for the currently pending instruction data is determined as B. n By setting g(n) cache units, Q can be optimized. n Information corresponding to multiple instruction data can be pre-processed and cached, accelerating data distribution efficiency. The specific value of g(n) can be determined based on chip area, P... m The optimal setting is determined by a combination of factors, including the data transmission situation, with all values ​​of g(n) set to 2.

[0053] As one example, Q n The received instruction data and its corresponding memory identifier are stored in the idle C memory using a polling method. i n In the middle. Therefore, in step S35, Q... n Used to poll non-idle C i n The instruction data is determined to be Q. n The corresponding memory identifier for the currently pending instruction data is determined as B. n .

[0054] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0055] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.

[0056] The embodiment of the present application also provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are used for executing the method provided by the embodiment of the present application.

[0057] The embodiment of the present application sets a memory group for each input channel, stores the initialization data corresponding to each input channel in the memory group, and sets a plurality of output processing modules running in parallel. The output processing modules distribute the initialization data from the corresponding initialization data in each register according to the storage order according to the instruction requirement, and do not need to read the initialization data in the memory through the address addressing mode, so that the efficiency of data distribution can be improved on the basis of avoiding consuming a large amount of resources.

[0058] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above with the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes, without departing from the technical solution of the present application. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still belong to the scope of the technical solution of the present application.

Claims

1. A data distribution method, characterized by, Comprising: Step S1, obtaining P m The transmitted initialization data is stored in P m Corresponding memory group A m , P m is the mth input channel, m is in the range of 1 to M, M is the total number of input channels, A m is P m Corresponding memory group, each P m Comprises at least two memories, and initialization data and instruction data are one-to-one corresponding, and each initialization data is stored in a memory; Step S2, obtaining P m transmitted instruction data U m , obtaining U m corresponding instruction sequence number, target Q n identification, initialization data length, storage identification of initialization data, and adding to U m and transmitting to the corresponding target Q n , Q n is the nth output processing module, n is in the range of 1 to N, U m corresponding instruction sequence number is generated according to the order of the instruction data transmitted by P m ; Step S3, obtaining Q n The memory identifier B corresponding to the current to-be-distributed instruction data n If the current other Q n There is no corresponding memory identifier B n And the instruction sequence number corresponding to the instruction data before the current to-be-distributed instruction data and there is no other Q n The operation of reading data from B n Corresponding memory, if the condition is met, step S4 is performed; Step S4, Q n According to the initialization data length corresponding to the current to-be-distributed instruction data from B n Read the corresponding initialization data of the current to-be-distributed instruction data in the memory Q n And issue the instruction data and the corresponding initialization data to the downstream processing engine unit Q n Corresponding.

2. The method of claim 1, wherein, In the step S2, the U m The corresponding target Q n Identification, comprising: Step C21, according to P m the priority of the same P m the sending order of the corresponding instruction data, and the load of Q n corresponding to each initialization data is determined by one or more factors of the target Q n .

3. The method of claim 1, wherein, The step S3 comprises: Step S31, obtaining Q n The memory identifier B corresponding to the current to-be-distributed instruction data n ; Step S32, judging whether there is memory identification of all Q n the to-be-distributed instruction data is B n Step S36 is executed, otherwise, step S33 is executed. Step S33, judging whether there is other Q n is being executed from B n corresponding memory read data operation, if not, step S34 is executed, otherwise, step S35 is executed; Step S34, judging whether there is a corresponding memory identifier B n and the corresponding instruction sequence number is in the current to be distributed instruction data. If there is, step S35 is executed, otherwise, step S36 is executed. Step S35, re-determine Q n If the current instruction data to be distributed corresponds, return to step S31 for execution. Step S36, determine that the current other Q n The corresponding memory identifier does not exist in B n And the corresponding instruction sequence number is the instruction data before the current to-be-distributed instruction data and there is no other Q n Executing from B n The operation of the corresponding memory reading data, execute step S4.

4. The method of claim 3, wherein, Each P m A corresponding set of instruction sequence number data structures {R1 m R2 m }, R1 m For P m The first part of the instruction sequence number's data structure, R2 m For P m The second part of the instruction sequence number data structure, R1 m R² is one of the numbers in [0,2]. m Let Q be one of the numbers in [0, X], where X is any number among all Q. n The maximum amount of instruction data that can be cached, R1 m R2 m The initial values ​​are all 0; In the step S2, the U m The corresponding instruction sequence number includes: Step S21, acquiring current P m corresponding {R1 m ,R2 m}; Step S22, if R2 m < X, then update R1 m = R1 m , R2 m = R2 m + 1; If R2 m = X, and R1 m ≠ 2, then update R1 m = R1 m + 1, R2 m = 1; If R2 m = X, and R1 m = 2, then update R1 m = 0, R2 m = 1; The updated {R1 m ,R2 m} is determined as the instruction sequence number corresponding to U m .

5. The method of claim 4, wherein, The step S34 comprises: Step S341, if Q n If the first part of the sequence number corresponding to the current to-be-distributed instruction data is 0, it is determined whether there is a memory identifier also being B n and the first part of the sequence number corresponding to the instruction is 2, or there is a memory identifier also being B n and the first part of the sequence number corresponding to the instruction is 0 and the second part is less than Q n If the second part of the sequence number corresponding to the current to-be-distributed instruction data is the instruction data, if there is, it is determined that there is a memory identifier also being B n and the sequence number corresponding to the instruction is in the current to-be-distributed instruction data, otherwise, step S342 is performed; Step S342, if Q n If the first part of the sequence number corresponding to the current to-be-distributed instruction data is 1, it is determined whether there is a memory identifier also being B n and the first part of the sequence number corresponding to the instruction is 0, or there is a memory identifier also being B n and the first part of the sequence number corresponding to the instruction is 1 and the second part is less than Q n If the second part of the sequence number corresponding to the current to-be-distributed instruction data is 1, it is determined whether there is a memory identifier also being B n and the sequence number corresponding to the instruction is in the current to-be-distributed instruction data, otherwise, step S343 is executed; Step S342, if Q n If the first part of the sequence number corresponding to the current to-be-distributed instruction data is 2, it is determined whether there is a memory identifier also being B n And the first part of the instruction sequence number is 1, or there is a memory identifier also being B n And the first part of the instruction sequence number is 2 and the second part is less than Q n If the instruction data of the second part of the sequence number corresponding to the current to-be-distributed instruction data exists, it is determined that there is a memory identifier also being B n And the corresponding instruction sequence number is in the current to-be-distributed instruction data, otherwise, it is determined that there is no memory identifier also being B n And the corresponding instruction sequence number is in the current to-be-distributed instruction data.

6. The method of claim 1, wherein, Each A m Each of the two memories comprises two memory banks.

7. The method of claim 1, wherein, N is 2.

8. An electronic device, comprising: Comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executed by the at least one processor, the instructions configured to perform the method of any one of the preceding claims 1-7.

9. A computer-readable storage medium, characterized in that, Computer executable instructions stored in the memory, the computer executable instructions configured to perform the method of any one of the preceding claims 1-7.

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