Data processing method, electronic equipment and chip

Abstract

The invention relates to the technical field of data processing, in particular to a data processing method, electronic equipment and a chip. In the method, after a processor obtains a target address and a flushing signal, a first instruction corresponding to a first address obtained from a storage module is canceled based on the target address and the flushing signal, a target instruction is obtained from the storage module based on the target address, and then the processor executes the target instruction. On the basis, the time for the processor to obtain the target instruction is greatly shortened.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and in particular to a data processing method, an electronic device, and a chip. BACKGROUND

[0002] When a central processing unit (CPU) executes a branch instruction, the next instruction is not executed in sequence, but the target instruction corresponding to the target address obtained by the branch instruction is executed according to the target address.

[0003] It can be understood that when processing a program, the CPU generally fetches instructions from an internal cache. When no cache is configured in the CPU, for example, a level 1 cache (L1 cache), the memory subsystem of the CPU obtains the target instruction corresponding to the target address from a downstream memory.

[0004] For a traditional CPU, if the memory subsystem of the CPU can at most handle one fetch instruction operation at a time, when the CPU needs to jump to the target address to execute the target instruction, the memory subsystem of the CPU needs to fetch the target instruction from the downstream memory according to the target address. However, if the memory subsystem is currently processing a fetch instruction operation, for example, pre-fetching several subsequent instructions in address sequence that are predicted to be executed in advance. At this time, the memory subsystem of the CPU can only fetch the target instruction corresponding to the target address from the downstream memory after completing the current fetch instruction operation. The CPU takes a long time to obtain the target instruction. SUMMARY

[0005] To solve the above problems, the present application provides a data processing method, an electronic device, and a chip.

[0006] In a first aspect, an embodiment of the present application provides a data processing method applied to an electronic device, the electronic device including a processor and a storage module located outside the processor, the processor not being integrated with a cache, and the storage module storing instructions corresponding to addresses, the method including: obtaining, by the processor, a target address and a flush signal, the target address being an address corresponding to a next instruction to be executed pointed to by a branch instruction executed by the processor; canceling, by the processor based on the target address and the flush signal, fetching of a first instruction corresponding to a first address from the storage module, and fetching, by the processor based on the target address, a target instruction from the storage module, wherein the first instruction is a current instruction to be fetched by the processor, and the first address is different from the target address; and executing, by the processor, the target instruction.

[0007] It can be understood that the first instruction is an instruction originally required to be prefetched by the pipeline, when the processor obtains the target address, it means that the next instruction to be executed is the target instruction, at this time, the first instruction currently fetched is the instruction to be discarded, therefore, the first instruction corresponding to the first address is stopped from being fetched according to the flush signal, and the target instruction is fetched according to the target address, so that the time for the processor to fetch the target instruction from the storage module is saved, and the running efficiency of the electronic device is improved.

[0008] In a possible implementation of the first aspect, the first instruction is an instruction corresponding to a sequential address of a branch instruction.

[0009] In a possible implementation of the first aspect, the processor obtains the target address and the flush signal, including: a data processing unit of the processor obtains the target address during execution of the branch instruction, and generates the flush signal.

[0010] In a possible implementation of the first aspect, the processor cancels fetching the first instruction corresponding to the first address from the storage module based on the target address and the flush signal, and fetches the target instruction from the storage module based on the target address, including: a memory subsystem of the processor cancels fetching the first instruction corresponding to the first address from the storage module based on the target address and the flush signal, and fetches the target instruction from the storage module based on the target address, wherein the first instruction is a current instruction to be fetched by the memory subsystem.

[0011] In a possible implementation of the first aspect, the electronic device further includes a transmission module, and the memory subsystem of the processor cancels fetching the first instruction corresponding to the first address from the storage module based on the target address and the flush signal, and fetches the target instruction from the storage module based on the target address, including: the memory subsystem cancels sending a first memory access request to the transmission module according to the flush signal and the target address, and sends a second memory access request to the transmission module, the first memory access request includes the first address, and the first memory access request is used to request to fetch the first instruction corresponding to the first address from the storage module, the second memory access request includes the target address, and the second memory access request is used to request to fetch the target instruction corresponding to the target address from the storage module; the transmission module receives the second memory access request, fetches the target instruction from the storage module based on the target address, and sends the target instruction to the memory subsystem.

[0012] In a possible implementation of the first aspect, the memory subsystem includes a first register, and the method further includes: the first register storing the first access request; and the memory subsystem, according to the flush signal and the target address, canceling sending the first access request to the transmission module and sending the second access request to the transmission module, including: the memory subsystem, according to the flush signal, canceling an access transaction corresponding to the first register, and generating the second access request according to the target address, the access transaction being sending the first access request in the first register to the transmission module.

[0013] In a possible implementation of the first aspect, the memory subsystem includes a bus interface unit, and the transmission module is an advanced high-performance bus or an advanced extensible interface bus, and the bus interface unit is integrated on the processor.

[0014] In a possible implementation of the first aspect, the transmission module is an advanced high-performance bus, the first access request is obtained by the following manner: a bus interface unit in the memory subsystem obtains a first address at a first time, and generates the first access request; and the memory subsystem, according to the flush signal and the target address, cancels sending the first access request to the transmission module and sends the second access request to the transmission module, including: the bus interface unit, according to the received flush signal and the target instruction at a second time, cancels the first access request, and generates the second access request, wherein, at the second time, the bus interface unit does not transmit the first address to the advanced high-performance bus, and the first time is earlier than the second time.

[0015] In a second aspect, the present application provides an electronic device, including: a processor and a memory, the memory including a storage module, and the processor executing the data processing method in the first aspect and any one of the possible implementations of the first aspect.

[0016] In a third aspect, the present application provides a chip, including a processor and a memory, the memory including a storage module, and the chip executing the data processing method in the first aspect and any one of the possible implementations of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 According to some embodiments of the present application, a scenario diagram of an electronic device 100 executing a branch instruction is shown;

[0018] Figure 2 According to some embodiments of the present application, a schematic diagram of an instruction fetching architecture 200 is shown;

[0019] Figure 3 According to some embodiments of the present application, a schematic diagram of a time process of obtaining a target instruction is shown;

[0020] Figure 4AAccording to some embodiments of the present application, a data processing method flowchart is shown.

[0021] Figure 4B According to some embodiments of the present application, a schematic diagram of an architecture included in an electronic device 100 is shown.

[0022] Figure 5 According to some embodiments of the present application, another schematic diagram of a fetch instruction architecture 300 included in an electronic device 100 is shown.

[0023] Figure 6 According to some embodiments of the present application, another schematic diagram of a time process of obtaining a target instruction is shown.

[0024] Figure 7 According to some embodiments of the present application, a schematic diagram of the structure of an electronic device 100 is shown. DETAILED DESCRIPTION

[0025] The illustrative embodiments of the present application include but are not limited to a data processing method, an electronic device, and a chip.

[0026] The following first introduces the present application.

[0027] The memory subsystem of the CPU: a core component for connecting the CPU and the downstream memory (e.g., storage device), responsible for managing the transmission, caching and instruction processing of data between the CPU and the memory. In some embodiments of the present application, the memory subsystem is used to convert the memory access request of the CPU (such as the request to obtain the data corresponding to the address) into a transmission signal to obtain data from the storage module. For example, the memory subsystem includes a memory controller, a bus interface unit (BIU), etc. The downstream memory includes but is not limited to a random access memory (RAM), a solid state drive (SSD), etc.

[0028] Branch instruction: a special instruction used to change the order of program execution. It allows the program to jump to other code locations from the default sequential execution flow according to the condition judgment result or specific logic, realizing the conditional execution and loop control of the program.

[0029] In order to more clearly illustrate the scheme of the embodiments of the present application, the embodiments of the present application are described in detail below in conjunction with the drawings.

[0030] Figure 1According to some embodiments of the present application, a scenario diagram in which an electronic device 100 executes a branch instruction is shown. As shown in the figure, the electronic device 100 is taking a photo, and the electronic device 100 can automatically adjust the focal length according to the distance from the current shooting object. For example, the electronic device can determine whether the distance corresponding to the shooting object is greater than a distance threshold, and when the distance of the shooting object is greater than the distance threshold, a branch instruction is executed, which indicates to jump to an address corresponding to an increased focal length. At this time, the electronic device 100 needs to jump to the address and execute the increased focal length instruction corresponding to the address.

[0031] Specifically, it is assumed that the addresses of the instructions included in a shooting program executed by the electronic device 100 in memory are stored in order as 1000, 1004, 1008, 1012, …, 1020, 1024, …. Each address corresponds to an instruction. During the running process of the electronic device 100, the instructions are generally executed in address order. It is assumed that the CPU in the electronic device 100 starts to execute sequentially from address 1000, and when the instruction at address 1008 is executed, if the instruction is a branch instruction, it is assumed that the branch instruction points to the address corresponding to the next instruction to be executed by the CPU as 1054. At this time, the CPU no longer executes the instruction at address 1016 in order, but jumps to the target address 1054 and executes the target instruction corresponding to the address 1054.

[0032] It can be understood that when the CPU obtains the target address according to the branch instruction, since the CPU has no cache, at this time the memory subsystem of the CPU needs to obtain the target instruction corresponding to the target address from the downstream memory, so that the data processing unit (DPU) in the CPU executes the target instruction.

[0033] As described previously, for a traditional CPU, if the memory subsystem is currently processing a fetch instruction operation, and the CPU generates a target address, the memory subsystem generally can only fetch the instruction corresponding to the target address and return it to the CPU according to the target address after completing the current processing of the fetch instruction operation. At this time, the CPU takes a long time to obtain the target instruction.

[0034] The process of the CPU taking time to obtain the target instruction will be described in detail below. Figure 2 and Figure 3 The process of the CPU taking time to obtain the target instruction will be described in detail below.

[0035] Figure 2 According to some embodiments of the present application, a fetch instruction architecture 200 is shown.

[0036] Specifically, the instruction fetching architecture 200 includes a central processing unit 210, a downstream memory 220, and an advanced high-performance bus 230, the downstream memory 220 and the central processing unit 210 perform data transmission based on the advanced high-performance bus 230. Moreover, the central processing unit 210 does not configure a level one cache. The central processing unit 210 includes a data processing unit 211, an instruction fetching unit 212, and a memory subsystem 213, and the like. The data processing unit 211 is configured to parse and execute instructions. The instruction fetching unit 212 is configured to fetch instructions according to addresses. The memory subsystem 213 is configured to obtain instructions from an external memory. The bus interface unit 2130 included in the memory subsystem 213 is configured to be responsible for the interaction between the CPU and the external bus.

[0037] When the CPU executes a program, if there is no cache in the CPU, the CPU pipeline usually uses the memory subsystem to pre-fetch instructions from the downstream memory according to the address sequence. For example, when the CPU executes an instruction H1, the subsequent instructions of the currently executed instruction H1 are pre-fetched according to the address sequence, such as an instruction H2, an instruction H3, and the like. However, since the instruction H1 executed by the CPU is a branch instruction, and the instruction H1 indicates that the next instruction to be executed is a target instruction corresponding to a target address, the target instruction is not the instruction H2. At this time, the CPU no longer executes the instruction H2, and needs to jump to the target address to execute the target instruction corresponding to the target address.

[0038] However, since the pipeline usually pre-fetches instructions, assuming that the CPU executes the instruction H1, the memory subsystem of the CPU has pre-fetched the instruction H2 corresponding to the next sequential address of the branch instruction H1, and is pre-fetching the instruction H3 corresponding to the next sequential address of the instruction H2. The memory subsystem needs to fetch the target instruction corresponding to the target address after fetching the instruction H3, which causes a long time for the CPU to obtain the target instruction.

[0039] Reference Figure 3 The time process diagram for obtaining the target instruction is shown. The instruction H3 corresponds to an address D3.

[0040] At T0 moment: The instruction fetching unit 212 sends a memory access request corresponding to the instruction fetching to the memory subsystem 213, for obtaining the instruction H3 corresponding to the address D3. The bus interface unit 2130 in the memory subsystem 213 successfully receives the address D3.

[0041] It can be understood that after the bus interface unit 2130 receives the address D3, the data in the downstream memory 220 can be obtained only through the advanced high-performance bus 230. Since a plurality of modules can access the advanced high-performance bus 230, the bus interface unit 2130 needs to wait for a period of time to access the advanced high-performance bus 230, so as to transmit the address D3 to the advanced high-performance bus 230. For example, as shown in FIG. 2, the bus interface unit 2130 needs to wait for a period of time to access the advanced high-performance bus 230, so as to transmit the address D3 to the advanced high-performance bus 230.Figure 3 As shown in FIG. 10, the bus interface unit 2130 needs to wait from time T0 to time Tn, and the specific duration of this time period is not fixed. At time Tn, the bus interface unit 2130 successfully sends the address D3 to the advanced high-performance bus 230.

[0042] At time Tm: The data processing unit 211 calculates the target address to which it needs to jump during the execution of the instruction H1. The CPU determines that the instructions are no longer executed in the order of the addresses, and needs to jump to a new address (i.e., the target address) to execute the target instruction (referred to as “redirection” in the figure). At this time, the instruction fetching unit 212 sends a memory access request corresponding to the target instruction to the bus interface unit 2130 in the memory subsystem 213, for obtaining the target instruction corresponding to the target address.

[0043] As can be understood, since the memory subsystem 213 is currently fetching the instruction H3 at the address D3, and generally only one instruction fetching operation can be processed at a time, the target address sent by the instruction fetching unit 212 can only be successfully received after the memory access request corresponding to the instruction at the address D3 is processed, so that the subsequent access to the advanced high-performance bus 230 is enabled. Therefore, after the redirection occurs, the memory subsystem 213 needs to continue to wait for a period of time, such as the time period from Tm to Tn as shown in FIG. 10, until the memory subsystem 213 successfully accesses the advanced high-performance bus 230 at time Tn, and the address D3 is delivered to the advanced high-performance bus 230. At this time, the memory subsystem 213 can process the target address related transaction after time Tn. Figure 3

[0044] At time Tn: The bus interface unit 2130 in the memory subsystem 213 successfully sends the memory access request corresponding to the address D3 to the advanced high-performance bus 230. After the advanced high-performance bus 230 successfully receives the address D3, the address D3 is transmitted to the downstream memory 220.

[0045] As can be understood, the memory subsystem 213 can only receive the target address after the bus interface unit 2130 successfully sends the memory access request corresponding to the address D3 to the advanced high-performance bus 230, and the advanced high-performance bus 230 successfully receives the address D3. Since the advanced high-performance bus 230 can only process one instruction fetching memory access request at a time, the advanced high-performance bus 230 can only process the memory access request corresponding to the target instruction fetching the target address after successfully obtaining the instruction H3 corresponding to the address D3 from the downstream memory 220, and returning the instruction H3 to the memory subsystem 213. Therefore, during the time period from Tn to Tx, the advanced high-performance bus 230 needs to obtain the instruction H3 corresponding to the address D3.

[0046] ​At the Tx moment: the high-level high-performance bus 230 successfully obtains the data corresponding to the address D3, i.e., the instruction H3, from the downstream memory 220, and returns the instruction H3 to the bus interface unit 2130 in the memory subsystem 213. The high-level high-performance bus 230 completes the operation of fetching the instruction H3, thereby obtaining the target address, so that the target instruction corresponding to the target address can be subsequently fetched from the downstream memory 220.

[0047] At the Ty moment: the high-level high-performance bus 230 successfully obtains the data corresponding to the target address, i.e., the target instruction, from the downstream memory 220, and returns the target instruction to the bus interface unit 2130 in the memory subsystem 213.

[0048] Through the above description, the total time length for the CPU to obtain the target instruction is Ty-Tm. It can be understood that this process takes a long time.

[0049] It can be understood that when the data processing unit is executing a branch instruction (for example, the instruction H1), after obtaining the target address to which it needs to jump, a flush signal is given to the pipeline, so that the sequentially fetched instructions in the processor are cleared, so as to subsequently execute the target instruction.

[0050] Therefore, in order to solve the above problems, the present application provides a data processing method. In the method, the processor is configured to cancel the function of obtaining the instruction corresponding to a certain address from the storage module according to a flush signal. When the processor obtains the target address and the flush signal, the target address is the address corresponding to the next instruction to be executed pointed by the branch instruction executed by the processor. At this time, the first instruction corresponding to the first address is cancelled based on the target address and the flush signal, and the target instruction is obtained from the storage module according to the target address, wherein the first instruction is the instruction to be obtained by the processor at present but not obtained yet, the first address is different from the target address, and then the target instruction is executed.

[0051] It can be understood that the first instruction is the instruction originally needed to be prefetched by the pipeline. When the processor obtains the target address, it indicates that the next instruction to be executed is the target instruction. At this time, the first instruction obtained at present is the instruction to be discarded. Therefore, the first instruction corresponding to the first address is stopped according to the flush signal, and the target instruction is obtained according to the target address, thereby saving the time of obtaining the target instruction from the storage module by the processor, and further improving the running efficiency of the electronic device.

[0052] Figure 4A According to some embodiments of the present application, a data processing method flow diagram is shown. The specific steps are as follows.

[0053] S401, the processor obtains the target address and the flush signal.

[0054] In some embodiments, the processor obtains an address corresponding to a next instruction to be executed during execution of the branch instruction, and since the address corresponding to the next instruction to be executed is not a sequential instruction, a flush signal is sent to flush the prefetched instructions in the pipeline.

[0055] S402, the processor cancels obtaining the first instruction corresponding to the first address from the storage module based on the target address and the flush signal, and obtains the target instruction from the storage module based on the target address.

[0056] The storage module is located outside the processor and stores instructions corresponding to addresses. For example, the storage module is the downstream memory mentioned above.

[0057] It can be understood that the processor generally prefetched instructions in sequence for execution, when the processor obtains the target address, at this time the processor may be obtained from the storage module in sequence to execute the first instruction in advance, that is, the first instruction is the instruction corresponding to the sequential address of the branch instruction, and the first instruction is the Nth instruction taken from the branch instruction in sequence, N is a positive integer. The value of N is not determined.

[0058] In some embodiments, the memory subsystem of the processor cancels obtaining the first instruction corresponding to the first address from the storage module based on the target address and the flush signal, and obtains the target instruction from the storage module based on the target address, wherein the first instruction is the instruction currently to be obtained by the memory subsystem.

[0059] Specifically, the processor is connected to the storage module through a transmission module, and the transmission module is a module for transmitting data, for example, the transmission module includes an advanced high-performance bus (AHB), an advanced extensible interface (AXI) bus, etc. And the transmission module can support the request of more modules, so when the memory subsystem in the processor needs to obtain data through the transmission module, sometimes it needs to wait for a period of time before accessing the transmission module. In some embodiments, the memory subsystem (for example, the bus interface unit in the memory subsystem) of the processor can preconfigure a register (i.e. first register), which is used to store the memory access request corresponding to the prefetched instruction. When waiting to send the memory access request of the first register to the transmission module, if the flush signal is received, the access transaction of the first register will be cancelled at this time, and the access transaction is to send the first access request in the first register to the transmission module. Thus, the memory subsystem has the ability to cancel obtaining a certain instruction.

[0060] For example, Figure 4BAn architecture diagram of an electronic device 100 is shown in the figure. Figure 4B The architecture of the electronic device 100 includes a processor, a storage module, and a transmission module, and the processor is connected to the storage module through the transmission module. The memory subsystem in the processor cancels sending a first memory access request to the transmission module according to a flush signal and a target address, and sends a second memory access request to the transmission module, the first memory access request includes a first address, and the first memory access request is used to request to obtain a first instruction corresponding to the first address from the storage module, and the second memory access request includes the target address, and the second memory access request is used to request to obtain a target instruction corresponding to the target address from the storage module.

[0061] Specifically, the memory subsystem can cancel an access transaction corresponding to the first register according to the flush signal, and generate a second memory access request according to the target address, the access transaction being sending a first access request in the first register to the transmission module. It can be understood that when the transmission module receives the second memory access request, the target instruction is obtained from the storage module based on the target address, and the target instruction is sent to the memory subsystem.

[0062] S403, the processor executes the target instruction.

[0063] In some embodiments, after the memory subsystem in the processor obtains the target instruction, the data processing unit in the processor executes the target instruction.

[0064] The following will be combined Figure 5 and Figure 6 to explain the time saving brought by the data processing method of the present application by taking the processor as a central processing unit, the transmission module as a high-level high-performance bus, and the storage module as a downstream memory. It can be understood that Figure 5 and Figure 6 are comparative diagrams of the above Figure 2 and Figure 3

[0065] Figure 5 According to some embodiments of the present application, another instruction fetching architecture 300 included in an electronic device 100 is shown.

[0066] Specifically, the instruction fetching architecture 300 includes a central processing unit 310, a downstream memory 220, and a high-level high-performance bus 230, the downstream memory 220 and the central processing unit 310 perform data transmission based on the high-level high-performance bus 230. And the central processing unit 310 is not configured with a level one cache. The central processing unit 310 includes a data processing unit 211, an instruction fetching unit 212, and a memory subsystem 313, etc. The data processing unit 211 and the instruction fetching unit 212 are the same as in the above Figure 2 ​The functions described in the foregoing are the same as those described in the foregoing, and thus will not be described again. The memory subsystem 313 is configured to obtain instructions from an external memory, and is capable of canceling a certain instruction obtaining process. The bus interface unit 3130 included in the memory subsystem 313 is configured to be responsible for the interaction between the central processing unit 310 and an external bus, and is capable of canceling a certain memory access request for obtaining an instruction corresponding to a certain address, which has not been sent to the advanced high-performance bus 230. Specifically, the bus interface unit 3130 is configured with a first register, which is configured to write a first access request corresponding to a first address. During the process in which the bus interface unit 3130 waits for accessing the advanced high-performance bus 230, if the bus interface unit 3130 obtains a target address and a flush signal, the bus interface unit 3130 will cancel the first memory access request corresponding to the first address in the first register (i.e., cancel the access transaction corresponding to the first register), and instead send a second memory access request corresponding to the target address to the advanced high-performance bus 230.

[0067] Reference is made to Figure 6 FIG. 3 shows a time process diagram for obtaining a target instruction. In this diagram, the first address is address D3, and the first instruction is instruction H3.

[0068] At T0: the instruction obtaining unit 212 sends a memory access request corresponding to the instruction obtaining to the memory subsystem 313, for obtaining the instruction H3 corresponding to the address D3. The bus interface unit 3130 in the memory subsystem 313 successfully receives the address D3.

[0069] As described in the foregoing, the bus interface unit 2130 in the memory subsystem 312 is capable of canceling a certain memory access request corresponding to a certain address, which has not been sent to the advanced high-performance bus 230. The bus interface unit 3130 in the memory subsystem 313 is the same as the bus interface unit 2130 in the memory subsystem 312, and thus will not be described again. Figure 2 After receiving the address D3, the bus interface unit 3130 in the memory subsystem 313 needs to wait for a period of time to access the advanced high-performance bus 230, and then transmit the address D3 to the advanced high-performance bus 230.

[0070] At Tm: the data processing unit 211 obtains a target address during the execution of the instruction H1. At this time, the central processing unit 310 determines that the instructions are no longer executed in the order of the addresses, and needs to jump to a new address (i.e., the target address) to execute a target instruction (referred to as "re-direction" in the diagram). The bus interface unit 3130 is capable of canceling a certain access request, which has not been sent to the advanced high-performance bus 230, but is to be sent. After the re-direction occurs, the instruction obtaining unit 212 will send a memory access request corresponding to the target address to the bus interface unit 3130, and the data processing unit 211 will send a flush signal to each unit, including the bus interface unit 3130. At this time, the bus interface unit 3130 will cancel the memory access request for obtaining the instruction H3 according to the address D3 according to the flush signal, and generate a memory access request for obtaining a target instruction according to the target address.

[0071] It can be understood that a first register is configured in the bus interface unit 3130, and the bus interface unit 3130 writes the memory access request of the instruction H3 corresponding to the address D3 in the first register. After receiving the flushing signal, the bus interface unit 3130 cancels the access transaction of the first register to the advanced high-performance bus 230. At this time, the memory access request of the target instruction of the target address is generated, and the access to the advanced high-performance bus 230 is waited. Since there are many modules that need to access the advanced high-performance bus 230, the bus interface unit 3130 needs to wait for a period of time, such as the Tm to Tn period of time as shown in FIG. 13B, until the bus interface unit 3130 successfully accesses the advanced high-performance bus 230 at the Tn moment, and the target address is included in the memory access request, so that the target address is successfully transmitted to the advanced high-performance bus 230. Figure 6

[0072] At the Tn moment: the bus interface unit 3130 successfully sends the memory access request corresponding to the target address to the advanced high-performance bus 230, and after the advanced high-performance bus 230 successfully receives the target address, the target address is transmitted to the downstream memory 220.

[0073] At the Tx moment: the advanced high-performance bus 230 successfully obtains the target instruction from the downstream memory 220, and returns the target instruction to the bus interface unit 3130.

[0074] Through the above description, the total time length of the central processing unit 310 obtaining the target instruction is Tx-Tm.

[0075] Compared with the time as shown in FIG. 13B, the total time length of obtaining the target instruction is reduced from Ty-Tm to Tx-Tm. It can be understood that the process as shown in FIG. 13C consumes less time. Figure 3 Figure 6

[0076] It can be understood that for the memory subsystem, the longer the time for the bus interface unit to obtain the instruction from the advanced high-performance bus, for example, the longer the time for obtaining the instruction H3 corresponding to the address D3, the more obvious the benefits of the bus interface unit canceling obtaining the instruction H3 from the advanced high-performance bus and directly obtaining the target instruction.

[0077] Figure 7 According to some embodiments of the present application, a hardware structure schematic diagram of an electronic device 100 is shown.

[0078] As shown in the figure, the electronic device 100 can include one or more processors 101, one or more memories 102, one or more communication interfaces 103, and a bus 104 for coupling the processor, the memory, and the communication unit.

[0079] ​​​The processor 101 can include any one or more of a CPU, a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP), among other processors. In particular, any one of the processor 101 can include, but is not limited to, a memory subsystem, an instruction fetch unit, a data processor unit, and the like. In embodiments of the present application, the processor 101 can execute the data processing method as described above. Figure 4A

[0080] The memory 102 can include a storage module having instructions stored therein. In particular, the storage module can include, but is not limited to, a volatile memory such as a RAM. The memory 102 can also include a non-volatile memory such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or an SSD. In embodiments of the present application, the processor 101 can acquire instructions to be executed from the memory 102 through the bus 104 in the process of executing the data processing method as described above. Figure 4A

[0081] The communication interface 103 uses a transceiving module such as, but not limited to, a network interface card, a transceiver, and the like to enable communication between the electronic device 100 and other devices or communication networks.

[0082] The bus 104 is a path for transferring information between components (e.g., the processor 101, the memory 102, the communication interface 103) of the electronic device. For example, the bus 104 can be an advanced high-performance bus, an advanced extensible interface bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, Figure 7 only one line is shown, but this does not mean that there is only one bus or only one type of bus.

[0083] It can be understood that Figure 7 The structure of the electronic device 100 as described above is only an example, and in other embodiments, the electronic device 100 can include more or fewer components than shown, or combine certain components, or split certain components, or different component arrangements. The components shown can be implemented in hardware, software, or a combination of software and hardware.

[0084] ​​This application also discloses a chip, which includes a processor, a memory, and a data transmission module (e.g., a bus) for data transmission, wherein the memory includes a storage module. In some embodiments of this application, the processor can perform the above-described... Figure 4A The data processing method is illustrated. For example, the chip includes the above-described... Figure 7 The processor 101, memory 102, and bus 104 are included. The processor 101 executes the above-mentioned... Figure 4A During the data processing method shown, instructions to be executed can be retrieved from memory 102 via bus 104.

[0085] The various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0086] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0087] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0088] It has to be noted that, as used in this patent specification and claims, the terms "comprises", "comprising", "includes", "including" or "contains", "containing" when used in this patent specification and claims are taken to specify the presence of stated features, integers, steps or components but do not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

[0089] Although the application has been illustrated and described with respect to several preferred embodiments thereof, after reading the foregoing specification, one skilled in the art will readily appreciate that various changes, modifications or equivalents can be made thereto without departing from the spirit and scope of the application as defined in the appended claims.

Claims

1. A data processing method applied to an electronic device, the electronic device comprising a processor and a storage module located external to the processor, the processor not integrating a cache, the storage module storing instructions corresponding to addresses, characterized in that, include: The processor obtains the target address and the flush signal. The target address is the address corresponding to the next instruction to be executed, which is pointed to by the branch instruction being executed by the processor. The processor cancels the acquisition of the first instruction corresponding to the first address from the storage module based on the target address and the flushing signal, and acquires the target instruction from the storage module based on the target address, wherein the first instruction is the instruction that the processor is currently to acquire, and the first address and the target address are different addresses; The processor executes the target instruction.

2. The method according to claim 1, characterized in that, The first instruction is the instruction corresponding to the sequential address of the branch instruction.

3. The method according to claim 1, characterized in that, The processor acquires the target address and the flushing signal, including: During the execution of the branch instruction, the processor's data processing unit obtains the target address and generates a flush signal.

4. The method according to claim 1, characterized in that, The processor cancels the retrieval of the first instruction corresponding to the first address from the storage module based on the target address and the flushing signal, and retrieves the target instruction from the storage module based on the target address, including: The processor's memory subsystem cancels the acquisition of the first instruction corresponding to the first address from the storage module based on the target address and the flushing signal, and acquires the target instruction from the storage module based on the target address, wherein the first instruction is the instruction that the memory subsystem is currently to acquire.

5. The method according to claim 4, characterized in that, The electronic device also includes a transmission module, and, The processor's memory subsystem cancels the retrieval of the first instruction corresponding to the first address from the storage module based on the target address and the flush signal, and retrieves the target instruction from the storage module based on the target address, including: The memory subsystem cancels sending a first memory access request to the transmission module and sends a second memory access request to the transmission module based on the flushing signal and the target address. The first memory access request includes the first address and is used to request the first instruction corresponding to the first address from the storage module. The second memory access request includes the target address and is used to request the target instruction corresponding to the target address from the storage module. The transmission module receives the second memory access request, retrieves the target instruction from the storage module based on the target address, and sends the target instruction to the memory subsystem.

6. The method according to claim 5, characterized in that, The memory subsystem includes a first register. The method further includes the first register storing the first memory access request, and the memory subsystem canceling the transmission of the first memory access request to the transmission module and sending a second memory access request to the transmission module based on the flush signal and the target address, including: The memory subsystem cancels the access transaction corresponding to the first register according to the flush signal, and generates a second memory access request according to the target address. The access transaction is to send the first access request in the first register to the transmission module.

7. The method according to any one of claims 5 or 6, characterized in that, The memory subsystem includes a bus interface unit, and the transmission module is an advanced high-performance bus or an advanced scalable interface bus, wherein the bus interface unit is integrated on the processor.

8. The method according to claim 5, characterized in that, The transmission module is an advanced high-performance bus, and the first memory access request is obtained in the following way: the bus interface unit in the memory subsystem obtains the first address at the first moment and generates the first memory access request. Furthermore, the memory subsystem, based on the flush signal and the target address, cancels sending the first memory access request to the transmission module and sends a second memory access request to the transmission module, including: The bus interface unit, based on the received flushing signal and target instruction at a second moment, cancels the first memory access request and generates the second memory access request. In the second moment, the bus interface unit did not pass the first address to the high-performance bus, and the first moment was earlier than the second moment.

9. An electronic device, characterized in that, include: A processor and a memory, the memory including a storage module, the processor performing the data processing method as described in any one of claims 1-8.

10. A chip, characterized in that, The chip includes a processor and a memory, the memory including a storage module, and the chip performs the data processing method as described in any one of claims 1-8.

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