TLB cache, memory management unit, chip, electronic equipment and method

Abstract

The invention relates to a TLB cache, a memory management unit, a chip, electronic equipment and a data processing method, and belongs to the field of computers. The TLB cache comprises a scalar data array, a vector tag array and a control unit. The scalar data array is used for storing page table data; the vector tag array is used for storing TAG tags, the TAG tags are used for judging whether page table data corresponding to address translation requests are stored in the TLB cache or not, and the vector tag array supports multiple page table sizes; and the control unit is used for combining the plurality of TAG tags under the condition that the plurality of TAG tags in the same row correspond to the same page table data in the vector tag array. According to the method and the device, the storage resources cached by the TLB can be released, the jolting condition of the TLB is reduced, and the memory access performance of the processor is further improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of computer, and particularly relates to a TLB cache, a memory management unit, a chip, an electronic device and a data processing method. BACKGROUND

[0002] In a processor structure, an MMU (Memory Management Unit) is usually used to complete conversion of a virtual address to a physical address. One of important components of the MMU is a TLB (Translation Lookaside Buffer), which is used to cache PTEs (Page Table Entries) recording mapping relationship of the virtual address to the physical address. Deployment of the TLB cache can greatly improve efficiency of access of a processing system to a memory.

[0003] Generally, a processor system needs to support multiple page table sizes (such as 4KB page table and 2M page table) at the same time. Once a TLB cache miss occurs, regardless of a real page table size, the TLB cache can only acquire a PTE according to a minimum page table size (such as 4KB). If the real page table size (such as 2MB) is greater than the minimum page table size (such as 4KB), a tag array and a corresponding data array of the TLB cache will cache multiple redundant PTEs. Since the TLB cache itself has a small capacity, and multiple redundant PTEs are cached therein, TLB thrashing will occur in some scenarios, causing a great decline in processor memory access performance. SUMMARY

[0004] In view of this, the present application aims to provide a TLB cache, a memory management unit, a chip, an electronic device and a data processing method, so as to release storage resources of the TLB cache, reduce occurrence of TLB thrashing, and further improve processor memory access performance.

[0005] Embodiments of the present application are implemented as follows: In a first aspect, the embodiments of the present application provide a TLB cache, comprising: a scalar data array, a vector tag array, and a control unit; the scalar data array is used to store page table data; the vector tag array is used to store TAG tags, the TAG tags are used to determine whether the TLB cache stores page table data corresponding to an address translation request, and the vector tag array supports multiple page table size sizes; and the control unit is used to, in a case where multiple TAG tags in the same row of the vector tag array correspond to the same page table data, merge the multiple TAG tags.

[0006] In the above embodiment, by adopting the vector tag array with the merging capability, multiple page table size sizes are supported, and when multiple TAG tags of the same row in the vector tag array correspond to the same page table data, the multiple TAG tags are merged, so that the storage resources of the TLB cache are released, the TLB thrashing situation is reduced, and the processor memory access performance is improved. At the same time, only the tag array uses the vector array, and the data array still maintains the original scalar array, so compared with the scheme of simply increasing the TLB cache capacity, a large amount of area can be saved.

[0007] With reference to a possible implementation of the first aspect, the control unit is further configured to: detect whether a first TAG tag exists in the vector tag array, the address range of the first TAG tag is located in the address range of a target TAG tag, the first TAG tag is located in the same row as the target TAG tag, and the state identifier of the first TAG tag is in the pending state; and wherein the state identifier of the target TAG tag is in the valid state; and in the case where the first TAG tag exists, the target TAG tag and the first TAG tag correspond to the same page table data.

[0008] In the above embodiment, by detecting whether the first TAG tag exists in the vector tag array, if the first TAG tag exists, it indicates that the target TAG tag and the first TAG tag correspond to the same page table data, so that the target TAG tag and the first TAG tag can be merged subsequently, thereby releasing the storage resources of the TLB cache.

[0009] With reference to a possible implementation of the first aspect, the control unit is specifically configured to: update the count value of the target TAG tag to be the sum of the count value of the target TAG tag and the count value of the first TAG tag; reset the count value of the first TAG tag to an initial value; and update the state identifier of the first TAG tag to be the invalid state.

[0010] In the above embodiment, when the target TAG tag and the first TAG tag are merged, by updating the count value of the target TAG tag to be the sum of the count value of the target TAG tag and the count value of the first TAG tag, the count function of the first TAG tag is inherited, at the same time, the count value of the first TAG tag is reset to an initial value and the state identifier of the first TAG tag is updated to be the invalid state, so that the tag is synthesized, thereby releasing the storage resources.

[0011] In a possible implementation of the first aspect, the control unit is further configured to: detect whether a second TAG tag exists in the vector tag array, where an address range of the second TAG tag is located in an address range of a target TAG tag, the second TAG tag is not located in a same row as the target TAG tag, and a state identifier of the second TAG tag is in a valid state or a pending state; and in a case where the second TAG tag exists, update a page table size of the second TAG tag to an actual page table size of page table data corresponding to the target TAG tag.

[0012] In the above embodiment, by detecting whether the second TAG tag exists in the vector tag array, and updating the page table size of the second TAG tag to the actual page table size of the page table data corresponding to the target TAG tag, TLB thrashing can be reduced. For example, a 0 address request occupies TAG00 (i.e., the target TAG tag), the control unit updates TAG00 to a 4 KB page table size, a 4K address request occupies TAG10 (i.e., the second TAG tag), and at the next moment, a PTE corresponding to TAG00 has been returned and the PTE indicates a 2 MB page table size. Because a PTE corresponding to the 4K address has not been returned, but the 0 address PTE has been returned, translation can be completed quickly. After completion, if a request in a 2 MB page table starting from the 0 address occurs, a PTE corresponding to the TAG0 row can be kicked out of the TLB. However, if the page table size of TAG10 is not updated to 2 MB, the 0 address request occupies a new TAG when sent again, resulting in thrashing. However, if the page table size of TAG10 is updated to 2 MB, the 0 address request hits TAG10 when sent again.

[0013] In a possible implementation of the first aspect, the control unit is further configured to: in a case where the address translation request does not hit a TAG tag in the vector tag array, fill key information in the address translation request into a target TAG tag in the vector tag array, update a state identifier of the target TAG tag to a pending state, update a page table size identifier of the target TAG tag to a minimum page table size, and update a count value of the target TAG tag to a next value, where the next value after the update is greater than the value before the update; after sending a PTE acquisition request including a tag coordinate of the target TAG tag, update the state identifier of the target TAG tag to a valid state; after returning page table data of the tag coordinate, update the page table size of the target TAG tag to an actual page table size of the returned page table data, and fill the returned page table data into a data array corresponding to the target TAG tag.

[0014] In the above embodiment, the control unit is further configured to allocate a target TAG tag for the address translation request in case of miss, and attach the tag coordinates of the target TAG tag in the subsequent PTE obtaining request, so that after obtaining the PTE, the tag coordinates can be used to know which data array the PTE should be filled in, thereby quickly establishing the mapping relationship between the TAG tag and the PTE, and avoiding the secondary addressing overhead. Meanwhile, after filling the key information in the address translation request into the target TAG tag, the state identifier, the page table size identifier, and the count value of the target TAG tag are updated, and after sending the PTE obtaining request, the state identifier is updated to the valid state, and the target TAG tag page table size is updated to the actual page table size of the returned page table data, so as to ensure the accuracy of address translation, and the state of the corresponding state identifier can be used to know which stage of address translation is currently in, and the count value can be used to know whether the corresponding PTE is used up.

[0015] In a possible implementation of the first aspect, the TLB cache further includes a pending cache; and the control unit is further configured to: in case that the address translation request misses the TAG tag of the vector tag array, store the tag coordinates of the target TAG tag allocated for the address translation request and the address translation request in the pending cache; in case that the address translation request hits the TAG tag of the vector tag array, store the tag coordinates of the hit TAG tag and the address translation request in the pending cache; and obtain the tag coordinates corresponding to the address translation request from the pending cache, and obtain the page table data in the data array corresponding to the tag coordinates if the content in the data array is valid.

[0016] In the above embodiment, the address translation request and the attached tag coordinates are stored in the pending cache regardless of whether it is hit or not, and then the tag coordinates corresponding to the address translation request are obtained from the pending cache, and the page table data in the data array corresponding to the tag coordinates is obtained if the content in the data array is valid. The address translation request is cached through the pending cache, so as to reduce the back pressure on the source end sending the address translation request in case of miss, thereby improving the performance of the processor.

[0017] In a possible implementation of the first aspect, the TAG tag includes: a high-order part of a virtual address, a state identifier, a page table size identifier, and a count value; the state identifier is one of a pending state, a valid state, and an invalid state; the page table size identifier is one of a minimum page table size and an actual page table size of page table data; and the count value is used to represent whether the page table data corresponding to the TAG tag is used up.

[0018] In the above embodiment, each TAG tag is attached with state identification, page table size identification and count value in addition to the basic tag (containing the high bit part of the virtual address), so that the state of the tag can be known through the state identification whether the tag is valid and in which stage of address translation, whether the corresponding page table data is used up can be known through the count value, and whether the subsequent address translation request is hit or miss can be quickly judged through the page table size. Taking a 48-bit [47:0] virtual address VA as an example, VA[47:12] stored in the TAG tag is used to judge whether the subsequent address translation request is hit or miss if the page table size is 4KB, VA[47:14] stored in the TAG tag is used to judge whether the subsequent address translation request is hit or miss if the page table size is 16KB, and VA[47:21] stored in the TAG tag is used to judge whether it is hit or miss if the page table size is 2MB. The part of the virtual address stored in the TAG tag is different for different page table sizes.

[0019] In combination with a possible implementation manner of the first aspect, the vector tag array is an M*N tag array, one tag array is used to store one TAG tag, and M and N are both integers greater than or equal to 2; the scalar data array is an M*1 data array, one data array is used to store one page table data; and the N tag arrays in the same row time-division multiplex one data array.

[0020] In the above embodiment, the vector tag array and the scalar data array with the above sizes are used, so that the N tag arrays in the same row time-division multiplex one data array, and one data array is time-division multiplexed by multiple tag arrays, thereby the area overhead of the cache can be saved.

[0021] In the second aspect, the embodiments of the present application further provide a memory management unit, comprising: a page table traversal unit and the TLB cache provided in the first aspect and / or any possible implementation manner in combination with the first aspect.

[0022] In the third aspect, the embodiments of the present application further provide a chip, comprising: a core and the memory management unit provided in the second aspect, wherein the core is connected with the memory management unit.

[0023] In the fourth aspect, the embodiments of the present application further provide an electronic device, comprising: a memory and the chip provided in the third aspect, wherein the chip is connected with the memory.

[0024] In a fifth aspect, the embodiments of the present application further provide a data processing method, which comprises: detecting whether multiple TAG tags in the same row of a vector tag array of a TLB cache correspond to the same page table data; and merging the multiple TAG tags in the case that the multiple TAG tags in the same row of the vector tag array correspond to the same page table data.

[0025] In a possible implementation of the fifth aspect, the detecting whether multiple TAG tags in the same row of a vector tag array of a TLB cache correspond to the same page table data comprises: detecting whether a first TAG tag, which has an address range within an address range of a target TAG tag, is in the same row as the target TAG tag and has a pending state; wherein the target TAG tag has a valid state; and in the case that the first TAG tag exists, the target TAG tag and the first TAG tag correspond to the same page table data; and correspondingly, the merging the multiple TAG tags comprises: updating a count value of the target TAG tag to a sum of the count value of the target TAG tag and a count value of the first TAG tag; resetting the count value of the first TAG tag to an initial value; and updating a state identifier of the first TAG tag to an invalid state.

[0026] In a possible implementation of the fifth aspect, the method further comprises: detecting whether a second TAG tag, which has an address range within an address range of a target TAG tag, is not in the same row as the target TAG tag and has a valid state or a pending state; and in the case that the second TAG tag exists, updating a page table size of the second TAG tag to an actual page table size of page table data corresponding to the target TAG tag.

[0027] With reference to a possible implementation of the fifth aspect, before detecting whether there is a first TAG tag in the vector tag array, whose address range is within the address range of the target TAG tag, and is in the same row as the target TAG tag, and whose state identifier is in the pending state, the method further comprises: in the case that the address translation request does not hit a TAG tag of the vector tag array, filling the key information in the address translation request into the target TAG tag in the vector tag array, updating the state identifier of the target TAG tag to the pending state, updating the page table size identifier of the target TAG tag to the minimum page table size, and updating the count value of the target TAG tag to the next value, wherein the updated next value is greater than the previous value; after sending a PTE obtaining request containing the tag coordinates of the target TAG tag, updating the state identifier of the target TAG tag to the valid state; after returning the page table data of the tag coordinates, updating the page table size of the target TAG tag to the actual page table size of the returned page table data, and filling the returned page table data into the data array corresponding to the target TAG tag.

[0028] With reference to a possible implementation of the fifth aspect, the method further comprises: in the case that the address translation request does not hit a TAG tag of the vector tag array, storing the tag coordinates of the target TAG tag allocated for the address translation request and the address translation request into the pending cache; in the case that the address translation request hits a TAG tag of the vector tag array, storing the tag coordinates of the hit TAG tag and the address translation request into the pending cache; obtaining the tag coordinates corresponding to the address translation request from the pending cache, and obtaining the page table data in the data array corresponding to the tag coordinates if the content in the data array is valid.

[0029] Other features and advantages of the present application will be described in the following description and other parts of the specification. The purpose and other advantages of the present application can be achieved and obtained by the structure specifically pointed out in the written description and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art according to these drawings. Through the drawings shown, the above and other purposes, features and advantages of the present application will be more clear.

[0031] Figure 1 A structure diagram of a TLB cache provided by an embodiment of the present application is shown.

[0032] Figure 2 A corresponding diagram of a vector tag array and a scalar data array is shown.

[0033] Figure 3 A format diagram of a TAG tag is shown.

[0034] Figure 4 An update diagram of a tag state is shown.

[0035] Figure 5 A format diagram of a PTE is shown.

[0036] Figure 6 Another structure diagram of a TLB cache is shown.

[0037] Figure 7 A principle diagram of a TLB cache is shown.

[0038] Figure 8 A flow diagram of a data processing method is shown.

[0039] Figure 9 A structure diagram of an electronic device is shown. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the protection scope of the present application. Those skilled in the art can understand that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0041] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, the relationship terms such as "first", "second" and the like are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device.

[0042] Furthermore, the term “and / or” in the present application is only used to describe the associated relationship of associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone.

[0043] In the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the technical term “connection” can be direct connection or indirect connection through an intermediate medium.

[0044] In view of the current processor system, once a TLB cache miss occurs, the TLB cache is prone to cache multiple redundant page table data (PTEs), which not only wastes the storage resources of the TLB cache but also causes TLB thrashing in some scenarios, thereby causing a significant decline in processor memory access performance.

[0045] The thrashing scenario is as follows: the processor can use parallel computing address commands to load matrices (such as A matrix and B matrix) needed for subsequent computation. Assuming that the PTE size is 2MB, the A matrix and the B matrix each occupy an independent 16MB space, then the A matrix and the B matrix each need 8 PTEs, and a total of 16 PTEs. For the above scenario, theoretically, 16 tag arrays and 16 data arrays (one PTE corresponds to one tag array and one data array) supporting a single 2MB page table size can meet the high-performance design requirements, but the real TLB cache needs to support mixed page table sizes (multiple page table sizes), and only after the PTE is returned, the TLB cache will know the real page table size, before that, no matter how the real page table size is, the TLB cache can only obtain the PTE according to the smallest page table size (such as 4KB) supported by the processor, which will cause a large number of redundant tags to reside in the tag array of the TLB cache. If the processor uses address interleaving (or alternation) when loading the A matrix and the B matrix, that is, 16 address requests related to the A matrix -> 16 address requests related to the B matrix -> 16 address requests related to the A matrix -> 16 address requests related to the B matrix… until the A and B matrices are loaded. Since the tag storage capacity of the TLB cache is only 16, the loading addresses of the A and B matrices will occupy the TLB cache in a loop, and a large delay needs to be introduced each time the loading is performed, thereby greatly reducing the performance of the system.

[0046] To address the aforementioned processor performance degradation issue, this application provides a TLB cache comprising a vector tag array with merging capabilities and a scalar data array. When multiple tags in the same row of the vector tag array correspond to the same PTE, these tags are merged, thereby freeing up TLB cache storage resources, reducing TLB thrashing, and ultimately improving processor memory access performance. In this application, only the tag array uses a vector array, while the data array remains a scalar array. Therefore, compared to simply increasing the TLB cache capacity, this saves a significant amount of area. Furthermore, when multiple tags in the same row correspond to the same PTE, the tags are automatically merged, thus mitigating the PTE redundancy problem of the TLB cache to some extent. In addition, this application does not require page table size identification on the virtual address side, thus preserving the ease of use and versatility of the TLB cache in processor systems.

[0047] The TLB cache in this application can be an L0-TLB cache, an L1-TLB cache, an L2-TLB cache, etc. Among them, the L0 (Level 0) cache is a level 0 cache, the L1 (Level 1) cache is a level 1 cache, and the L2 (Level 2) cache is a level 2 cache. Usually, the L0 cache has the smallest capacity.

[0048] The following is combined with Figure 1 The TLB cache provided in this application embodiment is described below. The TLB cache includes a scalar data array, a vector tag array, and a control unit, with the control unit connected to both the scalar data array and the vector tag array. The control unit is responsible for updating data in the scalar data array and the vector tag array (including operations such as adding, modifying, and deleting). The control unit in the TLB cache can be connected to a page table traversal unit, which is used to retrieve the PTE corresponding to the address translation request from subsequent caches or external memory when the TLB cache does not find the address translation request.

[0049] A scalar data array is used to store PTEs. A vector tag array is used to store TAGs, which are used to determine whether the TLB cache contains a PTE corresponding to an address translation request.

[0050] The vector tag array corresponds to the scalar data array, ensuring that each TAG tag has a corresponding PTE. In some possible implementations, the vector tag array is an M×N tag array, and similarly, the scalar data array is also an M×N data array, where M and N are both integers greater than or equal to 2. One tag array is used to store one TAG tag, and one data array is used to store one PTE. In this implementation, one tag array corresponds to one data array.

[0051] In yet some possible implementation, the vector tag array is an MxN tag array, and the scalar data array is an Mxl data array, wherein the N tags in the same row are time-division multiplexed with one data array. For example, as shown in Figure 2 FIG. 16, the vector tag array is a 16x4 tag array, and the scalar data array is a 16xl data array, wherein the 4 tags in the same row are time-division multiplexed with one data array, for example, the 4 TAGs in Row0 are time-division multiplexed with one Date Array0, the 4 TAGs in Row1 are time-division multiplexed with one Date Array1, and so on.

[0052] wherein each TAG tag includes a high bit part of a virtual address (VA), a status, a page table size identifier (Size), and a counter value (Counter), and in some possible implementation, each TAG tag can further include a process address space identifier (PASID). For example, as shown in Figure 3 FIG. 17, each base tag is composed of a PASID+ VA[47:12] (here, it is assumed that the virtual address is 48 bits, and [11:0] is a page table internal address offset, which is not resident in the TAG tag), and in this case, the address translation request is composed of a PASID+ virtual address [47:0]. In addition, the base tag is further attached with a Status, a Size, and a Counter identifier.

[0053] The status of the status identifier can be one of a pending status, a valid status, and an invalid status. The status change process of the status identifier, or the status change process of the tag status is as shown in Figure 4As shown, when the data array content of the row is empty, such as after the TLB cache reset / reset or after the cache invalidation, the Status is set to the invalid state, and when an address translation request miss occurs, the address translation request is filled into the basic tag of the TAG tag according to a certain rule. After the content is filled into the TAG tag, the state is updated to the pending state, and when multiple TAG tags in the same row are in the Pending state, a round-robin arbitration strategy is used to decide which TAG tag can be responded to (here, responding refers to sending a PTE acquisition request to the page table traversal unit to acquire a PTE). After the PTE acquisition request (Ready to Fetch PTE) is sent, the corresponding tag state is updated to the valid state, wherein only one TAG tag in the same row can be in the Valid state. When the data in the data array of the row where the TAG tag is located is evicted (Data Array eviction), the state of the corresponding TAG tag is updated to Invalid.

[0054] In the process of filling the address translation request into the basic tag of the TAG tag according to a certain rule, the address translation request can be sequentially filled into TAG tag 0 of each row in the order of increasing tag array row number, and when the column corresponding to TAG tag 0 is filled, the column corresponding to TAG tag 1 and TAG tag 2 is sequentially filled. For example, TAG (0, 0) is preferentially filled, if TAG (0, 0) is already occupied, TAG (1, 0) is preferentially filled, if TAG (1, 0) is already occupied, TAG (2, 0) is preferentially filled, and so on. Assuming that TAG (0, 0) ~ TAG (15, 0) are all occupied, the column where TAG tag 1 is located is preferentially filled; if TAG (0, 1) ~ TAG (15, 1) are all occupied, the column where TAG tag 2 is located is preferentially filled, and so on. If all the TAG tags are occupied, some strategies (including but not limited to arbitration strategies such as LRU or round robin) can be used to select the filled TAG tag. For example, based on LRU (Least Recently Used, least recently used algorithm), the TAG tag whose state is Valid and whose count value is 0 and whose data array corresponding PTE is the longest time not accessed can be preferentially evicted. If the tag state is Invalid, it indicates that the TAG tag is not used.

[0055] The page table size identifier is one of the minimum page table size and the actual page table size of the PTE. Since the present application supports multiple page table sizes (only one size of page table for the same address) such as 4KB, 16KB, 64KB and 2MB, any TAG in the tag array is accompanied by a Size to identify the page table size. When the TLB cache misses the address translation request, the Size is filled with the minimum page table size such as 4KB by default. When the PTE is returned, the actual page table size in the PTE is filled in the Size of the TAG with a Valid status. Subsequent address translation requests can determine whether it is a Hit-on-Miss according to the Size of the tag. For example, if the Size is 4KB, VA[47:12] stored in the TAG is used for Hit-on-Miss determination; if the Size is 16KB, VA[47:14] stored in the TAG is used for Hit-on-Miss determination; if the Size is 64KB, VA[47:16] stored in the TAG is used for Hit-on-Miss determination; and if the Size is 2MB, VA[47:21] stored in the TAG is used for Hit-on-Miss determination.

[0056] Hit-on-Miss refers to a scenario in which the TAG has been filled and updated after a miss, but the PTE has not been returned. Hit-on-Miss hit is different from the conventional hit. Hit-on-Miss hit indicates that the tag hits, but the PTE in the corresponding data array has not been returned, while the conventional hit indicates that the tag hits and the PTE in the corresponding data array already exists.

[0057] Taking a 48-bit physical address (PA) as an example, the format of the PTE can be as follows: Figure 5As shown, Page Size is 0, representing 4KB page table, then {PA[47:12], VA[11:0]} is the translated address; Page Size is 1, representing 16KB page table, then {PA[47:14], VA[13:0]} is the translated address; Page Size is 2, representing 64KB page table, then {PA[47:16], VA[15:0]} is the translated address; Page Size is 3, representing 2MB page table, then {PA[47:21], VA[20:0]} is the translated address. PTE[9:0] is other control bits, which contains an identification bit for representing whether the PTE is stored, and the tag coordinate of the tag array corresponding to the current PTE, such as TAG(0, 0), indicating that the PTE in the current data array is the PTE corresponding to TAG(0, 0), instead of the PTEs corresponding to TAG(0, 1), TAG(0, 2), and TAG(0, 3). The update rule of the identification bit is: when the PTE is empty at the beginning, the identification is 0, after the PTE is obtained, the identification is updated to 1, and when the PTE is discarded, the identification is cleared to 0.

[0058] It can be understood that, Figure 2 VA[47:12] in the above formula and Figure 3 PA[47:12] in the above formula are exemplified with the minimum page table size of 4KB; if the minimum page table size is 16KB, then Figure 2 VA[47:12] in the above formula needs to be changed to VA[47:14], and Figure 3 PA[47:12] in the above formula needs to be changed to PA[47:14], and if the minimum page table size is 64KB, then Figure 2 VA in the above formula and Figure 3 PA in the above formula also need to be changed accordingly.

[0059] Counter, used to represent whether the PTE corresponding to the TAG tag to which it belongs is used up. When the TLB cache misses an address translation request, the corresponding basic tag and its attached Size, Status are updated according to the aforementioned rules, at the same time, its corresponding Counter also needs to be updated, such as Counter = Counter + fixed value, the fixed value can be 1. When the TLB cache hits (including the above-mentioned regular hit and Hit-on-Miss scenario hit) address translation request, the tag attached Size, Status is not updated, but its attached Counter needs to be updated, Counter = Counter + fixed value. Whenever an address translation request is completed, the address translation corresponding to the Valid state Counter = Counter - fixed value. When the Valid state tag attached Counter is the initial value, such as 0, it represents that this PTE has been used up, the content in the corresponding data array can be refilled (or kicked out), when multiple data arrays are allowed to be kicked out, a round-robin arbitration strategy is used to decide the kick-out order.

[0060] In a possible implementation, the control unit is configured to merge multiple TAG tags in the case that multiple TAG tags in the same row of the vector tag array correspond to the same PTE. The control unit can also be configured to detect whether multiple TAG tags in the same row of the vector tag array correspond to the same PTE. For example, detecting whether a first TAG tag whose address range is within the address range of a target TAG tag, is in the same row as the target TAG tag, and whose status identifier is a pending state; in the case that the first TAG tag exists, it represents that the target TAG tag and the first TAG tag correspond to the same PTE.

[0061] The control unit can detect whether the first TAG tag exists in the vector tag array after the page table walking unit returns the PTE corresponding to the target TAG tag and updates the page table size of the target TAG tag to the actual page table size of the returned PTE. The status identifier of the target TAG tag is a valid state. The first TAG tag is a TAG tag whose address range is within the address range of the target TAG tag, is in the same row as the target TAG tag, and whose status identifier is a pending state.

[0062] The control unit, when merging multiple TAG tags in the same row, can update the count value of the TAG tag with a valid state to the sum of the count value of the TAG tag with a valid state and the count value of the remaining TAG tags, reset the count value of the remaining TAG tags to an initial value (e.g., 0), and update the state identification of the remaining TAG tags to an invalid state. For example, for the case where the target TAG tag and the first TAG tag correspond to the same PTE, the control unit is specifically configured to update the count value of the target TAG tag to the sum of the count value of the target TAG tag and the count value of the first TAG tag, reset the count value of the first TAG tag to an initial value (e.g., 0), and update the state identification of the first TAG tag to an invalid state. For example, after the page table traversal unit returns the PTE corresponding to the target TAG tag and updates the page table size of the target TAG tag to the actual page table size of the returned PTE, an intra-row horizontal merge check is performed. When there are both Valid and Pending state tags in the row, for the Pending state tag, check whether it falls within the address range of the Valid state tag according to the attached Size, for example, if the returned Size is 4KB, use the VA[47:12] stored in the TAG tag to determine, if the VA[47:12] of the two tags are the same, then the address range is within the address range of the target TAG tag; similarly, if the Size is 16KB, use the VA[47:14] stored in the TAG to determine, if the VA[47:14] of the two tags are the same, then the address range is within the address range of the target TAG tag; similarly, if the Size is 64KB, use the VA[47:16] stored in the TAG to determine, if the VA[47:16] of the two tags are the same, then the address range is within the address range of the target TAG tag; similarly, if the Size is 2MB, use the VA[47:21] stored in the TAG to determine, if the VA[47:21] of the two tags are the same, then the address range is within the address range of the target TAG tag. If so, update the sum of the Counter of the Pending state and the Counter of the Valid state to the Counter of the tag with a Valid state, and update the Counter of the tag with a Pending state to 0 and the Status to Invalid.

[0063] In a possible implementation, the control unit is further configured to detect whether a second TAG tag exists in the vector tag array, the second TAG tag having an address range located within the address range of the target TAG tag, not located in the same row as the target TAG tag, and having a state identifier indicating a valid state or a pending state; and in a case where the second TAG tag exists, update a page table size of the second TAG tag to an actual page table size of the PTE corresponding to the target TAG tag. The second TAG tag is a TAG tag having an address range located within the address range of the target TAG tag, not located in the same row as the target TAG tag, and having a state identifier indicating a valid state or a pending state.

[0064] For example, after the page table traversal unit returns the PTE corresponding to the target TAG tag and updates the page table size of the target TAG tag to the actual page table size of the returned PTE, the control unit performs a vertical other row check to detect whether the address range corresponding to a tag in a valid state falls within the address range corresponding to the target TAG tag, and if so, updates the Size of the other row tag in the valid state to the actual page table size of the PTE corresponding to the target TAG tag, such as 2 MB; if not, the other row tag and the Size thereof are not updated.

[0065] In a possible implementation, the control unit is further configured to, in a case where the address translation request does not hit a TAG tag in the vector tag array, fill key information in the address translation request into a target TAG tag in the vector tag array, update a state identifier of the target TAG tag to a pending state, update a page table size identifier of the target TAG tag to a minimum page table size, and update a count value of the target TAG tag to a next value, wherein the next value after the update is greater than the value before the update; after sending a PTE obtaining request containing a tag coordinate of the target TAG tag, update the state identifier of the target TAG tag to a valid state; and after returning a PTE of the tag coordinate, update the page table size of the target TAG tag to an actual page table size of the returned PTE, and fill the returned PTE into a data array corresponding to the target TAG tag.

[0066] When the control unit fills key information (such as PASID+VA[47:12]) in the address translation request into a target TAG tag in the vector tag array, the target TAG tag needs to be selected according to the foregoing rule, such as selecting a currently available TAG tag as the target TAG tag in the order of increasing tag array row number.

[0067] In a possible implementation, as Figure 6As shown, the TLB cache further comprises a pending cache connected with the control unit. The control unit is further configured to: in case that the address translation request does not hit the TAG tag of the vector tag array, store the tag coordinate of the target TAG tag allocated for the address translation request and the address translation request into the pending cache; in case that the address translation request hits the TAG tag of the vector tag array, store the tag coordinate of the hit TAG tag and the address translation request into the pending cache; then acquire the tag coordinate corresponding to the address translation request from the pending cache, and if the content in the data array corresponding to the tag coordinate is valid, acquire the PTE in the data array, then return the corresponding PTE to the source end sending the address translation request, and after returning the corresponding PTE, decrease the count value of the TAG tag corresponding to the PTE by a fixed value, such as Counter = Counter - 1.

[0068] The tag coordinate mentioned above can be a two-dimensional coordinate, such as TAG (0, 0), TAG (0, 1), etc. In a possible implementation, the tag coordinate can also be a tag row number (such as Tag Row ID). In the example shown in Figure 2 , four tag arrays in the same row correspond to one data array. In this implementation, the tag coordinate is the tag row number, i.e. Tag Row ID, such as Tag Row1, etc. Figure 2

[0069] For the convenience of illustration / understanding, the following will be described in combination with Figure 7 ​The principle is shown. Taking the L0-TLB cache as an example, after receiving an address translation request (including PASID+VA[47:0]) from a source end (such as a kernel), the control unit will compare all TAG tags in the tag array in parallel, and if a TAG tag is matched, it means that the TAG tag is hit, and if no TAG tag is matched, it means that the TAG tag is not hit. In the case of an address translation request that does not hit the TAG tag of the vector tag array, fill the key information in the address translation request into the target TAG tag in the vector tag array (the currently available TAG tag can be selected as the target TAG tag according to the order of the tag array row number from small to large), assuming that the target TAG tag is TAG(0, 15), and update the state identifier of the target TAG tag to the pending state, update the page table size identifier of the target TAG tag to the minimum page table size (such as 4KB), and increase the count value of the target TAG tag by 1. Then, initiate a PTE acquisition request to the page table traversal unit, which includes the tag coordinates (such as Tag Row ID) of the target TAG and PASID+VA[47:12], and the page table traversal unit returns the PTE corresponding to the tag coordinates (Tag Row ID+PTE) after acquiring the PTE, fills the returned PTE into the data array corresponding to the target TAG tag, and updates the page table size of the target TAG tag to the actual page table size of the returned PTE (such as 2MB); then perform an intra-row horizontal merging check, update the count value of the target TAG tag to the sum of the count value of the target TAG tag and the count value of the first TAG tag in the vector tag array, reset the count value of the first TAG tag to the initial value (such as 0), and update the state identifier of the first TAG tag to the invalid state; and also perform a vertical other row check, and update the page table size of the second TAG tag checked to the actual page table size of the returned PTE.

[0070] At the same time, whether the address translation request hits or misses the TAG tag of the vector tag array, the address translation request and its attached tag coordinates will be stored in the Pending Buffer (pending buffer). For example, when it is not hit, the tag coordinates of the target TAG tag allocated for the address translation request and the address translation request are stored in the pending buffer; when it is hit, the tag coordinates of the hit TAG tag and the address translation request are stored in the pending buffer, and if multiple TAG tags are hit, the smallest tag coordinates, such as the smallest tag row number, are stored in the pending buffer. When the Pending Buffer has multiple writable positions, write in the order of addresses from small to large.

[0071] The depth of the Pending Buffer is determined by the latency of PTE acquisition. This application uses a Pending Buffer depth of 64 as an example. In extreme scenarios, if the Pending Buffer is full and the required PTE for address translation has not been returned, the Pending Buffer can exert back pressure on the tag array filling logic (i.e., the control unit). Similarly, if the tag array is already full and no new address request can be filled, or if the Pending Buffer is full, the tag array filling logic can exert back pressure on the source that initiated the address translation request.

[0072] Next, the control unit can retrieve the tag coordinates corresponding to the address translation request from the pending buffer. If the content in the data array corresponding to the tag coordinates is valid, the PTE in that data array is retrieved. When there are multiple readable entries (address translation request + tag coordinates) in the pending buffer, polling arbitration is performed. After the entry is read, the row of the corresponding data array is accessed according to the row number of the tag coordinates to complete the address translation. Then, the count value of the TAG tag corresponding to the PTE is subtracted by a fixed value, such as Counter = Counter - 1.

[0073] This application also provides a data processing method, which will be described below in conjunction with... Figure 8 This will be explained. The data processing method includes S1 and S2.

[0074] S1: Detect whether there are multiple TAG tags in the same row corresponding to the same page table data in the vector tag array of the TLB cache.

[0075] In some possible implementations, S1 may include: detecting whether there exists a first TAG tag in the vector tag array whose address range is within the address range of the target TAG tag, is located in the same row as the target TAG tag, and is identified as being in a pending state; if the first TAG tag exists, it indicates that the target TAG tag and the first TAG tag correspond to the same page table data, wherein the status of the target TAG tag is identified as being in a valid state.

[0076] S2: When multiple TAG tags in the same row in a vector tag array correspond to the same page table data, merge the multiple TAG tags.

[0077] In some possible implementations, if the first TAG tag and the target TAG tag correspond to the same page table data, merging multiple TAG tags may include: updating the count value of the target TAG tag to the sum of the count value of the target TAG tag and the count value of the first TAG tag; resetting the count value of the first TAG tag to the initial value; and updating the status flag of the first TAG tag to an invalid state.

[0078] The data processing method described above can be applied to the TLB cache described above, and can also be applied to an apparatus, a chip, or a device, etc. containing the TLB cache, for example, can be applied to a processor.

[0079] The data processing method provided by the application embodiment has the same implementation principle and technical effects as the foregoing TLB cache embodiment. For brief description, the part not mentioned in the method embodiment can refer to the corresponding content in the foregoing TLB cache embodiment. The application embodiment further provides a memory management unit (MMU), which comprises a page table traversal unit and the TLB cache described above. The TLB cache is connected with the page table traversal unit, and in the case that the address translation request does not hit the TAG label in the TLB cache, the TLB cache will send a PTE acquisition request to the page table traversal unit. The page table traversal unit performs page table traversal after acquiring the PTE acquisition request, thereby obtaining the corresponding PTE, and returns the PTE to the TLB cache.

[0080] The TLB cache provided by the application embodiment has the same implementation principle and technical effects as the foregoing TLB cache embodiment. For brief description, the part not mentioned in the memory management unit embodiment can refer to the corresponding content in the foregoing TLB cache embodiment. The application embodiment further provides a chip, which comprises a core and the memory management unit described above. The core is connected with the memory management unit, for example, the core can send an address translation request to the memory management unit, and the memory management unit completes the address translation.

[0081] The chip provided by the embodiments of the present application can be an integrated circuit chip, which has a signal processing capability. The chip can be a general processor, including a central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), an accelerated processing unit, a multimedia application processor (MAP), a microprocessor, etc. The chip can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. Alternatively, the chip can also be any conventional processor, etc.

[0082] The embodiments of the present application further provide an electronic device, which includes a memory and the chip described above. In a possible implementation manner, as shown in Figure 9 The electronic device includes a transceiver, a memory, a communication bus and a processor. The transceiver, the memory and the processor are directly or indirectly electrically connected with each other to realize data transmission or interaction. For example, the elements can be electrically connected with each other through one or more communication buses or signal lines. The transceiver is configured to transceive data. The memory is configured to store data and a computer program, wherein the computer program includes at least one software function module in the form of software or firmware, which is stored in the memory or solidified in an operating system (OS) of the electronic device. The processor is configured to execute the software function module or the computer program stored in the memory. For example, the processor is configured to execute the data processing method described above.

[0083] The memory can be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), and the like.

[0084] The processor can be an integrated circuit chip with processing capability. The processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), an accelerated processing unit, a multimedia application processor (MAP), a microprocessor, and the like. The processor can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The processor can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application. Alternatively, the processor can be any conventional processor.

[0085] The electronic device can include, but is not limited to, a mobile phone, a tablet, a notebook computer, a desktop computer, a server, and the like.

[0086] It should be noted that each of the embodiments in the present specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other.

[0087] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented by other manners. The apparatus embodiments described above are merely illustrative, for example, the flowcharts and block diagrams in the drawings show the possible implementation architecture, function and operation of the apparatus, method and computer program product according to the embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code, which contains one or more executable instructions for implementing the specified logic function. It should also be noted that in some alternative implementation manners, the functions noted in the blocks can also occur in different order from that noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can also be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for executing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0088] In addition, the function modules in the embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0089] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, and the computer software product is stored in a computer readable storage medium, including a number of instructions for causing a computer device (which can be a personal computer, a notebook computer, a server, or an electronic device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned computer readable storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0090] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A TLB cache, characterized in that, include: Scalar data array used to store page table data; A vector tag array is used to store TAG tags. The TAG tags are used to determine whether the TLB cache stores page table data corresponding to the address translation request. The vector tag array supports multiple page table sizes. The control unit is configured to merge the multiple TAG tags when multiple TAG tags in the same row in the vector tag array correspond to the same page table data.

2. The TLB cache according to claim 1, characterized in that, The control unit is also used for: Detect whether there exists a first TAG tag in the vector tag array whose address range is within the address range of the target TAG tag, is located in the same row as the target TAG tag, and has a status of pending; wherein the status of the target TAG tag is a valid status; When the first TAG tag exists, it indicates that the target TAG tag and the first TAG tag correspond to the same page table data.

3. The TLB cache according to claim 2, characterized in that, The control unit is specifically used for: Update the count value of the target TAG tag to the sum of the count value of the target TAG tag and the count value of the first TAG tag; The count value of the first TAG is reset to the initial value, and the status identifier of the first TAG is updated to invalid.

4. The TLB cache according to claim 1, characterized in that, The control unit is also used for: Detect whether there exists a second TAG tag in the vector tag array whose address range is within the address range of the target TAG tag, is not located in the same row as the target TAG tag, and has a status identifier of valid or pending. If the second TAG exists, update the page table size of the second TAG to the actual page table size of the page table data corresponding to the target TAG.

5. The TLB cache according to claim 1, characterized in that, The control unit is also used for: If the address translation request does not hit the TAG tag of the vector tag array, the key information in the address translation request is filled into the target TAG tag in the vector tag array, the status identifier of the target TAG tag is updated to pending status, the page table size identifier of the target TAG tag is updated to the minimum page table size, and the count value of the target TAG tag is updated to the next value, wherein the updated next value is greater than the value before the update; After sending a PTE acquisition request containing the tag coordinates of the target TAG, the status identifier of the target TAG is updated to a valid status. After the page table data of the tag coordinates is returned, the page table size of the target TAG tag is updated to the actual page table size of the returned page table data, and the returned page table data is filled into the data array corresponding to the target TAG tag.

6. The TLB cache according to claim 1, characterized in that, The TLB cache also includes a pending cache; the control unit is further configured to: If the address translation request does not hit the TAG tag of the vector tag array, the tag coordinates of the target TAG tag allocated to the address translation request and the address translation request are stored in the pending cache; If the address translation request hits a TAG tag in the vector tag array, the tag coordinates of the hit TAG tag and the address translation request are stored in the pending cache; Obtain the tag coordinates corresponding to the address translation request from the pending cache. If the content in the data array corresponding to the tag coordinates is valid, obtain the page table data in the data array.

7. The TLB cache according to any one of claims 1-6, characterized in that, The TAG includes: the high-order part of the virtual address, a status identifier, a page table size identifier, and a count value; The status identifier is one of the following: pending status, valid status, or invalid status. The page table size identifier is one of the minimum page table size or the actual page table size of the page table data; The count value is used to indicate whether the page table data corresponding to its TAG tag has been used up.

8. The TLB cache according to any one of claims 1-6, characterized in that, The vector tag array is an M×N tag array, where one tag array is used to store one TAG tag, and M and N are both integers greater than or equal to 2. The scalar data array is an M×1 data array, and one data array is used to store one page table data; In this configuration, N label arrays in the same row share a single data array in a time-division multiplexing manner.

9. A memory management unit, comprising: The page table traversal unit and the TLB cache as described in any one of claims 1-8, wherein the TLB cache is connected to the page table traversal unit.

10. A chip, characterized in that, include: The kernel and the memory management unit as described in claim 9, wherein the kernel is connected to the memory management unit.

11. An electronic device, characterized in that, include: The memory and the chip as described in claim 10, wherein the chip is connected to the memory.

12. A data processing method, characterized in that, The method includes: Detect whether there are multiple TAG tags in the same row corresponding to the same page table data in the vector tag array of the TLB cache; If multiple TAG tags in the same row in the vector tag array correspond to the same page table data, the multiple TAG tags are merged.

13. The method according to claim 12, characterized in that, Detect whether multiple tags in the same row of the vector tag array in the TLB cache correspond to the same page table data, including: Detect whether there exists a first TAG tag in the vector tag array whose address range is within the address range of the target TAG tag, is located in the same row as the target TAG tag, and has a status of pending; wherein the status of the target TAG tag is a valid status; When the first TAG tag exists, it indicates that the target TAG tag and the first TAG tag correspond to the same page table data; accordingly, Merging the multiple TAG tags includes: Update the count value of the target TAG tag to the sum of the count value of the target TAG tag and the count value of the first TAG tag; The count value of the first TAG is reset to the initial value, and the status identifier of the first TAG is updated to invalid.

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