External device and bus configuration for interconnecting electronic components and devices

Abstract

The invention relates to an external device and a bus configuration for interconnecting electronic components and devices. A computer-implemented method includes, for each pin of a component on a physical or virtual board, determining a signal to import or export the pin and creating an association between the signal and the pin, and determining a shortest path connection between the pin and a pin of a configuration target and creating a mapping between a pin of a selected component and the pin of the configuration target; merging the associations and mappings to detect whether there is an incompatible signal associated with the pins of the component; in response to detecting the incompatible signal, an alternative hardware configuration is searched to change the at least one mapping.

Description

Technical Field

[0001] This disclosure relates to the field of hardware configuration. More specifically, this disclosure relates to hardware configurations of microcontroller units or other configuration targets that interconnect with and control board components (e.g., electronic components or devices) on one or more printed circuit boards. Background Technology

[0002] Electronic circuit boards (e.g., printed circuit boards (PCBs)) are media used to connect or “wire” components in a circuit to each other. Almost all electronic products use electronic circuit boards. A microcontroller, or microcontroller unit (MCU), is a small computer on a single integrated circuit. An MCU may include one or more processor cores, as well as memory and programmable input / output external devices. Microcontrollers are used for the automated control of products and devices such as automotive engine control systems, implantable medical devices, remote controls, office machines, appliances, power tools, toys, and other embedded systems. There remains a need for efficient and flexible technologies for hardware configuration related to and controlling MCUs or other configuration targets that interconnect with and control board components (e.g., electronic components or devices) on one or more electronic circuit boards.

[0003] All topics discussed in the Background section are not necessarily prior art and should not be considered prior art simply because they are discussed in the Background section. Therefore, any awareness of a problem in the prior art discussed in the Background section, or any problem related to such topics, should not be considered prior art unless explicitly stated otherwise. Instead, the discussion of any topic in the Background section should be considered as part of the inventor's solution to a specific problem, which may itself be inventive. Summary of the Invention

[0004] For many microcontrollers or other configuration targets (CTs), some of their pins can be configured in multiple ways and can have different functions depending on the selected configuration. There are hardware limitations that require analyzing the CT's datasheets and reference manuals to accurately determine which specific functions can be enabled for a given pin. Furthermore, when using such a CT, there may be many different variations with varying numbers of pins and associated functions for each pin. In this complex and diverse environment, configuring a CT to control a device (e.g., a microphone) is far more complex than in a static hardware configuration environment (e.g., where the function of each pin is predefined and does not need to be or cannot be configured by the CT firmware).

[0005] Typically, to enable CT firmware to control board components located on expansion boards, these expansion boards are dynamically connected to the motherboard (where the CT resides) via one or more connectors (or wires). This requires analyzing the schematics of the motherboard, expansion boards, and connectors, and tracing the wires between them to obtain the data needed for proper CT configuration. If more expansion boards are connected, electrical incompatibility issues may arise and need to be resolved. New wires can be added to expand functionality and / or breadboards can be used to organize the connections.

[0006] Embodiments of this disclosure provide a computer-implemented method for automatically resolving connector and wire connections across a motherboard and an expansion board, and detecting and resolving electrical incompatibilities. The method includes: receiving a netlist representation of a motherboard and at least one expansion board, wherein, according to the netlist representation, for each component on the motherboard and at least one expansion board: the component corresponds to a different master node in the netlist representation, and each pin of the component corresponds to a different pin node directly linked to the master node; creating at least one link between at least one node on the motherboard and at least one node on the at least one expansion board based on the physical connections between the motherboard and at least one expansion board; incorporating the created at least one link into the netlist representation to logically merge the motherboard and at least one expansion board into a single virtual board; and performing a connection path search on the single virtual board represented according to the netlist representation between: (a) pins of selected components on the motherboard or at least one expansion board and (b) a configuration target including at least one microprocessor on the motherboard or at least one expansion board.

[0007] Typically, to enable CT firmware to control board components (e.g., microphones) on an existing board, it's necessary to analyze the board schematic and the relevant board component's datasheet / reference manual to understand the pin connections between the CT and the board component. Then, the CT needs to be configured, for example, enabling the communication bus and other general-purpose input / output (GPIO) pins to the board component, while ensuring the correct pins are selected and properly configured. If conflicts occur, certain devices may need to be disabled, or new hardware configurations may need to be tested.

[0008] Embodiments of this disclosure provide a computer-implemented method for configuring a circuit breaker (CT) to interconnect one or more board components, comprising: for each of a plurality of pins of a selected component on a physical or virtual board, determining a signal configured to enter or exit the pin and creating an association between the signal and the pin; for each of the plurality of pins of the selected component on the physical or virtual board, determining a connection path between the pin and a pin of the configuration target and creating a mapping between the pin of the selected component and the pin of the configuration target; merging the associations and mappings of the plurality of pins of the selected component to detect the presence of an incompatible signal associated with a pin of the selected component; and performing at least one of the following: in response to detecting an incompatible signal associated with a pin of the selected component, searching for alternative hardware configurations, including changing board routing to change at least one mapping between the pin of the selected component and the pin of the configuration target; or in response to detecting no incompatible signal associated with any pin of the selected component, grouping at least a subset of the plurality of pins of the selected component into one or more buses.

[0009] When board components are connected to a CT, it may be necessary to activate certain CT external devices in a specific manner, and certain pins on the CT package may be dedicated to implementing specific external device functions. If a single board component is connected to a CT external device, the acceptable configuration range for that external device is determined by the board component to which it is connected. Any conflicts can be detected and resolved based on the board configuration and active devices.

[0010] Embodiments of this disclosure provide a computer-implemented method for configuring a CT peripheral device based on board component interconnects, comprising: for each CT pin in a subset of configuration target (CT) pins grouped using different semantic tags associated with the board component, selecting a CT signal from among supported CT signals, wherein the CT signal selected for the subset of CT pins corresponds to a target CT peripheral device instance among a plurality of CT peripheral device instances; determining whether the selected CT signal is available for use and whether the target CT peripheral device instance can be assigned; and performing at least one of the following: in response to determining that the selected CT signal is available for use and the target CT peripheral device instance can be assigned: associating the subset of CT pins with the selected CT signal and assigning the target CT peripheral device instance to the board component; and marking the selected CT signal as unavailable and the target CT peripheral device instance as unassignable; or in response to determining that the selected CT signal is unavailable or the target CT peripheral device instance cannot be assigned: searching for alternative hardware configurations of a physical or virtual board accommodating the CT and the board component, including changing the board routing, for example, by changing the configuration of at least one of solder bridges, switches, or jumpers.

[0011] When using multiple board components connected to the same CT external device interface (e.g., bus), all CT external devices associated with that board component's interface need to be properly configured, taking into account various configuration constraints arising from the connection between the CT and the board component. This includes finding the minimum and maximum operating frequencies applicable to all board components and CTs connected on the same bus, configuring the CT clock to ensure all frequency constraints are met (e.g., when using a MEMS microphone), managing the impact of CT external device operating modes on other relevant pins (e.g., potentially requiring additional chip select pins), and handling interrupt conflicts on the same line but different ports.

[0012] Embodiments of this disclosure provide a computer-implemented method for configuring a CT peripheral device based on constraints injected by a plurality of board components, comprising: for each board component in a set of board components configured to connect to a configuration target (CT) instance of the CT peripheral device, acquiring component characteristics for operating the board component; determining a minimum subset of compatibility parameters in the acquired component characteristics for operating individual board components in the set of board components; determining whether the minimum subset of compatibility parameters is compatible with the CT peripheral device instance; and performing at least one of the following: in response to determining that the minimum subset of compatibility parameters is compatible with the CT peripheral device instance, applying the minimum subset of compatibility parameters to the CT peripheral device instance; or in response to determining that the minimum subset of compatibility parameters is incompatible with the CT peripheral device instance, searching for alternative hardware configurations accommodating the CT and the physical or virtual board of the set of board components, including changing the board wiring, for example, by changing the configuration of at least one of solder bridges, switches, or jumpers. Attached Figure Description

[0013] Figure 1 This is a block diagram of a hardware configuration system according to some embodiments.

[0014] Figure 2 This is a block diagram illustrating elements of an example computing device or system utilized in some embodiments of the technology described herein.

[0015] Figure 3 This is a flowchart illustrating an example process for automatically resolving connections of connectors and wires across a motherboard and (multiple) expansion boards, according to some embodiments.

[0016] Figure 4 This is a flowchart illustrating an example process for configuring configuration targets to interconnect one or more selected board components, according to some embodiments.

[0017] Figure 5 This is a flowchart illustrating an example process for configuring an external device for a configuration target based on a single board component interconnect, according to some embodiments.

[0018] Figure 6 This is a flowchart illustrating an example process for configuring a target external device based on constraints injected by multiple board components, according to some embodiments.

[0019] Figure 7 It is shown according to some embodiments Figure 1 A block diagram illustrating an example implementation of a certain stage of the system shown.

[0020] Figure 8 An example of active and inactive components specified in a netlist according to some embodiments is shown.

[0021] Figure 9 An example of a representation of a board component having multiple pins according to some embodiments is shown.

[0022] Figure 10 An example of a network according to some embodiments is shown, which represents the connection between components.

[0023] Figure 11 An example of panel-based graphical connection path search is shown according to some embodiments.

[0024] Figure 12 Examples of physical connections to (multiple) add-on boards or (multiple) separate components according to some embodiments are shown.

[0025] Figure 13 An example of a connection path search based on a graph representing a virtual board, according to some embodiments, is shown.

[0026] Figure 14 An example of parsing signals from board component pins is shown according to some embodiments.

[0027] Figure 15 and Figure 16 An example is shown of parsing the wires between the configuration target and (multiple) board components according to some embodiments.

[0028] Figure 17 An example of altering the hardware configuration for alternative exploration, according to some embodiments, is shown.

[0029] Figure 18 An example of detecting and configuring CT external devices according to some embodiments is shown.

[0030] Figure 19 An example is shown of resource-based allocation of CT external devices and configuration of them according to limitations, based on some embodiments. Detailed Implementation

[0031] The following description and accompanying drawings illustrate certain specific details to provide a comprehensive understanding of the various embodiments disclosed. However, those skilled in the art will understand that the disclosed embodiments can be implemented in various combinations without requiring one or more of these specific details, or in combination with other methods, components, devices, materials, etc. In other instances, well-known structures or components relevant to the context of this disclosure (including, but not limited to, communication systems, networks, and environments) are not shown or described to avoid unnecessarily obscuring the description of the embodiments. Furthermore, the various embodiments can be methods, systems, media, or devices. Therefore, the various embodiments can combine software and hardware aspects. For example, the following list includes certain terms and acronyms used herein.

[0032] Board configuration: A combination of solder bridges, jumpers, switches, or any other electronic configuration devices that produce the intended behavior on the board.

[0033] Board component: Electronic equipment other than the configuration target (CT), which is mounted on one of the electronic circuit boards of the hardware (HW) platform including the CT.

[0034] Breadboard: A flexible electronic circuit board that allows for the testing and organization of wires between electronic circuit prototypes without the need to design a dedicated board.

[0035] Bus: A communication system for transmitting data between internal components of a computer, or between computers.

[0036] Configuration Target (CT): The MCU or other CPU that is the target of hardware configuration via currently disclosed technologies.

[0037] Central Processing Unit (CPU): A programmable hardware device that executes instructions for computer programs, such as arithmetic, logic, control, and input / output (I / O) operations.

[0038] CT external devices: Electronic components that enable the functions of electronic external devices (e.g., typically embedded in chip packages), such as "General Purpose I / O" (GPIO) or "Serial External Interface" (SPI).

[0039] Expansion board: An electronic circuit board containing circuitry that connects hardware components via wires, designed to extend the functionality of the motherboard, and typically linked to the motherboard via connectors.

[0040] Hardware (HW) conflict: An error that occurs when two devices are connected or configured in a manner that applies conflicting electrical values.

[0041] Hardware (HW) component limitations: Specific configuration requirements imposed on the connecting wires by board components for proper functioning. For example, certain wires require the SPI bus electronics to be implemented and operate within a specific frequency range.

[0042] HW Platform: Motherboard, which can optionally be connected to one or more expansion boards.

[0043] HW Platform Configuration: An aggregation of configuration settings for the boards included in the HW platform.

[0044] Jumper wire (JP): An HW component that connects two points in a schematic to close a circuit. The concept of a JP is similar to a solder bridge, but it is more expensive and requires more space.

[0045] Motherboard: An electronic circuit board containing circuitry that connects hardware components via wires and includes configuration targets (CTs). The motherboard may contain pathways to extend its functionality via connector plugs.

[0046] Netlist: A description of the connectivity of an electronic circuit board, such as detailed information about how the pins of different board components are interconnected.

[0047] Pin layout: The cross-reference between the contacts or pins of an electrical connector or electronic component and their function.

[0048] Solder bridge (SB): A point on the board where a conductor is intentionally interrupted, allowing a connection to be made or kept open by soldering a conductive element to fill the gap (thus closing the circuit). The board manufacturer and the user can decide whether to keep the corresponding connection open or closed.

[0049] Switch (SW): An electronic switch that connects two or more points to create a circuit. It is more expensive than a jumper wire, but more flexible.

[0050] Throughout the specification, claims, and drawings, unless the context clearly specifies otherwise, the following terms have the meanings explicitly relevant herein. The term “this document” refers to the specification, claims, and drawings relating to this application. The phrases “in one embodiment,” “in another embodiment,” “in various embodiments,” “in some embodiments,” “in other embodiments,” and their variations refer to one or more features, structures, functions, limitations, or characteristics of this disclosure and are not limited to the same or different embodiments unless the context clearly specifies otherwise. The term “or” as used herein is an inclusive “or” operator, equivalent to the phrases “A or B, or both” or “A or B or C, or any combination thereof,” and lists containing additional elements are treated similarly. The term “based on” is not exclusive and allows for reliance on additional features, functions, aspects, or limitations not described, unless the context clearly specifies otherwise. Furthermore, throughout the specification, the meanings of “a,” “an,” and “the” include both singular and plural.

[0051] Unless otherwise stated or contradicted by the context, the term “set” (e.g., “item set”) as used herein should be interpreted as a non-empty set that includes one or more members or instances.

[0052] Unless otherwise stated or contradicted by the context, the term “subset” (e.g., “subset of a collection of items”) as used herein shall be interpreted as a non-empty set that includes one or more components or instances of a collection.

[0053] Furthermore, the term "subset" as used in this paper refers to a proper subset, which is a collection of one or more components or instances whose total number is less than the set or number of components or instances included in the subset. For example, a subset of a set of 10 items will have fewer than 10 items but at least 1 item.

[0054] Figure 1 This is a block diagram of a hardware configuration system 100 according to some embodiments. As shown, the inputs to system 100 may include netlists and HW configurations (e.g., whether SB is closed or open) of one or more boards selected as HW platforms, and pin layouts and characteristic descriptions (e.g., HW component constraints) of one or more board components that may be used on the HW platform. The system may receive input in standard formats, such as multiple HW board packages and multiple HW component packages in Open-CMSIS-Pack (OCP) format.

[0055] For example, when configuring a system-on-a-chip (SoC) device (e.g., an MCU) present on a printed circuit board (PCB), system 100 can determine the connection methods between other board components present on the PCB and the SoC device to be configured. Here, the SoC device is the configuration target (CT).

[0056] For each board component on the PCB, the connection between each pin of the component and its connection to the circuit breaker (CT) is determined by analyzing the PCB's wiring (e.g., analyzing the PCB's netlist). The PCB wiring may depend on PCB configuration choices (jump wires, solder bridges, or switches), which can affect how each board component is connected to the CT. When a board component cannot be connected to the CT via the current wiring, alternative PCB wiring can be automatically searched by changing certain PCB configuration choices to find a matching PCB wiring.

[0057] Once a matching PCB routing is found, for each pin of each board component located on the same PCB as the CT, the system 100 can determine which pin of the CT the pin is routed to, what the logic signal transmitted through the wiring is, and whether the signal is part of a bus protocol. In some embodiments, a virtual board (rather than a PCB or other physical electronic circuit board) that incorporates multiple physical boards can be used as the basis for determination, analysis, and other processes associated with configuring the CT.

[0058] System 100 can combine or aggregate data regarding: pin layout of the CT and board components, netlists (or other routing representations) of a single board or combinations of boards, bus information for grouping signals / pins associated with external devices, hardware limitations or other constraints (e.g., clock, configurable options, etc.), and memory mappings (e.g., for DMA). Based on the aggregated information, System 100 can automatically resolve hardware constraints and identify which communication bus to use, on which pins, and at what frequency, thereby automatically selecting the correct configuration options for the CT firmware and component drivers. System 100 or other systems receiving the configuration options can generate firmware configuration code applicable to the CT and board components.

[0059] like Figure 1 As shown, system 100 may include four phases: phase #0 involves combining or merging representations of multiple boards to create a representation of a single virtual board of the HW platform; phase #1 involves calculating the wiring connections between the CT and board components present on the HW platform; phase #2 involves configuring CT external devices based on the connections of a single board component; and phase #3 involves configuring CT external devices based on constraints injected by multiple board components.

[0060] More specifically, for stage #0, in the context of configuring CTs (e.g., SoC devices) present on a printed circuit board (PCB), system 100 can combine information from multiple such PCBs, where one PCB holds the CTs to be configured, and create a single “virtual” PCB description by logically unifying all these PCBs for use in additional configuration operations. Connecting the PCBs together is performed using physical connectors (which may be standard or non-standard) or even using “floating wires” directly soldered to the PCB (or using wires with at least one end connected to a physical connector (unsoldered)). To be able to “virtually” merge these PCBs, a logical description of each PCB is required, including a list of board components present on the PCB (including connectors) and the routing of the PCB traces connecting all the PCB components together (e.g., in netlist format). Connection information between PCBs, such as male / female connectors linked together, or the location of floating wire solders or connector pins, can also be obtained. “Merging” multiple PCBs together can include merging their component lists (and, where applicable, resolving naming conflicts), and merging their netlists based on the connection information between the PCBs. In some embodiments, netlist-level conflicts can also be resolved.

[0061] More specifically, for stage #1, in the context of configuring CTs existing on a physical board (e.g., a PCB) or virtual board (e.g., merging multiple PCBs), system 100 can determine how each of the other board components on the board is connected to the CT to be configured. Board information can be obtained from stage #0 of system 100 or from other devices or systems. For each such board component on the board, the connection method can be determined by analyzing the board's wiring (e.g., represented in netlist format) to identify each pin of the board component and its connection to the CT. The board wiring may depend on board configuration options (e.g., jumpers, solder bridges, switches), which may affect how each board component is connected to the CT. When a board component cannot be connected to the CT via the current wiring, alternative board wiring can be automatically searched by changing certain board configuration options to find a matching wiring. Once a matching board wiring is found, for each pin of each board component present on the board, system 100 can determine which pin of the CT the pin is wired to, which logic signal is transmitted through the wiring corresponding to that pin, and whether the signal is part of a bus protocol.

[0062] More specifically, for phase #2, in the context of configuring the CTs present on the physical or virtual board, system 100 can determine which CT external device instances are available for connection to each other board component present on the board, and how to configure the CT pin layout mapping to enable the connection. Board information can be obtained from phase #1 of system 100, or from other devices or systems. To determine the external device instances, system 100 can obtain structured information describing all external device instances of the CT (e.g., UART or I2C instances), and all pin layout mapping possibilities for linking such external device instances to physical CT package pins. System 100 can also obtain information for each pin of other board components present on the board, including: which pin of the CT it is routed to, which logic signal is transmitted through the wiring, and whether the signal is part of a bus protocol, to facilitate this determination.

[0063] More specifically, for stage #3, in the context of configuring the CTs present on the physical or virtual board, system 100 can determine the optimal configuration of CT external device instances that can be used to connect to each other board component present on the board and resolve potential conflicts. Board information can be obtained from stage #0 of system 100 or from other devices or systems. To determine the configuration of CT external device instances, system 100 can obtain structured information describing the CT external device instances that can be used to connect to each other board component present on the board, especially when such CT external device instances are shared by multiple board components. This information can be obtained from stage #2 of system 100 or from other devices or systems. System 100 can also obtain information for each component connected to the CT according to the above information, including actual or potential constraints and characteristics (e.g., bus operating frequency, SPI polarity, I2C address, etc.), which can be used to configure the corresponding CT external device instance and / or resolve conflicts. This information can then be used to determine the optimal configuration for each used CT external device instance based on the constraints and characteristics of the board components connected to each instance of the CT external device being used (e.g., setting a bus operating frequency compatible with all components connected to the same bus) and to detect conflicts (e.g., using the same I2C slave address twice on the same bus).

[0064] Conflict resolution may include changing how the conflict plate component is connected to the CT, for example, this may be performed in phase #1 of system 100; system 100 may again determine which CT external device instances can be used, for example, this may be performed in phase #2 of system 100.

[0065] System 100 can output various hardware configuration information, including board configuration, CT pin and external device assignments, external device configuration, board component configuration, etc. This output can be firmware configuration code, or it can serve as the basis for generating applicable firmware configuration code for the CT and related board components.

[0066] Figure 1 The diagram illustrates the data flow and interaction between system inputs and the various stages themselves. This data flow and interaction can be implemented using suitable communication connections (not shown in the diagram). Communication connections may include one or more hardwired connections, one or more computer networks, one or more wired or wireless networks, satellite transmission media, one or more cellular networks, or some combination thereof. Communication connections may include publicly accessible linked networks, which may be operated by different parties, such as the Internet. Communication connections may also include other network types, such as one or more private networks (e.g., corporate or university networks that are completely or partially inaccessible to non-privileged users), or combinations of these networks, enabling, for example, one or more private networks to access one or more public networks. Furthermore, communication connections may include various types of wired and / or wireless networks in various situations, including satellite transmissions. In addition, the communication connection may include one or more communication interfaces, including radio frequency (RF) transceivers, cellular communication interfaces and antennas, USB interfaces, ports and connections (e.g., USB Type-A, USB Type-B, USB Type-C (or USB-C), USB mini A, USB mini B, USB micro A, USB micro C), and other RF transceivers (e.g., infrared transceivers, based on the IEEE 802.15.4 OpenThread protocol, etc.). Protocol or IEEE 802.15.4 MAC layer connection interface Connection interface, wireless Ethernet (“Wi-Fi”) interface, short-range wireless (e.g., Low power consumption (BLE) interface, etc.

[0067] Figure 3 The flowchart illustrates an example process 3000 for automatically resolving connector and wire connections between the motherboard and expansion board. Process 3000 can be partially or entirely routed via methods such as... Figure 1 The system implementation of system 100 (e.g., stage #0) is shown. In some embodiments, at least a portion of process 3000 is executed in real time relative to the extraction and generation of the netlist of the board.

[0068] Process 3000 begins at block 3002, receiving netlist representations of the motherboard and at least one expansion board. For example, based on the netlist representation, for each board component on the motherboard and expansion board: the component corresponds to a different master node in the netlist representation, and each pin of the component corresponds to a different pin node directly linked to the master node.

[0069] At block 3004, based on the physical connection between the motherboard and the expansion boards(s), at least one link is created between at least one node of the motherboard and at least one node of the expansion boards(s).

[0070] At block 3006, the created (multiple) links are incorporated into the netlist representation to logically merge the motherboard and (multiple) expansion boards into a single virtual board.

[0071] At block 3008, on a single virtual board represented according to the netlist representation, a connection path search is performed between the pins of a component on the motherboard or expansion board(s) and the CT (e.g., one of the CT pins) on the motherboard.

[0072] Figure 7 It is shown Figure 1 A block diagram of an example implementation of stage #0 in system 100. In some embodiments, Figure 7 also with Figure 3 Correspondingly. For example, Figure 7 As shown, the netlists of the motherboard and one or more expansion boards are input into system 100 for processing. System 100 merges the netlists of all boards and outputs a representation of a single virtual board (e.g., a single merged netlist).

[0073] Figures 8-13 It shows according to Figure 3 Process 3000 and / or Figure 1 The netlist merging aspects of stage #0 of system 100 are shown.

[0074] For example, for each pin of each component on the board (e.g., the motherboard where the CT resides), its corresponding CT pin will be automatically calculated, and the routing between the CT pin and the component pin will be automatically determined. The netlist can include all "point-to-point" electrical connections on the board, or it can include all components and test points on the board. Here, a component can be a connector, electronic assembly, sensor, or other entity on the board with pins. For each component, the netlist can specify its status, for example:

[0075] • Activity: When a component arrives at the CT, its pins must be configured; or

[0076] • Inactive: The component can be ignored through CT pin layout configuration.

[0077] Figure 8An example of active and inactive parts specified in the netlist is shown.

[0078] Each pin of each component is a node representing a graphic of the board. Each component represents or corresponds to a "master node" on the graphic, which is linked to each pin node. Figure 9 An example of a component U1 with four pins (1, 2, 3, 4) is shown.

[0079] In a netlist, a net represents the connection between all components in the net. Figure 10 An example of a network is shown, illustrating the connection (e.g., soldered together) between pin H6 of component U13, pin D4 of component U20, and pin 7 of component U37, as well as the three corresponding links included in the figure.

[0080] Figure 11 An example of a graphical connection path search based on the display panel is shown. The search can start from a component pin and proceed to a CT pin, for example, using breadth-first search (BFS) or other suitable graphical search methods to find the shortest path from the component pin node to the CT pin node on the graph. In some embodiments, system 100 selects some or all of the active components(s) and performs a connection path search on their pins, while ignoring or otherwise excluding all inactive components.

[0081] One or more boards (e.g., via connectors and / or floats) or individual components (e.g., via floats) can be added to the HW platform including CT and corresponding physical connections can be established. Figure 12 An example of physical connection to (multiple) additional boards or (multiple) independent components (e.g., from the motherboard) is shown.

[0082] For example, for each additional physical connection, it involves: nodes in the netlist of board 1 and nodes in the netlist of board 2, or nodes in the netlist of a board and pins of an independent component. Virtual nets can be created on the graph to represent these additional physical connections. These virtual nets can include a set of additional links on the graph for connecting multiple netlists. Thus, multiple netlists representing multiple boards, boards with (multiple) additional independent components, or multiple boards with (multiple) additional independent components can be merged into a single, larger graph or merged netlist to represent a virtual board. Figure 13 An example of a connection path search based on a larger graph representing a virtual board (e.g., using BFS) is shown. In some embodiments, system 100 selects some or all of the active components(s) and performs a connection path search on their pins, while ignoring or otherwise excluding all inactive components.

[0083] According to the search, when accessing a node, the following can be performed:

[0084] ○ If the node is a CT pin, the search ends when the target pin is found; or

[0085] ○ If the node is not a CT pin:

[0086] Continue visiting the next (or more) nodes.

[0087] ■ In some embodiments, when a node is visited, a set of checks can be performed to determine whether the path to the currently visited node should be eliminated. For example, if the node represents an electronic component (e.g., a resistor, capacitor, etc.), the node would lead to a longer path, but the path would not be eliminated; instead, the next(s) node(s) would continue to be visited.

[0088] Figure 4 The flowchart illustrates an example process 3100 for configuring CTs to interconnect one or more selected board components. Process 3100 may be partially or entirely via, for example... Figure 1 A system implementation such as System 100 (e.g., Stage #1) is shown. In some embodiments, at least a portion of process 3100 is executed in real time relative to, for example, a plurality of board components selected by the user.

[0089] Process 3100 begins at block 3102 and, for each pin of a selected component on a physical or virtual board, determines the signal configured to enter or exit that pin to create an association between the signal and the pin.

[0090] In block 3104, for each pin of the selected component on the physical or virtual board, the shortest path connection between that pin and the CT pin is determined to create a mapping between the selected component's pins and the CT pins. As will be described in more detail below, this mapping ultimately affects the configuration of the configuration target itself.

[0091] In block 3106, the pin associations and mappings of the selected components are merged to detect the presence of incompatible signals associated with the pins of the selected components. For example, additional merging and checking actions are performed by aggregating the mappings of all selected components to check for potential cross-component incompatibilities (e.g., pins from multiple components are mapped to the same CT pin (unless it is a bus, which can be confirmed in phase #2) or the CT external device configuration is affected by the CT pin assignment).

[0092] In block 3108, a search or grouping of pin / signal alternatives is performed. For example, system 100 may perform at least one of the following: in response to detecting an incompatible signal associated with a pin of the selected component, search for alternative hardware configurations, including changing the board routing, for example, changing at least one mapping between the pins of the selected component and the pins of the CT by changing the configuration of at least one of the solder bridges, switches, or jumpers; or in response to not detecting an incompatible signal associated with any pin of the selected component, group at least a subset of multiple pins of the selected component (and their associated signals) into one or more buses.

[0093] Figures 14-17 It shows the method for using according to Figure 4 Process 3100 and / or Figure 1 The phase #1 of the system 100 shown configures various aspects of the connection between the CT and (multiple) plate components.

[0094] Figure 14 An example of parsing signals from board component pins is shown. For example, system 100 may acquire the identifier of the CT, the identifier of the selected board component, and a netlist representing the corresponding HW platform (e.g., a physical board or virtual board) to be processed. For each pin on the component (excluding VDD or GND in some embodiments), system 100 may calculate or otherwise determine the signal configured or expected to be inbound or outbound on the pin. Using the netlist and component pin layout information, system 100 may identify the expected signal or other active signal on each pin. The results may be organized into a database table or list 1402, associating each pin with its corresponding signal.

[0095] Figure 15 and Figure 16 An example is shown illustrating the connection between the CT scanner and the plate(s) component(s). For instance, refer to... Figure 15 System 100 can acquire the identifier of the CT, the identifier of the selected board component, and a netlist representing the corresponding HW platform (e.g., physical board or virtual board) to be processed. For each pin on the component (excluding VDD or GND in some embodiments), system 100 can search the netlist for connection paths (e.g., shortest paths) to connect the individual pin of the component to the individual pin of the CT. In this way, system 100 can map each pin of the component to a pin of the CT. System 100 can detect whether the mapping successfully matches between the component pin and the CT pin. If a conflict exists (e.g., overlapping pin mappings), system 100 can flag the conflict to explore alternatives; if the mapping matches successfully, the results can be organized into a database table or list 1502 indicating the mapping between the board component pin and the CT pin.

[0096] For example, refer to Figure 16 The mapping results between board component pins and CT pins (e.g., database table 1502) and the association results between board component pins and signals (e.g., database table 1402) are merged or otherwise combined to create associations between board component pins, CT pins, and signals. System 100 can detect the presence of incompatible signals associated with any pin. If present, system 100 can flag the conflict to explore alternatives; otherwise, the created association results can be organized into database table or list 1602 for CT signal resolution. Each CT pin or component pin (including associated signals) can be labeled or grouped to belong to a bus. For example, this can be achieved by analyzing data from board component and bus descriptions applied to signals associated with the pin. Tagging or grouping information can be appended to the created association results in the form of database table or list 1604. This information can be fed into stage #2 of system 100.

[0097] Figure 17 An example of changing the hardware configuration to explore alternative solutions is illustrated. For example, system 100 may acquire relevant configuration information and netlists corresponding to the hardware platform to be processed. If a conflict is detected (e.g., in stages #1, #2, and / or #3), system 100 may continue searching for alternative hardware configurations (e.g., by changing one or more of the SB, JP, or SW settings or configurations) to allow for another attempt to resolve the wires between the CT and (multiple) board components. If no such alternative is found, system 100 may automatically (or prompt the user) disable one or more components (multiple) that are not properly connected to the CT. If an alternative is found, system 100 may apply the valid changes to the hardware configuration and continue resolving the wires between the CT and board components (e.g., in stage #1). In some embodiments, system 100 may notify the user of the hardware configuration change or request the user's approval before applying the change.

[0098] Figure 5 A flowchart of an example process 3200 configured for a CT external device based on interconnected individual board components. Process 3200 may be partially or wholly routed via, for example... Figure 1 The system implementation of system 100 shown (e.g., stage #2). In some embodiments, at least a portion of process 3200 is executed in real time relative to the completion of process 3100.

[0099] Process 3200 begins at block 3202, whereby for each CT pin in a subset of CT pins grouped using different semantic tags associated with the board component, a CT signal is selected for that CT pin from the supported CT signals based on the signal of the pin of the board component mapped to that CT pin. Here, the CT signal selected for that subset of CT pins corresponds to the target CT external device instance among all CT external device instances.

[0100] At block 3204, it is determined whether the selected CT signal is available for use and whether the target CT external device instance is available for allocation.

[0101] In block 3206, CT pin signal association and CT external device assignment are performed, or alternative solutions are searched. For example, system 100 may perform at least one of the following: in response to determining that a selected CT signal is available for use and a target CT external device instance can be assigned: associating a subset of CT pins with the selected CT signal, assigning a target CT external device instance to the selected CT signal, marking the selected CT signal as unavailable, and marking the target CT external device instance as unassignable; or in response to determining that a selected CT signal is unavailable or a target CT external device cannot be assigned: searching alternative hardware configurations for the physical or virtual board housing the CT and board components, including changing the board routing (e.g., by changing the configuration of at least one of solder bridges, switches, or jumpers).

[0102] Figure 18 It shows according to Figure 5 Process 3200 and / or Figure 1 The diagram shows an example of Phase 2 of the system 100 for detecting and configuring external CT devices. For example, system 100 can obtain, for instance, the detection and configuration of external CT devices in Phase 2. Figure 15 and Figure 16 The wiring between the CT and (or typically from) the plate components shown is at least partially output (e.g., a database table or list 1604) from the analysis (or typically from stage #1). In some embodiments, plate component pins are not taken into account when detecting and configuring CT external devices, or typically in stage #2. System 100 can use semantic tags to map the signal (or signal tuple) of each plate component to the corresponding CT signal (or set of CT signals) selected from supported CT signal options. Figure 18 In the example shown, "I2C1_SCL" is a signal name. While there are no specific rules regarding its format or semantics, for simplicity, this signal name is associated with a protocol description (e.g., through an association table). An exemplary explanation follows:

[0103] -Bus type: I2C

[0104] -Example of an external CT device: I2C1

[0105] -Signal type: SCL

[0106] Here, the semantic label “bus1” of the board component signal tuple can be used to map to the CT signal “I2C1_SCL” selected for CT pin F9 (and similarly for the CT signal “I2C1_SDA” selected for CT pin E10), where “I2C1” represents a CT external device instance.

[0107] Since the same CT external device instance may already be configured for use on other CT pins, in order to achieve the correct configuration, system 100 can determine whether the instance is available for the CT pin under consideration based on the mapping relationship. At this time, signal incompatibility can be tested at the bus level (or signal tuple level). Figure 18 An example test procedure is illustrated, in which system 100 can determine whether the CT signal selected for the CT pin is not in S_List and whether the corresponding CT external device instance is not in I_List. If so, the selected CT signal (e.g., "I2C1_SCL") is added to S_List so that the CT signal cannot be used again; the corresponding CT external device instance (e.g., "I2C1") is added to I_List; and the CT pin and its selected CT signal are added to the output table. If not, system 100 determines that no suitable configuration for the CT pin has been found and marks the conflict as detected. By detecting the conflict, system 100 can perform alternative exploration, for example, using... Figure 17 The process is shown.

[0108] Figure 6 The flowchart illustrates an example process 3300 for configuring a CT external device based on constraints injected by multiple plate components. Process 3300 may be partially or entirely via, for example... Figure 1 A system implementation such as System 100 shown (e.g., Phase #3). In some embodiments, at least a portion of process 3300 is executed in real time relative to the completion of process 3200.

[0109] Process 3300 begins at block 3302, where for each of a set of board components configured to connect to a CT external device instance, component characteristics for operating that board component are obtained.

[0110] At block 3304, determine the minimum subset of compatibility parameters obtained from the component characteristics of individual board components used to operate the group of board components.

[0111] At block 3306, determine whether the minimum subset of compatibility parameters is compatible with the CT external device instance.

[0112] In block 3308, a minimum set is defined or applied to the CT external device, or alternatives are searched. For example, system 100 may perform at least one of the following: in response to determining that a minimum subset of compatibility parameters is compatible with the CT external device instance, assigning or applying the minimum subset of compatibility parameters to the CT external device instance; or in response to determining that a minimum subset of compatibility parameters is incompatible with the CT external device instance, searching for alternative hardware configurations of the physical or virtual board accommodating the CT and the board assembly, including changing the board routing (e.g., by changing the configuration of at least one of solder bridges, switches, or jumpers).

[0113] Figure 19 It shows according to Figure 6 Process 3300 and / or Figure 1 Phase #3 of system 100 shown is an example of allocating CT external devices based on resources and configuring them according to limitations. For example, system 100 can obtain, for instance, the following... Figure 18 The diagram shows at least a portion of the output from detecting and configuring the CT external device (or typically obtained from stage #2) (e.g., a mapping between the CT external device instance and the connected plate components). System 100 may also obtain a characteristic description for the target CT external device instance and for the plate components(s) connected to it.

[0114] If the target CT external device instance is connected to only a single board component, the system 100 can determine whether the characteristics of that component are compatible with the target CT external device instance. If compatible, the system 100 can apply the component characteristics (or any applicable portion thereof) to the target CT external device instance and configure it accordingly; if incompatible, the system 100 can mark the conflict as detected.

[0115] If the target CT external device instance is shared across multiple board components, system 100 may attempt to determine a minimum subset of compatibility parameters among the characteristics of the multiple board components. If the minimum subset is empty or cannot be found, system 100 may mark the conflict as detected. Otherwise, system 100 may determine whether the minimum subset is compatible with the target CT external device instance. If compatible, system 100 may apply the minimum subset (or any applicable portion thereof) to the target CT external device instance and configure it accordingly; if incompatible, system 100 may mark the conflict as detected.

[0116] By detecting any conflict, system 100 can perform alternative explorations, for example, using... Figure 17 The process is shown.

[0117] Those skilled in the art should understand that, through Figure 1 and Figures 3-19The various operations shown, as well as those described elsewhere in this document, can be modified in a variety of ways. For example, a specific order of operations can be rearranged; some operations can be executed in parallel; the operations shown can be omitted, or other operations can be included; the operations shown can be broken down into one or more component operations, or multiple operations shown can be combined into a single operation, and so on.

[0118] Figure 2 This is a block diagram illustrating the elements of an example computing device or system 200 used in certain embodiments of the technology described herein. Exemplarily, computing device 200 corresponds to an implementation... Figure 1 System 100 Figure 3 Process 3000 Figure 4 Process 3100 Figure 5 Process 3200 Figure 6 The process 3300 or at least a portion thereof is a computing device.

[0119] In some embodiments, the computing device 200 may be implemented using one or more general-purpose or special-purpose computing systems or devices. Furthermore, in some embodiments, the computing device 200 may include one or more different computing systems or devices and may be distributed across multiple locations. Figure 2 Each block shown may represent one or more such blocks applicable to a particular embodiment, or may be combined with other blocks. Furthermore, the configuration manager 222 may be implemented via software, hardware, firmware, or a combination thereof to achieve the functionality described herein.

[0120] As shown in the figure, computing device 200 includes computer memory (“memory”) 201, display 202 (including but not limited to light-emitting diode (LED) panels, cathode ray tube (CRT) displays, liquid crystal displays (LCDs), touchscreen displays, projectors, etc.), one or more central processing units (CPUs) or other processors 203, input / output (I / O) devices 204 (e.g., keyboards, mice, RF or infrared receivers, universal serial bus (USB) ports, high-definition multimedia interface (HDMI) ports, other communication ports, etc.), other computer-readable media 205, network connectivity 206, power supply (or power interface) 207, and audio outputs 208 (including but not limited to speakers, buzzers, mobile phones, etc.). Configuration manager 222 resides in memory 201 as shown. In other embodiments, some contents of configuration manager 222 and some or all components may be stored on and / or transmitted via other computer-readable media 205. Components of computing device 200 and configuration manager 222 may execute on one or more processors 203 and perform the applicable functions described herein. In some embodiments, configuration manager 222 may run as, be part of, or work in conjunction with other software applications stored in memory 201 or other various computing devices. In some embodiments, configuration manager 222 may also facilitate communication with external devices via I / O device 204 or with other devices or systems via network connection 206.

[0121] One or more configuration modules 224 are configured to perform operations directly or indirectly related to netlist writing, wire resolution, CT external device allocation and configuration, hardware configuration changes, or other functions described herein. In some embodiments, configuration modules 224 store, retrieve, or otherwise access at least some configuration-related data on portions of configuration data storage 216 or other data storage internal or external to computing device 200. In various embodiments, at least some configuration modules 224 may be implemented in software or hardware.

[0122] Other code or programs 230 (e.g., other data processing modules, communication modules, web servers, etc.) and potential other data repositories (e.g., data repository 220 for storing other data) may also reside in memory 201 and may be executed on one or more processors 203. It is worth noting that... Figure 2 One or more components may or may not be present in any particular implementation. For example, some embodiments may not provide additional computer-readable media 205, display 202, or audio output 208.

[0123] In some embodiments, computing device 200 and configuration manager 222 include APIs that provide programmatic access for adding, removing, or changing one or more functionalities of computing device 200. In some embodiments, components / modules of computing device 200 and configuration manager 222 are implemented using standard programming techniques. For example, configuration manager 222 may be implemented as an executable file running on processor 203, accompanied by one or more static or dynamic libraries. In other embodiments, computing device 200 and configuration manager 222 may be implemented as instructions processed by a virtual machine, which execute as one of other programs 230. Typically, such exemplary embodiments can be implemented using a variety of programming languages ​​known in the art, including representative implementations of various programming language paradigms, including but not limited to object-oriented (e.g., Java, C++, C#, Visual Basic.NET, Smalltalk, etc.), functional (e.g., ML, Lisp, Scheme, etc.), procedural (e.g., C, Pascal, Ada, Modula, etc.), scripting (e.g., Perl, Ruby, Python, JavaScript, VBScript, etc.) or declarative (e.g., SQL, Prolog, etc.).

[0124] In a software or firmware implementation, instructions stored in memory configure one or more processors of computing device 200 to perform the functions of configuration manager 222 upon execution. In some embodiments, the instructions cause one or more processors 203 or some other processors (e.g., I / O controllers / processors) to perform at least some of the functions described herein.

[0125] The above embodiments may also utilize well-known or other synchronous or asynchronous client-server computing technologies. However, various components may also be implemented using more monolithic programming techniques, for example, as an executable running on a single-CPU computer system, or decomposed using various structured techniques known in the art, including but not limited to multiprogramming, multithreading, client-server, or peer-to-peer, running on one or more computer systems, each with one or more CPUs or other processors. Some embodiments may execute concurrently and asynchronously, communicating using messaging techniques. The implementation of configuration manager 222 also supports equivalent synchronous embodiments. Furthermore, other functions may be implemented and / or executed by different components / modules in different orders, but the functionality of computing device 200 and configuration manager 222 can still be achieved.

[0126] Furthermore, as part of the computing device 200 and configuration manager 222, the programming interface for storing data can be provided through standard mechanisms, such as C, C++, C#, and Java APIs; libraries for accessing files, databases, or other data repositories; scripting languages ​​(e.g., XML); or web servers, FTP servers, NFS file servers, or other servers that provide access to stored data. The configuration data store 216 and data repository 220 can be implemented as one or more database systems, file systems, or any other technology used to store such information, or any combination of the above technologies, including implementations using distributed computing technologies.

[0127] The techniques described herein can be used with different program and data configurations and locations. Various distributed computing technologies are applicable to the components of the illustrated embodiments implemented in a distributed manner, including but not limited to TCP / IP sockets, RPC, RMI, HTTP, and Web services (XML-RPC, JAX-RPC, SOAP, etc.). Other variations are also possible. Each component / module may also provide additional functionality, or existing functionality may be distributed differently among components / modules while still achieving the functionality of configuration manager 222.

[0128] Furthermore, in some embodiments, some or all components of computing device 200 and configuration manager 222 may be implemented or provided in other ways, for example, at least in part in firmware and / or hardware, including but not limited to one or more application-specific integrated circuits (“ASICs”), standard integrated circuits, controllers (e.g., by executing appropriate instructions, including microcontrollers and / or embedded controllers), field-programmable gate arrays (“FPGAs”), complex programmable logic devices (“CPLDs”), etc. Some or all system components and / or data structures may also be stored as content (e.g., executable or other machine-readable software instructions or structured data) on a computer-readable medium (e.g., a hard disk; memory; a computer network, cellular wireless network, or other data transmission medium; or a portable media article readable by an appropriate drive or via an appropriate connection, such as a DVD or flash memory device) to enable or configure the computer-readable medium and / or one or more associated computing systems or devices to perform or otherwise use, or to provide content to perform at least part of the techniques described.

[0129] In some embodiments, a computer-implemented method includes receiving a netlist representation of a motherboard and at least one expansion board, wherein, according to the netlist representation, for each component on the motherboard and at least one expansion board: the component corresponds to a different master node in the netlist representation, and each pin of the component corresponds to a different pin node, the pin node being directly linked to the master node; based on the physical connection between the motherboard and at least one expansion board, at least one link is created between at least one node on the motherboard and at least one node on the at least one expansion board; the created at least one link is incorporated into the netlist representation to logically merge the motherboard and at least one expansion board into a single virtual board; and

[0130] On a single virtual board represented according to the netlist representation, a connection path search is performed between (a) the pins of selected components on the motherboard or at least one expansion board and (b) a configuration target that includes at least one microprocessor on the motherboard or at least one expansion board.

[0131] In some embodiments, the motherboard and at least one expansion board include one or more printed circuit boards. In some embodiments, the configuration target includes a microcontroller unit (MCU) or a microprocessor unit (MPU).

[0132] In some embodiments, the selected component is selected at least in part based on the component's active or inactive state. In some embodiments, any component on the motherboard or at least one expansion board that is inactive is excluded from the execution of the connection path search.

[0133] In some embodiments, the connection path search is performed based at least in part on a graph representing a single virtual board. In some embodiments, the connection path search is performed based at least in part on breadth-first search (BFS).

[0134] In some embodiments, the method includes creating at least one second link between at least one node of the motherboard or at least one expansion board and at least one node of the independent component, based on the physical connection between the motherboard or at least one expansion board and the independent component. In some embodiments, the created at least one second link is incorporated into a netlist representation.

[0135] In some embodiments, a non-transitory computer-readable medium stores content that causes one or more processors to perform actions, the actions including: receiving a netlist representation of a motherboard and at least one expansion board, wherein, according to the netlist representation, for each component on the motherboard and at least one expansion board: the component corresponds to a different master node in the netlist representation, and each pin of the component corresponds to a different pin node, the pin node being directly linked to the master node; creating at least one link between at least one node on the motherboard and at least one node on the at least one expansion board based on the physical connection between the motherboard and at least one expansion board; incorporating the created at least one link into the netlist representation to logically merge the motherboard and at least one expansion board into a single virtual board; and performing a connection path search on the single virtual board represented according to the netlist representation between: (a) the pins of selected components on the motherboard or at least one expansion board and (b) a configuration target including at least one microprocessor on the motherboard or at least one expansion board.

[0136] In some embodiments, the selected component is selected at least in part based on the component’s active or inactive state.

[0137] In some embodiments, the connection path search is performed based at least in part on a graph representing a single virtual board. In some embodiments, the connection path search is performed based at least in part on breadth-first search (BFS).

[0138] In some embodiments, these actions include creating at least one second link between at least one node of the motherboard or at least one expansion board and at least one node of the independent component, based on the physical connection between the motherboard or at least one expansion board and the independent component. In some embodiments, the created at least one second link is incorporated into the netlist representation.

[0139] In some embodiments, the system includes one or more processors; and a memory storing content that, when executed by the one or more processors, causes the system to perform actions including: receiving a netlist representation of a motherboard and at least one expansion board, wherein, according to the netlist representation, for each component on the motherboard and at least one expansion board: the component corresponds to a different master node in the netlist representation, and each pin of the component corresponds to a different pin node, the pin node being directly linked to the master node; creating at least one link between at least one node on the motherboard and at least one node on the at least one expansion board based on the physical connection between the motherboard and at least one expansion board; incorporating the created at least one link into the netlist representation to logically merge the motherboard and at least one expansion board into a single virtual board; and performing a connection path search on the single virtual board represented according to the netlist representation between (a) the pins of selected components on the motherboard or at least one expansion board and (b) a configuration target including at least one microprocessor on the motherboard or at least one expansion board.

[0140] In some embodiments, the configuration target includes a microcontroller unit (MCU) or a microprocessor unit (MPU). In some embodiments, the selected component is selected at least in part based on the component's active or inactive state. In some embodiments, the connection path search is performed at least in part based on a graph representing a single virtual board. In some embodiments, the action includes incorporating at least one second link between at least one node of the motherboard or at least one expansion board and at least one node of the independent component into the netlist representation based on the physical connection between the motherboard or at least one expansion board and the independent component.

[0141] In some embodiments, a computer-implemented method includes: for each of a plurality of pins of a selected component on a physical board or virtual board, determining a signal configured to import or export the pin, and creating an association between the signal and the pin; for each of the plurality of pins of the selected component on the physical board or virtual board, determining a connection path between the pin and a pin of the configuration target, and creating a mapping between the pin of the selected component and the pin of the configuration target; merging the associations and mappings of the plurality of pins of the selected component to detect the presence of an incompatible signal associated with a pin of the selected component; and in response to detecting an incompatible signal associated with a pin of the selected component, searching for alternative hardware configurations to change at least one mapping between the pin of the selected component and the pin of the configuration target. In some embodiments, searching for alternative hardware configurations includes changing the board wiring, for example, by changing the configuration of at least one of solder bridges, switches, or jumpers.

[0142] In some embodiments, the physical or virtual board includes a printed circuit board. In some embodiments, the configuration target includes a microcontroller unit (MCU) or a microprocessor unit (MPU). In some embodiments, the determination of signals or connection paths is based at least in part on a netlist representing the physical or virtual board. In some embodiments, the determined connection path is the shortest path connection. In some embodiments, the association between signals and pins, and the mapping between the pins of the selected component and the pins of the configuration target, are represented in the form of a database table.

[0143] In some embodiments, the method includes detecting whether there is a conflict with a mapping created between a single pin of the selected component and a single pin of the configuration target. In some embodiments, the method further includes: in response to detecting a conflict in the created mapping, searching for alternative hardware configurations, including changing the board routing, for example by changing the configuration of at least one of solder bridges, switches, or jumpers, to change at least one mapping between the pins of the selected component and the pins of the configuration target.

[0144] In some embodiments, a non-transitory computer-readable medium stores content that causes one or more processors to perform actions, including: for each of a plurality of pins of a selected component on a physical or virtual board, determining a signal configured to import or export the pin, and creating an association between the signal and the pin; for each of a plurality of pins of a selected component on a physical or virtual board, determining a connection path between the pin and a pin of a configuration target, and creating a mapping between the pin of the selected component and the pin of the configuration target; merging the associations and mappings of the plurality of pins of the selected component to detect the presence of an incompatible signal associated with a pin of the selected component; and in response to detecting an incompatible signal associated with a pin of the selected component, searching for alternative hardware configurations to change at least one mapping between the pin of the selected component and the pin of the configuration target. In some embodiments, searching for alternative hardware configurations includes changing board wiring, for example, by changing the configuration of at least one of solder bridges, switches, or jumpers.

[0145] In some embodiments, determining at least one of a signal or determining a connection path is based at least in part on a netlist representing a physical or virtual board. In some embodiments, the determined connection path is the shortest path connection. In some embodiments, the associations between signals and pins, and the mapping between pins of selected portions and pins of configuration targets, are represented in the format of database tables.

[0146] In some embodiments, the action includes detecting whether there is a conflict with a mapping created between a single pin of the selected component and a single pin of the configuration target. In some embodiments, the action includes searching for alternative hardware configurations in response to detecting a conflict with the created mapping, including changing the board wiring, for example by changing the configuration of at least one of solder bridges, switches, or jumpers, to change at least one mapping between the pins of the selected component and the pins of the configuration target.

[0147] In some embodiments, a system includes: one or more processors; and one or more processors; and a memory storing content, which, when executed by the one or more processors, causes the system to perform actions including: for each of a plurality of pins of a selected component on a physical or virtual board, determining a signal configured to import or export the pin, and creating an association between the signal and the pin; for each of a plurality of pins of a selected component on a physical or virtual board, determining a connection path between the pin and a pin of a configuration target, and creating a mapping between the pin of the selected component and the pin of the configuration target; merging the associations and mappings of the plurality of pins of the selected component to detect the presence of an incompatible signal associated with a pin of the selected component; and in response to detecting an incompatible signal associated with a pin of the selected component, searching for alternative hardware configurations to change at least one mapping between the pin of the selected component and the pin of the configuration target. In some embodiments, searching for alternative hardware configurations includes changing the board wiring, for example, by changing the configuration of at least one of solder bridges, switches, or jumpers.

[0148] In some embodiments, the configuration target includes a microcontroller unit (MCU) or a microprocessor unit (MPU). In some embodiments, determining at least one of the signals or determining the connection path is based at least in part on a netlist representing a physical board or a virtual board. In some embodiments, the determined connection path is the shortest path connection.

[0149] In some embodiments, these actions include detecting whether a mapping conflict exists between a single pin of the selected component and a single pin of the configuration target. In some embodiments, these actions include: in response to detecting a conflict in the created mapping, searching for alternative hardware configurations, including changing the board routing, for example by changing the configuration of at least one of solder bridges, switches, or jumpers, to change at least one mapping between the pins of the selected component and the pins of the configuration target.

[0150] In some embodiments, a computer-implemented method includes: for each CT pin in a subset of configured target CT pins grouped using different semantic tags associated with board components, selecting a CT signal from among supported CT signals, wherein the CT signal selected for the subset of CT pins corresponds to a target CT external device instance among a plurality of CT external device instances; determining whether the selected CT signal is available and whether the target CT external device instance can be assigned; and performing at least one of the following: in response to determining that the selected CT signal is available and the target CT external device instance can be assigned: associating the subset of CT pins with the selected CT signal and assigning the target CT external device instance to the board component; and marking the selected CT signal as unavailable and the target CT external device instance as unassignable; or in response to determining that the selected CT signal is unavailable or the target CT external device instance cannot be assigned: searching for alternative hardware configurations of a physical board or virtual board housing the CT and the board component, including changing the board routing.

[0151] In some embodiments, the physical or virtual board includes a printed circuit board. In some embodiments, the CT includes a microcontroller unit (MCU) or a microprocessor unit (MPU). In some embodiments, a semantic tag indicates a specific bus. In some embodiments, a semantic tag represents a signal tuple of a board component. In some embodiments, the selection of CT signals is based on board component pin signals mapped to CT pins. In some embodiments, the selection of CT signals is based on semantic tags, regardless of any pins of the board component. In some embodiments, a target CT external device instance is assigned to two or more board components.

[0152] In some embodiments, a non-transitory computer-readable medium stores content that causes one or more processors to perform actions, the actions including: selecting a CT signal for each CT pin in a subset of configured target CT pins grouped using different semantic tags associated with board components, wherein the CT signal selected for the subset of CT pins corresponds to a target CT external device instance among a plurality of CT external device instances; determining whether the selected CT signal is available and whether the target CT external device instance can be assigned; and performing at least one of the following: in response to determining that the selected CT signal is available and the target CT external device instance can be assigned: associating the subset of CT pins with the selected CT signal and assigning the target CT external device instance to the board component; and marking the selected CT signal as unavailable and the target CT external device instance as unassignable; or in response to determining that the selected CT signal is unavailable or the target CT external device instance cannot be assigned: searching for alternative hardware configurations of a physical or virtual board accommodating the CT and the board component, including changing the board routing.

[0153] In some embodiments, semantic tags indicate a specific bus. In some embodiments, semantic tags represent signal tuples of board components. In some embodiments, the selection of CT signals is based on the signals of board component pins mapped to that CT pin. In some embodiments, the selection of CT signals is based on semantic tags, regardless of any pins of the board component. In some embodiments, a target CT external device instance is assigned to two or more board components.

[0154] In some embodiments, a system includes: one or more processors; and a memory for storing content that, when executed by the one or more processors, causes the system to perform actions. The actions include: selecting a CT signal for each CT pin in a subset of target CT pins grouped using different semantic tags associated with board components, from among supported CT signals, wherein the CT signal selected for the subset of CT pins corresponds to a target CT external device instance among a plurality of CT external device instances; determining whether the selected CT signal is available and whether the target CT external device instance can be assigned; and performing at least one of the following: in response to determining that the selected CT signal is available and the target CT external device instance can be assigned: associating the subset of CT pins with the selected CT signal and assigning the target CT external device instance to the board component; and marking the selected CT signal as unavailable and the target CT external device instance as unassignable; or in response to determining that the selected CT signal is unavailable or the target CT external device instance cannot be assigned: searching for alternative hardware configurations of a physical or virtual board housing the CT and the board component, including changing the board routing, for example, by changing the configuration of at least one of solder bridges, switches, or jumpers.

[0155] In some embodiments, the CT includes a microcontroller unit (MCU) or a microprocessor unit (MPU). In some embodiments, a semantic label indicates a specific bus. In some embodiments, a semantic label represents a signal tuple of a board component. In some embodiments, the selection of CT signals is based on the signals of board component pins mapped to CT pins. In some embodiments, the selection of CT signals is based on semantic labels, regardless of any pins of the board component.

[0156] In some embodiments, a computer-implemented method includes: for each board component in a set of board components configured to connect to a CT external device instance configured to target a CT, acquiring component characteristics for operating the board component; determining a minimum subset of compatibility parameters from the acquired component characteristics for operating individual board components in the set of board components; determining whether the minimum subset of compatibility parameters is compatible with the CT external device instance; and performing at least one of the following: in response to determining that the minimum subset of compatibility parameters is compatible with the CT external device instance, applying the minimum subset of compatibility parameters to the CT external device instance; or in response to determining that the minimum subset of compatibility parameters is not compatible with the CT external device instance, searching for alternative hardware configurations of a physical or virtual board accommodating the CT and the set of board components, including changing the board wiring, for example, by changing the configuration of at least one of solder bridges, switches, or jumpers.

[0157] In some embodiments, the physical or virtual board includes a printed circuit board. In some embodiments, the CT includes a microcontroller unit (MCU) or a microprocessor unit (MPU).

[0158] In some embodiments, component characteristics include hardware constraints or limitations. In some embodiments, hardware constraints or limitations include at least one of bus operating frequency, SPI polarity, or I2C address.

[0159] In some embodiments, a group of board components consists of individual board components. In some embodiments, the minimum subset of compatibility parameters is the obtained component characteristics for operating individual board components.

[0160] In some embodiments, applying a minimal subset of compatibility parameters to a CT external device instance includes configuring the CT external device instance based on a portion of a minimal subset that is compatible with the characteristics of the CT external device instance.

[0161] In some implementations, a non-transitory computer-readable medium stores content that causes one or more processors to perform actions, including: acquiring component characteristics for operating a component for each of a set of board components in a CT external device instance configured to connect to a configured target CT; determining a minimum subset of compatibility parameters from the acquired component characteristics for operating individual board components in the set of board components; determining whether the minimum subset of compatibility parameters is compatible with the CT external device instance; and performing at least one of the following: applying the minimum subset of compatibility parameters to the CT external device instance in response to determining that the minimum subset of compatibility parameters is compatible with the CT external device instance; or searching for alternative hardware configurations for accommodating the CT and a set of board components, including changing the board wiring, for example, by changing the configuration of at least one of solder bridges, switches, or jumpers.

[0162] In some embodiments, component characteristics include hardware constraints or limitations. In some embodiments, hardware constraints or limitations include at least one of bus operating frequency, SPI polarity, or I2C address.

[0163] In some embodiments, a group of board components consists of individual board components. In some embodiments, the minimum subset of compatibility parameters is the obtained component characteristics for operating individual board components.

[0164] In some embodiments, applying a minimum subset of compatibility parameters to a CT external device instance includes configuring the CT external device instance based on a portion of a minimum subset that is compatible with the characteristics of the CT external device instance.

[0165] In some embodiments, the system includes: one or more processors; and a memory for storing content, which, when executed by the one or more processors, performs corresponding actions. The actions include: for each board component in a set of board components configured to connect to a CT external device instance configured to target a CT, acquiring component characteristics for operating the board component; determining a minimum subset of compatibility parameters from the acquired component characteristics for operating individual board components in the set of board components; determining whether the minimum subset of compatibility parameters is compatible with the CT external device instance; and performing at least one of the following: in response to determining that the minimum subset of compatibility parameters is compatible with the CT external device instance, applying the minimum subset of compatibility parameters to the CT external device instance; or in response to determining that the minimum subset of compatibility parameters is not compatible with the CT external device instance, searching for alternative hardware configurations for accommodating the CT and the set of board components, including changing the board routing, for example, by changing the configuration of at least one of solder bridges, switches, or jumpers.

[0166] In some embodiments, the CT includes a microcontroller unit (MCU) or a microprocessor unit (MPU). In some embodiments, component characteristics include hardware constraints or limitations.

[0167] In some embodiments, a group of board components consists of individual board components. In some embodiments, the minimum subset of compatibility parameters is the obtained component characteristics for operating individual board components.

[0168] In some embodiments, applying a minimum subset of compatibility parameters to a CT external device instance includes configuring the CT external device instance based on a portion of a minimum subset that is compatible with the characteristics of the CT external device instance.

[0169] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the full scope of the equivalents conferred by those claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A computer-implemented method, comprising: Receive a netlist representation of a motherboard and at least one expansion board, wherein, according to the netlist representation, for each component on the motherboard and the at least one expansion board: The components correspond to different master nodes in the netlist representation, and Each pin of the component corresponds to a different pin node, and the pin node has a direct link to the master node; Based on the physical connection between the motherboard and the at least one expansion board, at least one link is created between at least one node of the motherboard and at least one node of the at least one expansion board; The created at least one link is incorporated into the netlist representation to logically merge the motherboard and the at least one expansion board into a single virtual board; and According to the netlist representation, a connection path search is performed on the single virtual board between: (a) the pins of selected components on the motherboard or the at least one expansion board and (b) a configuration target on the motherboard or the at least one expansion board that includes at least one microprocessor.

2. The method of claim 1, wherein the motherboard and the at least one expansion board comprise one or more printed circuit boards.

3. The method of claim 1, wherein the configuration target includes a microcontroller unit (MCU) or a microprocessor unit (MPU).

4. The method of claim 1, wherein the selected component is selected at least in part based on the active or inactive state of the component.

5. The method of claim 4, wherein any component on the motherboard or the at least one expansion board that is inactive is excluded from the execution of the connection path search.

6. The method of claim 1, wherein the connection path search is performed at least in part based on a graph representing the single virtual board.

7. The method of claim 6, wherein the connection path search is performed at least in part based on breadth-first search (BFS).

8. The method of claim 1, further comprising creating at least one second link between at least one node of the motherboard or the at least one expansion board and at least one node of the independent component based on the physical connection between the motherboard or the at least one expansion board and the independent component.

9. The method of claim 8, wherein the at least one second link created is incorporated into the netlist representation.

10. A non-transitory computer-readable medium storing content that causes one or more processors to perform actions, the actions including: Receive a netlist representation of a motherboard and at least one expansion board, wherein, according to the netlist representation, for each component on the motherboard and the at least one expansion board: The components correspond to different master nodes in the netlist representation, and Each pin of the component corresponds to a different pin node, and the pin node has a direct link to the master node; Based on the physical connection between the motherboard and the at least one expansion board, at least one link is created between at least one node of the motherboard and at least one node of the at least one expansion board; The created at least one link is incorporated into the netlist representation to logically merge the motherboard and the at least one expansion board into a single virtual board; and According to the netlist representation, a connection path search is performed on the single virtual board between: (a) the pins of selected components on the motherboard or the at least one expansion board and (b) a configuration target on the motherboard or the at least one expansion board that includes at least one microprocessor.

11. The non-transitory computer-readable medium of claim 10, wherein the selected component is selected at least in part based on the active or inactive state of the component.

12. The non-transitory computer-readable medium of claim 10, wherein the connection path search is performed at least in part based on a graph representing the single virtual board.

13. The non-transitory computer-readable medium of claim 12, wherein the connection path search is performed at least in part based on breadth-first search (BFS).

14. The non-transitory computer-readable medium of claim 10, wherein the action includes creating at least one second link between at least one node of the motherboard or the at least one expansion board and at least one node of the independent component based on the physical connection between the motherboard or the at least one expansion board and the independent component.

15. The non-transitory computer-readable medium of claim 14, wherein the at least one second link created is incorporated into the netlist representation.

16. A system comprising: One or more processors; as well as A memory storing content, which, when executed by the one or more processors, causes the system to perform actions, including: Receive a netlist representation of a motherboard and at least one expansion board, wherein, according to the netlist representation, for each component on the motherboard and the at least one expansion board: The components correspond to different master nodes in the netlist representation, and Each pin of the component corresponds to a different pin node, and the pin node is directly linked to the main node; Based on the physical connection between the motherboard and the at least one expansion board, at least one link is created between at least one node of the motherboard and at least one node of the at least one expansion board; The created at least one link is incorporated into the netlist representation to logically merge the motherboard and the at least one expansion board into a single virtual board; and According to the netlist representation, a connection path search is performed on the single virtual board between: (a) the pins of selected components on the motherboard or the at least one expansion board and (b) a configuration target on the motherboard or the at least one expansion board that includes at least one microprocessor.

17. The system of claim 16, wherein the configuration target includes a microcontroller unit (MCU) or a microprocessor unit (MPU).

18. The system of claim 16, wherein the selected component is selected at least in part based on the active or inactive state of the component.

19. The system of claim 16, wherein the connection path search is performed at least in part based on a graph representing the single virtual board.

20. The system of claim 16, wherein the action includes incorporating the following into the netlist representation based on the physical connection between the motherboard or the at least one expansion board and the independent component: at least one second link between at least one node of the motherboard or the at least one expansion board and at least one node of the independent component.

21. A computer-implemented method, comprising: For each of multiple pins of a selected component on a physical or virtual board, determine the signal configured to import or export the pin, and create an association between the signal and the pin; For each of the plurality of pins of the selected component on the physical board or the virtual board, determine the connection path between the pin and the pin of the configuration target, and create a mapping between the pin of the selected component and the pin of the configuration target; The associations and mappings for the plurality of pins of the selected component are combined to detect whether there are incompatible signals associated with the pins of the selected component; as well as In response to the detection of an incompatible signal associated with a pin of the selected component, alternative hardware configurations are searched to change at least one mapping between the pins of the selected component and the pins of the configuration target.

22. The method of claim 21, wherein the physical board or the virtual board comprises a printed circuit board.

23. The method of claim 21, wherein the configuration target includes a microcontroller unit (MCU) or a microprocessor unit (MPU).

24. The method of claim 21, wherein determining at least one of the signal or determining the connection path is based at least in part on a netlist representing the physical board or the virtual board.

25. The method of claim 21, wherein the determined connection path is the shortest path connection.

26. The method of claim 21, wherein the association between the signal and the pin and the mapping between the pin of the selected portion and the pin of the configuration target are represented in the format of a database table.

27. The method of claim 21, further comprising detecting whether there is a conflict with the mapping created between a single pin of the selected component and a single pin of the configuration target.

28. The method of claim 27, further comprising, in response to detecting a conflict with the created mapping, searching for alternative hardware configurations, the search for alternative hardware configurations comprising changing board wiring to change at least one mapping between the pins of the selected component and the pins of the configuration target.

29. A non-transitory computer-readable medium storing content that causes one or more processors to perform actions, the actions including: For each of the multiple pins of a selected component on a physical or virtual board, determine the signal configured to import or export the pin, and create an association between the signal and the pin; For each of the plurality of pins of the selected component on the physical board or the virtual board, determine the connection path between the pin and the pin of the configuration target, and create a mapping between the pin of the selected component and the pin of the configuration target; The associations and mappings for the plurality of pins of the selected component are combined to detect whether there are incompatible signals associated with the pins of the selected component; as well as In response to the detection of an incompatible signal associated with a pin of the selected component, alternative hardware configurations are searched to change at least one mapping between the pins of the selected component and the pins of the configuration target.

30. The non-transitory computer-readable medium of claim 29, wherein determining at least one of the signal or determining the connection path is based at least in part on a netlist representing the physical board or the virtual board.

31. The non-transitory computer-readable medium of claim 29, wherein the determined connection path is the shortest path connection.

32. The non-transitory computer-readable medium of claim 29, wherein the association between the signal and the pin and the mapping between the pin of the selected portion and the pin of the configuration target are represented in the format of a database table.

33. The non-transitory computer-readable medium of claim 29, wherein the action includes detecting whether there is a conflict with the mapping created between a single pin of the selected portion and a single pin of the configuration target.

34. The non-transitory computer-readable medium of claim 33, wherein the action includes searching for alternative hardware configurations in response to detecting a conflict with the created mapping, the search for alternative hardware configurations including changing the board wiring to change at least one mapping between the pins of the selected component and the pins of the configuration target.

35. A system comprising: One or more processors; as well as A memory storing content, which, when executed by one or more processors, causes the system to perform actions, including: For each of the multiple pins of a selected component on a physical or virtual board, determine the signal configured to import or export the pin, and create an association between the signal and the pin; For each of the plurality of pins of the selected component on the physical board or the virtual board, determine the connection path between the pin and the pin of the configuration target, and create a mapping between the pin of the selected component and the pin of the configuration target; The associations and mappings for the plurality of pins of the selected component are combined to detect the presence of incompatible signals associated with the pins of the selected component; and In response to the detection of an incompatible signal associated with a pin of the selected component, alternative hardware configurations are searched to change at least one mapping between the pins of the selected component and the pins of the configuration target.

36. The system of claim 35, wherein the configuration target includes a microcontroller unit (MCU) or a microprocessor unit (MPU).

37. The system of claim 35, wherein determining at least one of the signal or determining the connection path is based at least in part on a netlist representing the physical board or the virtual board.

38. The system of claim 35, wherein the determined connection path is the shortest path connection.

39. The system of claim 35, wherein the action includes detecting whether there is a mapping conflict created between a single pin of the selected component and a single pin of the configuration target.

40. The system of claim 39, wherein the action includes searching for alternative hardware configurations in response to detecting a conflict with the created mapping, the search for alternative hardware configurations including changing the board wiring to change at least one mapping between the pins of the selected component and the pins of the configuration target.

41. A computer-implemented method, comprising: For each CT pin in a subset of configuration target CT pins grouped using different semantic tags associated with board components, a CT signal is selected for the CT pin from among the supported CT signals, wherein the CT signal selected for the subset of CT pins corresponds to a target CT external device instance among a plurality of CT external device instances; Determine whether the selected CT signal is available and whether the target CT external device instance can be assigned; as well as Perform at least one of the following: In response to determining that the selected CT signal is available and the target CT external device instance can be assigned: Associate the subset of the CT pins with the selected CT signal and assign the target CT external device instance to the board component; as well as Mark the selected CT signal as unavailable and mark the target CT external device instance as unassignable; or In response to determining that the selected CT signal is unavailable or the target CT external device instance cannot be assigned: Search for alternative hardware configurations for the physical or virtual board that houses the CT and the board components, including changing the circuit board wiring.

42. The method of claim 41, wherein the physical board or the virtual board comprises a printed circuit board.

43. The method of claim 41, wherein the CT includes a microcontroller unit (MCU) or a microprocessor unit (MPU).

44. The method of claim 41, wherein the semantic tag indicates a specific bus.

45. The method of claim 41, wherein the semantic tag represents a signal tuple of the board component.

46. ​​The method of claim 41, wherein the selection of the CT signal is based on the signal of a pin of the board component mapped to the CT pin.

47. The method of claim 41, wherein the selection of the CT signal is based on the semantic tag without regard to any pins of the board component.

48. The method of claim 41, wherein the target CT external device instance is assigned to two or more plate components.

49. A non-transitory computer-readable medium storing content that causes one or more processors to perform actions, the actions including: For each CT pin in a subset of target CT pins grouped using different semantic tags associated with board components, a CT signal is selected for the CT pin from among the supported CT signals, wherein the CT signal selected for the subset of CT pins corresponds to a target CT external device instance among a plurality of CT external device instances; Determine whether the selected CT signal is available and whether the target CT external device instance can be assigned; as well as Perform at least one of the following: In response to determining that the selected CT signal is available and the target CT external device instance can be assigned: Associate the subset of CT pins with the selected CT signal and assign the target CT external device instance to the board component; as well as Mark the selected CT signal as unavailable and mark the target CT external device instance as unassignable; or In response to determining that the selected CT signal is unavailable or the target CT external device instance cannot be assigned: Search for alternative hardware configurations for the physical or virtual board that houses the CT and the board components, including changing the circuit board wiring.

50. The non-transitory computer-readable medium of claim 49, wherein the semantic tag indicates a specific bus.

51. The non-transitory computer-readable medium of claim 49, wherein the semantic tag represents a signal tuple of the board component.

52. The non-transitory computer-readable medium of claim 49, wherein the selection of the CT signal is based on a signal of a pin of the board component mapped to the CT pin.

53. The non-transitory computer-readable medium of claim 49, wherein the selection of the CT signal is based on the semantic tag without regard to any pins of the board component.

54. The non-transitory computer-readable medium of claim 49, wherein the target CT external device instance is assigned to two or more plate components.

55. A system comprising: One or more processors; as well as A memory storing content, which, when executed by the one or more processors, causes the system to perform actions, including: For each CT pin in a subset of target CT pins grouped using different semantic tags associated with board components, a CT signal is selected for the CT pin from among the supported CT signals, wherein the CT signal selected for the subset of CT pins corresponds to a target CT external device instance among a plurality of CT external device instances; Determine whether the selected CT signal is available and whether the target CT external device instance can be allocated; and Perform at least one of the following: In response to determining that the selected CT signal is available and the target CT external device instance can be assigned: Associate the subset of CT pins with the selected CT signal and assign the target CT external device instance to the board component; and Mark the selected CT signal as unavailable and mark the target CT external device instance as unassignable; or In response to determining that the selected CT signal is unavailable or the target CT external device instance cannot be assigned: Search for alternative hardware configurations for the physical or virtual board that houses the CT and the board components, including changing the circuit board wiring.

56. The system of claim 55, wherein the CT includes a microcontroller unit (MCU) or a microprocessor unit (MPU).

57. The system of claim 55, wherein the semantic tag indicates a specific bus.

58. The system of claim 55, wherein the semantic tag represents a signal tuple of the board component.

59. The system of claim 55, wherein the selection of the CT signal is based on a signal of a pin of the board component mapped to the CT pin.

60. The system of claim 55, wherein the selection of the CT signal is based on the semantic tag without regard to any pins of the board component.

61. A computer-implemented method, comprising: For each of a set of board components configured to connect to a CT external device instance configured to target a CT, obtain the component characteristics for operating the board component; Determine the smallest subset of compatibility parameters among the component characteristics obtained for operating individual board components in the set of board components; Determine whether a minimum subset of the compatibility parameters is compatible with the CT external device instance; as well as Perform at least one of the following: In response to determining that a minimum subset of the compatibility parameters is compatible with the CT external device instance, the minimum subset of the compatibility parameters is applied to the CT external device instance; or In response to determining that the smallest subset of the compatibility parameters is incompatible with the CT external device instance, alternative hardware configurations for accommodating the CT and the set of board components, including changing the board wiring, are searched.

62. The method of claim 61, wherein the physical board or the virtual board comprises a printed circuit board.

63. The method of claim 61, wherein the CT includes a microcontroller unit (MCU).

64. The method of claim 61, wherein the component characteristics include hardware constraints or limitations.

65. The method of claim 64, wherein the hardware constraint or the limitation includes at least one of bus operating frequency, SPI polarity, or I2C address.

66. The method of claim 61, wherein the set of plate components comprises a single plate component.

67. The method of claim 66, wherein the minimum subset of the compatibility parameters is the obtained component characteristics for operating the individual board component.

68. The method of claim 61, wherein applying a minimum subset of the compatibility parameters to the CT external device instance comprises: The CT external device instance is configured based on a minimum subset that is compatible with the characteristics of the CT external device instance.

69. A non-transitory computer-readable medium storing content that causes one or more processors to perform actions, said actions including: For each of a set of board components configured to connect to a CT external device instance configured to target a CT, obtain the component characteristics for operating the board component; Determine the smallest subset of compatibility parameters from the component characteristics obtained for operating individual board components in the set of board components; Determine whether a minimum subset of the compatibility parameters is compatible with the CT external device instance; as well as Perform at least one of the following: In response to determining that a minimum subset of the compatibility parameters is compatible with the CT external device instance, the minimum subset of the compatibility parameters is applied to the CT external device instance; or In response to determining that the smallest subset of the compatibility parameters is incompatible with the CT external device instance, alternative hardware configurations for accommodating the CT and the set of board components, including changing the board wiring, are searched.

70. The non-transitory computer-readable medium of claim 69, wherein the component characteristics include hardware constraints or hardware limitations.

71. The non-transitory computer-readable medium of claim 70, wherein the hardware constraint or the limiting constraint includes at least one of bus operating frequency, SPI polarity, or I2C address.

72. The non-transitory computer-readable medium of claim 69, wherein the set of board components comprises a single board component.

73. The non-transitory computer-readable medium of claim 72, wherein the minimum subset of the compatibility parameters is the obtained component characteristics for operating the individual board component.

74. The non-transitory computer-readable medium of claim 69, wherein applying a minimal subset of the compatibility parameters to the CT external device example comprises: The CT external device instance is configured based on a minimum subset that is compatible with the characteristics of the CT external device instance.

75. A system comprising: One or more processors; as well as A memory storing content, which, when executed by the one or more processors, causes the system to perform actions, including: For each of a set of board components configured to connect to a CT external device instance configured to target a CT, obtain the component characteristics for operating the board component; Determine the smallest subset of compatibility parameters from the component characteristics obtained for operating individual board components in the set of board components; Determine whether a minimum subset of the compatibility parameters is compatible with the CT external device instance; and Perform at least one of the following: In response to determining that a minimum subset of the compatibility parameters is compatible with the CT external device instance, the minimum subset of the compatibility parameters is applied to the CT external device instance; or In response to determining that the smallest subset of the compatibility parameters is incompatible with the CT external device instance, alternative hardware configurations for accommodating the CT and the set of board components, including changing the board wiring, are searched.

76. The system of claim 75, wherein the CT includes a microcontroller unit (MCU) or a microprocessor unit (MPU).

77. The system of claim 75, wherein the component characteristics include hardware constraints or hardware limitations.

78. The system of claim 75, wherein the set of plate components comprises a single plate component.

79. The system of claim 78, wherein the minimum subset of the compatibility parameters is the obtained component characteristics for operating the individual board component.

80. The system of claim 75, wherein applying a minimal subset of the compatibility parameters to the CT external device instance comprises: The CT external device instance is configured based on a minimum subset that is compatible with the characteristics of the CT external device instance.

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