Data processing method, storage medium, electronic device and program product
By directly retrieving downstream memory data when the cache miss occurs, the request latency problem caused by cache miss is solved, and data processing efficiency is improved.
Patent Information
- Application Number
- CN202511114651.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-08
- Publication Date
- 2025-11-21
AI Technical Summary
缓存未命中导致的请求延迟，降低了数据处理效率。
When a request is received, it is determined whether the request carries a non-cached flag or whether the cache is unavailable. If so, the cache is skipped and the data is retrieved directly from the downstream memory to avoid the delay caused by cache miss.
By directly obtaining downstream memory data, the wasted clock cycles caused by cache misses are avoided, thus improving data processing efficiency.
Smart Images
Figure CN120994586A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of data processing, and in particular to a data processing method, a storage medium, an electronic device and a program product. BACKGROUND
[0002] In the process of data processing of data such as images, audios or texts, the processor of an electronic device usually needs to request instructions and data from the corresponding storage space; for example, the processor can request instructions and data from the cache, random access memory (RAM) or read-only memory (ROM) and the like.
[0003] However, the processor usually needs to initiate a request to the cache first; when the cache is not hit, the request is reinitiated to the downstream storage space (such as RAM, ROM) of the cache. However, cache miss will cause request delay, resulting in reduced data processing efficiency. SUMMARY
[0004] The present application provides a data processing method, a storage medium, an electronic device and a program product.
[0005] In a first aspect, the present application provides a data processing method applied to an electronic device, which comprises: receiving, by the electronic device, a first request in the process of running a target stage of a first pipeline, wherein the first request is used to indicate that first data is obtained from a first cache; determining, by the electronic device, that the first request meets a first condition in the target stage, and / or determining, by the electronic device, that the first cache meets a second condition in the target stage, wherein the first condition indicates that the first request carries a non-cache identifier, and the second condition indicates that the first cache is unavailable; and obtaining, by the electronic device, the first data from a first memory based on the first request, wherein the first memory is a downstream storage space of the first cache.
[0006] In the embodiment of the present application, when the electronic device receives the first request, it first judges whether the first request carries a non-cache identifier and whether the first cache is unavailable; when it is determined that the first request carries a non-cache identifier and / or the first cache is unavailable, it skips the first cache and directly obtains the first data from the first memory, thereby avoiding the request delay caused by cache miss and ensuring the data processing efficiency.
[0007] In a possible implementation of the first aspect, the electronic device includes a memory authentication unit, where the memory authentication unit stores a correspondence between different addresses and different address attributes, and the address attributes include a cacheable attribute, a non-cacheable attribute, and a peripheral memory attribute; the electronic device determines that the first request meets the first condition in the target stage, including: the electronic device determines a first address of the first request, and obtains a first address attribute corresponding to the first address from the memory authentication unit based on the first address; when the first address attribute is the non-cacheable attribute or the peripheral memory attribute, the first request carries a non-cacheable identifier.
[0008] In a possible implementation of the first aspect, the electronic device determines that the first cache meets the second condition in the target stage, including: when the electronic device determines that the first cache is in a locked state, a maintenance state, or a police state, the first cache is unavailable.
[0009] In a possible implementation of the first aspect, the electronic device includes a prefetch unit, the target stage includes a first stage, the first request includes an instruction acquisition request, the first cache includes an instruction cache unit, and the first data includes instruction data, where the electronic device receives the first request in the target stage of running the first pipeline, including: the electronic device receives the instruction acquisition request in the first stage through the prefetch unit, where the instruction acquisition request is used to indicate that the instruction data is acquired from the instruction cache unit; the electronic device determines that the first request meets the first condition in the target stage, and / or the electronic device determines that the first cache meets the second condition in the target stage, including: the electronic device determines that the instruction acquisition request meets the first condition in the first stage through the prefetch unit, and / or the electronic device determines that the instruction cache unit meets the second condition in the first stage through the prefetch unit.
[0010] In a possible implementation of the first aspect, the electronic device includes a first address bus, where the electronic device acquires the first data from the first memory based on the first request, including: the electronic device sends the instruction acquisition request to the first memory based on the first address bus in the first stage through the prefetch unit; the electronic device receives the instruction data returned by the first memory based on the first address bus in a second stage of the first pipeline through the prefetch unit.
[0011] In a possible implementation of the first aspect, the electronic device includes a data processing unit, where after the electronic device acquires the first data from the first memory based on the first request, including: the electronic device sends the instruction data to the data processing unit in the second stage through the prefetch unit; the electronic device decodes the received instruction data to obtain a decoding result in a third stage of the first pipeline through the data processing unit, where the decoding result is used for the data processing unit to generate a data loading request.
[0012] In a possible implementation of the first aspect, the electronic device includes a data processing unit, the target stage includes a fourth stage, the first request includes a data loading request, the first cache includes a data cache unit, and the first data includes operation data. In the process of running the target stage of the first pipeline, the electronic device receiving the first request includes: the electronic device receiving, by the data processing unit, the data loading request at the fourth stage, where the data loading request is used to indicate that the operation data is obtained from the data cache unit; and the electronic device determining that the first request meets the first condition at the target stage and / or the electronic device determining that the first cache meets the second condition at the target stage includes: the electronic device determining, by the data processing unit, that the data loading request meets the first condition at the fourth stage and / or the electronic device determining, by the data processing unit, that the data cache unit meets the second condition at the fourth stage.
[0013] In a possible implementation of the first aspect, the electronic device includes a first address bus. In the process of running the target stage of the first pipeline, the electronic device receiving the first request includes: the electronic device sending, by the data processing unit, the data loading request to the first memory based on the first address bus at the fourth stage; and the electronic device receiving, by the data processing unit, the operation data returned by the first memory based on the first address bus at the fifth stage of the first pipeline.
[0014] In a possible implementation of the first aspect, the electronic device includes an instruction obtaining unit configured to obtain instruction data. Before the electronic device receiving the first request in the process of running the target stage of the first pipeline, the electronic device receiving, by the data processing unit, the instruction data sent by the instruction obtaining unit at the third stage of the first pipeline and decoding the instruction data to obtain a decoding result, where the decoding result is used to generate the data loading request by the data processing unit.
[0015] In a possible implementation of the first aspect, the method further includes: determining that the first request does not meet the first condition and the first cache does not meet the second condition; and obtaining the first data from the first cache based on the first request.
[0016] In the second aspect, an embodiment of the present application provides a computer readable storage medium, which stores instructions. The instructions, when executed on an electronic device, cause the electronic device to implement any one of the data processing methods provided in the first aspect and the possible implementations of the first aspect.
[0017] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a memory configured to store instructions for execution by one or more processors of the electronic device; and a processor, one of the processors of the electronic device, configured to execute the instructions stored in the memory to implement any of the data processing methods provided in the first aspect and various possible implementations of the first aspect.
[0018] In a fourth aspect, an embodiment of the present application provides a program product, which comprises instructions, and when the instructions are executed by an electronic device, the electronic device can implement any of the data processing methods provided in the first aspect and various possible implementations of the first aspect. BRIEF DESCRIPTION OF DRAWINGS
[0019] Figure 1 According to some embodiments of the present application, a block diagram of an electronic device 11 is shown;
[0020] Figure 2 According to some embodiments of the present application, a schematic diagram of a pipeline is shown;
[0021] Figure 3 According to some embodiments of the present application, a block diagram of an electronic device 31 is shown;
[0022] Figure 4 According to some embodiments of the present application, a schematic diagram of another pipeline is shown;
[0023] Figure 5 According to some embodiments of the present application, a flowchart of a data processing method is shown;
[0024] Figure 6 According to some embodiments of the present application, a structural diagram of an electronic device 10 is shown. DETAILED DESCRIPTION
[0025] Illustrative embodiments of the present application include, but are not limited to, a data processing method, a storage medium, an electronic device and a program product.
[0026] The technical solutions of the present application will be described below with reference to the accompanying drawings.
[0027] The method provided in this application can be applied to any electronic device, including but not limited to mobile stations (MS) and mobile terminals (MT). For example, the electronic device can be a mobile phone, smart TV, wearable device, tablet computer, desktop computer, laptop computer, virtual reality (VR) device, augmented reality (AR) device, terminal in industrial control, terminal in self-driving, terminal in remote medical surgery, terminal in smart grid, terminal in transportation safety, terminal in smart city, terminal in smart home, etc. This application does not limit the specific form of the electronic device.
[0028] Figure 1 A framework diagram of an electronic device 11 is shown according to some embodiments of this application. Figure 1 As shown, the electronic device 11 includes a processor 110, which includes a pre-fetch unit (PFU), a data processing unit (DPU), an instruction cache unit (ICU), and a data cache unit (DCU). In other embodiments, the processor 110 may also include more or fewer other units, without limitation.
[0029] In some embodiments, the data processing procedure of the electronic device 11 includes five stages: Fetch Address (FA) stage, Fetch Data (FD) stage, Decode (DE) stage, Execute (EX) stage, and Complex Execute (CX) stage. In other embodiments, the data processing procedure of the electronic device 11 may also include more or fewer stages, without limitation.
[0030] It is understood that the data processing process of the aforementioned electronic device 11 can be the process by which the electronic device 11 processes data such as images, audio or text through the processor 110. For example, the electronic device 11 can perform classification, recognition, rendering and other processing on image data through the processor 110, and there are no specific limitations.
[0031] In conjunction Figure 1 , the following is an example illustration of the various units in the processor 110 and the various stages. Figure 2
[0032] Figure 2 According to some embodiments of the present application, a schematic diagram of a pipeline is shown.
[0033] Exemplarily, as Figure 2 shown, PFU-FA represents that the PFU initiates an instruction fetch request at the FA stage, for example, the PFU sends a corresponding instruction address to the ICU-IC1 for an instruction address query at the ICU-IC1.
[0034] PFU-FD represents that the PFU fetches an instruction at the FD stage, for example, the ICU-IC1 performs an address query according to the instruction address, and returns the instruction data corresponding to the instruction address to the PFU when the cache hits, and the PFU sends the instruction data to the DPU after obtaining the instruction data.
[0035] DPU-DE represents that the DPU decodes at the DE stage, for example, the DPU decodes the received instruction data to obtain a decoding result (such as an operand and an operation code) after receiving the instruction data sent by the PFU.
[0036] DPU-EX represents that the DPU initiates a data load request at the EX stage, for example, the DPU sends a load request of operation data (such as an operand) to the DCU-DC1 according to the decoding result, so that the DCU-DC1 performs an operation data query.
[0037] DPU-CX represents that the DPU fetches operation data and performs at the CX stage, for example, the DPU receives operation data from the DCU-DC2 and performs data processing (such as floating point operation).
[0038] In some embodiments, the execution of each of the foregoing stages usually needs to consume 1 clock cycle; for example, the processor 110 needs to consume at least 5 clock cycles to execute PFU-FA, PFU-FD, DPU-DE, DPU-EX and DPU-CX. In other embodiments, each stage can also consume more or less clock cycles, which is not limited in particular.
[0039] In some embodiments, the ICU and the DCU are usually located in the cache of the processor 110. It can be understood that the processor 110 usually initiates a request to the cache first; when the cache misses, a request is re-initiated to the downstream storage space (such as RAM, ROM or flash memory, etc.) of the cache. It can be understood that the downstream storage space can also be any other storage space located downstream of the cache, such as a hard disk drive, etc., which is not limited in particular.
[0040] In some embodiments, the cache miss case includes a case where the cache is unavailable and the cache does not store the requested data.
[0041] For example, continuing to refer to Figure 2 As shown, in the FD stage, the ICU performs an address query according to the instruction address requested by the PFU; if the ICU cache hits, the corresponding instruction data is sent to the PFU; if the ICU cache misses, a request is initiated to the downstream storage space through the address bus to obtain the corresponding instruction data from the downstream storage space and send it to the PFU. Similarly, in the CX stage, if the DCU cache misses, a request is initiated to the downstream storage space through the address bus to obtain the corresponding operation data from the downstream storage space and send it to the DPU.
[0042] It can be understood that the ICU needs to perform an address query in the FD stage to determine whether the cache hits or misses, that is, the execution of the FD stage still needs to consume 1 clock cycle; and if the ICU determines that the cache misses, the corresponding instruction data needs to be obtained from the downstream storage space, and obtaining data from the downstream storage space also needs to consume at least 1 clock cycle. That is, if the ICU cache misses in the FD stage, obtaining the corresponding instruction data from the downstream storage space needs to consume at least 2 clock cycles. Similarly, if the DCU cache misses in the CX stage, obtaining the corresponding instruction data from the downstream storage space needs to consume at least 2 clock cycles.
[0043] It can be understood that obtaining data from the downstream storage space can also consume more clock cycles, such as 2, 5, or other numbers greater than 2, which are not limited.
[0044] As described above, if the ICU and the DCU are both cache misses during the data processing of the electronic device 11, the entire execution process needs to consume at least 7 clock cycles, and the processing efficiency is low. That is, cache miss will cause request delay, resulting in reduced data processing efficiency.
[0045] Therefore, the present application provides a data processing method. The method comprises: an electronic device receives a first request, wherein the first request is used to indicate that first data is obtained from a first cache; it is determined that the first request satisfies a first condition, and / or it is determined that the first cache satisfies a second condition, wherein the first condition indicates that the first request carries a non-cache identifier, and the second condition indicates that the first cache is unavailable; and the first data is obtained from a first memory based on the first request, wherein the first memory is a downstream storage space of the first cache.
[0046] In some embodiments, the first request can be the aforementioned instruction obtaining request or the data loading request.
[0047] It is understood that when the electronic device of this application receives the first request, it first determines whether the first request carries a non-cached identifier and whether the first cache is unavailable; when it is determined that the first request carries a non-cached identifier and / or the first cache is unavailable, it skips the first cache and directly obtains the first data from the first memory, thereby avoiding request delays caused by cache misses and ensuring data processing efficiency.
[0048] Figure 3 A framework diagram of an electronic device 31 is shown according to some embodiments of this application. Figure 3 As shown, the electronic device 31 includes a processor 310, which includes a memory authentication unit (MAU), a PFU, a DPU, an ICU, and a DCU. For example, the MAU stores the correspondence between different addresses and different address attributes, where the address attributes include cacheable attributes, non-cacheable attributes, and external device memory attributes (hereinafter referred to as peripheral memory attributes). For example, the MAU stores the correspondence between different instruction addresses and different instruction address attributes; or, for example, the MAU stores the correspondence between different data addresses and different data address attributes, etc.
[0049] In other embodiments, the processor 310 may also include more or fewer other units, without limitation.
[0050] It is understood that the data processing process of electronic device 31 is similar to that of electronic device 11, including five stages: FA stage, FD stage, DE stage, EX stage, and CX stage. In other embodiments, the data processing process of electronic device 31 may also include more or fewer stages, without limitation.
[0051] Combination Figure 3 The following is through Figure 4 Examples are provided for each unit and stage in processor 310.
[0052] Figure 4 According to some embodiments of this application, a schematic diagram of another production line is shown.
[0053] For example, such as Figure 4 As shown, PFU-FA indicates that PFU initiates an instruction acquisition request and performs request detection during the FA phase.
[0054] In some embodiments, in the FA stage, when the PFU receives an instruction fetch request (corresponding to the example of the first request), the instruction address is obtained from the instruction fetch request, and the instruction address attribute corresponding to the instruction address is obtained from the MAU; further, the PFU determines that the instruction fetch request carries a non-cache identifier when detecting that the obtained instruction address attribute is a non-cacheable attribute or a peripheral memory attribute; at this time, the PFU skips the ICU and directly initiates a fetch request to the downstream storage space (such as the first memory, hereinafter referred to as the first memory) of the ICU through the first address bus.
[0055] In other embodiments, in the FA stage, when the PFU receives an instruction fetch request, the PFU determines that the ICU (corresponding to the example of the first cache) is unavailable when detecting that the ICU is in a locked state, a maintenance state, or a police state; at this time, the PFU skips the ICU and directly initiates a fetch request to the first memory through the first address bus.
[0056] It can be understood that, in the FA stage, when the PFU determines that the instruction fetch request carries a non-cache identifier, and / or when the PFU determines that the ICU is unavailable, the PFU skips the ICU and directly initiates a fetch request to the first memory through the first address bus.
[0057] Exemplarily, the first address bus can be an advanced microcontroller bus architecture high-performance bus (AHB); in other embodiments, the first address bus can also be other types of address buses, which are not limited in particular.
[0058] PFU-FD indicates that the instruction is obtained in the FD stage. For example, in the FD stage, the first memory performs address query according to the instruction address, and returns the instruction data (corresponding to the example of the first data) corresponding to the instruction address to the PFU through the first address bus, and the PFU sends the instruction data to the DPU after obtaining the instruction data. It can be understood that the first memory usually has a large storage capacity and usually has backups of various types of data, i.e., the first memory can usually be directly hit.
[0059] For example, in the FA stage, the PFU initiates a fetch request to the first memory through the AHB in the AHB-address phase (AP); in the FD stage, the PFU obtains the instruction data returned by the first memory through the AHB in the AHB-data phase (DP).
[0060] DPU-DE represents that the DPU decodes in the DE stage. For example, in the DE stage, the DPU decodes the received instruction data to obtain the decoding result (such as the operation number and the operation code) after receiving the instruction data sent by the PFU.
[0061] Continuing to refer to Figure 4 As shown, DPU-EX represents that the DPU initiates a data loading request and performs request detection in the EX stage.
[0062] In some embodiments, in the EX stage, when the DPU receives the data loading request (corresponding to the example of the first request), the data address is obtained from the data loading request, and the data address attribute corresponding to the data address is obtained from the MAU; further, the DPU determines that the data loading request carries the non-cache identifier when detecting that the obtained data address attribute is the non-cacheable attribute or the peripheral memory attribute; at this time, the DPU skips the DCU and directly initiates the loading request to the first memory through the first address bus.
[0063] In other embodiments, in the EX stage, when the DPU receives the data loading request, the DPU determines that the DCU is unavailable when detecting that the DCU (corresponding to the example of the first cache) is in the locked state, the maintenance state or the police state; at this time, the DPU skips the DCU and directly initiates the loading request to the first memory (corresponding to the example of the first memory) through the first address bus.
[0064] It can be understood that in the EX stage, when the DPU determines that the data loading request carries the non-cache identifier, and / or when the DPU determines that the DCU is unavailable, the DPU skips the DCU and directly initiates the loading request to the first memory through the first address bus.
[0065] DPU-CX represents that the data is obtained in the CX stage. For example, in the CX stage, the first memory performs address query according to the data address, and returns the operation data (corresponding to the example of the first data) corresponding to the data address to the DPU through the first address bus, and the DPU obtains the operation data and performs data processing. It can be understood that the first memory usually has large storage capacity and usually has backup for various types of data, that is, the first memory can usually be directly hit.
[0066] For example, in the EX stage, the DPU initiates the obtaining request to the first memory through the AHB in AHB-AP; in the CX stage, the DPU obtains the operation data returned by the first memory through the AHB in AHB-DP.
[0067] It can be understood that in combination with Figure 3 and Figure 4As shown, when the PFU receives the instruction fetch request, if the PFU determines that the instruction fetch request carries the non-cacheable identifier, and / or determines that the ICU is unavailable, the PFU skips the ICU and initiates the fetch request to the first memory directly; and when the DPU receives the data load request, if the DPU determines that the data load request carries the non-cacheable identifier, and / or determines that the DCU is unavailable, the DPU skips the DCU and initiates the fetch request to the first memory directly; in this way, the PFU and the DPU can avoid wasting at least one clock cycle due to cache miss, avoid request delay caused by wasting clock cycles, and ensure data processing efficiency.
[0068] It can be understood that, in Figure 4 , the PFU consumes only one clock cycle to detect the request in the FA stage and initiate the instruction fetch request to the first memory, and the PFU also consumes only one clock cycle to receive the instruction data sent from the first memory in the FD stage; the DPU consumes only one clock cycle to detect the request in the EX stage and initiate the data load request to the first memory, and the DPU also consumes only one clock cycle to receive the operation data sent from the first memory in the CX stage; that is, if Figure 4 the requested instruction data and operation data are all cache-miss data, and / or the cache is unavailable, Figure 4 the flow shown also only needs five clock cycles, not Figure 2 at least seven clock cycles shown in
[0069] In other embodiments, as shown in Figure 4 , in the FA stage, when the PFU determines that the instruction fetch request does not carry the non-cacheable identifier (for example, the instruction address attribute is a cacheable attribute), and the ICU is available (for example, the ICU is in a non-locked state, a maintenance state, and a warning state), the PFU initiates the fetch request to the ICU. Since the instruction address attribute corresponding to the instruction fetch request is a cacheable attribute, it indicates that the instruction data corresponding to the instruction address is cacheable data, and since the ICU is available, it indicates that the ICU can be accessed, so the result of the PFU initiating the fetch request to the ICU is usually a cache hit, that is, there will be no wasting of at least one clock cycle due to cache miss.
[0070] In other embodiments, as shown in Figure 4As shown, in the EX stage, when the DPU determines that the data load request does not carry a non-cacheable identifier (e.g., the data address attribute is a cacheable attribute), and the DCU is available (e.g., the DCU is in a non-locked state, a maintenance state, and a warning state), the DPU initiates a load request to the DCU. Since the data address attribute corresponding to the data load request is a cacheable attribute, it indicates that the operation data corresponding to the data address is cacheable data, and since the DCU is available, it indicates that the DCU can be accessed. At this time, the result of the DPU initiating a load request to the DCU is usually a cache hit, that is, there will be no waste of at least one clock cycle due to a cache miss.
[0071] Figure 5 According to some embodiments of the present application, a flowchart of a data processing method is shown. It can be understood that, Figure 5 The execution subject of the flowchart is an electronic device. In order to simplify the description, the following will not be repeated when introducing Figure 5 the flowchart. For example, Figure 5 The flowchart includes but is not limited to the following flowcharts:
[0072] S501: receiving a first request in the process of running a target stage of a first pipeline.
[0073] The first request is used to indicate that the first data is obtained from the first cache.
[0074] Exemplarily, as shown in Figure 3 and Figure 4 The first pipeline can be Figure 4 the flowchart, the target stage can be the FA stage or the EX stage, the first request can be an instruction fetch request or a data load request, and the first data can be instruction data or operation data.
[0075] S502: determining that the first request satisfies a first condition in the target stage, and / or determining that the first cache satisfies a second condition in the target stage.
[0076] The first condition indicates that the first request carries a non-cacheable identifier, and the second condition indicates that the first cache is unavailable.
[0077] Exemplarily, as shown in Figure 3 and Figure 4 The first cache can be an ICU or a DCU.
[0078] In some embodiments, the electronic device determines a first address of the first request when receiving the first request, obtains a first address attribute corresponding to the first address from the MAU of the electronic device based on the first address, and carries a non-cacheable identifier when the first address attribute is a non-cacheable attribute or a peripheral memory attribute. The MAU stores a correspondence between different addresses and different address attributes, and the address attribute includes a cacheable attribute, a non-cacheable attribute, and a peripheral memory attribute. In other embodiments, the electronic device determines that the first cache is in a locked state, a maintenance state, or a police state when receiving the first request, and the first cache is unavailable.
[0079] S503: Obtain the first data from the first memory based on the first request.
[0080] The first memory is a downstream storage space of the first cache.
[0081] In some embodiments, the electronic device determines that the first request meets the first condition, and / or the electronic device determines that the first cache meets the second condition, skips the first cache, and directly obtains the first data from the first memory, which can avoid at least one clock cycle waste caused by cache miss, avoid request delay caused by clock cycle waste, and ensure data processing efficiency.
[0082] In other embodiments, the electronic device obtains the first data from the first cache based on the first request when the electronic device determines that the first request does not meet the first condition and the first cache does not meet the second condition.
[0083] In some embodiments, in combination with Figures 3 to 5 , the following illustrates the case where the first request is an instruction obtaining request.
[0084] Illustratively, continuing to refer to Figures 3 to 5 , when the first request is an instruction obtaining request, the target stage is the first stage (corresponding to the example of the FA stage, hereinafter referred to as the first stage), the first cache is the ICU, and the first data is instruction data.
[0085] In process S501, the electronic device receives an instruction obtaining request in the first stage through the PFU. The instruction obtaining request is used to indicate that the instruction data is obtained from the ICU.
[0086] In the process S502, the electronic device determines, by the PFU in the first stage, that the instruction obtaining request satisfies the first condition, and / or the electronic device determines, by the PFU in the first stage, that the ICU satisfies the second condition. For example, when the PFU determines that the instruction address attribute corresponding to the instruction obtaining request is the non-cacheable attribute or the peripheral memory attribute, and determines that the instruction obtaining request carries the non-cache identifier, that is, the first request satisfies the first condition; for another example, when the PFU detects that the ICU is in the locking state, the maintenance state or the police state, it is determined that the ICU is unavailable, that is, the first request satisfies the second condition.
[0087] In the process S503, the electronic device sends, by the PFU in the first stage, the instruction obtaining request to the first memory through the first address bus; then, the electronic device receives, by the PFU in the second stage (corresponding to the example of the FD stage, hereinafter referred to as the second stage) of the first pipeline, the instruction data returned by the first memory through the first address bus.
[0088] After the process S503, the electronic device sends, by the PFU in the second stage, the instruction data to the DPU of the electronic device; then, the DPU decodes the received instruction data in the third stage (corresponding to the example of the DE stage, hereinafter referred to as the third stage) of the first pipeline to obtain a decoding result, wherein the decoding result is used for the DPU to generate a data loading request.
[0089] It can be understood that when the first request is the instruction obtaining request, and the PFU determines that the instruction obtaining request carries the non-cache identifier, and / or when the PFU determines that the ICU is unavailable, the PFU skips the ICU and directly initiates the instruction obtaining request to the first memory through the first address bus to obtain the instruction data, which can avoid at least one clock cycle waste caused by cache miss, avoid request delay caused by clock cycle waste, and ensure data processing efficiency.
[0090] In some other embodiments, in combination with Figures 3 to 5 The following illustrates the case that the first request is a data loading request.
[0091] For example, continuing to refer to the Figures 3 to 5 When the first request is the data loading request, the target stage is the fourth stage (corresponding to the example of the EX stage, hereinafter referred to as the fourth stage), the first cache is the DCU, and the first data is the operation data.
[0092] Before the process S501, the electronic device receives, by the DPU in the third stage, the instruction data sent by the PFU, and decodes the instruction data to obtain a decoding result, wherein the decoding result is used for the DPU to generate a data loading request.
[0093] In procedure S501, the electronic device receives, through the DPU, the data loading request in the fourth stage, where the data loading request is used to indicate to obtain operation data from the DCU.
[0094] In procedure S502, the electronic device determines, through the DPU, that the data loading request meets the first condition in the fourth stage, and / or the electronic device determines, through the DPU, that the DCU meets the second condition in the fourth stage. For example, when the DPU determines that the data address attribute corresponding to the data loading request is the non-cacheable attribute or the peripheral memory attribute, and determines that the data loading request carries the non-cache identifier, that is, the first request meets the first condition. For another example, when the DPU detects that the DCU is in the lock state, the maintenance state, or the police state, it is determined that the DCU is unavailable, that is, the first request meets the second condition.
[0095] In procedure S503, the electronic device sends, through the DPU, the data loading request to the first memory through the first address bus in the fourth stage. Then, the electronic device receives, through the DPU, the operation data returned by the first memory through the first address bus in the fifth stage of the first pipeline (corresponding to the example of the CX stage, hereinafter referred to as the fifth stage).
[0096] It can be understood that when the first request is the data loading request, and the DPU determines that the data loading request carries the non-cache identifier, and / or when the DPU determines that the DCU is unavailable, the DPU skips the DCU and directly initiates the loading request to the downstream memory through the address bus to obtain the operation data, which can avoid at least one clock cycle waste caused by cache miss, avoid request delay caused by clock cycle waste, and ensure data processing efficiency.
[0097] In some embodiments, as described above Figure 3 and Figure 5According to the description, the electronic device can initiate a request for instruction data to the first memory through the first address bus directly via the ICU when the first condition and / or the second condition are met in the first stage, and initiate a request for operation data to the DCU when the first condition and the second condition are not met in the fourth stage; or the electronic device can initiate a request for instruction data to the ICU when the first condition and the second condition are not met in the first stage, and initiate a request for operation data to the first memory through the first address bus directly via the DCU when the first condition and / or the second condition are met in the fourth stage; or the electronic device can initiate a request for instruction data to the first memory through the first address bus directly via the ICU when the first condition and / or the second condition are met in the first stage, and initiate a request for operation data to the first memory through the first address bus directly via the DCU when the first condition and / or the second condition are met in the fourth stage, without limitation.
[0098] To implement the above-described scheme of the embodiments of the present application, the related device for implementing the above-described scheme is further provided.
[0099] Exemplarily, Figure 6 According to some embodiments of the present application, a structural schematic diagram of an electronic device 10 is shown. Exemplarily, the electronic device 10 can be taken as an example of the foregoing electronic device 11 or the electronic device 31.
[0100] In some embodiments, the electronic device 10 can include one or more processors 1004, system control logic 1008 connected with at least one of the processors 1004, system memory 1012 connected with the system control logic 1008, non-volatile memory (NVM) 1016 connected with the system control logic 1008, and network interface 1020 connected with the system control logic 1008.
[0101] In some embodiments, the processor 1004 can include one or more single-core or multi-core processors. In some embodiments, the processor 1004 can include any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, baseband processors, etc.). In embodiments in which the electronic device 10 adopts an evolved node B (eNB) or a radio access network (RAN) controller, the processor 1004 can be configured to perform various embodiments consistent with the disclosure. Exemplarily, the processor 1004 can include Figure 3 The processor 310 and / or Figure 1The illustrated processor 110.
[0102] In some embodiments, the system control logic 1008 can include any suitable interface controllers to provide for any suitable interface to at least one of the processors 1004 and / or any suitable device or component in communication with the system control logic 1008.
[0103] In some embodiments, the system control logic 1008 can include one or more memory controllers to provide an interface to the system memory 1012. The system memory 1012 can be used to load and store data and / or instructions for use by at least one of the processors 1004. In some embodiments, the memory 1012 of the system 1000 can include any suitable volatile memory, such as suitable dynamic random access memory (DRAM), for example.
[0104] The NVM 1016 can include one or more tangible, non-transitory computer- readable media used for storage of data and / or instructions. In some embodiments, the NVM 1016 can include any suitable non-volatile storage, such as flash memory, and / or any suitable non-volatile storage device, such as at least one of a hard disk drive (HDD), a compact disk (CD) drive, a digital versatile disk (DVD) drive.
[0105] The NVM 1016 can include a portion of the storage resources on the device on which the electronic device 10 is installed, or it can be accessed by the device but not necessarily part of the device. For example, the NVM 1016 can be accessed over a network via the network interface 1020.
[0106] In particular, the system memory 1012 and the NVM 1016 can include, respectively, a temporary copy of and a permanent copy of the instructions 1024. The instructions 1024 can include instructions that, when executed by at least one of the processors 1004, cause the electronic device 10 to perform a method as illustrated, for example. Figure 5 In some embodiments, the instructions 1024, hardware, firmware, and / or software components thereof can additionally / alternatively be placed in the system control logic 1008, the network interface 1020, and / or the processors 1004.
[0107] The network interface 1020 can include a transceiver to provide the electronic device 10 with a radio interface to communicate with any other suitable device (e.g., a front end module, an antenna, etc.) over one or more networks. In some embodiments, the network interface 1020 can be integrated with other components of the electronic device 10. For example, the network interface 1020 can be integrated with at least one of the processor 1004, the system memory 1012, the NVM 1016, and a firmware device (not shown) having instructions that, when executed by at least one of the processors 1004, enable the electronic device 10 to perform the methods as described herein. Figure 5
[0108] The network interface 1020 can further include any suitable hardware and / or firmware to provide a multiple-input multiple-output radio interface. For example, the network interface 1020 can be a network adapter, a wireless network adapter, a telephone modem, and / or a wireless modem.
[0109] In one embodiment, at least one of the processors 1004 can be packaged with logic for one or more controllers of the system control logic 1008 to form a system-in-package (SIP). In one embodiment, at least one of the processors 1004 can be integrated on the same die with logic for one or more controllers of the system control logic 1008 to form a system-on-chip (SOC).
[0110] The electronic device 10 can further include an input / output (I / O) device 1032.
[0111] In some embodiments, the embodiments of the present application also provide a computer readable medium, which stores program codes, when the program codes are executed on a computer, the computer executes the method in the above aspects.
[0112] In some embodiments, the embodiments of the present application also provide a computer program product, which includes computer program codes, when the computer program codes are executed on a computer, the computer executes the method in the above aspects.
[0113] In the drawings, some of the structures or method features can be shown in particular arrangements and / or orders. However, it should be understood that such specific arrangements and / or orders can not be required. Instead, these features can be arranged in a different manner and / or order than shown in the illustrative drawings, in some embodiments. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments, and in some embodiments, such feature can not be included or can be combined with other features.
[0114] It should be noted that each unit / module mentioned in the embodiments of the devices of the present application is a logical unit / module, and in physical form, one logical unit / module can be a physical unit / module, or a part of a physical unit / module, or a combination of multiple physical unit / modules, and the physical implementation form of the logical unit / module itself is not the most important, and the combination of the functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned embodiments of the devices of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that the above-mentioned device embodiments do not have other units / modules.
[0115] It should be noted that in the examples and descriptions of the present patent, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including one" does not exclude the presence of another identical element in the process, method, article or device including the element.
[0116] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it should be understood by those skilled in the art that various changes in form and details can be made therein without departing from the scope of the present application.
Claims
1. A data processing method applied to electronic devices, characterized in that, The method includes: During the execution of a target stage of the first pipeline, the electronic device receives a first request, wherein the first request is used to instruct the retrieval of first data from a first cache; The electronic device determines in the target phase that the first request satisfies a first condition, and / or the electronic device determines in the target phase that the first cache satisfies a second condition, wherein the first condition indicates that the first request carries a non-cache identifier, and the second condition indicates that the first cache is unavailable; The electronic device retrieves the first data from the first memory based on the first request, wherein the first memory is the downstream storage space of the first cache.
2. The method according to claim 1, characterized in that, The electronic device includes a memory authentication unit, wherein the memory authentication unit stores a correspondence between different addresses and different address attributes, and the address attributes include cacheable attributes, non-cacheable attributes, and peripheral memory attributes. The electronic device determines in the target phase that the first request satisfies the first condition, including: The electronic device determines the first address of the first request, and obtains the first address attribute corresponding to the first address from the memory authentication unit based on the first address; When the first address attribute is a non-cacheable attribute or a peripheral memory attribute, the first request carries a non-cacheable identifier.
3. The method according to claim 1, characterized in that, The electronic device determines in the target phase that the first cache satisfies the second condition, including: The first cache becomes unavailable when the electronic device determines that the first cache is in a locked state, a maintenance state, or a warning state.
4. The method according to any one of claims 1 to 3, characterized in that, The electronic device includes a prefetch unit, the target stage includes a first stage, the first request includes an instruction fetch request, the first cache includes an instruction cache unit, and the first data includes instruction data, wherein... The electronic device receives a first request during the target stage of the first production line operation, including: The electronic device receives the instruction acquisition request in the first stage through the prefetch unit, wherein the instruction acquisition request is used to instruct the acquisition of instruction data from the instruction cache unit; The electronic device determines, at the target stage, that the first request satisfies a first condition, and / or determines, at the target stage, that the first cache satisfies a second condition, including: The electronic device determines in the first stage, through the prefetching unit, that the instruction retrieval request satisfies the first condition, and / or the electronic device determines in the first stage, through the prefetching unit, that the instruction cache unit satisfies the second condition.
5. The method according to claim 4, characterized in that, The electronic device includes a first address bus, wherein, The electronic device retrieves the first data from the first memory based on the first request, including: In the first stage, the electronic device sends the instruction fetch request to the first memory based on the first address bus through the prefetch unit. The electronic device receives the instruction data returned from the first memory based on the first address bus in the second stage of the first pipeline via the prefetch unit.
6. The method according to claim 5, characterized in that, The electronic device includes a data processing unit, wherein, After the electronic device retrieves the first data from the first memory based on the first request, it includes: The electronic device sends the instruction data to the data processing unit through the prefetching unit in the second stage; The electronic device decodes the received instruction data in the third stage of the first pipeline through the data processing unit to obtain a decoding result, wherein the decoding result is used by the data processing unit to generate a data loading request.
7. The method according to any one of claims 1 to 3, characterized in that, The electronic device includes a data processing unit, the target stage includes a fourth stage, the first request includes a data loading request, the first cache includes a data caching unit, and the first data includes operation data, wherein... The electronic device receives a first request during the target stage of the first production line operation, including: The electronic device receives the data loading request in the fourth stage through the data processing unit, wherein the data loading request is used to instruct the acquisition of the operation data from the data caching unit; The electronic device determines, at the target stage, that the first request satisfies a first condition, and / or determines, at the target stage, that the first cache satisfies a second condition, including: The electronic device determines in the fourth stage, through the data processing unit, that the data loading request satisfies the first condition, and / or the electronic device determines in the fourth stage, through the data processing unit, that the data caching unit satisfies the second condition.
8. The method according to claim 7, characterized in that, The electronic device includes a first address bus, wherein, The electronic device retrieves the first data from the first memory based on the first request, including: In the fourth stage, the electronic device sends the data loading request to the first memory based on the first address bus through the data processing unit. The electronic device receives the operation data returned by the first memory based on the first address bus in the fifth stage of the first pipeline via the data processing unit.
9. The method according to claim 7, characterized in that, The electronic device includes an instruction acquisition unit, which is used to acquire instruction data, wherein... Before the electronic device receives the first request during the target stage of the first production line operation, it includes: The electronic device receives instruction data sent by the instruction acquisition unit in the third stage of the first pipeline through the data processing unit, and decodes the instruction data to obtain a decoding result, wherein the decoding result is used by the data processing unit to generate the data loading request.
10. The method according to any one of claims 1 to 3, characterized in that, The method further includes: The electronic device determines that the first request does not meet the first condition, and the first cache does not meet the second condition; The electronic device retrieves the first data from the first cache based on the first request.
11. A computer-readable storage medium, characterized in that, The readable storage medium stores instructions that, when executed on an electronic device, cause the electronic device to perform the method of any one of claims 1 to 10.
12. An electronic device, characterized in that, include: Memory is used to store instructions executed by one or more processors of an electronic device; And a processor, one of the processors of the electronic device, for executing instructions stored in the memory to implement the method of any one of claims 1 to 10.
13. A program product, characterized in that, The program product includes instructions that, when executed on an electronic device, cause the electronic device to perform the method of any one of claims 1 to 10.