Write transmission device and method for CHI bus protocol system and AXI4 equipment

Abstract

According to the writing transmission device and method for the CHI bus protocol system and the AXI4 equipment, main equipment which does not support cache consistency and a CHI bus are interconnected for writing transmission under the condition that design is not modified, the cache consistency and address allocation of the whole system are maintained, the data consistency when the main equipment accesses shared data is ensured, and the reliability of the system is improved. And errors caused by non-updating of the cache or conflicts are avoided. The device receives a write command sent by AXI4 equipment, and converts the write command into various types of write requests of a CHI protocol; comparing the write addresses sent by the AXI4 device with the addresses in the address mapping table one by one, and after the comparison is successful, obtaining a destination identification code corresponding to the cache line; the transmission identification codes are gradually increased in a transmission command by the device, judging whether the transmission identification codes are a main memory or a cache, and determining a command identification code, a cache attribute and a monitoring attribute according to the main memory and the cache; when the total transmission amount is smaller than or equal to 64 bytes, the size in the request command packet is the actual total transmission amount.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, and in particular to a CHI bus protocol system and AXI4 device write transmission device and a working method of the CHI bus protocol system and AXI4 device write transmission device. BACKGROUND

[0002] AXI (Advanced eXtensible Interface) is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 4.0 protocol proposed by ARM, and is an on-chip bus with high performance, high bandwidth and low latency. The address / control and data of the AXI protocol are separate channels, supporting unaligned data transmission, and only the first address is required in burst transmission, with a maximum transmission length of 4KB. The AXI protocol supports separate read / write data channels, supports Outstanding transmission access and out-of-order access. The AXI high-performance bus system mainly consists of a master device, a controlled device and a basic framework.

[0003] AMBA CHI (Coherent Hub Interface) is a bus protocol designed for multi-core processors by ARM, which is used to ensure data consistency between multiple processor cores. CHI can ensure data synchronization in different processor core caches by supporting cache coherence protocols, avoiding data conflicts and errors. CHI bus supports MESI (Modified, Exclusive, Shared, Invalid) cache coherence protocol, point-to-point and broadcast data transmission mode, and coordinates memory and cache access in complex multi-core systems. CHI protocol uses a message passing-based mechanism to support efficient data transmission with low latency and high bandwidth. Its main advantages include efficient data consistency management, optimized memory access path and good scalability, and is widely used in high-performance computing, embedded systems and servers that require multi-processor collaboration.

[0004] With the development of multi-core processors, chip design has become more complex, especially when multiple processor cores share data, how to maintain cache consistency has become a key issue. CHI protocol is born for this purpose, which provides an efficient way to ensure data consistency between processors in a multi-core system. AMBA CHI bus is applied to multi-core processor systems, but the interface of the master device and the slave device in the system that does not support cache coherence is still the AMBA AXI4 bus. Only in the case of modifying the design, the master device that does not support cache coherence can be interconnected with the CHI bus for write transmission. SUMMARY

[0005] To overcome the defects of the prior art, the technical problem to be solved by the present application is to provide a write transmission device of a CHI bus protocol system and an AXI4 device, which can perform write transmission between a master device not supporting cache coherence and CHI bus interconnection without modifying the design, maintain cache coherence and address allocation of the entire system, has good compatibility, conforms to the AXI4 protocol and the CHI protocol, and the device maintains cache coherence in the system, ensures data consistency when the master device accesses shared data, and avoids errors caused by cache not being updated or conflict.

[0006] The technical solution of the present application is that the write transmission device of the CHI bus protocol system and the AXI4 device connects the AXI4 device to the request node of the CHI bus, the central processing unit CPU is connected to the request node of the CHI bus, and the external device and the memory are connected to the completion node of the CHI bus. The write transmission device receives the write command sent by the AXI4 device, converts the write command into various types of write requests of the CHI protocol, and sends the CHI write request to the CHI request node in the form of a command packet. The command packet contains a source identification code, a destination identification code, a transmission identification code, a command identification code, a weight, a transmission size, an address, a cache attribute, and a response attribute. The source identification code is a unique identification code of the device, which has uniqueness in the entire system. The write address sent by the AXI4 device is compared with the addresses in the address mapping table one by one, and when the comparison is successful, the destination identification code corresponding to the cache line is obtained. If the comparison is unsuccessful, it means that there is no such address in the entire system, and the AXI write reply channel replies an error. The transmission identification code is increased one by one in the transmission command. When the device receives the write command sent by the AXI4 device, it obtains whether the AXI write address corresponds to the main memory or the cache from the cache state of the corresponding address in the address mapping table. According to the main memory and the cache, the command identification code, the cache attribute, and the monitoring attribute are determined. The weight and the address are the corresponding weight and address in the write command sent by the AXI4 device. In the AXI protocol, the total amount of transmission data is equal to the size of the transmission data multiplied by the length of the transmission data. When the total amount of transmission is less than or equal to 64 bytes, the size in the request command packet is the actual total amount of transmission. When it is greater than 64 bytes, the total amount of transmission is divided by 64. If there is a remainder, the quotient obtained is added by 1, divided into several commands, and the transmission amount of the last command is the remainder. If there is no remainder, the quotient obtained is divided into several commands, and the transmission amount is 64 bytes.

[0007] The beneficial technical effects of the present application are as follows: 1. The device conforms to the AXI protocol and the CHI protocol. 2. The device has compatibility, and no additional function needs to be added in the existing AXI master device, so that the CHI bus can be adapted; 3. The device can communicate with the master device of the AXI interface without additional CHI bus function; 4. The device adds the distinction between the cache and the main memory in the existing cache state table, and maintains the cache consistency in the multi-core processor system.

[0008] A write transmission method of a CHI bus protocol system and an AXI4 device is also provided, which comprises the following steps: (1) receiving a write command initiated by the AXI4 device, wherein the write command contains a write address, a write data size, a write transmission length, and a write command weight; (2) obtaining the address according to the write command, calculating the transmission amount and the number of transmission commands; (3) judging whether a certain address in the address mapping table is hit, if yes, executing step (4), otherwise executing step (13); (4) obtaining an identification code, a size and a cache state from the address mapping table, and adding 1 to the transmission identification code; (5) judging the highest bit of the cache state, if the cache state is cache, executing step (6); if the cache state is main memory, and the write request command identification code is 29, executing step (7); (6) the write request command identification code is 25, indicating a write request in the monitoring area, the cache attribute is cache, and the monitoring attribute is monitoring, and the cache state in the address mapping table is changed; (7) writing the identification code and various attributes into the destination identification code in the request command packet, and assembling the command packet; (8) sending the write request command packet according to the CHI protocol; (9) receiving a reply; (10) sending write data; (11) judging the splitting enable, if 0, executing step (14); if 1, executing step (12); (12) calculating the address and the transmission size; and jumping to step (4); (13) returning an error value through the AXI write reply channel; (14) transmission is completed. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 FIG. 1 is a CHI bus system architecture diagram of a write transmission device of a CHI bus protocol system and an AXI4 device according to the present application.

[0010] Figure 2 FIG. 2 is a request command packet of a write transmission device of a CHI bus protocol system and an AXI4 device according to the present application.

[0011] Figure 3 is an address mapping table of a write transmission device of a CHI bus protocol system and an AXI4 device according to the application.

[0012] Figure 4 is a flow chart of a write transmission method of a CHI bus protocol system and an AXI4 device according to the application. DETAILED DESCRIPTION

[0013] AXI (Advanced eXtensible Interface) is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 4.0 protocol proposed by ARM, and is an on-chip bus with high performance, high bandwidth and low latency. The address / control and data of the AXI protocol are separate channels, supporting unaligned data transmission, and only the first address is required in burst transmission, with a maximum transmission length of 4KB. The AXI protocol supports separate read / write data channels, supports Outstanding transmission access and out-of-order access. The AXI high-performance bus system mainly consists of a master device, a controlled device and a basic framework.

[0014] AMBA CHI (Coherent Hub Interface) is a bus protocol designed for multi-core processors by ARM, which is used to ensure data consistency between multiple processor cores. CHI can ensure data synchronization in different processor core caches by supporting cache coherence protocols, avoiding data conflicts and errors. CHI bus supports MESI (Modified, Exclusive, Shared, Invalid) cache coherence protocol, point-to-point and broadcast data transmission mode, and coordinates memory and cache access in complex multi-core systems. CHI protocol uses a message passing-based mechanism to support efficient data transmission with low latency and high bandwidth. Its main advantages include efficient data consistency management, optimized memory access path and good scalability, and is widely used in high-performance computing, embedded systems and servers that require multi-processor collaboration.

[0015] In a multi-core processor system, when a master device that does not need to support cache coherence and a CHI bus interconnection are needed, a write transmission device of a CHI bus protocol system and an AXI4 device needs to be added. This device has good compatibility, conforms to the standard AXI4 protocol and CHI protocol, and maintains cache coherence in the system to ensure data consistency when the master device accesses shared data, avoiding errors caused by cache not being updated or conflicts.

[0016] As Figure 1As shown, the CHI bus protocol system is connected with a write transmission device of an AXI4 device, a request node of the AXI4 device to the CHI bus, a request node of a central processing unit CPU connected to the CHI bus, and a completion node of an external device and a memory connected to the CHI bus. The write transmission device receives a write command sent by the AXI4 device, converts the write command into various types of write requests of the CHI protocol, and sends the CHI write requests to the CHI request node in the form of a command packet, which contains a source identification code, a destination identification code, a transmission identification code, a command identification code, a weight, a transmission size, an address, a cache attribute, and a response attribute. The source identification code is a unique identification code of the device, which is unique in the entire system. The write address sent by the AXI4 device is compared with the addresses in the address mapping table one by one, and when the comparison is successful, the destination identification code corresponding to the cache line is obtained. If the comparison is unsuccessful, it indicates that there is no such address in the entire system, and the AXI write reply channel replies an error. The transmission identification code is increased one by one in the transmission command. When the device receives the write command sent by the AXI4 device, the cache state corresponding to the AXI write address is obtained from the address mapping table, and the command identification code, the cache attribute, and the monitoring attribute are determined according to the main memory and the cache. The weight and the address are the corresponding weight and address in the write command sent by the AXI4 device. In the AXI protocol, the total amount of transmission data is equal to the size of the transmission data multiplied by the length of the transmission data. When the total amount of transmission is less than or equal to 64 bytes, the size in the request command packet is the actual total amount of transmission. When it is greater than 64 bytes, the total amount of transmission is divided by 64. If there is a remainder, the quotient obtained is added by 1, and the number of commands is divided. The transmission amount of the last command is the remainder, and the transmission amount of the remaining commands is 64 bytes. If there is no remainder, the quotient obtained is divided into several commands, and the transmission amount of each command is 64 bytes. The cache attribute can be determined according to the cache state in the cache state table.

[0017] The beneficial technical effects of the present application are as follows: 1. The device conforms to the AXI protocol and the CHI protocol. 2. The device has compatibility, and additional functions do not need to be added in the existing AXI master device, so that the CHI bus can be adapted. 3. The device can interconnect and communicate with the AXI interface master device without additional CHI bus functions. 4. The device distinguishes between the cache and the main memory in the existing cache state table, and maintains the cache consistency in the multi-core processor system.

[0018] Preferably, the AXI4 device, the read transmission bridge device, the CPU, the external device, and the memory are two.

[0019] Preferably, the AXI4 device issues a write command containing a write address, a write transfer length, a write transfer mode, and a write command characteristic.

[0020] Preferably, the address mapping table contains an address corresponding to a cache line, an identification code, a size, and a cache state; the identification code represents an identification code corresponding to the address, the size represents the size of the cache in bytes; the cache state is divided into four bits, the lowest bit 0 is a clean bit, 1 indicates that the cache and the main memory data are consistent, 0 indicates that the cache and the main memory are inconsistent; the 1 bit is a shared bit, 1 indicates that the cache is shared, and the data in the cache may have a copy in other caches, 0 indicates that the cache is unique and has no copy in other caches; the 2 bit is a valid bit, 1 indicates that the cache is valid, and 0 indicates that the cache is invalid; the 3 bit is a cache bit, 1 is a cache, and 0 is a main memory.

[0021] As shown in Figure 4 A write transfer method of a CHI bus protocol system and an AXI4 device is also provided, which comprises the following steps: (1) receiving a write command initiated by the AXI4 device, wherein the write command contains a write address, a write data size, a write transfer length, and a write command weight; (2) obtaining the address according to the write command, calculating the transfer amount and the number of transfer commands; (3) judging whether a certain address in the address mapping table is hit, if yes, executing step (4), otherwise executing step (13); (4) obtaining the identification code, the size, and the cache state from the address mapping table, and adding 1 to the transfer identification code; (5) judging the highest bit of the cache state, if the cache state is cache, executing step (6); if the cache state is main memory, and the write request command identification code is 29, executing step (7); (6) the write request command identification code is 25, indicating a write request to the monitoring area, the cache attribute is cache, and the monitoring attribute is monitoring, and the cache state in the address mapping table is changed; (7) writing the identification code and various attributes into the destination identification code in the request command packet, and assembling the command packet; (8) sending the write request command packet according to the CHI protocol; (9) receiving a reply; (10) sending write data; (11) judging the split enable, if 0, executing step (14); if 1, executing step (12); (12) calculating the address and the transfer size; jumping to step (4); (13) returning an error value through the AXI write reply channel; (14) the transfer is completed.

[0022] Preferably, in the step (2), the write data size in the write command and the write transfer length are multiplied to calculate the total data transfer amount of the write command.

[0023] Preferably, in the step (6), the corresponding cache state in the address mapping table is changed to a unique and dirty, valid cache.

[0024] Preferably, before the step (5), the total data amount of the AXI write command and the size corresponding to the cache line are judged. If the total data amount is greater than the size corresponding to the cache line, it is indicated that the command needs to be split, the split enable is 1, the transfer size is changed to the size corresponding to the cache line, and the transfer data amount is changed to the total data amount minus the size corresponding to the cache line. If the total data amount is less than the cache line, it is indicated that the command does not need to be split, the split enable is 0, and the transfer size is the total data amount.

[0025] The application will be described in more detail below.

[0026] The application is a write transfer device of a CHI bus protocol system and an AXI4 device. The device is connected to the CHI bus at a position as shown in Figure 1 The device receives a write command issued by the AXI4 device, which contains a write address, a write transfer length, a write transfer mode, and a write command characteristic, and converts the write command into different types of write requests of the CHI protocol. The CHI write request is sent to the CHI request node in the form of a package, and the format of the package is as shown in Figure 2As shown, the command packet contains source identification code, destination identification code, transmission identification code, command identification code, weight, transmission size, address, cache attribute, response attribute. The source identification code is the unique identification code of the device, which is unique in the entire system. The AXI4 device sends the write address and the address in the address mapping table one by one, and when the comparison is successful, the corresponding destination identification code of the cache line is obtained. If the comparison is unsuccessful, it means that there is no such address in the entire system, and the AXI write reply channel replies an error. The transmission identification code is increased one by one in the transmission command of the device. When the device receives the write command sent by the AXI4 device, it needs to obtain from the cache state of the corresponding address in the address mapping table whether the AXI write address corresponds to the main memory or the cache, and according to the main memory and the cache, determine the command identification code, the cache attribute and the monitoring attribute. The weight and address are the corresponding weight and address in the write command sent by the AXI4 device. The total amount of data transmitted in the AXI protocol (in bytes) is equal to the size of the transmitted data (in bytes) multiplied by the length of the transmitted data. When the total amount of transmission is less than or equal to 64 bytes, the size in the request command packet is the actual total amount of transmission; When greater than 64 bytes, divide the total amount of transmission by 64, if there is a remainder, add 1 to the quotient, that is, divide into several commands, and the transmission amount of the last command is the remainder, and the rest are all 64 bytes. If there is no remainder, the quotient is obtained, that is, the number of commands, and the transmission amount is 64 bytes. When the AXI command is a command, the cache attribute needs to be determined according to the cache state in the cache state table.

[0027] The address mapping table in the entire system, as shown in Figure 3 As shown, it contains the address corresponding to the cache line, the identification code, the size, and the cache state. The identification code represents the identification code corresponding to the address. The size represents the size of the cache in bytes. The cache state table, as shown in Figure 4 As shown, it is divided into four bits, the lowest bit 0 is the clean bit, 1 indicates that the cache and the main memory data are consistent, and 0 indicates that the cache and the main memory data are inconsistent. Bit 1 is the sharing bit, 1 indicates that the cache is shared, and the data in the cache may have a copy in other caches, and 0 indicates that the cache is unique and has no copy in other caches. Bit 2 is the valid bit, 1 indicates that the cache is valid, and 0 indicates that the cache is invalid. The highest bit 3 is the cache bit, 1 is the cache, and 0 is the main memory.

[0028] The process of converting the write command sent by the AXI4 device into a CHI write request by the device is as follows Figure 4The device receives a write command initiated by an AXI 4 device, which contains a write address, a write data size, a write transmission length, and a write command weight. The write data size and the write transmission length in the write command are multiplied to calculate the total data transmission amount of the write command. According to the write address sent by the AXI 4 device, the address in the address mapping table is traversed and compared. When the address is consistent, it indicates a hit. When there is no consistent address in the entire table, it indicates a miss, indicating that there is no such address in the entire system. An error is returned through the reply signal in the AXI write reply channel, indicating that the write command is incorrect. When the write address hits an address in the address mapping table, the identification code, size, and cache state corresponding to the row are obtained. The identification code is the destination identification code in the CHI write request, and the transmission identification code is incremented by 1. The total data amount of the AXI write command and the size corresponding to the cache row are judged. If the total data amount is greater than the size corresponding to the cache row, it indicates that the command needs to be split, the split enable is 1, and the transmission size is changed to the size corresponding to the cache row. The transmission data amount is changed to the total data amount minus the size corresponding to the cache row. If the total data amount is less than the cache row, it indicates that the command does not need to be split, the split enable is 0, and the transmission size is the total data amount. The highest bit of the cache state is judged. If the cache state is main memory, the write request command identification code is 29, indicating that it is a write request without monitoring. The cache attribute is external storage, and the monitoring attribute is no monitoring. The identification code and various attributes are written into the request command package, and the command package is assembled. If the cache state is cache, the write request command identification code is 25, indicating that it is a write request to the monitoring area. The cache attribute is cache, and the monitoring attribute is monitoring. The identification code and various attributes are written into the command package, and the command package is assembled. When the cache state is cache, the write request with monitoring is sent, and the corresponding cache state in the address mapping table needs to be changed to a unique and dirty cache. The write request command package is sent, and the reply is waited. After receiving the reply, the cache identification code is obtained, and the write data is sent. The split enable is judged. If it is 0, the transmission is completed. If it is 1, the size is converted to the number of bytes, the address and the number of bytes are added to obtain the next address, and the address is compared with the address in the cache state table.

[0029] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made according to the technical essence of the present application to the above embodiment are still within the protection scope of the technical solution of the present application.

Claims

1. A write transfer apparatus for a CHI bus protocol system and an AXI4 device, characterized by: The request node of the AXI4 device is connected to the CHI bus, the request node of the central processing unit (CPU) is connected to the CHI bus, and the completion node of an external device and a memory is connected to the CHI bus; The write transmission device receives a write command sent by the AXI4 device, converts the write command into various types of write requests in the CHI protocol, and sends the CHI write requests to the CHI request node in the form of a command packet, wherein the command packet contains a source identification code, a destination identification code, a transmission identification code, a command identification code, a weight, a transmission size, an address, cache attribute, and response attribute; the source identification code is a unique identification code of the device, and the identification code has uniqueness in the entire system; the write address sent by the AXI4 device is compared with the addresses in the address mapping table one by one, and when the comparison is successful, the destination identification code corresponding to the cache line is obtained; if the comparison is unsuccessful, it indicates that there is no such address in the entire system, and the AXI write reply channel replies an error; The transmission identification code is increased one by one in the transmission command; when the write command sent by the AXI4 device is received, it is determined from the cache state of the corresponding address in the address mapping table whether the AXI write address corresponds to the main memory or the cache, and the command identification code, the cache attribute, and the monitoring attribute are determined according to the main memory and the cache; the weight and the address are the weight and the address corresponding to the write command sent by the AXI4 device; in the AXI protocol, the total amount of transmission data is equal to the size of the transmission data multiplied by the length of the transmission data; when the total amount of transmission is less than or equal to 64 bytes, the size in the request command packet is the actual total amount of transmission; when the total amount of transmission is greater than 64 bytes, the total amount of transmission is divided by 64, and if there is a remainder, the quotient obtained is added by 1, and the transmission amount is divided into several commands; the transmission amount of the last command is the remainder, and the transmission amounts of the remaining commands are all 64 bytes; if there is no remainder, the quotient obtained is divided into several commands, and the transmission amount of each command is 64 bytes.

2. The write transfer apparatus of a CHI bus protocol system and an AXI4 device according to claim 1, characterized in that: The AXI4 device, the read transmission bridge device, the CPU, the external device, and the memory are all two.

3. The write transfer apparatus of a CHI bus protocol system and an AXI4 device according to claim 2, wherein: The write command sent by the AXI4 device contains a write address, a write transmission length, a write transmission mode, and a write command characteristic.

4. The write transfer apparatus of a CHI bus protocol system and an AXI4 device according to claim 3, wherein: The address mapping table contains an address corresponding to a cache line, an identification code, a size, and a cache state; the identification code represents the identification code corresponding to the address, the size represents the size of the cache in bytes, and the cache state is divided into four bits; the lowest bit 0 bit is a clean bit, 1 indicates that the cache and the main memory data are consistent, and 0 indicates that the cache and the main memory data are inconsistent; the 1 bit is a shared bit, 1 indicates that the cache is shared, and the data in the cache may have a copy in other caches, and 0 indicates that the cache is unique and has no copy in other caches; the 2 bit is a valid bit, 1 indicates that the cache is valid, and 0 indicates that the cache is invalid; and the 3 bit is a cache bit, 1 is a cache, and 0 is a main memory.

5. A method of write transfer for a CHI bus protocol system with an AXI4 device, characterized in that: The method comprises the following steps: (1) receiving a write command initiated by an AXI4 device, wherein the write command contains a write address, a write data size, a write transmission length, and a write command weight; (2) obtaining an address according to the write command and calculating a transmission amount and a number of transmission commands; (3) determining whether an address in the address mapping table is hit, and if yes, executing step (4), otherwise executing step (13); (4) Get the identification code, size and cache state from the address mapping table, and add 1 to the transmission identification code; (5) Judge the highest bit of the cache state. If the cache state is cache, execute step (6); if the cache state is main memory, and the write request command identification code is 29, execute step (7); (6) The write request command identification code is 25, indicating a write request to the monitoring area. The cache attribute is cache, and the monitoring attribute is monitoring. Change the cache state in the address mapping table; (7) Write the identification code and various attributes into the destination identification code in the request command packet, and assemble the command packet; (8) Send the write request command packet according to the CHI protocol; (9) Receive the reply; (10) Send the write data; (11) Judge the split enable. If it is 0, execute step (14); if it is 1, execute step (12); (12) Calculate the address and transmission size; jump to step (4); (13) Return the error value through the AXI write reply channel; (14) Transmission is completed.

6. The method of write transfer of a CHI bus protocol system to an AXI4 device according to claim 5, wherein: In step (2), the total data transmission amount of the write command is calculated by multiplying the write data size and the write transmission length.

7. The method of claim 6, wherein the CHI bus protocol system and AXI4 device write transfer method further comprises: In step (6), the corresponding cache state in the address mapping table is changed to a unique and dirty, valid cache.

8. The method of write transfer of a CHI bus protocol system to an AXI4 device according to claim 7, wherein: Before step (5), judge the total data amount of the AXI write command and the size corresponding to the cache line. If the total data amount is greater than the size corresponding to the cache line, it means that the command needs to be split, the split enable is 1, the transmission size is changed to the size corresponding to the cache line, and the transmission data amount is changed to the total data amount minus the size corresponding to the cache line. If the total data amount is less than the cache line, it means that the command does not need to be split, the split enable is 0, and the transmission size is the total data amount.

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