Dynamic frame length serial bus communication method based on state recognition

Abstract

The invention discloses a dynamic frame length serial bus communication method based on state recognition, and belongs to the field of electronic communication. The method comprises the following steps: a host sends an address frame, and a target slave generates a first state signal based on the parity of the address frame for handshake verification; the host retransmits or sends the direction identifier according to the legality of the state signal, and then dynamically triggers data transmission or slave return; the first state signal, the second state signal and the third state signal are triggered and sent by multiplexing parity check bits into physical layer state signals and reversing a clock line, so that parity check, dynamic adjustment of frame length and triggering of bus control right transfer are realized to avoid the situation that an extra arbitration period is completed in the same clock period, and the technical effect is inseparable; according to the method, the limitation of one or combination of the problems that bandwidth is wasted due to the fixed frame length of an existing bus, redundant time sequences are generated in an independent verification period and control right transfer needs extra time sequences is solved, the high refresh rate and the number of multiple slaves can be automatically balanced, and the method is particularly suitable for a multi-node real-time control system.

Description

[0001] Areas involved

[0002] This invention relates to the field of electronic communication technology, and specifically to a self-balancing high refresh rate and multi-slave weighted serial bus communication method, which is a dynamic frame length serial bus communication method based on state recognition. Background Technology

[0003] A serial bus is an electronic communication architecture that transmits data sequentially through a single channel, significantly simplifying physical wiring compared to parallel buses. Serial buses are divided into synchronous and asynchronous buses. Synchronous buses use a clock line (SCL) to drive transmission; devices send and receive data at a uniform pace, relying on clock signals for bit-by-bit synchronization. Asynchronous buses do not share a clock and rely on start / stop bits / handshake signals for self-synchronization. They are further divided into duplex and simplex buses. Duplex buses can transmit signals bidirectionally, while simplex buses can only transmit signals from the master to the slave. The device controlling the bus is called the master, and other devices connected to the bus are called slaves. A bit is the smallest unit of binary bus transmission; one bit represents a 1 or 0. A data frame is the basic unit of network transmission composed of several bits, typically containing a frame header (address / control), a data segment (composed of multiple bits), and a frame trailer (checksum). The transmitted signal can be the target slave address, data (such as the angle of an operating mechanism, sensor data, etc.), or a command (such as commanding the slave to change mode, change the operating rate, etc.). Typical serial bus protocols include RS-232, I... 2 Serial buses include C, SPI, and CAN. A key advantage of serial buses lies in their scalability and flexibility. Modern evolution focuses on high speed and intelligence, emphasizing the importance of low latency, high refresh rates, and a large number of slave devices. Currently, serial buses are widely used in sensor networks, industrial automation, automotive electronics, and consumer electronics, becoming the infrastructure for device interconnection in the Internet of Things (IoT) era.

[0004] However, researchers both domestically and internationally face numerous challenges in practical communication applications. First, traditional serial buses have fixed data frame lengths. If the number of data bits is small, meaningless padding is required, limiting the maximum data bit size and consequently restricting the number of slave devices and signal resolution. Second, bus transmission is susceptible to interference, leading to erroneous received information. Furthermore, simplex serial buses cannot perform bidirectional transmission. Moreover, synchronous buses are mostly edge-triggered, requiring the clock line to be pulled low and then raised again after transmission. The long stabilization time and numerous steps significantly limit the refresh rate and maximum number of slave devices on the serial bus.

[0005] In recent years, with the continuous development of electronic information and embedded systems, various new serial buses have solved these problems to some extent. However, existing buses with variable frame length require pre-setting the number of data bits and multiple timing signals, resulting in significant timing overhead and impacting the bus refresh rate. Existing buses with parity functions require independent parity bits to verify data errors, necessitating additional timing. Existing full-duplex buses require independent signal bits or even data frames to transfer bus control, leading to short frame transmission efficiency below 40%. In summary, these methods still involve considerable redundant timing and do not effectively balance the conflict between high refresh rates and multiple slave devices, thus remaining limited in fields such as multi-slave industrial control and drones. Summary of the Invention

[0006] The purpose of this invention is to propose a serial bus communication method that uses only two lines, signal and clock, to transmit signals; it completes parity checking, dynamic frame length adjustment, and trigger bus control transfer in the same clock cycle to reduce timing by more than 30%; it dynamically adjusts the frame length to meet the slave number requirements while shortening the data frame bit width to improve the refresh rate; and it uses an inverted level trigger signal for transmission, reducing level conversion steps and time by 50% compared to traditional bus protocols to improve the transmission refresh rate.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] Step 1: After the master sends an address frame containing the slave address via the clock line (SCL) and signal line (SDA), it releases control of the clock and signal lines.

[0009] Step 2: After the target slave detects that there is no change in the state of the clock line within a preset time, it takes over the bus control and sends a first status signal. The value of this signal is determined by the parity of the number of 0s or 1s in the address frame.

[0010] Step 3: After the host receives the first status signal: if the status signal does not meet expectations, the address frame is retransmitted; if the status signal meets expectations, the transmission direction identification signal is sent.

[0011] Step 4: When the transmission direction identification signal indicates that the host needs to transmit: the host sends a signal type identification signal, the value of which is 1 or 0 to indicate that the following signal is data or command; the host sends data or command, and then releases control of the clock and signal lines; after the target slave detects that there is no change in the state of the clock line within a preset time, it takes over the bus control, sends the second status signal and sends the return data;

[0012] Step 5: When the transmission direction indicator signal indicates that the host does not need to transmit a signal, the target slave directly sends back the data;

[0013] Step 6: After all data transmission is completed, the slave device takes over the bus control after detecting that there is no change in the clock line state within a preset time and sends a third status signal. The value of this signal is determined by the parity of the number of 0s or 1s in the data frame.

[0014] Furthermore, the first, second, and third state signals are synchronously completed within the same time period through the same operation to realize data verification and physical end of the current frame, characterized in that: (a) their values ​​are generated based on the parity calculation result of the number of 0 or 1 in the corresponding transmission signal, and are used to verify the data; (b) by sending the verification value, it serves as the unique identifier signal for the end of the current data frame;

[0015] Furthermore, the first, second, and third status signals trigger the transfer of bus control to the receiver, characterized in that: the triggering process for the transfer of bus control is that after the receiver detects that no signal is emitted within a preset time, it takes over the bus, completes the transfer of control, and sends a status signal;

[0016] Furthermore, the first, second, and third state signals are characterized in that: the first, second, and third state signals are parity check values, and the transmission of the check value terminates the current frame and triggers the handover of control, and the check, the frame end identifier, and the handover of control are completed within the same time period;

[0017] Furthermore, the method of transmitting signals via clock lines and signal lines is characterized in that: both the clock and signal lines are controlled by the host or slave device currently transmitting the signal; the signal line is set to a high or low level corresponding to the 1 or 0 to be transmitted, the clock line level is reversed, and the host or slave device receiving the signal records the level state on the received signal after detecting the change in the clock line level;

[0018] Furthermore, the command identification signal described in S4 is characterized in that a single bit in the data frame represents the subsequent bits of the signal as either a command or data;

[0019] A further technical solution is that the present invention includes the following modules: a status signal generator, which generates status signals according to predefined encoding rules; a dynamic data controller, which parses control information in the address frame; and a bidirectional data transceiver module, which supports half-duplex communication mode.

[0020] The beneficial effects of this invention are as follows: The clock and signal lines of this invention are both controlled by the master or slave device currently transmitting the signal; and the clock line inversion level triggering of the signal transmission reduces level transition steps and time, thus improving the transmission refresh rate; this invention multiplexes the parity bit as a physical layer status signal, achieving parity checking, dynamic frame length adjustment, and bus control handover in the same time sequence, solving the problems of excessively long useless bits in the data frame and limited maximum data bits, increasing the effective data ratio to 75% (see [link]). Figure 3(In comparison) this results in a refresh rate increase of over 30%. The frame length (related to the number of available slave addresses and data resolution) has been increased from a fixed eight-bit binary length to an unlimited length; Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0022] Figure 1 This is a schematic diagram of the communication timing of the present invention;

[0023] Figure 2 This is a hardware structure block diagram of a bus communication device according to an embodiment of the present invention;

[0024] Figure 3 This is a comparison diagram of the dynamic frame length of this invention and traditional protocols. It shows: 1. The fixed frame header, invalid padding, and dedicated frame tail structure of the traditional protocol; 2. The integrated transmission of effective data and status signals in this invention; 3. Labels. Indicates zero-filling-overhead innovation area

[0025] Figure 4 This is the communication flowchart of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0027] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0028] One embodiment of the present invention is used for real-time high refresh rate bidirectional communication among multiple slave devices in an unmanned aerial vehicle (UAV) system. The communication process in this embodiment includes the following steps:

[0029] S101: Address Frame Transmission and Release

[0030] The host sends an 8-bit address frame 0xD2 (binary 11010010).

[0031] Set SCL / SDA to high impedance state to release the bus

[0032] S102: Slave Response and Status Signals

[0033] After the target servo detects the SCL level and remains stationary for >2μs:

[0034] Take over bus control

[0035] Calculate the parity of the address frame (number of 1s = 5 → odd parity).

[0036] Send the first status signal SS1=1

[0037] Release bus

[0038] S103 Data Transmission and Session Termination

[0039] The first state signal is verified to be correct (ss1 = 1).

[0040] S104: Host transmits direction identifier DIR = 1 (host transmits) → Type identifier CMD = 0 (data) → Transmits action mechanism action angle 0x01

[0041] Servo response: Send second status signal SS2=1 (data frame odd parity) → transmit sensor-acquired data 0xAA back

[0042] S105: DIE = 0 is not true, so skip this step.

[0043] S106: The host sends the third status signal SS3=1 to terminate the session.

[0044] The system hardware configuration in this embodiment is as follows:

[0045] Main controller: STM32H743VIT6 microcontroller (ARM Cortex-M7 core, 480MHz)

[0046] Slave devices: 48 self-made digital servos supporting this protocol, with the main controller using an STM32H743VIT6 microcontroller (supporting dynamic bus address allocation).

[0047] Clock line (SCL): Open-drain output mode, line length ≤ 1.5m, terminated with a 100Ω matching resistor.

[0048] Signal line (SDA): Push-pull output mode, inter-line capacitance ≤100pF

[0049] The implementation details of the innovative triple reuse technology for state signals in this embodiment are as follows:

[0050] Verification of object frame end action handover trigger direction

[0051] SS1 Address Frame Termination Address Frame Master → Slave

[0052] SS2 Data Frame Termination Command Frame Slave → Master

[0053] SS3 data return termination session system reset

[0054] Among them, such as Figure 1 The dynamic frame length is implemented as follows:

[0055] After transmitting data of any length, the receiver sends an SS signal to terminate the current frame.

[0056] Among them, such as Figure 1 The level inversion trigger operation shown is as follows:

[0057] Sending end operations:

[0058] assembly

[0059] MOV R0,[DATA_BUF]; Load data

[0060] STR R0,SDA_CTRL; Sets the SDA level.

[0061] XOR[SCL_CTRL], 0x01; Inverts the SCL level.

[0062] Receiver operation: SCL edge triggered interrupt sampling SDA

[0063] like Figure 1 As shown, the communication timing of the present invention includes the following key parts:

[0064] 1. Host transmission phase:

[0065] ① The host sends address frame 0xD2 (binary 11010010)

[0066] ○② Transmission direction identifier DIR = 1 (indicating host is sending)

[0067] ○③ Signal type identifier CMD=0 (indicates command type)

[0068] ○④ Data 0x01 (Motion Angle Data)

[0069] 2. Slave Response Phase:

[0070] ○⑤ First state signal SS1 = 1 (address frame verification result)

[0071] ○⑥ Second state signal SS2 = 1 (data frame verification result)

[0072] ○⑦ Data returned: 0xAA (sensor detection value)

[0073] 3. Innovation points highlighted:

[0074] SS region: Status signal synchronization implementation:

[0075] ■ Data Validation (Based on Parity)

[0076] ■ End-of-frame marker (physically terminates the current frame to adjust frame length)

[0077] ■SCL idle timeout detection triggers control transfer

[0078] Clock line (SCL) triggering: Uses an inverted triggering method to avoid level settling time and reset timing (i.e., after a high-level trigger, it must be switched to a low level before it can be triggered again).

[0079] 4. Control transfer process:

[0080] ○ The host releases the bus after sending the address frame (feature 1).

[0081] ○ The slave device takes over the bus after the detection timeout (feature 3).

[0082] ○ Release the bus after sending the status signal (feature 1)

[0083] like Figure 2 As shown, the hardware structure of the device in this embodiment includes four core modules:

[0084] ① Bus ​​status detection module

[0085] Chip: LMV7219 high-speed comparator

[0086] Function: Real-time monitoring of SCL level duration

[0087] Technical specifications: Response time ≤ 0.05μs

[0088] 2. State signal generator

[0089] Chip: 74HC280 9-bit parity checker

[0090] Functions: Calculates the parity of the transmitted signal and generates status signals for the integrated check bit / handover flag.

[0091] 3. Dynamic Data Controller

[0092] Implementation method: FPGA state machine (Xilinx Artix-7)

[0093] Functions: Parse signal type identifiers in address frames and dynamically adjust data frame length.

[0094] 4. Two-way data transceiver module

[0095] Chip: SN65HVD72 RS-485 transceiver

[0096] Function: Supports 10Mbps half-duplex communication

[0097] Drive capability: ±60mA output current

[0098] Module connection relationship: The SCL / SDA bus signal is first input to the bus status detection module (①), and after processing, it outputs a timeout signal to the status signal generator (②); the verification value output by the status signal generator is transmitted to the dynamic data controller (③) for protocol parsing; finally, the bidirectional data transceiver module (④) drives the actuator / sensor to complete the half-duplex communication closed loop.

[0099] like Figure 3 As shown, the dynamic frame length comparison chart includes:

[0100] Left half (traditional protocol): ① Fixed frame header (3 bytes), containing address and control fields; ② Invalid padding data (5 bytes), used to make up the fixed frame length; ③ Dedicated frame trailer (2 bytes), independently identifying the end of the frame. When transmitting short data or command frames, the effective data ratio is only 30%, and the data frame length is limited to eight bits. Right half (this invention): ④ Effective data (3 bytes), without any padding; ⑤ Status signal SS (1 byte), multiplexed as checksum, frame end identifier, and control handover trigger signal. The effective data ratio is increased to over 75%, and the data frame length is no longer limited.

[0101] Label Highlighting the "zero padding overhead" characteristic (corresponding to claim 2b), the frame is terminated via state signal ⑤.

[0102] Avoid the redundant overhead of ② and ③ in traditional protocols.

[0103] The implementation effect of this embodiment:

[0104] Refresh rate: 1.76kHz (1kHz for traditional PWM protocol)

[0105] Number of nodes: 256 (128 for traditional CAN bus)

[0106] Communication latency: ≤5μs (meets ASIL-D safety level)

[0107] Voltage monitoring accuracy: ±0.5mV (16-bit ADC full range)

[0108] Synchronization error of the actuation mechanism: ±0.05° (conventional solution ±0.2°)

[0109] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be within the scope of protection of the present invention.

Claims

1. A dynamic frame length serial bus communication method based on state recognition, characterized by, The method comprises the following steps: S1. The host releases the control of the clock line and the signal line (i.e. the control of the bus) after sending an address frame containing the address of the slave through the clock line and the signal line; S2. The target slave takes over the control of the bus and sends a first status signal after detecting that the clock line has no state change within a preset time, the value of the signal being determined by the parity of the number of 0s or 1s in the address frame; then the target slave releases the control of the clock line and the signal line S3. The host receives the first status signal and then: a) if the status signal is not as expected, sends an error signal and re-sends the address frame; b) if the status signal is as expected, sends a transmission direction identification signal; S4. When the transmission direction identification signal indicates that the host needs to transmit signals to the slave: a) the host sends a signal type identification signal, the value of which is 1 or 0 to indicate that the following signal is data or a command; the host sends data or a command, and then releases the control; c) the target slave takes over the control of the signal line and the clock line, sends a second status signal and sends back the return data, and then releases the control of the signal line and the clock line; S5. When the transmission direction identification signal indicates that the host does not need to transmit signals to the slave, the target slave directly takes over the control of the signal line and the clock line and sends back the return data, and then releases the control of the signal line and the clock line; S6. After all the data transmission is completed, the host takes over the control of the signal line and the clock line after detecting that the clock line has no state change within a preset time, and sends a third status signal.

2. The method according to claim 1, wherein: the first, second and third status signals are synchronously completed in the same timing cycle through the same operation to realize data checking and the physical end of the current frame: (a) the value of which is generated based on the parity of the number of 0s or 1s in the corresponding transmission signal to check the data; (b) the host or the slave receiving the data frame sends the check value, which is the only identification signal of the host or the slave physically ending the current data frame after receiving the signal.

3. The method according to claim 1, wherein: the first, second and third status signals trigger the transfer of the control of the bus to the receiver; wherein the trigger process of the transfer of the control of the bus is that the receiver takes over the bus and sends a status signal after detecting that no signal is sent on the two lines within a preset time, and the transfer of the control is completed.

4. The method according to claim 1 or 2 or 3, wherein: the first, second and third status signals are parity check values, and the sending of the check value ends the current frame and triggers the transfer of the control, so that the checking, the identification of the end of the frame and the transfer of the control are completed in the same timing cycle.

5. The method according to claim 1, wherein: both the clock line and the signal line are controlled by the host or the slave currently sending signals; the signal line is set to the level state corresponding to 1 or 0 to be sent, the level of the clock line is reversed, and the host or the slave receiving the signal detects the change of the level of the clock line and records the 1 or 0 corresponding to the level state of the signal line.

6. The method of claim 1, wherein: S4 the command identification signal is represented by a single bit in the data frame, and the following bits are signals for command or data.

7. A bus communication device for implementing the method of any one of claims 1 to 6, characterized by Comprise: a bus state detection module for judging the driving state of the clock line; a state signal generator for generating a state signal according to a predefined encoding rule; a dynamic data controller for parsing control information in the address frame; a bidirectional data transceiver module supporting a half-duplex communication mode.

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