Multi-mode coupled NAND memory chip test system

Abstract

The invention relates to the technical field of memory chip testing, in particular to a multi-mode coupled NAND memory chip testing system which comprises a busy signal acquisition module, a mode switching control module, a residence time judgment module, an abnormal fragment filing module and a fragment label management module. According to the method, the state is accurately captured through the combination of the statistics of the signal duty ratio and the time index, the time sequence parameters are recorded at the moment that the level is converted from high to low, and the mode switching mark is formed, so that the time sequence under different test modes is completely tracked, the potential abnormal interval is identified through the accumulation of the high-level residence time, and the accuracy of the detection result is improved. In the archiving stage, the time interval and the mode identifier are associated and subjected to time sequence tolerance separation, so that abnormal segments are continuously and independently archived and attached with traceable time labels, potential abnormal behaviors are recognized and recorded in time, the capacity of capturing performance fluctuation and time sequence abnormity of the NAND chip in a complex mode is improved, and the reliability of the NAND chip is improved. And the integrity and traceability of the test data are enhanced.

Description

Technical Field

[0001] This invention relates to the field of memory chip testing technology, and in particular to a multi-mode coupled NAND memory chip testing system. Background Technology

[0002] The field of memory chip testing technology involves performance and functional testing of various semiconductor memory devices, including testing of memory chips in terms of read / write speed, data retention, endurance, and interface protocols. It covers testing methods, test circuit design, and interface control methods for different types of memory chips such as NAND flash memory, NOR flash memory, and DRAM devices. Specifically, a NAND flash memory chip testing system refers to a system for functional and performance testing of NAND flash memory chips. It measures and verifies key characteristics of NAND chips such as data read / write, voltage response, erase / write cycles, and interface timing. Typically, this is achieved by configuring chip sockets on a test substrate and using external power and clock signals to drive the chip, while simultaneously using signal acquisition circuits and memory control circuits to perform step-by-step testing of the chip.

[0003] In current NAND flash memory chip testing, chip response is mainly obtained through baseboard signal driving and external acquisition methods. Data recording is mostly continuous sampling of the entire process, lacking fine decomposition of transient level changes. This makes it difficult to capture potential timing anomalies in a timely manner in multi-mode or rapid switching scenarios. Long-term high-level dwell time is easily overlooked. Data archiving only provides overall waveform or continuous test results, and cannot accurately locate and identify segments in different modes. When dealing with complex timing fluctuations or potential failure scenarios, it is easy to cause missed detections or difficulty in tracing. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a multi-mode coupled NAND memory chip testing system.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a multi-mode coupled NAND memory chip testing system comprising: The busy signal acquisition module acquires the standard busy signal level status output during the NAND memory chip test process, records the level status and time index of each sampling period, compares the difference between the level status of adjacent sampling points, statistically analyzes the signal duty cycle change trend, and generates a busy signal status sequence. Based on the busy signal state sequence, the mode switching control module detects the moment when the level of adjacent sampling points changes from high to low, combines the current test mode identifier and the time index of the corresponding sampling point, records the corresponding timing parameters to form a mode switching mark, and generates a mode switching record. The dwell time determination module accumulates the number of continuous dwell time sampling cycles of the busy signal high level according to the mode switching record. When the accumulated value exceeds the self-refresh timeout threshold, the corresponding time period is determined as a potential abnormal interval, and a corresponding time index interval is formed to generate a potential abnormal interval record. The abnormal fragment archiving module extracts test data fragments within the corresponding time interval based on the potential abnormal interval records, associates and stores the time index interval with the corresponding mode identifier, performs AC time-series tolerance window separation judgment on the archived fragments, forms continuous independent fragment records, and generates an abnormal fragment archiving sequence.

[0006] As a further embodiment of the present invention, the busy signal state sequence includes a level change trend record, a time index sequence, and a duty cycle statistical result; the mode switching record specifically includes a mode identifier mapping table, a mode switching time index, and a mode switching delay parameter; the potential abnormal interval record includes a time interval index, a timeout mark, and a dwell period count result; and the abnormal segment archive sequence includes a time interval association table, a mode identifier corresponding segment, and a timing tolerance determination result.

[0007] As a further aspect of the present invention, the busy signal acquisition module includes: The busy signal recording submodule acquires the RBn level status output during the NAND memory chip test, records the level status according to the sampling period and marks the time index, and continuously records to form a discrete level sequence, thus obtaining the discrete level sequence. The duty cycle comparison submodule compares the difference between the level states of adjacent sampling points based on the discrete level sequence, and sorts them together with the duration of high and low levels in each sampling period to obtain a record of the duty cycle change trend. The state sequence generation submodule records the duty cycle change trend, sorts and integrates the duty cycle change trend with the discrete level sequence within a continuous period, statistically analyzes the continuous change characteristics of the period, and generates a busy signal state sequence.

[0008] As a further aspect of the present invention, the mode switching control module includes: The level transition detection submodule reads the level status of adjacent sampling points based on the busy signal state sequence, identifies the transition position where the level of the previous sampling point is 1 and the level of the next sampling point is 0, extracts the time index and transition position index of the corresponding transition time, and marks them in combination with the sampling segment number where the transition occurs to obtain the falling edge trigger index. The mode identifier replacement submodule, based on the falling edge trigger index, compares the current test mode identifier and sampling time index corresponding to each switching position, makes judgments and number adjustments according to the mode switching rules, replaces the original test mode identifier at the sampling point that meets the switching conditions, writes the replacement result into the mode register configuration space, and calculates and obtains the mode switching position quantity. The switching information recording submodule extracts the index position and time index of the completed mode replacement based on the mode switching position quantity, records the time interval between the time point written to the mode register and the original conversion point as the delay time, and combines the replaced mode identifier and the new mode identifier to form a switching entry, which is uniformly recorded in the switching information buffer to establish a mode switching record.

[0009] As a further aspect of the present invention, the dwell time determination module includes: The high-level detection submodule obtains the busy signal state value sequence corresponding to each index based on the time series data of each trigger index point in the mode switching record, divides it into sampling period units, and judges whether the proportion of high-level states in a single period sampling point reaches the total number of sampling points. It then filters out the complete sampling period segment where the continuous high-level states are established and outputs the high-level sampling period interval. The continuous period statistics submodule arranges each continuous segment according to the high-level sampling period interval and in time sequence, extracts the time index difference between the start and end sampling points of adjacent segments, calculates and obtains the continuous dwell period offset value, and marks it as an overtime period when the offset value exceeds the minimum self-refresh period threshold, generating potential abnormal dwell amount data. The abnormal interval judgment submodule combines and pairs the start and end points of the time index based on the potential abnormal dwell volume data, removes records that do not meet the condition that the time interval is greater than the minimum refresh cycle, forms a valid time period segment sequence with a duration greater than the minimum self-refresh cycle threshold, and integrates the corresponding pattern identifier segments to generate potential abnormal interval records.

[0010] As a further aspect of the present invention, the abnormal fragment archiving module includes: The time segment extraction submodule extracts test data segments within the corresponding time range based on each time index interval in the potential anomaly interval record. It performs matching operations on all timestamped data in the test data sequence, checks and removes data segments with missing records or discontinuous segments during the sampling process, filters out test data segment sequences with complete structure and continuous time sequence, and arranges them in chronological order to obtain the time synchronization sampling segment. The pattern association storage submodule processes each data segment in the time synchronization sampling segment with the pattern identifier in the corresponding potential anomaly interval record, binds the time segment with its corresponding operating mode number, establishes a segment sequence number for each group of segments, and summarizes them according to the pattern identifier to obtain a list of pattern archived segments. The tolerance separation judgment submodule performs boundary range determination and interval attribution determination operations on each sampled segment recorded in the mode archive segment list according to the standard AC time series tolerance range. It performs anomaly marking processing on segments that are not within the tolerance range, re-numbers and archives the abnormal segments, and obtains the abnormal segment archive sequence.

[0011] As a further aspect of the present invention, the system further includes: The fragment tagging management module adds a test mode ID and timestamp tag to each abnormal fragment according to the abnormal fragment archive sequence, and organizes the tagged records into a traceable sequence to form multi-mode coupled NAND memory chip test data. The test data for the multi-mode coupled NAND memory chip includes abnormal fragment tags, test mode IDs, and nanosecond-level timestamps.

[0012] As a further aspect of the present invention, the fragment tag management module includes: The pattern tag marking submodule extracts the established archive number and fragment index position based on the attribution information of each fragment in the abnormal fragment archive sequence, performs a corresponding relationship matching operation on each fragment data, generates a pattern tag in a unified format, and obtains a pattern tag fragment set. The timestamp tag generation submodule reads the corresponding start sampling time and end sampling time according to the start index and end index of each segment in the pattern tag segment set, uniformly formats the timestamp tag and embeds it into the segment structure, and after inserting timestamp tags into all segments, summarizes the data segments and establishes a timestamp-labeled segment table. The sequence integration and output submodule reorders all marked abnormal fragment data in ascending order of timestamp based on the structured data records in the timestamp-marked fragment table, constructs a triplet sequence of start and end time, mode number, and data number, and exports it as structured output data to generate test data for multi-mode coupled NAND memory chips.

[0013] Compared with the prior art, the advantages and positive effects of the present invention are as follows: In this invention, the busy signal level is discretely sampled during testing to form a level change trend. The state is accurately captured by combining the statistics of the signal duty cycle with the time index. Timing parameters are recorded at the moment the level changes from high to low, and a mode switching mark is formed, so that the time series under different test modes can be completely tracked. Potential abnormal intervals are identified by accumulating the high level dwell time. In the archiving stage, the time interval is associated with the mode identifier and the timing tolerance is separated, so that abnormal segments are continuously and independently archived with traceable time tags. This enables timely identification and recording of potential abnormal behavior, improves the ability to capture NAND chip performance fluctuations and timing anomalies under complex modes, and enhances the integrity and traceability of test data. Attached Figure Description

[0014] Figure 1 This is a system flowchart of the present invention; Figure 2 This is a flowchart of the busy signal acquisition module of the present invention; Figure 3 This is a flowchart of the mode switching control module of the present invention; Figure 4 This is a flowchart of the dwell time determination module of the present invention; Figure 5 This is a flowchart of the abnormal fragment archiving module of the present invention; Figure 6 This is a flowchart of the fragment tag management module of the present invention. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0016] In the description of this invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, in the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0017] Please see Figure 1 A multi-mode coupled NAND memory chip testing system includes: The busy signal acquisition module acquires the standard busy signal (RBn) level status output during the NAND memory chip test. It records the level status and time index in each sampling period, continuously records to form a discrete level sequence, compares the difference between the level status of adjacent sampling points, statistically analyzes the signal duty cycle change trend of the busy signal, and generates a busy signal status sequence. The mode switching control module detects the moment when the level of adjacent sampling points changes from high to low based on the busy signal state sequence. Combining the current test mode identifier and the time index of the corresponding sampling point, it replaces the mode identifier with the next test mode and writes it into the mode register configuration space (following the standard mode register operation protocol). At the same time, it records the corresponding timing parameters (mode switching delay time) to form a mode switching mark and generates a mode switching record. The dwell time determination module accumulates the number of sampling cycles for the continuous high-level dwell of the busy signal based on the mode switching record. The accumulated value is compared with the self-refresh timeout threshold (the minimum self-refresh cycle specified by the standard, typically 160ns). When the accumulated value exceeds the self-refresh timeout threshold, the corresponding time period is determined as a potential abnormal interval, and a corresponding time index interval is formed, generating a potential abnormal interval record. The abnormal segment archiving module extracts test data segments within the corresponding time interval based on potential abnormal interval records, associates the time index interval with the corresponding pattern identifier for storage, performs AC time tolerance window (set according to standard ±5% time margin) separation judgment on the archived segments, forms continuous independent segment records, and generates an abnormal segment archiving sequence. The fragment tagging management module adds a test mode ID and a timestamp tag (nanosecond-level time stamp conforming to the test interface standard) to each abnormal fragment according to the abnormal fragment archive sequence, and organizes the tagged records into a traceable sequence to form multi-mode coupled NAND memory chip test data.

[0018] The busy signal status sequence includes a level change trend record, a time index sequence, and duty cycle statistics. The mode switching record specifically includes a mode identifier mapping table, a mode switching time index, and a mode switching delay parameter. The potential abnormal interval record includes a time interval index, a timeout mark, and a dwell period count result. The abnormal segment archive sequence includes a time interval association table, a segment corresponding to the mode identifier, and a timing tolerance judgment result. The multi-mode coupled NAND memory chip test data includes abnormal segment tags, test mode IDs, and nanosecond-level timestamps.

[0019] Please see Figure 2 The busy signal acquisition module includes: The busy signal recording submodule acquires the RBn level status output during the NAND memory chip test, records the level status according to the sampling period and marks the time index, and continuously records to form a discrete level sequence, thus obtaining the discrete level sequence. During NAND flash memory chip testing, it is necessary to first acquire the output RBn level status signal and record its changes at different sampling periods. This process is achieved by setting a sampling period of 1 microsecond on the sampling device. Assuming the test object is a 16Gb NAND chip, the number of level points acquired in one test cycle is 10. Each sampling point records the current level status as 0 or 1, and marks the time index. For example, the time of the first sampling point is 0μs, the time of the second sampling point is 1μs, and so on up to the time of the 10th sampling point. The sampling period is 9 μs. During the recording process, the level state of each sampling point is directly read by the logic analyzer. For example, the level sequence obtained in one sampling period is [1, 1, 0, 0, 1, 1, 1, 0, 0, 1], which forms a discrete level sequence array with time labeling {(0, 1), (1, 1), (2, 0), (3, 0), (4, 1), (5, 1), (6, 1), (7, 0), (8, 0), (9, 1)}. These records form the basic dataset for subsequent analysis and processing, and after processing, the discrete level sequence is obtained.

[0020] The duty cycle comparison submodule is based on a discrete level sequence. It compares the difference between the level states of adjacent sampling points and combines the duration of high and low levels in each sampling period to obtain a record of the duty cycle change trend. After obtaining the discrete level sequence, it is necessary to compare the differences in the level states of adjacent sampling points to identify the duration of each level segment and further organize the duty cycle change trend within each sampling period. For example, in the aforementioned level sequence, the level difference between adjacent sampling points is [0, 1, 0, 1, 0, 0, 1, 0, 1]. By statistically analyzing the position of each level change, the duration of the high level can be determined as 0-1μs, 4-6μs, and 9μs (single point), and the duration of the low level is 2-3μs and 7-8μs. The proportions of high and low levels are calculated respectively. The proportion of high level time is (2+3+1) / 10=0.6, and the proportion of low level time is 0.4. By organizing the proportion array within consecutive periods, the duty cycle change trend curve can be formed. To further illustrate with an example, if the proportions of high level in the subsequent three sampling periods are 0.6, 0.7, and 0.5 respectively, it can be described as the high level first increasing and then decreasing, forming a complete change trend. After summarizing the organized results, the duty cycle change trend record is obtained.

[0021] The state sequence generation submodule records the duty cycle change trend, sorts and integrates the duty cycle change trend with the discrete level sequence within the continuous period and correlates them with time, statistically analyzes the continuous change characteristics of the period, and generates a busy signal state sequence. After obtaining the duty cycle change trend record, the continuous periodic duty cycle change is time-aligned and sequentially integrated with the discrete level sequence. For example, the duty cycle of period 1 (0.6) corresponds to time index 0-9μs, the duty cycle of period 2 (0.7) corresponds to time index 10-19μs, and the duty cycle of period 3 (0.5) corresponds to time index 20-29μs. This integration method forms a continuous trend time axis. The sequence data generated by combining the discrete level sequence can be written as {(0,1), (1,1)...(29,0)}. The duty cycle identifier array {0.6, 0.7, 0.5} is inserted after every 10 sampling points to finally form a complete state identifier sequence. Through this process, the serialization and mapping between different periods are completed to obtain the busy signal state sequence.

[0022] Table 1 Busy Signal Acquisition and Duty Cycle Statistics As shown in Table 1, by statistically analyzing the time, level state, and cumulative high and low level time of each sampling point, the gradual accumulation of the high level ratio can be clearly seen. The duty cycle of the last sampling point is 0.6, which is directly used to construct the duty cycle change trend of continuous periods.

[0023] Please see Figure 3 The mode switching control module includes: The level transition detection submodule reads the level status of adjacent sampling points based on the busy signal state sequence, identifies the transition position where the level of the previous sampling point is 1 and the level of the next sampling point is 0, extracts the time index and transition position index of the corresponding transition time, and marks them in combination with the sampling segment number where the transition occurs to obtain the falling edge trigger index. After obtaining the busy signal state sequence in the NAND test structure, it is necessary to determine whether a transition from 1 to 0 has occurred based on the level state value between every two adjacent sampling points in the sequence. First, the complete set of sampling points is extracted. For example, if the sampling points are numbered 0 to 9 in a certain test cycle, the corresponding level values ​​are [1, 1, 0, 1, 0, 0, 1, 1, 0, 0]. According to the rules, the positions where the previous sampling point is high level 1 and the next sampling point is low level 0 can be determined. The three transition points 1 to 2, 3 to 4, and 7 to 8 can be identified, which occur at 2μs, 4μs, and 8μs respectively, corresponding to sampling point indices 2, 4, and 8. To improve the accuracy of error judgment, it is also necessary to further determine the duration of the level state before the transition, which stipulates that only when the previous state is not less than 1μs can the transition be determined. A falling edge is considered valid only if the time is 2μs. For example, in the above level sequence, the interval between the first and second segments is [1, 1], and the interval before the third and fourth segments is [0, 1]. These segments do not meet the condition and are discarded. Only the segments between the first and second segments and the segments between the seventh and eighth segments are retained. The sampling point indices are 2 and 8, and the transition times are 2μs and 8μs, respectively. Then, the test mode identifier and sampling period segment number of each sampling segment are combined to identify and label them. For example, if the period segment corresponding to 2μs is "Segment A" and the mode identifier is "Mode A", then the structure identifier "Segment A-Mode A-2" is formed. Finally, the above valid transition events are numbered to form a trigger index sequence for subsequent module processing. Each item in this sequence contains the sampling point index, transition time, and mode identifier, and finally, the falling edge trigger index is obtained.

[0024] Table 2. Busy Signal Conversion Recognition and Trigger Index Structure Table As shown in Table 2, by identifying the level state of each sampling point and the state before conversion, and by judging the length of the segment before conversion, data that does not meet the triggering conditions can be eliminated, and only the valid falling edge can be retained and marked.

[0025] The mode identifier replacement submodule, based on the falling edge trigger index, compares the current test mode identifier and sampling time index at each transition position, judges and adjusts the numbering according to the mode switching rules, and replaces the original test mode identifier at the sampling point that meets the switching conditions. The replacement result is then written to the mode register configuration space, using the formula: ; The operation retrieves the mode switch position value, where... Indicates the first The mode switching position quantity at the location, , Indicates the first and The system timestamp (in μs) corresponding to the sampling point of the next falling edge. , Indicates the first and The sampling time index of the next falling edge (in μs). This represents the synchronization control offset time (in μs) associated with the current mode switch. This represents the cumulative time difference of level state changes within the same period (in μs). Based on the extracted falling edge trigger index, the current mode identifier and sampling time index of each trigger point are combined for judgment. First, the maximum number of switching operations allowed in each sampling period is set to avoid frequent switching due to noise. The sampling window unit is 10μs, and only one valid switching operation is allowed per window. Then, the system timestamp of the trigger point is extracted. , With sampling time index , The values ​​were 170μs, 180μs, 171μs, and 182μs, respectively. Then, the synchronization control offset time was obtained. and the cumulative time difference of level transitions The calculation process, substituted with actual data, is as follows: ; The result indicates that the current mode switching position is 5.5μs, and the offset threshold is set to 6μs. This value is set based on the maximum allowable register response error range of the mode register under different level switching states. According to the actual timing environment of the NAND chip in test state with a sampling control frequency of 100MHz and a sampling period of 10μs, combined with the statistical results of the state feedback time fluctuation range after rising and falling edge triggering, a tolerance boundary is established on the basis that the level interference duration does not exceed 2μs and the level stabilization delay does not exceed 4μs. Therefore, 6μs is set as the acceptable offset limit of the maximum switching delay, and it is linearly converged and adjusted with the sampling frequency. When the sampling frequency is increased to 200MHz, the offset threshold will be automatically reduced to 3μs to ensure the stability of the timing boundary constraints. Since the current result is less than the threshold, the trigger condition is met, and the system performs a replacement operation on the test mode identifier. If the original identifier is "Mode A", it is converted to "Mode B" according to the switching strategy. Then, "Mode B" is written into the mode register configuration space to complete the logical identifier update.

[0026] Table 3 Calculation Table for Mode Switching Location As shown in Table 3, the current mode switching position is calculated as 5.5 μs by combining sampling time-series data from different sources with control offset values, which serves as the basis for subsequent judgment.

[0027] The mode switching position parameter is a core parameter used to quantify the time deviation between the mode switching trigger point and the actual switching behavior during the testing process. Specifically, it reflects the timing difference between the theoretical trigger timing and the actual switching behavior after being affected by system response delay and signal stability. The larger the value, the more the mode switching behavior deviates from the expectation, which may indicate the risk of control mismatch or synchronization interference. Conversely, it indicates that the switching behavior is more in line with the preset time window. Therefore, this parameter plays a role in timing verification and judgment in the entire switching control process. It can be used as an important criterion for determining whether to perform mode replacement and whether the synchronous switching goal has been achieved. It is a quantitative evaluation index of the reliability of register write operations. At the same time, it also has the reference significance for setting the system delay tolerance threshold and helps to establish reasonable switching control boundary conditions.

[0028] The formula's operational logic is based on the determination of mode switching timing offset, where the numerator part... This represents the magnitude of time variation in two dimensions: system time and sampling time. To improve the ability to express the actual handover delay, the two terms are added together and averaged to reflect the average handover interval under dual-time-domain synchronization conditions; √(term) Used to describe the combined effect of actual control errors during mode switching. Synchronization offset time represents the response delay between command triggering and control action. The duration of signal level variation reflects the interference effect of unstable level state on switching accuracy. Both are time-dependent sources of influence. The method of summing the squares and taking the square root is used to eliminate sign offset and equivalently synthesize the comprehensive timing disturbance intensity of the two types of errors. Finally, by subtracting the average switching interval from the synthesized disturbance and taking the absolute value, the degree of timing deviation between the "theoretical switching point" and the "offset point generated under actual influence" is quantified, forming a mode switching position quantity with comparability and upper and lower boundary definitions. This quantity can then be matched with a threshold to determine whether to perform mode replacement.

[0029] The switching information recording submodule extracts the index position and time index of the completed mode replacement based on the mode switching position quantity, records the time interval between the time point written to the mode register and the original conversion point as the delay time, and combines the replaced mode identifier and the new mode identifier to form a switching entry, which is uniformly recorded in the switching information buffer to establish a mode switching record. After obtaining the mode switching location and completing the mode identifier replacement, extract the system time at the corresponding switching operation sampling point when performing register writing. The corresponding falling edge trigger time is 170μs, so the delay time is 180μs-170μs=10μs. This delay time is recorded as the "mode switching delay time" and together with the preceding and following mode identifiers, it forms a switching entry, such as "mode A→mode B@10μs", constituting a complete record item. Subsequently, this entry is synchronously written into the system's switching information buffer, and a sequence index and control byte position description are added to the entry to build a structured record that is easy to query. After the entire process is completed, the system obtains a traceable switching information set, and the data of all nodes that have undergone valid switching are summarized and stored in the buffer, finally establishing a mode switching record.

[0030] Please see Figure 4 The dwell time determination module includes: The high-level detection submodule obtains the busy signal status value sequence corresponding to each index based on the time series data of each trigger index point in the mode switching record, divides it into sampling period units, and judges whether the proportion of high-level states in a single period sampling point reaches the total number of sampling points. It then filters out the complete sampling period segment where the high-level continuous state is established and outputs the high-level sampling period interval. Based on the time-series data of each trigger index point in the mode switching record, the busy signal status value sequence corresponding to each index is obtained and divided into sampling period units. According to the system setting, the number of sampling points per period is 4. The original sequence is segmented and processed. The level status sequence in each period is extracted in turn and the high level value is counted, that is, the number of sampling points with a level of 1. The condition for determining whether it is a complete high-level period is that the number is equal to the total number of sampling points in the current period. If the condition is not met, the data of that period is directly discarded. For example, the level status of period C1 is [1, 1, 1, 1], where the number of high levels is 4, which is equal to the total number of sampling points of 4, and it is determined to be a complete high-level period. Period C2 is [1, 1, 0, 1], with only 3 high levels, so it is discarded. The status of periods C3 and C4 is [1, 1, 1, 1], with a count of 4, so the judgment is valid. During the judgment process, all period data are recorded with the corresponding period number, level sequence, number of high levels and judgment result, and recorded in the period status table for subsequent operation processing. Finally, the period numbers with all judgment results of "yes" are obtained to form an interval, and the high-level sampling period interval is obtained.

[0031] Table 4. Statistics of High-Level Sampling Period As shown in Table 4, periods C1, C3, and C4 meet the criteria for determining a complete high-level period and are retained for subsequent continuous statistics.

[0032] The continuous period statistics submodule arranges each continuous segment according to the high-level sampling period interval and time sequence, extracts the time index difference between the start and end sampling points of adjacent segments, and uses the following formula: ; The continuous dwell time offset value is calculated. When the offset value exceeds the minimum self-refresh time threshold, it is marked as an overdue period, and potential abnormal dwell time data is generated. This indicates the offset value of the continuous residence period. This indicates the start time of the nth consecutive sampling period. This indicates the amplitude of the high-level state fluctuation within each cycle. This represents the jitter value of the signal sampling rate within the corresponding period. Indicates the number of periods. This refers to the processing of operations accumulated over a continuous resident sequence; Based on the high-level sampling period interval and arranging each continuous segment in time sequence, the start and end time differences of each pair of adjacent period segments are extracted. Let the corresponding times for C1, C3, and C4 be 100ns, 110ns, 120ns, and 130ns, respectively, forming a time sequence [t1, t2, t3, t4] = [100, 110, 120, 130]. ​​Then, the high-level fluctuation amplitude and sampling rate jitter value of the corresponding period are collected. The fluctuation amplitude is calculated using the variance of the level value for each period. For example, C1 has a variance of 0, C3 has a variance of 0.1, and C4 has a variance of 0.05, which are assigned the values ​​d1=0, d2=0.1, and d3=0.05 respectively. The sampling rate jitter is determined by comparing the range of time intervals between sampling points within the period. For example, if the time interval between each sampling point in C1 is 25ns, there is no jitter; if C3 has points at 22ns and 28ns, the jitter is 3ns; and if C4 fluctuates within ±2ns, it is denoted as 2ns. These are then denoted as v1=2, v2=3, and v3=2 respectively, and substituted into the formula: ; The calculation process is as follows: ; ; ; ; ; Finally, the continuous dwell period offset value of this continuous period was obtained as 25.875ns. Compared with the refresh period of 160ns, it did not meet the timeout judgment. The segment was recorded as not being an abnormal segment. This result shows that 25.875ns is the dwell disturbance time of the system under the condition of continuous high level maintenance. It did not reach the refresh failure critical condition set in the standard, and thus the potential abnormal dwell amount data was obtained.

[0033] The continuous dwell period offset is a comprehensive quantitative indicator that measures the degree of deviation between the duration of continuous high-level dwell behavior in the time dimension and the impact of signal disturbance. Specifically, it reflects the numerical difference between the cumulative time that the busy signal maintains a high-level state during a continuous sampling period and the amount of synthetic disturbance introduced by factors such as level fluctuations and sampling rate jitter during that period. If the value is small, it indicates that the dwell behavior is basically stable and not significantly disturbed. If the value is large, it indicates that the current dwell behavior has significantly exceeded the normal control rhythm in time or is disturbed by high-frequency jitter. Its essence is to establish a comparison relationship between dwell time and actual disturbance synthetic amplitude to identify whether the system is in a potentially unstable or self-refresh failure risk period. It is the core criterion for judging abnormal dwell intervals.

[0034] The formula's operational logic aims to quantify the deviation between the time extension of the continuous high-level dwell period and the perturbation synthesis quantity. First, the term... This represents the sum of the cumulative time intervals of all adjacent high-level sampling periods, reflecting the actual duration of a continuous high-level dwell, and has direct temporal significance; while the square root term... The combined effect of the disturbance factor is denoted as , where This represents the sum of squares of the voltage level fluctuations within each period. The sum of squares of sampling frequency jitter is represented. Both are variance-type statistics that reflect the instability of the signal state within this time period. The positive and negative offset effects are unified by squaring, and the magnitudes of different disturbance terms are converted back to the time scale by square root operation. Finally, the difference between the two parts is taken and the absolute value is added to obtain the numerical difference between the dwell time length and the total disturbance intensity. This quantifies whether the continuous dwell state is outside the stable time window. This structure can simultaneously capture the combined effect of prolonged dwell behavior and disturbance intensity, and is used to determine whether an abnormal segment is established.

[0035] The abnormal interval judgment submodule combines and pairs the start and end points of the time index based on the potential abnormal dwell volume data, removes records that do not meet the condition that the time interval is greater than the minimum refresh cycle, forms a valid time period segment sequence with a duration greater than the minimum self refresh cycle threshold, and integrates the corresponding pattern identifier segments to generate potential abnormal interval records. Based on the potential abnormal dwell time data, the start time index and end time index of all dwell time segments are obtained, and the time span is calculated. Assuming the start time is 160ns and the end time is 350ns, the duration is 190ns. This is then compared with the self-refresh threshold of 160ns to determine whether the dwell timeout requirement is met. Since 190ns is greater than the threshold of 160ns, this period is judged as an abnormal dwell time segment. The judgment condition is set according to the requirement of the lower limit of the self-refresh cycle of DDR SDRAM in the JEDEC JESD79 standard, and based on the controller's response time to the refresh signal at an 800MHz clock frequency, the standard lower limit is set to 160ns. In actual judgment, if the continuous dwell time reaches or exceeds this threshold, it is included in the abnormal candidate. Then, the judgment result is combined with the corresponding mode identifier to record the mode corresponding to the dwell time segment, for example, mode B. Finally, the abnormal entry "abnormal segment@mode B[160ns-350ns]" is generated in a structured manner, and all abnormal segments that meet the conditions are recorded and organized into structured information to finally obtain the potential abnormal interval record.

[0036] Please see Figure 5 The abnormal fragment archiving module includes: The time segment extraction submodule extracts test data segments within the corresponding time range based on each time index interval in the potential anomaly interval record. It performs matching operations on all timestamped data in the test data sequence, checks and removes data segments with missing records or discontinuous segments during the sampling process, filters out test data segment sequences with complete structure and continuous time sequence, and arranges them in chronological order to obtain the time synchronization sampling segment. Based on each indexed time period in the potential anomaly interval records, the start and end time indices are first extracted from the records. Then, according to the time index range, the timestamp field is retrieved item by item in the test dataset. By comparing the size relationship between the timestamp and the start and end times, all data items whose timestamps fall within the time interval are selected. For example, if the start time of the anomaly interval is 240ns and the end time is 460ns, all sampled data with timestamps greater than or equal to 240ns and less than or equal to 460ns are selected from the original test data as target segments. During the extraction process, fields such as signal level, power status, address bits, and command bits must be retained to ensure that the segments have a complete signal behavior sequence. For problems such as missing signal fields or sampling point intervals exceeding the specified period length (e.g., more than 20ns) in certain sampling periods, a rejection operation is performed to remove segments with discontinuous data or missing fields. The extracted segments are further sorted in ascending order by timestamp to ensure that the sampling points are continuously arranged on the time axis, and output in a unified standard data structure format, as shown in Table 5 below.

[0037] Table 5. Examples of Sampling Fragment Extraction within Abnormal Time Periods As shown in Table 5, the fragment sequence is continuous, the fields are complete, and the time order is correct, which meets the conditions for subsequent processing, and finally the time synchronization sampling segment is obtained.

[0038] The pattern association storage submodule processes each data segment in the time synchronization sampling segment with the pattern identifier in the corresponding potential anomaly interval record, binds the time segment with its corresponding running mode number, establishes a segment sequence number for each group of segments, and summarizes them according to the pattern identifier to obtain a list of pattern archived segments. Based on each sampled segment data in the time-synchronized sampling section, its start and end time indices are read one by one. The pattern number field to which it belongs is retrieved in the original record of the abnormal interval. The field-level binding between the sampled segment and the pattern number is completed by index field matching. Then, a unique number is generated for each successfully matched data pair. The numbering format adopts the combination structure of "pattern number + segment number". For example, if the second segment belongs to pattern M3, it is marked as "M3_P2" as a data archiving identifier. Then, an archiving tag field is added to each data segment and the structure definition is supplemented to uniformly establish the index structure information of the segment, such as the segment time length, the number of sampling points, the number of address changes, etc., forming a complete segment structured data unit. Then, an archiving index table is established with the pattern number as the classification primary key. All segments are grouped and summarized according to their respective pattern numbers, and their belonging relationship and segment attribute information are marked in the data structure. Finally, a basic data list that can be used for querying and further classification is formed, resulting in a pattern archived segment list.

[0039] The tolerance separation judgment submodule performs boundary range judgment and interval attribution judgment operations for each data segment based on the sampling segments recorded in the pattern archive segment list and the standard AC time series tolerance range. It performs anomaly marking for segments outside the tolerance range, re-numbers and archives the abnormal segments, and obtains the abnormal segment archive sequence. Based on the fragment information bound to mode identifiers in the mode archive fragment list, read the AC timing-related fields within each fragment, including the time difference between the write command and data sampling, command duration, address line hold time, and other field parameters. For each timing field, set the judgment interval according to the AC boundary time requirements specified in the JEDEC standard. For specific standard values, refer to the AC timing section of the DDR4 SDRAM specification. In the table, TRCD=13.5ns, TRP=13.5ns, and tRAS=36ns. A margin of ±5% is used for judgment; for example, the allowed range for TRCD is 12.825ns to 14.175ns. The actual measured values ​​of all relevant fields in the segment are extracted. If a segment has a TRCD of 15.0ns, exceeding 14.175ns, the segment is marked as an anomalous segment, and its field values ​​and corresponding standard range information are recorded. Further, it is determined whether the location of the anomalous field deviates continuously from other fields. If both TRCD and tRAS fields in a segment exceed their limits, and both fields appear consecutively on the timeline, the segment is treated as a complete and independent anomalous segment. If the anomalous fields are distributed across different segments or the interval is too long (exceeding 40ns), the segment is split into multiple anomalous segments and archived separately. Finally, all segments that meet the anomaly judgment are numbered, classified, rearranged, and included in the anomalous structure data list, constructing an anomalous segment archive sequence.

[0040] Please see Figure 6 The fragment tag management module includes: The pattern labeling submodule extracts the established archive number and fragment index position based on the attribution information of each fragment in the abnormal fragment archive sequence, performs a corresponding relationship matching operation on each fragment data, generates a pattern label in a unified format, and obtains a pattern label fragment set. Based on the attribution information of each segment in the abnormal segment archive sequence, the segment number and position index fields of each abnormal segment record are first read. Then, the attached pattern number information is extracted from the abnormal segment structure and bound to the segment index number. For example, if the segment number is P07 and the corresponding pattern number is M2, then the label "MODE_2" is generated for this segment. During the label generation process, a "pattern label" field is added to each segment structure data to record the label. Then, all segment structures are checked one by one to ensure that each data has a valid pattern number. If some segments are found to be without pattern information, they are added to the supplementary label sequence. The supplementary label is inferred by the time interval and pattern consistency of the segments before and after. For example, if P08 and P10 are MODE_2 respectively, and P09 is missing a label and the time difference is no more than 10ns, then P09 is supplemented with MODE_2. Finally, all tagged segments are summarized by number and structured information is constructed to form a pattern-labeled segment set.

[0041] The timestamp tag generation submodule reads the corresponding start and end sampling times based on the start and end indices of each segment in the pattern tag segment set, formats the timestamp tags uniformly and embeds them into the segment structure, summarizes the data segments after inserting timestamp tags into all segments, and establishes a timestamp-labeled segment table. Based on the information of each segment in the pattern label segment set, the start timestamp and end timestamp fields are extracted sequentially. This time range is used as the boundary for tag generation. The signal sequence in the segment structure is scanned for behaviors such as instruction switching, address jumps, or sampling rate abrupt changes. If a behavior change is detected, such as the command changing from WR to RD, the event record time point is inserted as a new intermediate tag into the segment structure to form a multi-segment time tag. For example, if the start time is 105ns, the instruction switching point is 132ns, and the end time is 165ns, then the three-segment tag is [105, 132, 165]. For segments without switching, a two-point tag [start time, end time] is used. All tags are formatted in integer nanosecond units, for example, 105ns is represented as "105", and embedded in the structure field "timestamp tag". After all segments are labeled, the result list is integrated and output to establish a timestamp-labeled segment table.

[0042] Table 6 Examples of Timestamp Annotated Fragments As shown in Table 6, P07 includes WR and RD switching behavior with an event marker inserted in the middle, while P08 has no event change and uses a double-dot marker structure, with complete label coverage.

[0043] The sequence integration and output submodule reorders all marked abnormal fragment data in ascending order of timestamp based on the structured data records in the timestamp-marked fragment table, constructs a triplet sequence of start and end time, mode number, and data number, and exports it as structured output data to generate test data for multi-mode coupled NAND memory chips. Based on all data records in the timestamp-marked segment table, the segments are uniformly reordered in ascending order according to the "start time" field. For example, if the start time of P07 is 105ns and the start time of P08 is 170ns, the sorting order is P07, P08. Then, the mode tag and segment number information corresponding to each segment are extracted, and each group of segments is repackaged in the format of "start time-end time-mode number-segment number" to construct a triplet structure. For example, P07 is assembled as [105-165, MODE_2, P07]. Then, segment discontinuity judgment is performed, and the time interval between adjacent segments after sorting is compared. If the interval is less than 15ns, it is considered as a continuous segment and spliced. For example, if the interval between P07 and P08 is 5ns, they are merged into one group. If it is greater than 15ns, such as an interval of 30ns, an "inter-segment splitting flag" is inserted in the middle to mark it as a discontinuous segment. Finally, after splicing, the complete segment data stream is output to establish test data for multi-mode coupled NAND memory chips.

[0044] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A testing system for multi-mode coupled NAND memory chips, characterized in that, The system includes: The busy signal acquisition module acquires the standard busy signal level status output during the NAND memory chip test process, records the level status and time index of each sampling period, compares the difference between the level status of adjacent sampling points, statistically analyzes the signal duty cycle change trend, and generates a busy signal status sequence. Based on the busy signal state sequence, the mode switching control module detects the moment when the level of adjacent sampling points changes from high to low, combines the current test mode identifier and the time index of the corresponding sampling point, records the corresponding timing parameters to form a mode switching mark, and generates a mode switching record. The dwell time determination module accumulates the number of continuous dwell time sampling cycles of the busy signal high level according to the mode switching record. When the accumulated value exceeds the self-refresh timeout threshold, the corresponding time period is determined as a potential abnormal interval, and a corresponding time index interval is formed to generate a potential abnormal interval record. The abnormal fragment archiving module extracts test data fragments within the corresponding time interval based on the potential abnormal interval records, associates and stores the time index interval with the corresponding mode identifier, performs AC time-series tolerance window separation judgment on the archived fragments, forms continuous independent fragment records, and generates an abnormal fragment archiving sequence.

2. The multi-mode coupled NAND memory chip testing system according to claim 1, characterized in that, The busy signal state sequence includes a level change trend record, a time index sequence, and duty cycle statistics. The mode switching record specifically includes a mode identifier mapping table, a mode switching time index, and a mode switching delay parameter. The potential abnormal interval record includes a time interval index, a timeout marker, and a dwell period count result. The abnormal segment archive sequence includes a time interval association table, a mode identifier corresponding segment, and a timing tolerance determination result.

3. The multi-mode coupled NAND memory chip testing system according to claim 1, characterized in that, The busy signal acquisition module includes: The busy signal recording submodule acquires the RBn level status output during the NAND memory chip test, records the level status according to the sampling period and marks the time index, and continuously records to form a discrete level sequence, thus obtaining the discrete level sequence. The duty cycle comparison submodule compares the difference between the level states of adjacent sampling points based on the discrete level sequence, and sorts them together with the duration of high and low levels in each sampling period to obtain a record of the duty cycle change trend. The state sequence generation submodule records the duty cycle change trend, sorts and integrates the duty cycle change trend with the discrete level sequence within a continuous period, statistically analyzes the continuous change characteristics of the period, and generates a busy signal state sequence.

4. The multi-mode coupled NAND memory chip testing system according to claim 1, characterized in that, The mode switching control module includes: The level transition detection submodule reads the level status of adjacent sampling points based on the busy signal state sequence, identifies the transition position where the level of the previous sampling point is 1 and the level of the next sampling point is 0, extracts the time index and transition position index of the corresponding transition time, and marks them in combination with the sampling segment number where the transition occurs to obtain the falling edge trigger index. The mode identifier replacement submodule, based on the falling edge trigger index, compares the current test mode identifier and sampling time index corresponding to each switching position, makes judgments and number adjustments according to the mode switching rules, replaces the original test mode identifier at the sampling point that meets the switching conditions, writes the replacement result into the mode register configuration space, and calculates and obtains the mode switching position quantity. The switching information recording submodule extracts the index position and time index of the completed mode replacement based on the mode switching position quantity, records the time interval between the time point written to the mode register and the original conversion point as the delay time, and combines the replaced mode identifier and the new mode identifier to form a switching entry, which is uniformly recorded in the switching information buffer to establish a mode switching record.

5. The multi-mode coupled NAND memory chip testing system according to claim 1, characterized in that, The dwell time determination module includes: The high-level detection submodule obtains the busy signal state value sequence corresponding to each index based on the time series data of each trigger index point in the mode switching record, divides it into sampling period units, and judges whether the proportion of high-level states in a single period sampling point reaches the total number of sampling points. It then filters out the complete sampling period segment where the continuous high-level states are established and outputs the high-level sampling period interval. The continuous period statistics submodule arranges each continuous segment according to the high-level sampling period interval and in time sequence, extracts the time index difference between the start and end sampling points of adjacent segments, calculates and obtains the continuous dwell period offset value, and marks it as an overtime period when the offset value exceeds the minimum self-refresh period threshold, generating potential abnormal dwell amount data. The abnormal interval judgment submodule combines and pairs the start and end points of the time index based on the potential abnormal dwell volume data, removes records that do not meet the condition that the time interval is greater than the minimum refresh cycle, forms a valid time period segment sequence with a duration greater than the minimum self-refresh cycle threshold, and integrates the corresponding pattern identifier segments to generate potential abnormal interval records.

6. The multi-mode coupled NAND memory chip testing system according to claim 1, characterized in that, The abnormal fragment archiving module includes: The time segment extraction submodule extracts test data segments within the corresponding time range based on each time index interval in the potential anomaly interval record. It performs matching operations on all timestamped data in the test data sequence, checks and removes data segments with missing records or discontinuous segments during the sampling process, filters out test data segment sequences with complete structure and continuous time sequence, and arranges them in chronological order to obtain the time synchronization sampling segment. The pattern association storage submodule processes each data segment in the time synchronization sampling segment with the pattern identifier in the corresponding potential anomaly interval record, binds the time segment with its corresponding operating mode number, establishes a segment sequence number for each group of segments, and summarizes them according to the pattern identifier to obtain a list of pattern archived segments. The tolerance separation judgment submodule performs boundary range determination and interval attribution determination operations on each sampled segment recorded in the mode archive segment list according to the standard AC time series tolerance range. It performs anomaly marking processing on segments that are not within the tolerance range, re-numbers and archives the abnormal segments, and obtains the abnormal segment archive sequence.

7. The multi-mode coupled NAND memory chip testing system according to claim 1, characterized in that, The system also includes: The fragment tagging management module adds a test mode ID and timestamp tag to each abnormal fragment according to the abnormal fragment archive sequence, and organizes the tagged records into a traceable sequence to form multi-mode coupled NAND memory chip test data. The test data for the multi-mode coupled NAND memory chip includes anomaly fragment tags, test mode IDs, and nanosecond-level timestamps.

8. The multi-mode coupled NAND memory chip testing system according to claim 7, characterized in that, The fragment tag management module includes: The pattern tag marking submodule extracts the established archive number and fragment index position based on the attribution information of each fragment in the abnormal fragment archive sequence, performs a corresponding relationship matching operation on each fragment data, generates a pattern tag in a unified format, and obtains a pattern tag fragment set. The timestamp tag generation submodule reads the corresponding start sampling time and end sampling time according to the start index and end index of each segment in the pattern tag segment set, uniformly formats the timestamp tag and embeds it into the segment structure, and after inserting timestamp tags into all segments, summarizes the data segments and establishes a timestamp-labeled segment table. The sequence integration and output submodule reorders all marked abnormal fragment data in ascending order of timestamp based on the structured data records in the timestamp-marked fragment table, constructs a triplet sequence of start and end time, mode number, and data number, and exports it as structured output data to generate test data for multi-mode coupled NAND memory chips.

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