Test rule checking method and device for layout

Abstract

The invention discloses a layout test rule checking method and device, and the method is carried out in a layout design process, and comprises the steps: S1, carrying out the type recognition and port position searching of a device of a layout in a code form; and S2, verifying the position of the port of the device according to the test rule, and reporting an error for the device which does not accord with the test rule. According to the invention, timely error reporting in the layout design process is realized, and timely error correction of a designer is facilitated, so that the layout design and test efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated optoelectronic device testing, and in particular to a layout test rule checking method and device. BACKGROUND

[0002] Silicon-based optoelectronic technology integrates photonic and electronic functional devices on a silicon chip, showing great market potential in the fields of optical communication, optical interconnection, optical computing and optical sensing. In recent years, the market for silicon optical chips has shown a rapid growth trend.

[0003] Under the background of rapid development of silicon optical technology, the testing of silicon optical devices is an indispensable part. At the current technical level, the following three difficulties are mainly faced: (1) silicon optical technology has moved towards mass production, resulting in a huge testing demand, and there is an urgent need for wafer-level silicon optical automatic testing platform; (2) the types and complexity of testing are increasing, including optical-optical testing, optical-electrical testing, electrical-electrical testing and radio frequency testing, and integrated optoelectronic device testing has certain requirements for the spatial layout of input and output ports; (3) there is a technical barrier between designers in the field of silicon-based optoelectronics and professional testing engineers, and a standardized process is urgently needed.

[0004] The development process of silicon optical devices includes software simulation, layout design, wafer processing, wafer testing, device packaging, and product verification. The time cost and economic cost of wafer processing are very high. In order to avoid the problem that the processed wafer does not meet the testing requirements, it is necessary to import the testing requirements in the layout design stage of the device, and to develop an efficient test design kit (TDK).

[0005] The prior art provides fixed optical / electrical test structure examples for designers to ensure that the designed optoelectronic structure can be tested on a specific chip / wafer testing machine. However, this scheme of the prior art has the problem of inflexibility, and the designer can only design according to the fixed structure size. However, in the actual design process, different sizes and structures of devices are involved, and it is difficult to design according to a certain or several fixed structures, and the actual needs of the design and the testing capacity of the testing machine must be fully considered.

[0006] Some prior art provides a design test rule diagram for designers to mark what conditions the relative positions of optical / electrical test ports need to meet. This scheme is more direct and clear for designers. However, in the actual mass production design layout, there are a large number of test structures, and these designed test structures cannot be automatically checked in the design stage, but can only be checked manually, which is low in efficiency.

[0007] The prior art test rule check needs to export a completed design layout as a GDS file, and a tester needs to visually identify a device and manually obtain coordinates, and then determine whether the test can be satisfied. The method is time-consuming and cannot check all test items at one time, and needs to be corrected by a designer multiple times. SUMMARY

[0008] The present application aims to provide a layout test rule check method and device to realize timely check and correction in the layout design stage, so that the final layout can directly meet the test requirements and improve the efficiency of layout design.

[0009] To solve the above technical problems, the present application provides a layout test rule check method, which is performed in the layout design process; the method comprises: S1, type identification and port position finding of a device in a code form layout; S2, checking the port position of the device according to the test rule, and reporting an error for the device that does not meet the test rule.

[0010] According to the above scheme, the layout design method comprises: S1011, customizing a basic device according to design requirements; S1012, connecting the devices through waveguides to generate a combined kit; S1013, generating a new combined kit through geometric transformation of the combined kit.

[0011] According to the above scheme, the layout design method comprises: S1014, performing geometric transformation on the combined kit obtained in step S1013 again to generate a new combined kit.

[0012] According to the above scheme, the layout is drawn by Python software.

[0013] According to the above scheme, the types of the device include grating light port, end face coupling light port, direct current port, radio frequency port and other self-defined optical and electrical ports.

[0014] According to the above scheme, the position finding of the device comprises: S1021, obtaining the port coordinates of the original device corresponding to the device according to the port coordinates of the device; the original device is obtained after geometric transformation of the device; S1022, obtaining the position of the device in the layout according to the port coordinates of the original device and the geometric transformation relationship from the original device to the device.

[0015] According to the above scheme, the layout design method comprises: the types of geometric transformation include translation, rotation, mirroring and scaling.

[0016] According to the above scheme, the test rule includes a limit on the width and height of the device, and a limit on the horizontal distance and vertical distance between different devices.

[0017] According to the above scheme, the error type includes a text error and a graphical error.

[0018] The present application also provides a layout test rule checking device, comprising: a test design kit module for identifying the type of a device in a code-form layout and finding the port position of the device, and checking the port position of the device according to a test rule, and reporting an error for a device that does not meet the test rule.

[0019] Advantages The present application synchronously performs test rule checking during the layout design process, which can timely find the problem of the port position of a device not meeting the test rule in the early design stage, avoids high time cost and economic cost caused by the design defect that cannot meet the test requirement after wafer processing, significantly reduces the design risk, and replaces the manual visual identification of the port, manual acquisition of the coordinates and judgment in the prior art, avoids the inefficiency and subjective error of manual checking, realizes the automation of the test rule checking, greatly improves the checking efficiency, and can complete the checking of all test items at one time, reducing the number of repeated corrections by the designer; compared with the scheme in the prior art that depends on fixed test structure size, the present application can adapt to the design requirements of devices of different sizes and structures through real-time dynamic checking, and can meet the test rule requirements of the test machine, ensuring the design flexibility and ensuring the test compatibility; through real-time feedback during the design process, the designer can correct the problem synchronously in the layout drawing stage, without the need for multiple rounds of rework after the design is completed, solving the process redundancy problem of multiple file export and repeated modification in the prior art, significantly shortening the design cycle, and improving the overall efficiency of the layout design.

[0020] Further, the present application automatically reversely deduces the port position by clearly associating the geometric transformation of the original device with the current device, accurately solving the problem of difficult accurate acquisition of the port position of the device after geometric transformation; this method ensures the accuracy of the port position data, provides a reliable basis for subsequent test rule checking, avoids invalid checking and design defects caused by incorrect position judgment, further improves the automation degree and accuracy of the test rule checking, reduces the number of design corrections, significantly shortens the layout design cycle, and reduces the time and economic cost caused by repeated adjustment. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1The flow chart of the test rule check method of the layout of an embodiment of the present application; Figure 2 The schematic diagram of the test structure of a common optoelectronic device; Figure 3 The flow chart of the design method of the layout of an embodiment of the present application; Figure 4 The schematic diagram of the layout logic of an embodiment of the present application; Figure 5 The schematic diagram of the actual layout of an embodiment of the present application; Figure 6 The schematic diagram of the actual layout of an embodiment of the present application; Figure 5 The schematic diagram of a single group in the present application; Figure 7 The schematic diagram of a single group in the present application; Figure 6 The schematic diagram of a single grating in the present application; Figure 8 The schematic diagram of the layout design and test flow of an embodiment of the present application; Figures 9-11 The schematic diagram of different error reporting types of an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any inventive effort fall within the protection scope of the present disclosure.

[0023] The embodiments of the present disclosure disclose a test rule check (TRC) method of a layout, which is performed in the layout design process; the method comprises: S1, type identification and port position searching are performed on the device of the layout in code form; S2, the port position of the device is checked according to a test rule (Test tule), and an error is reported for the device that does not meet the test rule.

[0024] The test rule is usually provided by a test manufacturer.

[0025] Further, referring to Figure 3 , the design method of the layout comprises: S1011, a basic device is customized according to design requirements; S1012, the devices are connected through waveguides to generate a combined kit; S1013, the combined kits are generated through geometric transformation to generate new combined kits; The logical diagram of the layout generated according to the above method is shown in FIG. 1. Figure 4 .

[0026] Further, the design method of the layout comprises: S1014, performing geometric transformation on the combined kit obtained in step S1013 again to generate a new combined kit.

[0027] Further, the layout is drawn by Python software.

[0028] Further, the types of the devices include grating light ports, end-coupling light ports, direct-current electrical ports, radio-frequency electrical ports and other self-defined optical and electrical ports.

[0029] Further, the port position finding of the device comprises: S1021, obtaining the coordinates of the original device corresponding to the device according to the coordinates of the device; the original device is obtained after geometric transformation of the device; S1022, obtaining the position of the device in the layout according to the coordinates of the original device and the geometric transformation relationship from the original device to the device.

[0030] Further, the design method of the layout comprises: the types of geometric transformation include translation, rotation, mirroring and scaling.

[0031] Further, the test rules include the restrictions on the width and height of the device, and the restrictions on the horizontal distance and vertical distance between different devices.

[0032] Further, the types of error reporting include text error reporting and graphical error reporting.

[0033] The embodiment also provides a layout test rule checking device, comprising: a test design kit module (TDK) for type identification and position finding of the devices of the layout in code form, and checking the positions of the devices according to test rules and reporting errors for the devices not meeting the test rules.

[0034] The code flow of the test rule checking device mainly comprises: device type identification→device port position finding→test rule (Test tule) judgment and error reporting.

[0035] First, the layout is drawn by software (Python), and the device is defined by code, and it is assumed that the device name in the code is “AA” or “BB”, the layout drawing is completed, and it is assumed that the name of the drawn layout is “Circult”.

[0036] The flow of TDK test rule checking (TRC) is as follows: (1) input the test rules (Test tule) provided by the test manufacturer into the TRC module; (2) Use AA or BB as the port input of the TRC module. This completes the identification of the port type (e.g., the port type includes grating optical port, end face coupled optical port, DC port, RF port, etc.). (3) Using Circult as the layout input of the TRC module, the locations of ports AA and BB are located. The search process is as follows: Ⅰ: After the identification in step (2), all ports AA and BB in the Circult file can be found; II: Find the original coordinates using the coordinates of AA and BB, and then obtain the final positions of AA and BB on the layout using all the transformation relationships of devices AA and BB in the Circul. This completes the port location finding process. III: After locating the port positions of all AA and BB, first, based on the connection relationships of the Circuit, group the connected AA and BB into one group. Then, for each group, use Test rules to check the placement of all components, and display text and graphical error messages for components that do not meet the rule requirements. This completes the TRC function.

[0037] by Figure 5 Taking the layout shown as an example, the port location identification process of the present invention is explained as follows: This layout consists of grating couplers (Dut1_Gc11, Dut1_Gc12, Dut2_Gc21, Dut2_Gc22) and connecting waveguides. Dut1_Gc12 and Dut2_Gc22 are obtained by rotating Dut1_Gc11 and Dut1_Gc21 by 180° and adjusting their positions. Given that the center point of the layout is (0,0), the specific steps to obtain the port coordinates of Dut1_Gc12 are as follows: ① Initialize the label transformation Where R is the rotation angle, T is the coordinates of the center point of the parent layout, V is the vertical mirror (a value of 1 indicates no mirroring operation, and a value of -1 indicates that a mirroring operation has been performed), and AM is the magnification factor; ② In the layout, the device Dut1 is recursively obtained with a rotation angle of 0 and no mirroring or scaling operations. This transformation is denoted as Dut1. The center point coordinates are (0, 50); calculated using formula (1) ; Requires transformation with the parent map Superimposed .

[0038] The formula (1) is as follows:

[0039] in, , R, V, AM in the post-adding transform respectively, , , R, V, AM in the post-adding transform respectively, , are the horizontal and vertical coordinates of the center of the current device (without considering the parent transform), , are the horizontal and vertical coordinates of the center of the parent layout of the current device, is the rotation angle of the current device, is the rotation angle of the parent layout of the current device, is the magnification of the current device, is the magnification of the parent layout of the current device, indicates whether the current device is mirrored, indicates whether the parent layout of the current device is mirrored; Note: The subscript 1 is the relevant parameter of the current device without considering the parent layout transform, and the subscript 2 is the relevant parameter of the parent layout of the current device. If the two transforms are different, the results obtained are also different.

[0040] ③Referring to Figure 6 , the rotation angle of the grating Gc2 of the device Dut1 is 180, without mirror and scaling operations, and the transform of Dut1_Gc12 is recorded as , the center point coordinates are (225, 0), which are calculated by formula (1) , and the transform of the parent layout is added to obtain .

[0041] ④Referring to Figure 7 , the in port coordinates of the grating Gc are (-12, 0), and are calculated by formula (1) , so the absolute coordinates of the in port are (237, 50); the out port coordinates are (25, 0), and are calculated by formula (1) , so the absolute coordinates of the out port are (200, 50); The test design kit module developed in this embodiment is to help quickly establish a communication channel between design and test, so that optoelectronic device designers can import test requirements in the design stage to speed up the subsequent test process. Embedding the test design kit module into the layout design software can provide the designer with the layout structure of the test instance, provide the designer with the layout test rule checking function, and realize the real-time feedback of whether the design meets the test requirements.

[0042] The test design kit module is embedded in the layout design software to provide the test rule check function for the designer in the design layout stage, and the test structure can be fed back in real time in the photoelectric device layout design stage whether it meets the test machine rule requirements. Generally, the test design kit module is highly bound with the test capacity of the test manufacturer, and the test capacity of the test manufacturer is limited by the physical size of the photoelectric probe, the carrier and the clamp, and the specification of the probe. Figure 2 The test structure of the common photoelectric device is given, and the input and output ports include the optical port, the direct current port and the radio frequency port, wherein the optical port can be divided into the grating coupling port and the end face coupling port. In the figure and respectively represent the width and height of the direct current port, and respectively represent the width and height of the radio frequency port, and respectively represent the horizontal and vertical distances between the electrical ports, and respectively represent the horizontal and vertical distances between the optical port and the direct current port or the radio frequency port, and respectively represent the horizontal and vertical distances between the optical ports. The distance dimensions must meet certain values to meet the test requirements, which are the test rules of the machine. Therefore, the test rule check also needs to be performed in the design process.

[0043] The layout design software generally generates the layout graphic file by the code, which is beneficial to the batch layout of the layout and the subsequent modification of the layout. The test design kit module is also realized by the code in the layout design software, and the specific work flow is as shown in Figure 8 The designer (user) inputs the layout design / layout modification code in the layout design software platform. In the left branch of the work flow diagram, the test design kit module first identifies the device and the corresponding optical / electrical input / output (I / O) port input by the designer and extracts the coordinates, and then judges the position of the I / O port through the test rule. If the judgment meets the test requirements, the layout is taped out and the wafer is manufactured, if the judgment does not meet the test requirements, the designer needs to modify the layout code again, and the test design kit module is used for test rule check. On the other hand, in the right branch of Figure 8 , the designer inputs the design layout, and can simultaneously input the test requirements of the corresponding test item to generate the preprocessing algorithm of each test item, and the preprocessing algorithm is combined with the wafer level automatic test when the wafer is tested to improve the test efficiency. In addition to the test rule check function and the preprocessing algorithm, the test design kit module can also provide the standard test example for the customer.

[0044] The test rule check function in the test design kit module can generate an error report for the layout design in the layout file, and the error report content is that the structure size does not meet the test requirement. Figure 9 As shown in the layout file of the prior art, and do not meet the requirement, and the error report is marked in the layout. As shown in the layout file of the prior art, Figure 10 As shown in the layout file of the prior art, and do not meet the requirement, and the error report is marked in the layout. As shown in the layout file of the prior art, Figure 11 As shown in the layout file of the prior art, and do not meet the requirement, and the error report is marked in the layout. The test correction can be realized at the same time of the layout design, and the loss of the designer caused by the long and high-cost wafer processing flow is avoided.

[0045] The technical effect of the present application is embodied in the aspects of timeliness and compatibility. The TRC judgment is performed synchronously while the layout is drawn. Since the layout drawing is completed by code writing, the design, placement and connection relationship of the graphics in the code are defined by the code, after the TDK module is embedded in the software, the searching and judgment are automatically performed through the algorithm, so that the real-time judgment and feedback are realized, and the high timeliness is achieved. The TDK module can be automatically compatible with multiple design PDK platforms. The TDK module is embedded in the software as an independent module, new functions are added without changing the original code, the interface of the PDK platform is connected with the TDK module through the setting interface, and the compatibility of any PDK with the designed TDK module is realized. The present application also realizes the positioning of the device\graphics through the nesting of the behavior relationship between the devices\graphics, and judges the relative relationship of the devices\graphics through the built-in rule relationship, which provides a basis for the realization of the TRC function. Moreover, the present application generates the error report mark in the layout, and intuitively feeds back the error report information. The GDS graphics with the error report information can be obtained by using the layout design function of the software, which is beneficial for the user to correct the error in time.

[0046] It should be noted that, according to the needs of implementation, each step / component described in the present application can be split into more steps / components, or two or more steps / components or part of the operation of the steps / components can be combined into a new step / component, so as to realize the purpose of the present application.

[0047] Those skilled in the art will readily understand that the above description is only the preferred embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for checking test rules of a layout, characterized in that, This is carried out during the layout design process; the method includes: S1. Identify the types of devices and locate port positions in the layout in code form; S2. Verify the position of the device's ports according to the test rules, and report errors for devices that do not conform to the test rules.

2. The layout testing rule checking method according to claim 1, wherein the layout design method includes: S1011. Customize basic components according to design requirements; S1012. Connect the various devices through waveguides to generate a combined kit; S1013. Generate new combination kits by geometric transformation of each combination kit.

3. The layout test rule checking method according to claim 2, characterized in that, The layout design method includes: S1014, performing geometric transformation on the combined kit obtained in step S1013 to generate a new combined kit.

4. The layout test rule checking method according to claim 1, characterized in that, The map was drawn using Python software.

5. The layout test rule checking method according to claim 1, characterized in that, The types of devices include grating optical ports, end-face coupled optical ports, DC electrical ports, RF electrical ports, and other custom optoelectronic ports.

6. The layout test rule checking method according to claim 1, characterized in that, Device location locating includes: S1021. Obtain the coordinates of the original device corresponding to the original device based on the coordinates of the original device; obtain the device after geometric transformation of the original device; S1022. Based on the coordinates of the original device and the geometric transformation relationship from the original device to the device, obtain the position of the device in the layout.

7. The layout test rule checking method according to claim 2, 3, or 6, characterized in that, The design methods for the layout include: geometric transformations such as translation, rotation, mirroring, and scaling.

8. The layout test rule checking method according to claim 1, characterized in that, The testing rules include restrictions on the width and height of the devices, as well as restrictions on the horizontal and vertical distances between different devices.

9. The layout test rule checking method according to claim 1, characterized in that, Error messages can be text-based or graphical.

10. A layout testing rule checking device, characterized in that, include: The Test Design Suite module is used to identify the type of devices and locate their ports in the code-based layout, and to verify the port locations of the devices according to the test rules, reporting errors for devices that do not conform to the test rules.

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