Memory, operation method thereof and memory system

Abstract

The embodiment of the invention provides a memory, an operation method thereof and a memory system. The memory includes: a memory cell array including a plurality of word lines; and a peripheral circuit coupled to the memory cell array and configured to discharge the word line to a first discharge voltage in a first memory mode; discharging the word line to a second discharge voltage in a second storage mode; wherein the first discharge voltage is different from the second discharge voltage.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory and its operation method, and a memory system. Background Technology

[0002] Currently, flash memory is becoming increasingly common in everyday life. Flash memory can be categorized into Single-Level Cell (SLC) flash memory and Multi-Level Cell (MLC) flash memory based on its internal architecture. Each cell in SLC flash memory can store one bit of data, while each cell in MLC flash memory can store at least two bits of data. MLC flash memory includes two-level cell flash memory, three-level cell (TLC) flash memory, four-level cell (QLC) flash memory, and flash memory with even more levels of cells.

[0003] SLC (Single-Card-Low) storage offers smaller capacity but faster speeds and higher data stability and reliability. MLC, TLC, or QLC (Multi-Card-Low) storage, on the other hand, offer larger capacity but slower speeds and reduced data stability and reliability. Therefore, flash memory can support switching between at least two different storage modes during programming, reading, and erasing operations to better meet user needs. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a memory and its operation method, and a memory system.

[0005] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a memory, the memory comprising: a memory cell array including a plurality of word lines; and peripheral circuitry coupled to the memory cell array, configured to: discharge the word lines to a first discharge voltage in a first memory mode; and discharge the word lines to a second discharge voltage in a second memory mode; wherein the first discharge voltage and the second discharge voltage are different.

[0007] In some embodiments, the peripheral circuit includes a discharge circuit for discharging the word line; the discharge circuit includes: a first discharge circuit connected to the word line of the memory and configured to: in the first memory mode, during the process of discharging the word line to a first discharge voltage, cause the channel potential to be coupled down to a first coupling voltage; a second discharge circuit connected to the word line of the memory and configured to: in the second memory mode, during the process of discharging the word line to a second discharge voltage, cause the channel potential to be coupled down to a second coupling voltage; wherein the first coupling voltage and the second coupling voltage are different.

[0008] In some embodiments, the first storage mode includes a single-level cell mode, and the second storage mode includes a multi-level cell mode; wherein the first discharge voltage is greater than the second discharge voltage, and the first coupling voltage is greater than the second coupling voltage.

[0009] In some embodiments, the multi-level cell pattern includes a three-level cell pattern and / or a four-level cell pattern.

[0010] In some embodiments, the discharge circuit is used to discharge the memory after a read operation or a verification operation.

[0011] In some embodiments, the first discharge circuit is specifically configured to: discharge the voltage on the word line from the pass voltage to the first discharge voltage in the first storage mode.

[0012] In some embodiments, the second discharge circuit is specifically configured to: in the second storage mode, discharge the voltage on the word line from the through voltage to the second discharge voltage.

[0013] In some embodiments, the first discharge circuit is further configured to: discharge the voltage on the word line from the through voltage to the first discharge voltage in the second storage mode; the second discharge circuit is further configured to: discharge the voltage on the word line from the first discharge voltage to the second discharge voltage in the second storage mode.

[0014] In some embodiments, the first discharge circuit includes a first discharge transistor, the first discharge transistor including a first terminal, a second terminal and a control terminal, the first terminal of the first discharge transistor being connected to the word line of the memory, and the second terminal of the first discharge transistor being connected to the first discharge voltage; the second discharge circuit includes a second discharge transistor, the second discharge transistor including a first terminal, a second terminal and a control terminal, the first terminal of the second discharge transistor being connected to the word line of the memory and the first terminal of the first discharge transistor, and the second terminal of the second discharge transistor being connected to the second discharge voltage.

[0015] In some embodiments, in the second storage mode, the second discharge transistor is configured to be in a turned-off state, the first discharge transistor is configured to be in a turned-on state, and discharges the voltage on the word line to the first discharge voltage; the first discharge transistor is configured to be in a turned-off state, the second discharge transistor is configured to be in a turned-on state, and discharges the voltage on the word line from the first discharge voltage to the second discharge voltage.

[0016] In some embodiments, the peripheral circuitry further includes a selection circuit that connects the discharge circuit to the word line and is configured to select at least one of the plurality of word lines for discharge.

[0017] In some embodiments, the memory includes NAND flash memory.

[0018] Secondly, embodiments of this disclosure provide a method for operating a memory, the method comprising: discharging the word lines of the memory to a first discharge voltage in a first storage mode; and discharging the word lines of the memory to a second discharge voltage in a second storage mode; wherein the first discharge voltage and the second discharge voltage are different.

[0019] In some embodiments, discharging the word line of the memory to a first discharge voltage in a first storage mode includes: in the first storage mode, during the process of discharging the word line to the first discharge voltage, causing the channel potential to be coupled down to a first coupling voltage; in a second storage mode, discharging the word line of the memory to a second discharge voltage includes: in the second storage mode, during the process of discharging the word line to the second discharge voltage, causing the channel potential to be coupled down to a second coupling voltage; wherein the first coupling voltage and the second coupling voltage are different.

[0020] In some embodiments, the first storage mode includes a single-level cell mode, and the second storage mode includes a multi-level cell mode; wherein the first discharge voltage is greater than the second discharge voltage, and the first coupling voltage is greater than the second coupling voltage.

[0021] In some embodiments, the multi-level cell pattern includes a three-level cell pattern and / or a four-level cell pattern.

[0022] In some embodiments, the operation method is used to discharge the memory after a read operation or a verification operation.

[0023] In some embodiments, discharging the word line of the memory to a first discharge voltage in the first storage mode includes: in the first storage mode, a first discharge circuit discharges the voltage on the word line from the pass voltage to the first discharge voltage.

[0024] In some embodiments, discharging the word line of the memory to a second discharge voltage in the second storage mode includes: in the second storage mode, a second discharge circuit discharges the voltage on the word line from the through voltage to the second discharge voltage.

[0025] In some embodiments, discharging the word line of the memory to a second discharge voltage in the second storage mode includes: in the second storage mode, a first discharge circuit discharges the voltage on the word line from the through voltage to the first discharge voltage, and a second discharge circuit discharges the voltage on the word line from the first discharge voltage to the second discharge voltage.

[0026] Thirdly, embodiments of this disclosure provide a memory system, the memory system comprising: a memory as described in the above technical solutions; and a controller coupled to the memory, configured to control the memory.

[0027] This disclosure provides a memory and its operation method, as well as a memory system. The memory includes: a memory cell array comprising multiple word lines; and peripheral circuitry coupled to the memory cell array, configured to: discharge the word lines to a first discharge voltage in a first memory mode; and discharge the word lines to a second discharge voltage in a second memory mode; wherein the first discharge voltage and the second discharge voltage are different. In this disclosure, different discharge voltages are used in different memory modes to improve the peak current and average current during the next operation, thereby reducing the difference in peak current and average current caused by different memory modes. Attached Figure Description

[0028] Figure 1 A block diagram of a system with memory shown in an embodiment of this disclosure;

[0029] Figure 2A This is a schematic diagram of a memory card with memory according to an embodiment of the present disclosure;

[0030] Figure 2B This is a schematic diagram of a solid-state drive with memory shown in an embodiment of the present disclosure;

[0031] Figure 3 This is a schematic diagram of a memory including peripheral circuitry, as shown in an embodiment of this disclosure;

[0032] Figure 4 This is a schematic cross-sectional view of a storage cell array including storage strings, as shown in an embodiment of this disclosure.

[0033] Figure 5 A block diagram of a memory including peripheral circuitry, as shown in an embodiment of this disclosure;

[0034] Figure 6 Figure (a) shows the threshold voltage distribution in a single-stage unit mode. Figure 6 Figure (b) shows the threshold voltage distribution in the three-level unit mode;

[0035] Figure 7 Timing diagrams of word line and channel potentials are provided for some examples in single-level and three-level cell modes;

[0036] Figure 8 A schematic diagram of a memory including a discharge circuit provided for an embodiment of this disclosure;

[0037] Figure 9 Timing diagrams of word line and channel potentials provided for single-level cell mode and three-level cell mode in embodiments of this disclosure;

[0038] Figure 10 A schematic diagram of a discharge circuit provided in an embodiment of this disclosure;

[0039] Figure 11 Voltage timing diagrams provided for single-level cell mode and three-level cell mode in embodiments of this disclosure;

[0040] Figure 12 This is a flowchart illustrating the operation method of a memory provided in an embodiment of the present disclosure. Detailed Implementation

[0041] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0042] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0043] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0044] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0045] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0047] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0048] For ease of understanding, the memory in the embodiments of this disclosure is described using a three-dimensional NAND type memory as an example.

[0049] refer to Figure 1 , Figure 1 This is a block diagram of a system with memory shown in an embodiment of this disclosure. Figure 1 As shown, system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0050] like Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0051] In some embodiments, controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Controller 106 can manage data stored in memory 104 and communicate with host 108.

[0052] In some embodiments, the controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0053] In some embodiments, the controller 106 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multi-media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0054] Controller 106 can be configured to control the operation of memory 104, such as read, erase, and program operations. Controller 106 can also be configured to manage various functions relating to data stored or to be stored in memory 104, including but not limited to bad block management, garbage collection, logical address to physical address translation, wear leveling, etc. In some embodiments, controller 106 is also configured to process error correcting codes (ECCs) relating to data read from or written to memory 104.

[0055] Controller 106 can also perform any other suitable function, such as formatting memory 104. Controller 106 can communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0056] The controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0057] refer to Figure 2A , Figure 2A This is a schematic diagram of a memory card with memory according to an embodiment of this disclosure. Figure 2A As shown, controller 106 and a single memory 104 can be integrated into memory card 202. Memory card 202 may include Personal Computer Memory Card International Association (PCMCIA) cards, CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (e.g., MMC, Reduced-Size MMC (RS-MMC), microMMC), SD cards (e.g., SD, miniSD, microSD, Secure Digital High Capacity (SDHC)), UFS, etc. Memory card 202 may also include a connector for connecting memory card 202 to a host computer (e.g., ...). Figure 1 The memory card connector 204 is coupled to the host 108.

[0058] refer to Figure 2B , Figure 2B This is a schematic diagram of a solid-state drive with memory, as shown in an embodiment of this disclosure. Figure 2B As shown, controller 106 and multiple memories 104 can be integrated into solid-state drive 206. Solid-state drive 206 may also include a connection between solid-state drive 206 and a host (e.g., Figure 1 The solid-state drive connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0059] refer to Figure 3 , Figure 3 This is a schematic diagram illustrating a memory including peripheral circuitry, as shown in an embodiment of this disclosure. The memory 300 may be... Figure 1 An example of memory 104 is shown. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of memory strings 308, each memory string 308 on a substrate (…). Figure 3 (Not shown in the diagram) Extending vertically upwards. In some embodiments, each memory string 308 includes a plurality of memory cells 306 that are series-coupled and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0060] In some embodiments, each memory cell 306 may be an SLC having two possible memory states and thus capable of storing one bit of data. For example, an SLC may have a first memory state "1" and a second memory state "0", where the threshold voltage distribution of the first memory state "1" may correspond to a first voltage range, and the threshold voltage distribution of the second memory state "0" may correspond to a second voltage range. The first memory state is an erase state, and the second memory state is a programmable state. In some embodiments, each memory cell 306 is an MLC capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits of data per cell, three bits of data per cell (also known as a TLC), or four bits of data per cell (also known as a QLC). Each MLC may be programmed to take a voltage range of possible threshold voltage distributions. In one example, if each MLC stores two bits of data, the MLC may have a first memory state "11", a second memory state "10", a third memory state "01", and a fourth memory state "00", where the threshold voltage distributions of the first, second, third, and fourth memory states correspond to the first, second, third, and fourth voltage ranges, respectively. In this configuration, the first storage state is the erase state, while the second, third, and fourth storage states are all programming states. Similarly, a TLC can have 8 storage states, including an erase state and 7 programming states; a QLC can have 16 storage states, including an erase state and 15 programming states.

[0061] like Figure 3 As shown, each memory string 308 may include a source-selective transistor 310 (SST) at its source end and a drain-selective transistor 312 (DST) at its drain end. The source-selective transistor 310 and drain-selective transistor 312 may be configured to activate the selected memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of memory strings 308 within the same memory block 304 are coupled via the same source line 314 (SL) (e.g., common SL). In other words, in some embodiments, all memory strings 308 within the same memory block 304 have an array common source (ACS). In some embodiments, the drain of the drain-selective transistor 312 of each memory string 308 is coupled to a corresponding bit line 316 (BL), which can be connected via an output bus (…). Figure 3(Not shown in the diagram) Data is read from or written to bit line 316. In some embodiments, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the drain select transistor 312) or a deselection voltage (e.g., 0V) to the corresponding drain select transistor 312 via one or more drain selective lines 313 (DSL) and / or by applying a selection voltage (e.g., higher than the threshold voltage of the source select transistor 310) or a deselection voltage (e.g., 0V) to the corresponding source select transistor 310 via one or more source selective lines 315 (SSL).

[0062] like Figure 3 As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which can have a source line 314 (e.g., a common SL coupled to ground). In some embodiments, each memory block 304 is the basic data unit for performing an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage Vers (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source lines 314 of the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318 (WL), which select which row of memory cells 306 is affected by read and program operations.

[0063] It should be noted that for SLC, each storage unit can store 1 bit of information, so at the physical layer, the information stored in one storage unit (i.e., one physical page) corresponds to the information of one logical page. For MLC, each storage unit can store 2 bits of information, so at the physical layer, the information stored in one storage unit (i.e., one physical page) corresponds to the information of two logical pages. For TLC, each storage unit can store 3 bits of information, so at the physical layer, the information stored in one storage unit (i.e., one physical page) corresponds to the information of three logical pages. For QLC, each storage unit can store 4 bits of information, so at the physical layer, the information stored in one storage unit (i.e., one physical page) corresponds to the information of four logical pages.

[0064] refer to Figure 4 , Figure 4This is a schematic cross-sectional view of a storage cell array including storage strings, as shown in an embodiment of this disclosure. Figure 4 As shown, the memory string 308 may extend vertically through the memory stack layer 404 above the substrate 402. The substrate 402 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0065] The memory stack 404 may include alternating gate conductive layers 406 and gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate dielectric layers 408 in the memory stack 404 determines the number of memory cells 306 in the memory cell array 301. The gate conductive layers 406 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding the memory cell 306 and may extend laterally at the top of the memory stack 404 as a drain select gate line 313, at the bottom of the memory stack 404 as a source select gate line 315, or between the drain select gate line 313 and the source select gate line 315 as a word line 318.

[0066] like Figure 4 As shown, the memory string 308 includes a channel structure extending vertically through the memory stack layer 404. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a memory layer (also referred to as a "charge trap / memory layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, memory layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0067] According to some embodiments, a well (e.g., a P-well and / or an N-well) may be formed in the substrate 402, and the source terminal of the memory string 308 may be in contact with the well. For example, a source line may be coupled to the well to apply an erase voltage to the well (i.e., the source of the memory string) during an erase operation. In some embodiments, the memory string may also include a channel plug at the drain terminal of the memory string 308. It should be understood that, although in Figure 4 Additional components, not shown in the diagram, can form the memory cell array 301. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0068] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, source-select-gate line 315, and drain-select-gate line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, source-select-gate line 315, and drain-select-gate line 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0069] refer to Figure 5 , Figure 5 This is a block diagram of a memory including peripheral circuitry, as shown in an embodiment of this disclosure. Figure 5 As shown, the peripheral circuitry includes a page buffer / sensor amplifier 504, a column driver / bit line driver 506, a row driver / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516 (I / F), and a data bus 518. It should be understood that in some examples, additional components may be included. Figure 5 Additional peripheral circuits not shown in the diagram.

[0070] Page buffer / sensor amplifier 504 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic unit 512. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column driver / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0071] The row driver / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row driver / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row driver / word line driver 508 can also select / deselect and drive source select gate line 315 and drain select gate line 313. As described in detail below, the row driver / word line driver 508 is configured to perform an erase operation on memory cells 306 coupled to (one or more) the selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0072] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer slave devices (…). Figure 5(Not shown) The interface 516 receives control commands and relays them to the control logic unit 512, and buffers status information received from the control logic unit 512 and relays it to the host. The interface 516 can also be coupled to the column driver / bit line driver 506 via the data bus 518, and acts as a data input / output (I / O) interface and data buffer to buffer data and relay it to or from the memory cell array 301.

[0073] In programming, reading, and erasing operations, most current flash memory (e.g., 3D NAND flash memory) can support switching between at least two different storage modes, such as switching between SLC and TLC modes, or between SLC and QLC modes. As the storage capacity of a single die increases and the number of storage planes increases, the peak current for multi-plane operations becomes increasingly large, leading to increasingly stringent current limitations in flash memory applications.

[0074] Test data from flash memory shows that there is a significant difference in peak current during multi-memory plane operation between SLC and TLC modes. In order to meet current specifications, there may be situations where operation time is sacrificed to achieve the required current performance.

[0075] refer to Figure 6 , Figure 6 Figure (a) shows the threshold voltage distribution in single-level cell mode. Each storage cell of an SLC flash memory can store one bit of data. An SLC can have a first storage state "1" and a second storage state "0". Here, the threshold voltage distribution of the first storage state "1" can correspond to a first voltage range, and the threshold voltage distribution of the second storage state "0" can correspond to a second voltage range. The first storage state is the erase state P0, and the second storage state is the programming state P1. Using a read voltage (e.g., RD ​​0.1V) located between the first and second voltage ranges, a read operation can distinguish between storage cells with a threshold voltage less than the read voltage and storage cells with a threshold voltage greater than the read voltage; the storage cells with a threshold voltage less than the read voltage are in the first storage state, and the storage cells with a threshold voltage greater than the read voltage are in the second storage state. Figure 6 Figure (a) also illustrates that the upper limit of the threshold voltage distribution in the erase state P0 is -2.0V, and the lower limit of the threshold voltage distribution in the programming state P1 is 0.5V (i.e., vpv 0.5V).

[0076] refer to Figure 6 , Figure 6Figure (b) shows the threshold voltage distribution in the three-level cell mode. Each storage cell of TLC flash memory can store three bits of data. TLC can have a first storage state "111", a second storage state "011", a third storage state "001", a fourth storage state "000", a fifth storage state "010", a sixth storage state "110", a seventh storage state "100", and an eighth storage state "101". Here, the threshold voltage distribution of the first storage state "111" can correspond to the first voltage range, the threshold voltage distribution of the second storage state "011" can correspond to the second voltage range, the threshold voltage distribution of the third storage state "001" can correspond to the third voltage range, the threshold voltage distribution of the fourth storage state "000" can correspond to the fourth voltage range, the threshold voltage distribution of the fifth storage state "010" can correspond to the fifth voltage range, the threshold voltage distribution of the sixth storage state "110" can correspond to the sixth voltage range, the threshold voltage distribution of the seventh storage state "100" can correspond to the seventh voltage range, and the threshold voltage distribution of the eighth storage state "101" can correspond to the eighth voltage range. The first storage state is the erase state P0, and the second, third, fourth, fifth, sixth, seventh, and eighth storage states are the programming states P1, P2, P3, P4, P5, P6, and P7, respectively. Figure 6 Figure (b) also illustrates that the upper limit of the threshold voltage distribution in the erase state P0 is -2V, and the lower limit of the threshold voltage distribution in the programming state P7 is 3.5V (i.e., vpv73.5V).

[0077] The threshold voltage distribution differs significantly across different storage modes, combined with Figure 6 As shown in Figures (a) and (b), there is a significant difference in the threshold voltage distribution between SLC and TLC modes. Compared to SLC mode, the threshold voltage distribution range is wider in TLC mode, and the threshold voltage distribution of each memory state is denser. This means that the window between adjacent memory states is smaller in TLC mode, making it more difficult to distinguish between the erase state P0 and the various programming states. Similarly, there is an even more significant difference in the threshold voltage distribution between SLC and QLC modes.

[0078] refer to Figure 7 , Figure 7 Timing diagrams of word line and channel potentials are provided for some examples in single-level and three-level cell modes. For example... Figure 7 As shown, before the first time T1, a through voltage Vpass is applied to WL, and a voltage VSS is applied to the channel, meaning the channel potential is VSS. At the first time T1, WL begins to discharge, and the voltage on WL decreases. At this time, the memory cell connected to WL is in the conducting state, and the channel potential remains unchanged, i.e., the channel potential remains at VSS.

[0079] Compared to SLC mode, TLC mode has a wider threshold voltage distribution range and a higher threshold voltage. Although both SLC and TLC modes have multiple different storage states, the average threshold voltage of a storage cell in TLC mode is higher than that in SLC mode. Therefore, during the discharge process at WL, as the voltage across WL decreases, storage cells in TLC mode will reach the shutdown state earlier than those in SLC mode.

[0080] At the second time point T2, during the discharge process of WL, the memory cell connected to WL in TLC mode is in a turned-off state, and the channel potential in TLC mode begins to couple down (e.g., Figure 7 (The solid line represents the channel potential).

[0081] At the third moment T3, during the discharge process of WL, the memory cell connected to WL in SLC mode is in a turned-off state, and the channel potential in SLC mode begins to couple down (e.g., Figure 7 (The dashed line represents the channel potential). In other words, because the average threshold voltage of a memory cell in TLC mode is greater than that in SLC mode, during the discharge process of WL, the memory cell in TLC mode is off at time 2 (T2), while the memory cell in SLC mode is off at time 3 (T3). Time 2 (T2) is earlier than time 3 (T3). In other words, the higher threshold voltage of the memory cell in TLC mode results in an earlier and greater reduction in channel potential due to coupling; conversely, the lower threshold voltage of the memory cell in SLC mode results in a later and less significant reduction in channel potential due to coupling.

[0082] At the fourth time T4, the discharge process of WL ends, and the voltage on WL is the first voltage V1 (e.g., VSS). At this time, the channel potential in TLC mode (i.e., the third voltage V3) is less than the channel potential in SLC mode (i.e., the fourth voltage V4).

[0083] At time T5, the channel potential in both TLC and SLC modes can rise until it recovers to VSS. At this time, WL in both TLC and SLC modes can be coupled up. Since the difference between the channel potential and VSS in TLC mode (i.e., VSS - third voltage V3) is greater than the difference between the channel potential and VSS in SLC mode (i.e., VSS - fourth voltage V4), the coupling voltage of WL in TLC mode, i.e., the second voltage V2 (i.e., TLC float voltage level), is greater than the coupling voltage of WL in SLC mode, i.e., the fifth voltage V5 (i.e., SLC float voltage level).

[0084] In the above technical solution, when switching between TLC and SLC modes, both modes use the same discharge circuit and discharge voltage to discharge the voltage on WL to VSS. However, when the channel potential rises back to VSS, the difference between the coupling voltage of WL in TLC mode and the coupling voltage of WL in SLC mode is ΔV1, where ΔV1 = second voltage V2 - fifth voltage V5. In the above technical solution, during the next operation, all WL starts from VDD. Compared to TLC mode, SLC mode requires charging from a lower voltage to VDD, consuming more current. Therefore, the peak current and average current are greater during the next operation in SLC mode.

[0085] refer to Figure 8 , Figure 8 This is a schematic diagram of a memory including a discharge circuit, provided for an embodiment of this disclosure. (As shown...) Figure 8 As shown, this embodiment of the disclosure provides a memory 600, which includes: a memory cell array 602, the memory cell array 602 including a plurality of word lines 606; and peripheral circuitry 604 coupled to the memory cell array 602 (such as...). Figure 8 As shown in the dashed box in the middle, it is configured to: discharge word line 606 to a first discharge voltage in a first storage mode; and discharge word line 606 to a second discharge voltage in a second storage mode; wherein the first discharge voltage and the second discharge voltage are different.

[0086] Here, for a description of the memory cell array, please refer to [reference needed]. Figure 3 Related descriptions.

[0087] Here, the peripheral circuitry 604 includes a page buffer / sensor amplifier 608, a column driver / bit line driver 610, a row driver / word line driver 612, a voltage generator 614, and a control logic unit 616. For a description of the page buffer / sensor amplifier, column driver / bit line driver, row driver / word line driver, voltage generator, and control logic unit, please refer to [reference needed]. Figure 5 Related descriptions.

[0088] In this embodiment of the disclosure, different discharge voltages are used in different storage modes to improve the peak current and average current during the next operation, thereby reducing the difference between peak current and average current caused by different storage modes and thus improving the reliability of the memory.

[0089] In some embodiments, the memory includes NAND flash memory.

[0090] Here, the NAND type memory provided in the embodiments of this disclosure is used as an example for explanation.

[0091] In some embodiments, the peripheral circuit 604 includes a voltage generator 614, which includes a voltage generation circuit 618 and a discharge circuit 626. The discharge circuit 626 is used to discharge the word line 606. The discharge circuit 626 includes: a first discharge circuit 628 connected to the word line 606 of the memory, configured to: in a first memory mode, during the discharge of the word line 606 to a first discharge voltage, cause the channel potential to be coupled down to a first coupling voltage; and a second discharge circuit 632 connected to the word line 606 of the memory, configured to: in a second memory mode, during the discharge of the word line 606 to a second discharge voltage, cause the channel potential to be coupled down to a second coupling voltage; wherein the first coupling voltage and the second coupling voltage are different.

[0092] Here, different discharge voltages are used for different storage modes. Specifically, the first discharge circuit 628 discharges WL in the first storage mode to a first discharge voltage, at which point the channel potential is coupled down to a first coupling voltage; the second discharge circuit 632 discharges WL in the second storage mode to a second discharge voltage, at which point the channel potential is coupled down to a second coupling voltage. Because the discharge voltage is different in different storage modes, the degree to which the channel potential is coupled down is different, resulting in different channel potentials.

[0093] Here, voltage generator 614 also includes voltage generation circuit 618, which includes programming voltage generation circuit 620. Programming voltage generation circuit 620 generates programming voltage Vpgm in response to control signals provided by control logic unit 616. Programming voltage generation circuit 620 provides programming voltage Vpgm to the selected word line.

[0094] Here, the voltage generation circuit 618 further includes a verification / read voltage generation circuit 622, which generates a programming verification voltage Vvfy, a read verification voltage Vrd, and an erase verification voltage Vev in response to a control signal provided by the control logic unit 616. The verification / read voltage generation circuit 622 provides the programming verification voltage Vvfy, the read verification voltage Vrd, and the erase verification voltage Vev to the selected word line.

[0095] Here, the voltage generation circuit 618 also includes a voltage generation circuit 624, which generates a pass voltage Vpass in response to a control signal provided by the control logic unit 616. The voltage generation circuit 624 provides the pass voltage Vpass to the unselected word line.

[0096] In some embodiments, the peripheral circuit 604 further includes a selection circuit 636 that connects the discharge circuit 626 to the word line 606 and is configured to select at least one of the multiple word lines 606 for discharge.

[0097] Here, the peripheral circuit 604 also includes a selection circuit 636, which is configured to select at least one word line among the multiple word lines 606 for discharge. For example, the selection circuit 636 is configured to select an unselected word line among the multiple word lines 606, that is, to select the pass voltage Vpass on the unselected word line for discharge.

[0098] As previously described, both the programming voltage generation circuit 620 and the verification / read voltage generation circuit 622 provide their generated voltages to the selected word lines, and the voltage generation circuit 624 provides its generated voltages to the unselected word lines. The programming voltage generation circuit 620, the verification / read voltage generation circuit 622, the voltage generation circuit 624, and the discharge circuit 626 operate on different word lines. Figure 8 The explanation only uses the selection circuit 636 as an example and does not show the specific structure of the selection circuit 636 in detail.

[0099] In some embodiments, the first storage mode includes a single-level cell mode, and the second storage mode includes a multi-level cell mode; wherein the first discharge voltage is greater than the second discharge voltage, and the first coupling voltage is greater than the second coupling voltage.

[0100] Here, the first storage mode may include SLC mode, and the second storage mode may include MLC mode, TLC mode, QLC mode, or more levels of cell mode. The discharge circuit provided in this disclosure is applicable not only to switching between SLC mode and TLC mode, but also to switching between SLC mode and QLC mode, and to switching between more levels of cell mode and SLC mode, thereby improving the peak current and average current when performing the next operation in SLC mode.

[0101] In some embodiments, the multi-level cell pattern includes a three-level cell pattern and / or a four-level cell pattern.

[0102] Here, we will use TLC mode as an example for explanation. (Reference) Figure 9 , Figure 9 Timing diagrams of word line and channel potentials provided for single-level cell mode and three-level cell mode in embodiments of this disclosure. (See diagrams for example.) Figure 9 As shown, before the first time T1, a through voltage Vpass is applied to WL, and a channel voltage VSS is applied to the channel, i.e., the channel potential is VSS. At the first time T1, WL begins to discharge, and the voltage on WL decreases. At this time, the memory cell connected to WL is in the conducting state, and the channel potential remains unchanged, i.e., the channel potential remains at VSS.

[0103] At the second time point T2, during the discharge process of WL, the memory cell connected to WL in TLC mode is in a turned-off state, and the channel potential in TLC mode begins to couple down (e.g., Figure 9 (The solid line represents the channel potential).

[0104] At the third moment T3, during the discharge process of WL, the memory cell connected to WL in SLC mode is in a turned-off state, and the channel potential in SLC mode begins to couple down (e.g., Figure 9 (As shown by the dashed line representing the channel potential). In other words, the threshold voltage of a memory cell in TLC mode is higher, the channel potential is coupled down earlier, and the channel potential is coupled down more; the threshold voltage of a memory cell in SLC mode is lower, the channel potential is coupled down later, and the channel potential is coupled down less.

[0105] At the fourth time T4, the discharge process of WL ends. WL in TLC mode discharges to the second discharge voltage (i.e., the first voltage V1), and the channel potential in TLC mode is the second coupling voltage (i.e., the third voltage V3). WL in SLC mode discharges to the first discharge voltage (i.e., the sixth voltage V6), and the channel potential in TLC mode is the first coupling voltage (i.e., the seventh voltage V7).

[0106] Here, the first discharge voltage (i.e., the sixth voltage V6) is greater than the second discharge voltage (i.e., the first voltage V1). In other words, the TLC mode uses a relatively small discharge voltage, while the SLC mode uses a relatively large discharge voltage.

[0107] Here, the first coupling voltage (the seventh voltage V7) is greater than the second coupling voltage (i.e., the third voltage V3). In other words, the channel potential is reduced more by coupling in TLC mode, resulting in a smaller channel potential; while the channel potential is reduced less by coupling in SLC mode, resulting in a larger channel potential.

[0108] It should be noted that, Figure 7 This illustrates that the same discharge voltage is used in different storage modes. The voltage on WL in SLC mode is the same as the voltage on WL in TLC mode, both being the first voltage V1; while Figure 9 This illustrates that different discharge voltages are used in different storage modes. The voltage on WL in SLC mode is greater than the voltage on WL in TLC mode, that is, the sixth voltage V6 is greater than the first voltage V1. Figure 7 The difference between the channel potential in SLC mode and the channel potential in TLC mode (i.e., fourth voltage V4 - third voltage V3) is less than Figure 9 The difference between the channel potential in SLC mode and the channel potential in TLC mode is shown (i.e., seventh voltage V7 - third voltage V3).

[0109] At time T5, the channel potential in both TLC and SLC modes can rise until it recovers to VSS. At this time, WL in both TLC and SLC modes can couple upwards. Since the difference between the channel potential and VSS in TLC mode (i.e., VSS - third voltage V3) is greater than the difference between the channel potential and VSS in SLC mode (i.e., VSS - fourth voltage V4), the coupling voltage of WL in TLC mode (i.e., TLC float voltage level) is greater than the coupling voltage of WL in SLC mode (i.e., SLC float voltage level), meaning the second voltage V2 is greater than the eighth voltage V8.

[0110] It should be noted that, Figure 7 The diagram illustrates that in SLC mode, the voltage on WL is coupled up from the first voltage V1 to the fifth voltage V5. Figure 9 The diagram illustrates that in SLC mode, the voltage on WL is coupled up from the sixth voltage V6 to the eighth voltage V8. Thus, Figure 7 The difference ΔV1 between the coupling voltage of WL in TLC mode and the coupling voltage of WL in SLC mode is shown to be greater than... Figure 9 The difference ΔV2 between the coupling voltage of WL in TLC mode and the coupling voltage of WL in SLC mode is shown, that is, (second voltage V2 - fifth voltage V5) is greater than (second voltage V2 - eighth voltage V8).

[0111] In the above technical solution, when switching between TLC and SLC modes, different discharge circuits and discharge voltages are used in TLC and SLC modes. During the next operation, all WL (Wireless Storage) loops start from VDD. The difference between the coupling voltage of WL in TLC mode and the coupling voltage of WL in SLC mode is smaller, which helps to improve the peak current and average current during the next operation, thereby reducing the difference in peak current and average current caused by different storage modes, and thus improving the reliability of the memory.

[0112] In some embodiments, the discharge circuit 626 is used to discharge the word line 606 of the memory after a read operation or a verification operation.

[0113] Here, during a read operation, a read voltage is applied to the selected character line, and a read pass voltage is applied to the unselected character line; during a verification operation, a verification voltage is applied to the selected character line, and a verification pass voltage is applied to the unselected character line. Therefore, the discharge circuit 626 provided in this embodiment is particularly suitable for discharging the pass voltage on the unselected character line.

[0114] Combination Figure 8 and Figure 9 As shown, in some embodiments, the first discharge circuit 628 is specifically configured to: discharge the voltage on the word line from the pass voltage Vpass to a first discharge voltage (i.e., the sixth voltage V6) in a first storage mode. In some embodiments, the second discharge circuit 632 is specifically configured to: discharge the voltage on the word line from the pass voltage Vpass to a second discharge voltage (i.e., the first voltage V1) in a second storage mode.

[0115] Here, a first discharge circuit 628 is used to discharge the word lines in the first storage mode, and a second discharge circuit 632 is used to discharge the word lines in the second storage mode. In some embodiments, in the first storage mode, the first discharge circuit 628 is used alone to discharge the word lines; and in the second storage mode, the second discharge circuit 632 is used alone to discharge the word lines.

[0116] In some embodiments, the first discharge circuit 628 is further configured to: discharge the voltage on the word line from the pass voltage Vpass to the first discharge voltage (i.e., the sixth voltage V6) in the second storage mode; the second discharge circuit 632 is further configured to: discharge the voltage on the word line from the first discharge voltage (i.e., the sixth voltage V6) to the second discharge voltage (i.e., the first voltage V1) in the second storage mode.

[0117] Here, considering that directly discharging the word line from the through voltage Vpass to the second discharge voltage in the second storage mode may result in excessive voltage changes on the word line before and after discharge, the first discharge circuit 628 and the second discharge circuit 632 can be used simultaneously to perform segmented discharge of the word line in the second storage mode. The first discharge circuit 628 is used to discharge the word line to the first discharge voltage first, and the second discharge circuit 632 is used to discharge the word line to the second discharge voltage later.

[0118] In other embodiments, in a first storage mode, the first discharge circuit 628 is used alone to discharge the word lines; and in a second storage mode, the first discharge circuit 628 and the second discharge circuit 632 are used sequentially to discharge the word lines.

[0119] For example, SLC mode can use the potential VCC or VDD near VDD as the first discharge voltage, while TLC / QLC mode can use a lower VDD or VSS as the second discharge voltage. TLC / QLC mode can perform segmented discharge, first discharging to VCC or VDD, and then discharging to a lower target potential VSS.

[0120] refer to Figure 10 , Figure 10 This is a schematic diagram of a discharge circuit provided in an embodiment of this disclosure. Figure 10 As shown, in some embodiments, the first discharge circuit 628 includes a first discharge transistor 630. The first discharge transistor 630 includes a first terminal 630a, a second terminal 630b, and a control terminal 630c. The first terminal 630a of the first discharge transistor is connected to the word line of the memory, the second terminal 630b of the first discharge transistor is connected to a first discharge voltage (e.g., VCC), and the control terminal 630c of the first discharge transistor is... Figure 10 The gate1 shown is as follows (e.g.) Figure 10(As shown in the dashed circle); the second discharge circuit 632 includes a second discharge transistor 634, which includes a first terminal 634a, a second terminal 634b, and a control terminal 634c. The first terminal 634a of the second discharge transistor is connected to the word line of the memory and the first terminal 630a of the first discharge transistor. The second terminal 634b of the second discharge transistor is connected to a second discharge voltage (e.g., VSS). The control terminal 634c of the second discharge transistor is... Figure 10 The illustrated gate2 (e.g.) Figure 10 (As shown in the dashed circle). For example, the first discharge voltage VCC is greater than the second discharge voltage VSS.

[0121] also, Figure 10 Other circuits connected to the selection circuit 636 are also illustrated; these other circuits can be, for example... Figure 8 The voltage generation circuits shown, such as programming voltage generation circuits, verification / reading voltage generation circuits, or voltage generation circuits, can also be implemented using transistors.

[0122] In some embodiments, in the second storage mode, the second discharge transistor 634 is configured to be in the off state, the first discharge transistor 630 is configured to be in the on state, and discharges the voltage on the word line to the first discharge voltage; the first discharge transistor 630 is configured to be in the off state, the second discharge transistor 634 is configured to be in the on state, and discharges the voltage on the word line from the first discharge voltage to the second discharge voltage.

[0123] refer to Figure 11 , Figure 11 Voltage timing diagrams for single-level and three-level cell modes provided in embodiments of this disclosure. For example... Figure 11 As shown, under SLC path control, the control terminal gate1 of the first discharge transistor is at a high level, and the control terminal gate2 of the second discharge transistor is at a low level. At this time, the first discharge transistor is configured to be in the on state, and the second discharge transistor is configured to be in the off state. In SLC mode, the first discharge transistor discharges the word line, causing the word line to discharge from the current voltage to the first discharge voltage. Subsequently, the control terminal gate1 of the first discharge transistor is at a low level, and the control terminal gate2 of the second discharge transistor is at a low level. At this time, the first discharge transistor is configured to be in the off state, and the second discharge transistor is configured to be in the off state.

[0124] In TLC path control mode, the control terminal gate1 of the first discharge transistor is at a high level, and the control terminal gate2 of the second discharge transistor is at a low level. At this time, the first discharge transistor is configured to be in the ON state, and the second discharge transistor is configured to be in the OFF state. In TLC mode, the first discharge transistor discharges the word line, causing the word line to discharge from the current voltage to the first discharge voltage. Then, the control terminal gate1 of the first discharge transistor is at a low level, and the control terminal gate2 of the second discharge transistor is at a high level. At this time, the first discharge transistor is configured to be in the OFF state, and the second discharge transistor is configured to be in the ON state. In TLC mode, the second discharge transistor discharges the word line, causing the word line to discharge from the first discharge voltage to the second discharge voltage.

[0125] Therefore, in the second storage mode, segmented discharge can be used to reuse the first discharge transistor, saving circuit space.

[0126] In some embodiments, the first discharge transistor and the second discharge transistor may include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs). Exemplarily, the first discharge transistor and the second discharge transistor may include NMOS transistors.

[0127] refer to Figure 12 , Figure 12 This is a flowchart illustrating the operation method of a memory provided in an embodiment of the present disclosure.

[0128] like Figure 12 As shown, this disclosure provides a method for operating a memory, the method including:

[0129] Step S1201: In the first storage mode, discharge the word lines of the memory to the first discharge voltage;

[0130] Step S1202: In the second storage mode, the word lines of the memory are discharged to a second discharge voltage; wherein the first discharge voltage and the second discharge voltage are different.

[0131] In this embodiment of the disclosure, different discharge voltages are used in different storage modes by mode signal control to improve the peak current and average current when performing the next operation, especially to improve the peak current and average current when performing the next operation in SLC mode, thereby reducing the difference in peak current and average current caused by different storage modes.

[0132] In some embodiments, step S1201 includes: in a first storage mode, during the process of discharging the word line to a first discharge voltage, causing the channel potential to be coupled down to a first coupling voltage; step S1202 includes: in a second storage mode, during the process of discharging the word line to a second discharge voltage, causing the channel potential to be coupled down to a second coupling voltage; wherein the first coupling voltage and the second coupling voltage are different.

[0133] In some embodiments, the first storage mode includes a single-level cell mode, and the second storage mode includes a multi-level cell mode; wherein the first discharge voltage is greater than the second discharge voltage, and the first coupling voltage is greater than the second coupling voltage.

[0134] In some embodiments, the multi-level cell pattern includes a three-level cell pattern and / or a four-level cell pattern.

[0135] In some embodiments, the operation method is used to discharge the memory after a read operation or a verification operation.

[0136] In some embodiments, step S1201 includes: in a first storage mode, a first discharge circuit discharges the voltage on the word line from the pass voltage to a first discharge voltage.

[0137] In some embodiments, step S1202 includes: in the second storage mode, the second discharge circuit discharges the voltage on the word line from the through voltage to the second discharge voltage.

[0138] In some embodiments, step S1202 includes: in a second storage mode, a first discharge circuit discharges the voltage on the word line from the through voltage to a first discharge voltage, and a second discharge circuit discharges the voltage on the word line from the first discharge voltage to a second discharge voltage.

[0139] like Figure 1 As shown, this disclosure provides a memory system 102, which includes: a memory 104 as described above; and a controller 106 coupled to the memory 104 and configured to control the memory 104.

[0140] This disclosure provides a memory and its operation method, as well as a memory system. The memory includes: a memory cell array comprising multiple word lines; and peripheral circuitry coupled to the memory cell array, configured to: discharge the word lines to a first discharge voltage in a first memory mode; and discharge the word lines to a second discharge voltage in a second memory mode; wherein the first discharge voltage and the second discharge voltage are different. In this disclosure, different discharge voltages are used in different memory modes to improve the peak current and average current during the next operation, thereby reducing the difference in peak current and average current caused by different memory modes.

[0141] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0142] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory, characterized in that, The memory includes: A memory cell array, the memory cell array including multiple word lines; and The peripheral circuitry coupled to the memory cell array is configured to: discharge the word line to a first discharge voltage in a first memory mode; and discharge the word line to a second discharge voltage in a second memory mode; wherein the first discharge voltage and the second discharge voltage are different.

2. The memory according to claim 1, characterized in that, The peripheral circuit includes a discharge circuit, which is used to discharge the word line; the discharge circuit includes: A first discharge circuit, connected to the word line of the memory, is configured to: during the discharge of the word line to a first discharge voltage in the first memory mode, cause the channel potential to be coupled down to a first coupling voltage. A second discharge circuit, connected to the word line of the memory, is configured to: in the second memory mode, during the discharge of the word line to a second discharge voltage, cause the channel potential to be coupled down to a second coupling voltage; wherein the first coupling voltage and the second coupling voltage are different.

3. The memory according to claim 2, characterized in that, The first storage mode includes a single-level cell mode, and the second storage mode includes a multi-level cell mode; wherein the first discharge voltage is greater than the second discharge voltage, and the first coupling voltage is greater than the second coupling voltage.

4. The memory according to claim 3, characterized in that, The multi-level unit pattern includes a three-level unit pattern and / or a four-level unit pattern.

5. The memory according to claim 3, characterized in that, The discharge circuit is used to discharge the memory after a read operation or a verification operation.

6. The memory according to claim 5, characterized in that, The first discharge circuit is specifically configured to: in the first storage mode, discharge the voltage on the word line from the pass voltage to the first discharge voltage.

7. The memory according to claim 6, characterized in that, The second discharge circuit is specifically configured to: in the second storage mode, discharge the voltage on the word line from the through voltage to the second discharge voltage.

8. The memory according to claim 6, characterized in that, The first discharge circuit is further configured to: in the second storage mode, discharge the voltage on the word line from the through voltage to the first discharge voltage; The second discharge circuit is further configured to discharge the voltage on the word line from the first discharge voltage to the second discharge voltage in the second storage mode.

9. The memory according to claim 3, characterized in that, The first discharge circuit includes a first discharge transistor, which includes a first terminal, a second terminal, and a control terminal. The first terminal of the first discharge transistor is connected to the word line of the memory, and the second terminal of the first discharge transistor is connected to the first discharge voltage. The second discharge circuit includes a second discharge transistor, which includes a first terminal, a second terminal, and a control terminal. The first terminal of the second discharge transistor is connected to the word line of the memory and the first terminal of the first discharge transistor, and the second terminal of the second discharge transistor is connected to the second discharge voltage.

10. The memory according to claim 9, characterized in that, In the second storage mode, the second discharge transistor is configured to be in the off state, the first discharge transistor is configured to be in the on state, and discharges the voltage on the word line to the first discharge voltage; the first discharge transistor is configured to be in the off state, the second discharge transistor is configured to be in the on state, and discharges the voltage on the word line from the first discharge voltage to the second discharge voltage.

11. The memory according to claim 2, characterized in that, The peripheral circuit also includes a selection circuit that connects the discharge circuit to the word line and is configured to select at least one word line among the plurality of word lines for discharge.

12. The memory according to claim 1, characterized in that, The memory includes: NAND type memory.

13. A method for operating a memory, characterized in that, The operation method includes: In the first storage mode, the word lines of the memory are discharged to a first discharge voltage; In the second storage mode, the word lines of the memory are discharged to a second discharge voltage; wherein the first discharge voltage and the second discharge voltage are different.

14. The method of operating the memory according to claim 13, characterized in that, In the first storage mode, discharging the word line of the memory to a first discharge voltage includes: In the first storage mode, during the process of discharging the word line to the first discharge voltage, the channel potential is coupled down to the first coupling voltage. In the second storage mode, discharging the word lines of the memory to a second discharge voltage includes: In the second storage mode, during the process of discharging the word line to the second discharge voltage, the channel potential is coupled down to the second coupling voltage; wherein the first coupling voltage and the second coupling voltage are different.

15. The method of operating the memory according to claim 14, characterized in that, The first storage mode includes a single-level cell mode, and the second storage mode includes a multi-level cell mode; wherein the first discharge voltage is greater than the second discharge voltage, and the first coupling voltage is greater than the second coupling voltage.

16. The method of operating the memory according to claim 15, characterized in that, The multi-level unit pattern includes a three-level unit pattern and / or a four-level unit pattern.

17. The method of operating the memory according to claim 15, characterized in that, The operation method is used to discharge the memory after a read operation or a verification operation.

18. The method of operating the memory according to claim 17, characterized in that, In the first storage mode, discharging the word line of the memory to a first discharge voltage includes: In the first storage mode, the first discharge circuit discharges the voltage on the word line from the pass voltage to the first discharge voltage.

19. The method of operating the memory according to claim 18, characterized in that, In the second storage mode, discharging the word lines of the memory to a second discharge voltage includes: In the second storage mode, the second discharge circuit discharges the voltage on the word line from the through voltage to the second discharge voltage.

20. The method of operating the memory according to claim 18, characterized in that, In the second storage mode, discharging the word lines of the memory to a second discharge voltage includes: In the second storage mode, the first discharge circuit discharges the voltage on the word line from the through voltage to the first discharge voltage, and the second discharge circuit discharges the voltage on the word line from the first discharge voltage to the second discharge voltage.

21. A memory system, characterized in that, The memory system includes: The memory as described in any one of claims 1 to 12; and A controller coupled to the memory is configured to control the memory.

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