Memory device, operation method thereof and memory system

Abstract

The embodiment of the invention provides a memory device, an operation method thereof and a memory system. The memory device comprises a memory cell array; a peripheral circuit coupled to the memory cell array, the peripheral circuit configured to: determine a target voltage difference according to a target programming voltage; determining a channel boost voltage according to the difference between the target programming voltage and the target voltage difference; in a channel boosting stage, applying the channel boosting voltage to a selected word line; in a programming pulse stage, the target programming voltage is applied to the selected word line.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device and its operation method, and a memory system. Background Technology

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) flash memory has become the mainstream product in the memory market due to its high storage density, controllable production cost, suitable erasure speed, and retention characteristics.

[0003] With the increasing demands on memory devices, improving programming efficiency has become one of the most pressing technical problems to be solved in this field. Summary of the Invention

[0004] This disclosure provides a memory device, its operation method, and a memory system.

[0005] In a first aspect, embodiments of this disclosure provide a memory device, the memory device comprising: a memory cell array; and peripheral circuitry coupled to the memory cell array, the peripheral circuitry being configured to: determine a target voltage difference based on a target programming voltage; determine a channel boost voltage based on the difference between the target programming voltage and the target voltage difference; apply the channel boost voltage to a selected word line during a channel boost phase; and apply the target programming voltage to the selected word line during a programming pulse phase.

[0006] In one alternative implementation, the magnitude of the target voltage difference is positively correlated with the magnitude of the target programming voltage.

[0007] In one alternative implementation, the target pressure differential increases during the programming of the selected memory cell.

[0008] In one alternative implementation, the peripheral circuit is configured to: compare the target programming voltage with a preset value; and determine the target voltage difference based on the comparison result.

[0009] In one optional implementation, the peripheral circuit is configured to: determine the target voltage difference as a first target voltage difference when the target programming voltage is less than or equal to the preset value; and determine the target voltage difference as a second target voltage difference when the target programming voltage is greater than the preset value; wherein the first target voltage difference is less than the second target voltage difference.

[0010] In one optional implementation, the control logic is configured to: determine the target voltage difference as a first target voltage difference when the target programming voltage is less than or equal to a first preset value; determine the target voltage difference as a second target voltage difference when the target programming voltage is greater than the first preset value and less than or equal to a second preset value; and determine the target voltage difference as a third target voltage difference when the target programming voltage is greater than the second preset value; wherein the first target voltage difference is less than the second target voltage difference, the second target voltage difference is less than the third target voltage difference, and the first preset value is less than the second preset value.

[0011] In one optional implementation, the peripheral circuitry includes control logic and a first voltage generator coupled to the control logic; the control logic is configured to: control the first voltage generator to generate the channel boost voltage and apply the channel boost voltage to a selected word line; control the first voltage generator to generate the target programming voltage and apply the target programming voltage to the selected word line.

[0012] In one alternative implementation, the peripheral circuitry further includes a row driver, wherein the first voltage generator is coupled to the selected word line via a first transistor in the row driver; the control logic is configured to: during a channel boost phase, turn on the first transistor to output a channel boost voltage generated by the first voltage generator to the selected word line; and during a programming pulse phase, turn on the first transistor to output a target programming voltage generated by the first voltage generator to the selected word line.

[0013] In one alternative implementation, the peripheral circuitry further includes a second voltage generator coupled to the control logic; the control logic is configured to: control the voltage generated by the second voltage generator to rise to a first voltage, and during the programming pulse phase, apply the first voltage to the gate of the first transistor to turn on the first transistor.

[0014] In a second aspect, embodiments of this disclosure provide a memory system, including: a memory device as described in any of the first aspects; and a memory controller; the memory controller being coupled to the memory device and used to control the memory device.

[0015] Thirdly, embodiments of this disclosure provide an operating method for a memory device, the operating method comprising: determining a target voltage difference based on a target programming voltage; determining a channel boost voltage based on the difference between the target programming voltage and the target voltage difference; applying the channel boost voltage to a selected word line during a channel boost phase; and applying the target programming voltage to the selected word line during a programming pulse phase.

[0016] In one alternative implementation, the magnitude of the target voltage difference is positively correlated with the magnitude of the target programming voltage.

[0017] In one alternative implementation, the target pressure differential increases during the programming of the selected memory cell.

[0018] In one optional implementation, determining the target voltage difference based on the target programming voltage includes: comparing the target programming voltage with a preset value; and determining the target voltage difference based on the comparison result.

[0019] In one optional implementation, determining the target voltage difference based on the comparison result includes: determining the target voltage difference as a first target voltage difference when the target programming voltage is less than or equal to the preset value; and determining the target voltage difference as a second target voltage difference when the target programming voltage is greater than the preset value; wherein the first target voltage difference is less than the second target voltage difference.

[0020] In one optional implementation, determining the target voltage difference based on the comparison result includes: determining the target voltage difference as a first target voltage difference when the target programming voltage is less than or equal to a first preset value; determining the target voltage difference as a second target voltage difference when the target programming voltage is greater than the first preset value and less than or equal to a second preset value; and determining the target voltage difference as a third target voltage difference when the target programming voltage is greater than the second preset value; wherein the second target voltage difference is less than the third target voltage difference, and the first preset value is less than the second preset value.

[0021] This disclosure provides a memory device and its operation method, a memory system, comprising: a memory cell array; and peripheral circuitry coupled to the memory cell array. The peripheral circuitry is configured to: determine a target voltage difference based on a target programming voltage; determine a channel boost voltage based on the difference between the target programming voltage and the target voltage difference; apply the channel boost voltage to a selected word line during a channel boost phase; and apply the target programming voltage to the selected word line during a programming pulse phase. In this disclosure, the target voltage difference is determined based on the target programming voltage; and the channel boost voltage is determined based on the difference between the target programming voltage and the target voltage difference. That is, in this disclosure, the target voltage difference changes with the target programming voltage, thereby controlling the target voltage difference within a certain range, thus avoiding damage to the first transistor M1 due to a high voltage difference and avoiding a longer programming time (tProg) due to a low voltage difference. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0023] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0024] Figure 2b This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0025] Figure 3a This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0026] Figure 3b This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure;

[0027] Figure 4 This is a schematic cross-sectional view of a memory array including NAND memory strings according to an embodiment of the present disclosure.

[0028] Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure;

[0029] Figure 6 This is a schematic diagram of the voltage timing on each element at different stages of the programming loop in one embodiment of the present disclosure;

[0030] Figure 7 This is a schematic diagram of the connections between the various elements in the memory according to an embodiment of the present disclosure;

[0031] Figure 8 This is a schematic diagram of word line voltage timing during different programming cycles in an embodiment of the present disclosure.

[0032] Figure 9 This illustration shows the word line voltage during different programming cycles in one embodiment of the present disclosure. Figure 1 ;

[0033] Figure 10 This is a schematic diagram of word line voltages during different programming cycles in one embodiment of the present disclosure;

[0034] Figure 11 This is a schematic diagram illustrating the implementation flow of an operation method for a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0035] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0037] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0041] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0042] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0043] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0044] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0045] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0046] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2a In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0047] Figure 3a An exemplary schematic diagram of a storage cell array for a three-dimensional NAND flash memory is provided, such as... Figure 3a As shown, the memory cell array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered memory cell rows parallel to the gate isolation structure. Each two rows of memory cell rows are separated by a gate isolation structure and an up-select gate isolation structure. Each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple memory blocks. Multiple second gate isolation structures can divide the memory blocks into multiple finger memory regions. An up-select gate isolation structure located in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory chips. Figure 3a The memory block shown contains 6 memory chips; however, in practical applications, the number of memory chips in a memory block is not limited to this. A memory cell in a memory block coupled to a word line can be called a memory page.

[0048] It should be noted that, Figure 3aThe number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0049] Figure 3b A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0050] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0051] like Figure 3bAs shown, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of NAND memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0052] like Figure 3b As shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304a, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block 304a and the unselected memory block 304b on the same face as the selected memory block 304a. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0053] Figure 4 A schematic cross-sectional view of an exemplary memory array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 4As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 can determine the number of memory cells included in the memory array 401.

[0054] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0055] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0056] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0057] Return to reference Figure 3b The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0058] Page buffer / sensor amplifier 504 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0059] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0060] In some specific embodiments, the programming operation may include multiple stages. For example, the programming operation may include a pre-charge stage, a channel boost stage, a programming pulse stage, and a recovery stage. In the pre-charge stage, a voltage generator may generate the voltage required for the next stage, such as the voltage applied to each gate, the channel boost voltage, etc.; in the channel boost stage, a channel boost voltage may be applied to the selected word line; in the programming pulse stage, the target programming voltage for each programming operation may be applied to the selected word line. In the recovery stage, the voltage may be reduced to the corresponding voltage, such as Vcc or Vdd, for both non-selected and selected word lines. The recovery stage may achieve this by stepping down the voltage to the corresponding voltage once or multiple times, for example, by first reducing the voltage to an intermediate voltage, maintaining it at that intermediate voltage for a period of time, and then reducing it to the corresponding voltage.

[0061] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0062] Figure 6This is a schematic diagram of the voltage timing on each element at different stages of the programming loop in one embodiment of the present disclosure; Figure 7 This is a schematic diagram of the connections between the various elements in the memory according to an embodiment of the present disclosure.

[0063] like Figure 6 As shown, during the channel boost phase, the selected word line (Sel wl) will rise to the channel boost voltage (WL_middle), such as 6.5V. During the programming pulse, the selected word line will rise to the target programming voltage (WL_target). Furthermore, the selected word line is connected to a first voltage generator (Vpe), and the voltage rise of the first voltage generator leads to the voltage rise of the selected word line to the target programming voltage. The boost voltage (Vpe_middle) of the first voltage generator is the same as or only slightly different from the channel boost voltage (WL_middle), and the target voltage (Vpe_target) of the first voltage generator is the same as or only slightly different from the target programming voltage (WL_target). Here, the first voltage generator is coupled to the selected word line. The voltage relationship between the two can be understood as follows: the boost voltage (Vpe_middle) is the same as or slightly different from the channel boost voltage (WL_middle), and the target voltage (Vpe_target) is the same as or slightly different from the target programming voltage (WL_target). This slight difference may be due to the loss of the connection line between the first voltage generator and the selected word line, or other small differences caused by the actual circuit environment.

[0064] It is understandable that, in the above embodiments, from the channel boost stage to the programming pulse stage, combined with Figure 7 It is known that when the first transistor M1 is turned on, the voltage generated by the first voltage generator (VPE) is connected to the selected word line (VWLSEL). A voltage switch occurs at the end of the first transistor M1 connected to the selected word line, connecting the selected word line (SEL WL) to the first voltage generator (VPE). At the instant the first transistor M1 is turned on, if the source-drain voltage (VDS) between VPE and SEL WL is large, it will cause performance degradation of the first transistor M1, ultimately leading to device performance degradation. If the source-drain voltage between VPE and SEL WL is small, the hot carrier injection (HCI) is small when the first transistor M1 is turned on. However, at this time, when the voltage of VPE rises, SEL WL is loaded onto VPE, which will slow down the rise of VPE. This slow rise of VPE, in turn, makes the rise rate of SEL WL slower than expected, thus affecting the voltage rise rate of the selected word line and consequently affecting the final programming time (tProg).

[0065] In response to one or more of the above-mentioned problems, embodiments of this disclosure provide another memory device, the memory device comprising: a memory cell array; and peripheral circuitry coupled to the memory cell array, the peripheral circuitry being configured to: determine a target voltage difference based on a target programming voltage; determine a channel boost voltage based on the difference between the target programming voltage and the target voltage difference; apply the channel boost voltage to a selected word line during a channel boost phase; and apply the target programming voltage to the selected word line during a programming pulse phase.

[0066] In some embodiments, the target voltage difference is the difference between the target programming voltage and the channel boost voltage. The channel boost voltage is obtained by subtracting the target voltage difference from the target programming voltage.

[0067] Here, the selected word line can be any one of multiple word lines in the memory cell array. The target programming voltage can be generated by a first voltage generator. The first voltage generator is subordinate to the aforementioned voltage generator 510, and is used to generate the channel boost voltage and the target programming voltage for application to the selected word line.

[0068] It is understood that, in the embodiments of this disclosure, incremental step-pulse programming (ISPP) can be used to program the memory device. Specifically, during the programming operation of the target state, a first target programming voltage is first applied to the selected word line, and then a verification operation is performed on the target memory cells connected to the selected word line to check whether the threshold voltage of each target memory cell connected to the selected word line reaches the target threshold voltage. If the number of target memory cells that have not been programmed to the target threshold voltage is greater than the allowable range, a second target programming voltage with a higher voltage is applied again, and the verification operation is performed again after applying the second target programming voltage. The above process of applying programming pulses and performing verification operations is repeated until the number of target memory cells that have not been programmed to the target threshold voltage is within the allowable range, at which point the programming ends.

[0069] It should be noted that before applying the channel boost voltage to the selected word line, the voltage generated by the first voltage generator (VPE) is increased to the channel boost voltage. Similarly, before applying the target programming voltage to the selected word line, the voltage generated by the first voltage generator is increased from the channel boost voltage to the target programming voltage. Refer to the previous... Figure 6 During the channel boost phase, the channel boost voltage is applied to the selected word line, and the voltage on the selected word line is drawn from the ground voltage V. dd (0V) rises to the channel boost voltage. During the programming pulse phase, the target programming voltage is applied to the selected word line. The voltage on the selected word line rises from the channel boost voltage and reaches the target programming voltage at a certain slope.

[0070] In this embodiment of the disclosure, when applying the programming voltage, an intermediate voltage, namely the channel boost voltage, is first applied to the selected word line, and then the target programming voltage is applied to the selected word line. This allows the selected word line to be boosted from the channel boost voltage to the target programming voltage, which can effectively achieve voltage buffering and reduce the damage to the first transistor caused by the high voltage difference from ground voltage to the target programming voltage at one time.

[0071] In this embodiment of the disclosure, a target voltage difference is determined based on the target programming voltage; and a channel boost voltage is determined based on the difference between the target programming voltage and the target voltage difference. That is, in this embodiment of the disclosure, the target voltage difference changes with the target programming voltage, thereby controlling the target voltage difference within a certain range. This avoids damage to the first transistor caused by a high voltage difference and also avoids a longer programming time (tProg) due to a low voltage difference.

[0072] In this embodiment of the disclosure, the peripheral circuit includes control logic and a first voltage generator coupled to the control logic; the control logic is configured to: control the first voltage generator to generate the channel boost voltage and apply the channel boost voltage to a selected word line; control the first voltage generator to generate the target programming voltage and apply the target programming voltage to the selected word line.

[0073] In this embodiment of the disclosure, the peripheral circuit further includes a row driver, and the first voltage generator is coupled to the selected word line through a first transistor in the row driver; the control logic is configured to: turn on the first transistor during the channel boost phase so that the channel boost voltage generated by the first voltage generator is output to the selected word line; and turn on the first transistor during the programming pulse phase so that the target programming voltage generated by the first voltage generator is output to the selected word line.

[0074] Here, the control logic can be referred to in the foregoing. Figure 5 The control logic 512 can be understood as follows. After receiving a programming operation (write) instruction, the control logic can start responding to the programming operation instruction and execute the programming operation. During the execution of the programming operation, it controls the first voltage generator to generate the channel boost voltage and applies the channel boost voltage to the selected word line; it also controls the first voltage generator to generate the target programming voltage and applies the target programming voltage to the selected word line.

[0075] In this embodiment of the disclosure, the peripheral circuit further includes a second voltage generator coupled to the control logic; the control logic is configured to: control the voltage generated by the second voltage generator to rise to a first voltage, and apply the first voltage to the gate of the first transistor during the programming pulse phase to turn on the first transistor.

[0076] Here, the row driver can specifically be the one described above. Figure 5 The WL driver 508; the second voltage generator also belongs to the aforementioned Figure 5 The voltage generator 510 in the middle, the second voltage generator is used to generate a gate voltage for application to the gate of the first transistor. The second voltage generator can correspond to Figure 7 vpeh in the middle.

[0077] Here, the value of the first voltage is related to the type of the first transistor. In some specific examples, the first transistor is an N-type metal-oxide-semiconductor (NMOS) transistor. In this case, the first voltage is greater than the target programming voltage, and the voltage difference between the first voltage and the target programming voltage needs to be greater than the turn-on voltage of the first transistor, so that the first transistor can be turned on.

[0078] In this embodiment of the disclosure, the magnitude of the target voltage difference is positively correlated with the magnitude of the target programming voltage.

[0079] In this embodiment, the target voltage difference increases with the increase of the target programming voltage. Thus, when the target programming voltage is small, a smaller target voltage difference is used; when the target programming voltage is large, a relatively larger target voltage difference is used. This ensures that the voltage rise rate of the selected word line is increased as much as possible without damaging the first transistor M1, thereby saving programming time (tProg).

[0080] In this embodiment of the disclosure, the target pressure difference increases during the programming of the selected memory cell.

[0081] In this embodiment of the disclosure, programming is performed using the ISPP method. During the programming of the selected memory cell, the target programming voltage increases, and thus the target voltage difference also increases.

[0082] Figure 8 This is a schematic diagram illustrating the word line voltage timing during different programming cycles in an embodiment of the present disclosure, as shown below. Figure 8As shown, in the initial stage of programming, the target programming voltage (WL_target) is less than or equal to the preset value, i.e., WL_target ≤ N. At this time, because the target programming voltage is small, c_vpgm_delta1 is used as the target voltage difference. Both the voltage difference from ground to the channel boost voltage and the voltage difference from the channel boost voltage to the target programming voltage are small, so no damage will be caused to the first transistor. In the middle and later stages of programming, the target programming voltage is greater than the preset value, i.e., WL_target > N. At this time, because the target programming voltage is large, if c_vpgm_delta1 is continued as the target voltage difference, the voltage difference from ground to the channel boost voltage may become large enough to cause degradation to the first transistor. Therefore, c_vpgm_delta2 is used as the target voltage difference. c_vpgm_delta2 is greater than c_vpgm_delta1, thereby reducing the voltage difference from ground to the channel boost voltage and avoiding damage to the first transistor due to high voltage difference.

[0083] In this embodiment of the disclosure, the peripheral circuit is configured to: compare the target programming voltage with a preset value; and determine the target voltage difference based on the comparison result.

[0084] In this embodiment of the disclosure, in order to adjust the value of the target voltage difference according to the magnitude of the target programming voltage, the target programming voltage is compared with a preset value. Thus, the target voltage difference can be determined based on the comparison result between the target programming voltage and the preset value.

[0085] In this embodiment of the disclosure, the peripheral circuit is configured to: determine the target voltage difference as a first target voltage difference when the target programming voltage is less than or equal to the preset value; and determine the target voltage difference as a second target voltage difference when the target programming voltage is greater than the preset value; wherein the first target voltage difference is less than the second target voltage difference.

[0086] In a specific example, the preset value could be set to 20, or 22, or 24, or 26.

[0087] It is understood that, in this embodiment of the disclosure, the programming operation can be divided into multiple programming cycles according to different target programming voltages. In each programming cycle, a corresponding target programming voltage is applied to a selected word line, and each programming cycle corresponds to a different programming pulse. Each programming cycle includes the aforementioned pre-charge stage, channel boost stage, programming pulse stage, and recovery stage. That is, the aforementioned scheme involving determining the target voltage difference based on the target programming voltage; determining the channel boost voltage based on the difference between the target programming voltage and the target voltage difference; applying the channel boost voltage to the selected word line in the channel boost stage; and applying the target programming voltage to the selected word line in the programming pulse stage can be applied to each programming cycle.

[0088] Figure 9 This illustration shows the word line voltage during different programming cycles in one embodiment of the present disclosure. Figure 1 ,like Figure 9 As shown, when the target programming voltage (WL_target) is less than or equal to a preset value, the target voltage difference is c_vpgm_delta1, which is the difference between the target programming voltage (WL_target) and the channel boost voltage (WL_middle). For example, in programming cycles up to the 25th programming cycle, the target programming voltage is less than or equal to the preset value. Therefore, c_vpgm_delta1 is used as the target voltage difference in programming cycles 1 to 25. When the target programming voltage is greater than the preset value, the target voltage difference becomes c_vpgm_delta2, which is the difference between the target programming voltage (WL_target) and the channel boost voltage (WL_middle). For example, in programming cycles after the 25th programming cycle, the target programming voltage is greater than the preset value. Therefore, c_vpgm_delta2 is used as the target voltage difference in programming cycles 26 and later. Among them, c_vpgm_delta2 is greater than c_vpgm_delta1. It should be noted that... Figure 9The dashed line in the figure represents the voltage curve where the difference between the target programming voltage (WL_target) and the channel boost voltage (WL_middle) is constant at c_vpgm_delta1. In this case, as the programming cycle progresses, the target programming voltage (WL_target) becomes increasingly larger. If c_vpgm_delta1 is continued to be used as the target voltage difference, the voltage difference from ground to the channel boost voltage may become large enough to cause degradation to the first transistor, ultimately leading to device performance degradation. However, in the device provided in this application, the target voltage difference is determined based on the target programming voltage. When the target programming voltage is greater than the preset value, c_vpgm_delta2 is used as the target voltage difference. c_vpgm_delta2 is greater than c_vpgm_delta1, thereby reducing the voltage difference from ground to the channel boost voltage and avoiding damage to the first transistor due to the high voltage difference.

[0089] In this embodiment of the disclosure, when the target programming voltage is less than or equal to a first preset value, the target voltage difference is determined to be a first target voltage difference; when the target programming voltage is greater than the first preset value and less than or equal to a second preset value, the target voltage difference is determined to be a second target voltage difference; when the target programming voltage is greater than the second preset value, the target voltage difference is determined to be a third target voltage difference; wherein, the first target voltage difference is less than the second target voltage difference, the second target voltage difference is less than the third target voltage difference, and the first preset value is less than the second preset value.

[0090] In a specific example, the first preset value can be set to 18, or 19, or 20, or 21. The second preset value can be set to 22, or 23, or 24, or 25.

[0091] Figure 10 This is a schematic diagram of word line voltages during different programming cycles in an embodiment of this disclosure; as shown in Figure 2. Figure 10As shown, when the target programming voltage (WL_target) is less than or equal to the first preset value, the target voltage difference is c_vpgm_delta1, that is, the difference between the target programming voltage (WL_target) and the channel boost voltage (WL_middle) is c_vpgm_delta1. For example, in the programming cycles up to the 15th programming cycle, the target programming voltage is less than or equal to the first preset value. Therefore, c_vpgm_delta1 is used as the target voltage difference in the 1st to 15th programming cycles. When the target programming voltage is greater than the first preset value and less than or equal to the second preset value, the target voltage difference becomes c_vpgm_delta2, which is the difference between the target programming voltage (WL_target) and the channel boost voltage (WL_middle). For example, in programming cycles from the 16th to the 21st programming cycle, the target programming voltage is greater than the preset value, so c_vpgm_delta2 is used as the target voltage difference in programming cycles from the 16th to the 21st. When the target programming voltage is greater than the second preset value, the target voltage difference becomes c_vpgm_delta3, which is the difference between the target programming voltage (WL_target) and the channel boost voltage (WL_middle). For example, in programming cycles after the 21st programming cycle, the target programming voltage is greater than the preset value, so c_vpgm_delta3 is used as the target voltage difference in programming cycles from the 22nd to the present. Among them, c_vpgm_delta2 is greater than c_vpgm_delta1, and c_vpgm_delta3 is greater than c_vpgm_delta2. It should be noted that... Figure 10The dashed line in the figure represents the voltage curve where the difference between the target programming voltage (WL_target) and the channel boost voltage (WL_middle) is constant at c_vpgm_delta1. In this case, as the programming cycle progresses, the target programming voltage (WL_target) becomes larger and larger. If c_vpgm_delta1 is continued to be used as the target voltage difference, the voltage difference from ground voltage to channel boost voltage may become large enough to cause degradation to the first transistor, thereby ultimately leading to device performance degradation. However, in the device provided in this application, the target voltage difference is determined based on the target programming voltage. When the target programming voltage is greater than a first preset value and less than or equal to a second preset value, c_vpgm_delta2 is used as the target voltage difference. When the target programming voltage is greater than the second preset value, c_vpgm_delta3 is used as the target voltage difference. c_vpgm_delta3 is greater than c_vpgm_delta2 and c_vpgm_delta2 is greater than c_vpgm_delta1, thereby reducing the voltage difference from ground voltage to channel boost voltage and avoiding damage to the first transistor caused by high voltage difference.

[0092] In some embodiments, the memory device includes a three-dimensional NAND type memory.

[0093] However, the memory device in this disclosure is not limited to three-dimensional NAND type memory. In this disclosure, the memory device can be a semiconductor memory, including but not limited to three-dimensional NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), or nano random access memory (NRAM), etc.

[0094] This disclosure also provides a memory system, the memory system comprising:

[0095] One or more memory devices as described in any of the above embodiments; and

[0096] A memory controller; the memory controller is coupled to the memory device and is used to control the memory device.

[0097] Here, the specific structure and composition of the memory system can be referred to the foregoing. Figure 1 , Figure 2a , Figure 2b The relevant structure and composition of the memory system 102 are described below. For the sake of brevity, they will not be elaborated here.

[0098] In some embodiments, the memory system includes a memory card or a solid-state drive.

[0099] Based on the above-described memory device, this disclosure also provides a method for operating the memory device, such as... Figure 11 As shown, the method includes:

[0100] Step 1101: Determine the target voltage difference based on the target programming voltage;

[0101] Step 1102: Determine the channel boost voltage based on the difference between the target programming voltage and the target voltage difference; during the channel boost phase, apply the channel boost voltage to the selected word line; during the programming pulse phase, apply the target programming voltage to the selected word line.

[0102] In some embodiments, the magnitude of the target voltage difference is positively correlated with the magnitude of the target programming voltage.

[0103] In some embodiments, the target differential pressure increases during the programming of the selected memory cell.

[0104] In some embodiments, determining the target voltage difference based on the target programming voltage includes: comparing the target programming voltage with a preset value; and determining the target voltage difference based on the comparison result.

[0105] In some embodiments, determining the target voltage difference based on the comparison result includes: determining the target voltage difference as a first target voltage difference when the target programming voltage is less than or equal to the preset value; and determining the target voltage difference as a second target voltage difference when the target programming voltage is greater than the preset value; wherein the first target voltage difference is less than the second target voltage difference.

[0106] In some embodiments, determining the target voltage difference based on the comparison result includes: determining the target voltage difference as a first target voltage difference when the target programming voltage is less than or equal to a first preset value; determining the target voltage difference as a second target voltage difference when the target programming voltage is greater than the first preset value and less than or equal to a second preset value; and determining the target voltage difference as a third target voltage difference when the target programming voltage is greater than the second preset value; wherein the second target voltage difference is less than the third target voltage difference, and the first preset value is less than the second preset value.

[0107] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0108] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory device, characterized in that, The memory device includes: Storage cell array; Peripheral circuitry, coupled to the memory cell array, is configured as follows: Determine the target voltage difference based on the target programmed voltage; The channel boost voltage is determined based on the difference between the target programming voltage and the target voltage difference. During the channel boost phase, the channel boost voltage is applied to the selected word line; during the programming pulse phase, the target programming voltage is applied to the selected word line.

2. The memory device according to claim 1, characterized in that, The magnitude of the target voltage difference is positively correlated with the magnitude of the target programming voltage.

3. The memory device according to claim 1, characterized in that, The target pressure difference increases during the programming of the selected memory cell.

4. The memory device according to claim 1, characterized in that, The peripheral circuit is configured to: compare the target programming voltage with a preset value; and determine the target voltage difference based on the comparison result.

5. The memory device according to claim 4, characterized in that, The peripheral circuit is configured to: determine the target voltage difference as a first target voltage difference when the target programming voltage is less than or equal to the preset value; and determine the target voltage difference as a second target voltage difference when the target programming voltage is greater than the preset value. Wherein, the first target pressure difference is less than the second target pressure difference.

6. The memory device according to claim 4, characterized in that, The control logic is configured to: determine the target voltage difference as a first target voltage difference when the target programming voltage is less than or equal to a first preset value; determine the target voltage difference as a second target voltage difference when the target programming voltage is greater than the first preset value and less than or equal to a second preset value; and determine the target voltage difference as a third target voltage difference when the target programming voltage is greater than the second preset value. Wherein, the first target pressure difference is less than the second target pressure difference, the second target pressure difference is less than the third target pressure difference, and the first preset value is less than the second preset value.

7. The memory device according to any one of claims 1 to 6, characterized in that, The peripheral circuitry includes control logic and a first voltage generator coupled to the control logic. The control logic is configured to: control the first voltage generator to generate the channel boost voltage and apply the channel boost voltage to the selected word line; control the first voltage generator to generate the target programming voltage and apply the target programming voltage to the selected word line.

8. The memory device according to claim 7, characterized in that, The peripheral circuitry also includes a row driver, wherein the first voltage generator is coupled to the selected word line via a first transistor in the row driver; the control logic is configured to: During the channel boost phase, the first transistor is turned on so that the channel boost voltage generated by the first voltage generator is output to the selected word line; During the programming pulse phase, the first transistor is turned on so that the target programming voltage generated by the first voltage generator is output to the selected word line.

9. The memory device according to claim 7, characterized in that, The peripheral circuit also includes a second voltage generator, which is coupled to the control logic; the control logic is configured to: The voltage generated by the second voltage generator is controlled to rise to a first voltage, and during the programming pulse phase, the first voltage is applied to the gate of the first transistor to turn on the first transistor.

10. A memory system, characterized in that, include: The memory device as described in any one of claims 1 to 9; as well as Memory controller; The memory controller is coupled to the memory device and is used to control the memory device.

11. A method of operating a memory device, characterized in that, The operation method includes: Determine the target voltage difference based on the target programming voltage; The channel boost voltage is determined based on the difference between the target programming voltage and the target voltage difference; during the channel boost phase, the channel boost voltage is applied to the selected word line; during the programming pulse phase, the target programming voltage is applied to the selected word line.

12. The method of operating the memory device according to claim 11, characterized in that, The magnitude of the target voltage difference is positively correlated with the magnitude of the target programming voltage.

13. The method of operating the memory device according to claim 11, characterized in that, The target pressure difference increases during the programming of the selected memory cell.

14. The method of operating the memory device according to claim 10, characterized in that, Determining the target voltage difference based on the target programming voltage includes: The target programming voltage is compared with a preset value; based on the comparison result, the target voltage difference is determined.

15. The method of operating the memory device according to claim 14, characterized in that, The step of determining the target pressure difference based on the comparison results includes: When the target programming voltage is less than or equal to the preset value, the target voltage difference is determined to be the first target voltage difference; When the target programming voltage is greater than the preset value, the target voltage difference is determined to be the second target voltage difference; Wherein, the first target pressure difference is less than the second target pressure difference.

16. The method of operating the memory device according to claim 15, characterized in that, The step of determining the target pressure difference based on the comparison results includes: When the target programming voltage is less than or equal to a first preset value, the target voltage difference is determined to be the first target voltage difference; When the target programming voltage is greater than the first preset value and less than or equal to the second preset value, the target voltage difference is determined to be the second target voltage difference; When the target programming voltage is greater than the second preset value, the target voltage difference is determined to be the third target voltage difference; Wherein, the second target pressure difference is less than the third target pressure difference, and the first preset value is less than the second preset value.

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