Memory device and method of performing row access count operation

Abstract

The invention relates to a memory device and a method of performing a row access count operation. A memory device includes: a memory bank configured to store a row count value corresponding to a number of times each word line is accessed when an activation operation is performed; and a column control circuit configured to perform a count read operation and a count write operation during a period in which a column selection operation set by the pre-charge command is performed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0065481, filed on May 20, 2024. Technical Field

[0003] Some embodiments of this disclosure relate to methods for performing row access counting operations and storage devices thereof. Background Technology

[0004] The memory cells included in the memory device are connected to multiple word lines, and at least one word line can be accessed when an activation operation is performed. According to the activation operation, data stored in the memory cells connected to the accessed word line can be transferred via bit line pairs and sensed and amplified by a bit line sensing amplifier. When a particular word line is frequently accessed through activation operations, the charge of memory cells connected to adjacent word lines may be lost due to the influence of the accessed word line. Therefore, it is necessary to manage frequently accessed word lines. Summary of the Invention

[0005] This disclosure provides a storage device including: a memory bank configured to store row count values ​​corresponding to the number of times each word line is accessed during an activation operation; and column control circuitry configured to perform a count read operation and a count write operation during a period in which a column selection operation set by a precharge command is executed. In this disclosure, the column control circuitry can output the row count values ​​stored in the memory bank to a local input / output pair during a count read operation, and store an updated row count value transmitted via the local input / output pair in the memory bank during a count write operation.

[0006] Furthermore, this disclosure provides a storage device including: a command delay circuit configured to delay a precharge command to sequentially generate a set signal, a write signal, and a reset signal; a column control signal generation circuit configured to generate a column control signal for a column selection operation based on the set signal and the reset signal; a write / read signal generation circuit configured to generate write / read signals based on the precharge command and the write signal; and a column control circuit configured to perform a count read operation and a count write operation during a period in which the column selection operation is performed based on the column control signal and the write / read signal. In this disclosure, the column control circuit can output a row count value stored in the memory to a local input / output pair when a count read operation is performed, and store an updated row count value transmitted via the local input / output pair in the memory when a count write operation is performed.

[0007] Furthermore, this disclosure may provide a method for performing a row access counting operation, comprising: generating a column control signal for a column selection operation when a first delay period has elapsed since the time when the precharge command was generated; performing a count read operation in the column selection operation to output a row count value stored in the memory; updating the row count value output during the count read operation; and performing a count write operation to store the updated row count value back into the memory when a second delay period has elapsed since the time when the precharge command was generated. Attached Figure Description

[0008] Figure 1 A configuration of a memory system according to an embodiment of the present disclosure is shown.

[0009] Figure 2 The configuration of the storage device according to an embodiment of the present disclosure is shown.

[0010] Figure 3 The configuration of an alarm signal generation circuit according to an embodiment of the present disclosure is shown.

[0011] Figure 4 The configuration of the row control circuit and column control circuit according to an embodiment of the present disclosure is shown.

[0012] Figure 5 The configuration of a storage bank according to an embodiment of the present disclosure is shown.

[0013] Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 This is a diagram illustrating a row access counting operation performed in a storage device according to an embodiment of the present disclosure.

[0014] Figure 11 , Figure 12 and Figure 13 This is a diagram illustrating an alarm signal generation operation performed in a storage device according to an embodiment of the present disclosure. Detailed Implementation

[0015] In the following description of embodiments, when a parameter is referred to as "predetermined," the value of the parameter can be determined in advance when the parameter is used in a process or algorithm. The value of the parameter can be determined at the beginning of the process or algorithm, or it can be determined during the execution of the process or algorithm.

[0016] Although the terms “first,” “second,” “third,” etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another and are not intended to imply an order or number of elements. Therefore, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of this disclosure.

[0017] When a component is referred to as "connected" or "coupled" to another component, the component can be directly connected or coupled to the other component, or there may be intermediate components. When a component is referred to as "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0018] Logic "high" and logic "low" levels can be used to describe the logic levels of electrical signals. A logic "high" level signal is distinct from a logic "low" level signal. For example, when a first voltage signal corresponds to a logic "high" level signal, a second voltage signal can correspond to a logic "low" level signal. In embodiments, the voltage level of a logic "high" level can be higher than the voltage level of a logic "low" level. The logic levels of signals can be different or opposite depending on the embodiment. For example, a signal that is at a logic "high" level in one embodiment may be at a logic "low" level in another embodiment.

[0019] The term "logic bit group" can refer to a combination of logic levels of the bits included in a signal. The logic bit group of a signal can differ when the logic levels of the individual bits vary. For example, when a signal includes two bits, if each bit is at a logic low level, the logic bit group can be the first logic bit group; if each bit is at a logic low level and a logic high level, the logic bit group can be the second logic bit group.

[0020] The various embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. These embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0021] Figure 1 The configuration of a memory system 10 according to an embodiment of the present disclosure is shown.

[0022] like Figure 1 As shown, the memory system 10 may include a controller 100 and a storage device 110.

[0023] The controller 100 can apply a command address CA and a clock signal CLK to the memory device 110 to control the overall operation of the memory system 10. The command address CA may include multiple bits, with logical bit groups configured for activation, read, write, precharge, precharge and read, and precharge and write operations. The command address CA may be applied synchronously with the clock signal CLK; however, this is merely an example, and the disclosure is not limited thereto. For example, a precharge operation may be performed after an activation operation. In another example, a precharge operation may be performed after an activation operation followed by a read or write operation. In yet another example, a precharge operation may be performed concurrently with a read or write operation performed after an activation operation. A precharge operation may be performed to release a word line accessed during the activation operation. Releasing an accessed word line may mean releasing it via a word line driver (e.g., Figure 4 151) in the middle will put all word lines (e.g., Figure 4 The controller 100 can receive an alarm signal ALERT from the storage device 110. The controller 100 can receive the alarm signal ALERT to control the storage device 110 to perform a refresh or repair operation to prevent the storage (e.g., ...) from being activated. Figure 2 The charge loss in the memory cell included in 124) is an example. However, this is merely an example and the present disclosure is not limited thereto.

[0024] Storage device 110 can be electrically connected to controller 100 to receive command address CA and clock signal CLK from controller 100. Storage device 110 can perform activation operations, read operations, write operations, precharge operations, precharge and read operations, and precharge and write operations based on command address CA and clock signal CLK. When a precharge command (e.g., ...) is executed... Figure 2 When the PCG-BK in the memory is generated, the storage device 110 can perform a row access count operation to update the row count value. The row count value can correspond to each word line when the activation operation is performed (e.g., ...). Figure 4 The number of times the WL (row access count) is accessed is recorded, and the row count value for each word line is stored in at least one memory cell connected to the accessed word line. The storage device 110 can store the activation address for which an activation operation is performed when the updated row count value, as a result of the row access counting operation, reaches a preset threshold. The storage device 110 can also generate an activation address when the stored activation address (e.g., ...) is accessed. Figure 3 The address storage circuit of ACT-ADD in (e.g., Figure 3The alarm signal ALERT is activated when the storage space of (143) is full. The storage device 110 can apply the alarm signal ALERT to the controller 100. The storage device 110 may include a command decoder (CMD DEC) 111, a command delay circuit (CMD DLY) 113, a counter adder (CNT ADDER) 115, and an alarm signal generation circuit (ALERT GEN) 117.

[0025] Command decoder 111 can decode command address CA to generate an activation command for activation operations (e.g., Figure 2 In ACT-BK), and can generate precharge commands for precharge operations (e.g., Figure 2 (PCG-BK in the middle).

[0026] Command delay circuit 113 can delay the precharge command generated for the precharge operation after the activation operation is executed (e.g., Figure 2 PCG-BK in the process, to sequentially generate signals for controlling the count read operation and count write operation in the row access count operation (e.g., Figure 2 The signal includes the set signal SET, the input / output sense amplifier control signal IOSTBP-PRAC, the latch pulse LPUL, the write driver control signal BWEN-PRAC, the write signal WT-PRAC, and the reset signal RST.

[0027] The counter adder 115 can update the data from the memory bank (e.g., during a count read operation) by incrementing the row count value by one value (i.e., 1). Figure 2 The row count value output in 124) can be latched during a count write operation to output the row count value so that the row count value can be stored in the memory (e.g., Figure 2 (124) in the middle.

[0028] When the updated row count value in the row access counting operation reaches a threshold, the alarm signal generation circuit 117 can activate the address (e.g., Figure 3 The ACT-ADD in the address storage circuit (e.g., Figure 3 In 143). When the address storage circuit (e.g., Figure 3 When the storage space of 143) is full, the alarm signal generation circuit 117 can generate an activated alarm signal ALERT.

[0029] Figure 2 An embodiment according to this disclosure is shown. Figure 1 The configuration of storage device 110 in the middle. For example... Figure 2As shown, the storage device 110 may include a command decoder (CMD DEC) 111, a command delay circuit (DLY) 113, a column control signal generation circuit (BYP-PRAC GEN) 121, a column control circuit (YCTR) 122, a row control circuit (XCTR) 123, a memory bank 124, an input / output sense amplifier (IOSA) 125, an error correction circuit (ECC) 126, a counter adder (CNT ADDER) 115, an alarm signal generation circuit (ALERT GEN) 117, a write driver (WDRV) 127, a write / read signal generation circuit (WTRD GEN) 128, and a precharge signal generation circuit (PCG GEN) 129.

[0030] Command decoder 111 can generate an activation command ACT-BK and a precharge command PCG-BK based on command address CA. Command decoder 111 can decode command address CA to generate an activation command ACT-BK for an activation operation and a precharge command PCG-BK for a precharge operation. Each of the activation command ACT-BK and the precharge command PCG-BK can be generated for each memory bank where the activation operation and precharge operation are performed independently; however, this is merely an example, and this disclosure is not limited thereto. As an example, command decoder 111 can generate a precharge command PCG-BK for a precharge operation after an activation operation. As another example, after an activation operation, command decoder 111 can generate a precharge command PCG-BK for a precharge operation after performing a read operation or a write operation. As yet another example, when a precharge operation is performed after an activation operation with a read operation or a write operation, command decoder 111 can generate a precharge command PCG-BK for a precharge operation.

[0031] Command delay circuit 113 can be electrically connected to command decoder 111 to receive precharge command PCG-BK from command decoder 111. Command delay circuit 113 can sequentially generate a set signal SET, an input / output sense amplifier control signal IOSTBP-PRAC, a latch pulse LPUL, a write driver control signal BWEN-PRAC, a write signal WT-PRAC, and a reset signal RST based on the precharge command PCG-BK. Command delay circuit 113 can include delayers 131, 132, 133, 134, 135, and 136. Command delay circuit 113 can delay the precharge command PCG-BK by a first delay period via delayer 131 to generate the set signal SET. Command delay circuit 113 can delay the set signal SET by a second delay period via delayer 132 to generate the input / output sense amplifier control signal IOSTBP-PRAC. Command delay circuit 113 can delay the input / output sense amplifier control signal IOSTBP-PRAC by a third delay period via delayer 133 to generate the latch pulse LPUL. Command delay circuit 113 can delay the latch pulse LPUL by a fourth delay period via delayer 134 to generate the write driver control signal BWEN-PRAC. Command delay circuit 113 can delay the write driver control signal BWEN-PRAC by a fifth delay period via delayer 135 to generate the write signal WT-PRAC. Command delay circuit 113 can delay the write signal WT-PRAC by a sixth delay period via delayer 136 to generate the reset signal RST. Command delay circuit 113 can generate the set signal SET at a time point after a first delay period from the time point of generating the precharge command PCG-BK, can generate the input / output sense amplifier control signal IOSTBP-PRAC at a time point after a second delay period from the time point of generating the set signal SET, and can generate the latch pulse LPUL at a time point after a third delay period from the time point of generating the input / output sense amplifier control signal IOSTBP-PRAC. Furthermore, the command delay circuit 113 can generate the write driver control signal BWEN-PRAC at a time point after a fourth delay period from the time point of generating the latch pulse LPUL, generate the write signal WT-PRAC at a time point after a fifth delay period from the time point of generating the write driver control signal BWEN-PRAC, and generate the reset signal RST at a time point after a sixth delay period from the time point of generating the write signal WT-PRAC. Each of the first to sixth delay periods can be configured in various ways according to the embodiment.

[0032] The column control signal generation circuit 121 can be electrically connected to the command delay circuit 113 to receive the set signal SET and the reset signal RST from the command delay circuit 113. The column control signal generation circuit 121 can generate a column control signal BYP-PRAC based on the set signal SET and the reset signal RST. The column control signal generation circuit 121 can generate an active column control signal BYP-PRAC when the set signal SET is generated, and can generate a deactivated column control signal BYP-PRAC when the reset signal RST is generated. The column control signal generation circuit 121 can generate a column control signal BYP-PRAC that remains active during the period from the generation of the set signal SET to the generation of the reset signal RST (i.e., the period during which the column selection operation for the row access counting operation is performed).

[0033] Column control circuit 122 can be electrically connected to column control signal generation circuit 121 to receive column control signal BYP-PRAC from column control signal generation circuit 121. Column control circuit 122 can perform a column selection operation for row access counting based on the column control signal BYP-PRAC. The column selection operation can refer to generating a column selection signal for row access counting (e.g., ...). Figure 4 BL / BLB) and segment input / output pairs (e.g., Figure 4 The count column selection signal connected to the SIO / SIOB in the signal (e.g., Figure 4 YI-PRAC in the middle) and column selection signals (e.g., Figure 5 The operation of YI<0:63> in the memory. The column control circuit 122 can sense and amplify the output from the memory bank 124 based on the write-read signal WTRD during the count read operation, and can be transmitted via segment input / output pairs (e.g., Figure 4 The row count value transmitted by the SIO / SIOB in the memory bank 124 is used to generate the sense amplifier activation signal LSAEN, which is used to output the row count value to the local input / output line pair LIO / LIOB. The column control circuit 122 can generate the input / output line switch activation signal IOSWEN based on the write / read signal WTRD to transmit the updated row count value to the segment input / output line pair SIO / SIOB via the local input / output line pair LIO / LIOB during the count write operation. The count read operation can be performed to output the row count value stored in the memory bank 124, while the count write operation can be performed to store the updated row count value in the memory bank 124. Both the count read operation and the count write operation can be performed during the column selection operation for the row access count operation. Updating the row count value can mean incrementing the number of times the active word line has been accessed (i.e., the row count value) by 1.

[0034] The row control circuit 123 can be electrically connected to the command decoder 111 to receive the activation command ACT-BK from the command decoder 111. When the activation command ACT-BK is generated and the activation operation is executed, the row control circuit 123 can access at least one word line based on the activation address ACT-ADD (e.g., Figure 4 (WL in the original text). Accessing a word line can refer to loading data and row count values ​​stored in the memory cells connected to the accessed word line within the memory bank 124 to the bit line pair BL / BLB; it can also be called row access. The row control circuit 123 can be electrically connected to the precharge signal generation circuit 129 to receive a precharge signal PCG from the precharge signal generation circuit 129. The row control circuit 123 can release word lines accessed in a previous activation operation when the precharge signal PCG is generated.

[0035] Memory bank 124 may include word lines (e.g., Figure 4 The storage bank 124 comprises multiple storage units connected by a WL (Wide Link Array). Data and row count values ​​can be stored in the storage units included in the storage bank 124. The row count values ​​stored in the storage bank 124 can be output and updated during row access counting operations, and then stored again. More specifically, when a count read operation is performed during the period when a column selection operation for row access counting is executed, the row count values ​​stored in the storage bank 124 can be output, and when a count write operation is performed during the period when a column selection operation for row access counting is executed, the updated row count values ​​can be stored again.

[0036] The input / output sense amplifier 125 can be electrically connected to the local input / output line pair LIO / LIOB to receive signals transmitted through the local input / output line pair LIO / LIOB, and can be electrically connected to the command delay circuit 113 to receive the input / output sense amplifier control signal IOSTBP-PRAC from the command delay circuit 113. When the input / output sense amplifier control signal IOSTBP-PRAC is generated, the input / output sense amplifier 125 can receive the row count value output from the memory bank 124 according to the count read operation through the local input / output line pair LIO / LIOB, and can sense and amplify the received row count value to output the row count value as read data RDA.

[0037] Error correction circuit 126 can be electrically connected to input / output sense amplifier 125 and counter adder 115 to receive read data RDA from input / output sense amplifier 125 and update count signal CNT-A from counter adder 115. Error correction circuit 126 can correct errors included in read data RDA to output corrected read data RDA as count signal CNT-B. Count signal CNT-B can correspond to the row count value stored in memory bank 124. Error correction circuit 126 can correct errors included in update count signal CNT-A to generate corrected data CDA. Update count signal CNT-A can correspond to the updated row count value. Error correction circuit 126 can be implemented using Hamming code, Reed-Solomon code (RS code), and Bose-Chaudhuri-Hocquenghem code (BCH code) to correct errors included in signals and data; however, this is merely an example and this disclosure is not limited thereto.

[0038] The counter adder 115 can be electrically connected to the error correction circuit 126 and the command delay circuit 113 to receive the counting signal CNT-B from the error correction circuit 126 and the latch pulse LPUL from the command delay circuit 113. The counter adder 115 can increment the row count value by 1 based on the counting signal CNT-B to generate an update count signal CNT-A. Based on the latch pulse LPUL, the counter adder 115 can latch and output the update count signal CNT-A.

[0039] Alarm signal generation circuit 117 can be electrically connected to counter adder 115 to receive update count signal CNT-A from counter adder 115. Based on update count signal CNT-A, threshold code TH-CD, and activation address ACT-ADD, alarm signal generation circuit 117 can generate alarm signal ALERT. When the row count value corresponding to update count signal CNT-A reaches the threshold corresponding to threshold code TH-CD, alarm signal generation circuit 117 can store activation address ACT-ADD in address storage circuit (e.g., ...). Figure 3 In section 143), the activation address ACT-ADD can be set to the address entered in the activation operation performed before the precharge command PCG-BK is generated. The alarm signal generation circuit 117 can be located in the address storage circuit (e.g., Figure 3 When the storage space of 143) is full, an active alarm signal ALERT is generated.

[0040] The write driver 127 can be electrically connected to the command delay circuit 113 and the error correction circuit 126 to receive the write driver control signal BWEN-PRAC from the command delay circuit 113 and the corrected data CDA from the error correction circuit 126. When the write driver control signal BWEN-PRAC is generated, the write driver 127 can drive the local input / output pair LIO / LIOB based on the corrected data CDA to transmit the corrected data CDA to the column control circuit 122 via the local input / output pair LIO / LIOB.

[0041] The write / read signal generation circuit 128 can be electrically connected to the command decoder 111 and the command delay circuit 113 to receive a precharge command PCG-BK from the command decoder 111 and a write signal WT-PRAC from the command delay circuit 113. Based on the precharge command PCG-BK and the write signal WT-PRAC, the write / read signal generation circuit 128 can generate a write / read signal WTRD. When the precharge command PCG-BK is generated, the write / read signal generation circuit 128 can generate the write / read signal WTRD, causing a count read operation to be performed. When the write signal WT-PRAC is generated, the write / read signal generation circuit 128 can generate the write / read signal WTRD, causing a count write operation to be performed. The state of the write / read signal WTRD generated for performing the count read operation and the state of the write / read signal WTRD generated for performing the count write operation can be set differently, and the state of the write / read signal WTRD can be set separately by logic levels or logic bit groups; however, this is merely an example, and this disclosure is not limited thereto.

[0042] The precharge signal generation circuit 129 can be electrically connected to the command decoder 111 to receive the precharge command PCG-BK from the command decoder 111. The precharge signal generation circuit 129 can generate the precharge signal PCG at a point in time after the precharge command PCG-BK is generated, elapsed after a precharge delay period. Since the precharge operation needs to be performed after the row access counting operation is executed, it is desirable to set the precharge delay period to be longer than the period during which the column selection operation used for the row access counting operation is executed.

[0043] Figure 3 An embodiment according to this disclosure is shown. Figure 2 The configuration of the alarm signal generation circuit 117. For example... Figure 3 As shown, the alarm signal generation circuit 117 may include a code comparison circuit (CD COM) 141 and an address storage circuit 143.

[0044] Based on the threshold code TH-CD and the update count signal CNT-A, the code comparison circuit 141 can generate an update signal Q-UP. The code comparison circuit 141 compares the threshold corresponding to the threshold code TH-CD with the row count value corresponding to the update count signal CNT-A to generate the update signal Q-UP. The code comparison circuit 141 generates an activated update signal Q-UP when the row count value corresponding to the update count signal CNT-A reaches the threshold corresponding to the threshold code TH-CD.

[0045] Address storage circuit 143 can be electrically connected to code comparison circuit 141 to receive update signal Q-UP from code comparison circuit 141. Based on update signal Q-UP and activation address ACT-ADD, address storage circuit 143 can generate alarm signal ALERT. Address storage circuit 143 may include queue control circuit (Q-CTR) 145 and multiple queues (queues 1 to N) 147-1 to 147-N. When update signal Q-UP is activated, queue control circuit 145 can sequentially store activation address ACT-ADD in multiple queues 147-1 to 147-N. When all queues 147-1 to 147-N have stored activation address ACT-ADD, that is, when the storage space of address storage circuit 143 is full, queue control circuit 145 can generate activated alarm signal ALERT.

[0046] Figure 4 An embodiment according to this disclosure is shown. Figure 2 The configuration of the row control circuit 123 and the column control circuit 122.

[0047] When the activation command ACT-BK is generated and the activation operation is executed, the row control circuit 123 can access at least one word line WL based on the activation address ACT-ADD. When the precharge signal PCG is generated and the precharge operation is executed, the row control circuit 123 can release the word line accessed during the activation operation.

[0048] The column control circuit 122 may include a counting column selection signal generation circuit (YI-PRAC GEN) 151, an input / output control circuit (IO CTR) 153, a column selection switch (YISW) 155, a sense amplifier (LSA) 157, and an input / output line switch (IOSW) 159.

[0049] The counting column selection signal generation circuit 151 can generate the counting column selection signal YI-PRAC when the column control signal BYP-PRAC for the column selection operation used for row access counting operation is generated.

[0050] The input / output control circuit 153 can generate a sense amplifier activation signal LSAEN when the write / read signal WTRD for the count read operation is generated. The input / output control circuit 153 can also generate an input / output line switch activation signal IOSWEN when the write / read signal WTRD for the count write operation is generated.

[0051] Column selection switch 155 can be electrically connected to counting column selection signal generation circuit 151 to receive counting column selection signal YI-PRAC from counting column selection signal generation circuit 151. During the period when the column selection operation for row access counting operation is performed, when the counting column selection signal YI-PRAC is generated, column selection switch 155 can connect bit line pair BL / BLB and segment input / output line pair SIO / SIOB.

[0052] The sense amplifier 157 can be electrically connected to the input / output control circuit 153 to receive the sense amplifier activation signal LSAEN from the input / output control circuit 153. When a count read operation is performed and the sense amplifier activation signal LSAEN is generated, the sense amplifier 157 can sense and amplify the row count value output from the memory bank 124 and transmitted via the segment input / output line pair SIO / SIOB during the count read operation, so as to output the row count value to the local input / output line pair LIO / LIOB.

[0053] Input / output line switch 159 can be electrically connected to input / output control circuit 153 to receive input / output line switch activation signal IOSWEN from input / output control circuit 153. When a count write operation is performed and input / output line switch activation signal IOSWEN is generated, input / output line switch 159 can transmit the updated row count value transmitted via local input / output line pair LIO / LIOB to section input / output line pair SIO / SIOB.

[0054] Figure 5 An embodiment according to this disclosure is shown. Figure 4 The configuration of the storage unit 124 shown is as follows. Figure 5 As shown, the storage bank 124 may include first to fifth unit blocks 201, 202, 203, 204 and 205. Each of the first to fifth unit blocks 201, 202, 203, 204 and 205 may be referred to as a matrix block (mat).

[0055] The first cell block 201 may include a plurality of memory cells connected to the first bit line group BL1. The first bit line group BL1 of the first cell block 201 may include 64 bit lines selected by the first to 64th column selection signals YI<0:63>. When column selection operations for write and read operations are performed, at least one of the 64 bit lines included in the first bit line group BL1 of the first cell block 201 may be selected by the first to 64th column selection signals YI<0:63>. Normal data input and output during write and read operations may be stored in the plurality of memory cells connected to the first bit line group BL1 of the first cell block 201; however, this is merely an example and the present disclosure is not limited thereto.

[0056] The second unit block 202 may include multiple memory cells connected to the second bit line group BL2. The second bit line group BL2 of the second unit block 202 may include 64 bit lines selected by the first to 64th column selection signals YI<0:63>, and a first count column selection signal YI-PRAC. <0> The selected count bit line, and the RYI-PRAC selected signal from the first redundant count column. <0> The selected redundant counting bit line. When a column selection operation for a write or read operation is performed, at least one of the 64 bit lines included in the second bit line group BL2 of the second cell block 202 can be selected by the first to 64th column selection signals YI<0:63>. Parity data used in error correction operations can be stored in multiple memory cells connected to the 64 bit lines included in the second bit line group BL2 of the second cell block 202; however, this is merely an example and the disclosure is not limited thereto. When a row access counting operation is performed, the second cell block 202 can be based on the first counting column selection signal YI-PRAC. <0> Select the count bit line. The row count value can be stored in multiple memory cells connected to the count bit line of the second cell block 202. When a defect is detected in the count bit line, a row access counting operation is performed, and the second cell block 202 can select the first redundant count column selection signal RYI-PRAC based on this signal. <0> Select redundant count bit lines. Row count values ​​can be stored in multiple memory cells connected to the redundant count bit lines of the second cell block 202.

[0057] The third unit block 203 may include multiple memory cells connected to the third bit line group BL3. The third bit line group BL3 of the third unit block 203 may include 32 bit lines selected by the first to 32 column selection signals YI<0:31>, and the second count column selection signal YI-PRAC. <1> The selected count bit line, and the RYI-PRAC signal selected by the second redundant count column. <1> The selected redundant counting bit lines. When a column selection operation for a write or read operation is performed, at least one of the 32 bit lines included in the third bit line group BL3 of the third unit block 203 can be selected by the first to the 32nd column selection signals YI<0:31>. Redundant data used in the repair operation can be stored in multiple memory cells connected to the 32 bit lines included in the third bit line group BL3 of the third unit block 203; however, this is merely an example and the disclosure is not limited thereto. When a row access counting operation is performed, the third unit block 203 can be based on the second counting column selection signal YI-PRAC. <1> Select the count bit line. The row count value can be stored in multiple memory cells connected to the count bit line of the third cell block 203. When a defect is detected in the count bit line, a row access counting operation is being performed, and the third cell block 203 can select the second redundant count column based on the RYI-PRAC signal. <1> Select redundant count bit lines. Row count values ​​can be stored in multiple memory cells connected to the redundant count bit lines of the third cell block 203.

[0058] The fourth unit block 204 may include multiple memory cells connected to the fourth bit line group BL4. The fourth bit line group BL4 of the fourth unit block 204 may include 64 bit lines selected by the first to 64th column selection signals YI<0:63>, and the third count column selection signal YI-PRAC. <2> The selected count bit line, and the RYI-PRAC signal selected by the third redundant count column. <2> Selected redundant counting bit lines. When a column selection operation for a write or read operation is performed, at least one of the 64 bit lines included in the fourth bit line group BL4 of the fourth unit block 204 can be selected by the first to the 64th column selection signals YI<0:63>. Parity data used in error correction operations can be stored in multiple memory cells connected to the 64 bit lines included in the fourth bit line group BL4 of the fourth unit block 204; however, this is merely an example and the disclosure is not limited thereto. When a row access counting operation is performed, the fourth unit block 204 can be based on the third counting column selection signal YI-PRAC. <2> Select the count bit line. The row count value can be stored in multiple memory cells connected to the count bit line of the fourth cell block 204. When a defect is detected in the count bit line, a row access counting operation is being performed, and the fourth cell block 204 can select the third redundant count column based on the RYI-PRAC signal. <2> Select redundant count bit lines. Row count values ​​can be stored in multiple memory cells connected to the redundant count bit lines of the fourth cell block 204.

[0059] The fifth cell block 205 may include multiple memory cells connected to the fifth bit line group BL5. The fifth bit line group BL5 of the fifth cell block 205 may include 64 bit lines selected by column selection signals YI<0:63> from the first to the 64th column. When a column selection operation for a write or read operation is performed, at least one of the 64 bit lines included in the fifth bit line group BL5 of the fifth cell block 205 can be selected by the first to the 64th column selection signals YI<0:63>. Normal data input and output during write and read operations may be stored in the multiple memory cells connected to the 64 bit lines included in the fifth bit line group BL5 of the fifth cell block 205; however, this is merely an example, and this disclosure is not limited thereto.

[0060] When a count read operation is performed in a row access counting operation for memory bank 124, the row count value stored in the memory cell connected to the count bit line selected by the first to third count column selection signals YI-PRAC<0:2> can be output. When a count write operation is performed in a row access counting operation, the updated row count value can be stored in the memory cell connected to the count bit line selected by the first to third count column selection signals YI-PRAC<0:2>.

[0061] Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 This illustrates an embodiment of the present disclosure. Figure 2 A diagram showing the row access counting operation performed in the storage device 110 shown.

[0062] First, such as Figure 6 and Figure 7 As shown, when the command address CA is decoded in the command decoder 111 at time T11 and the precharge command PCG-BK for the precharge operation is generated, the column control signal BYP-PRAC can be generated for the column selection operation of the row access counting operation, and the write-read signal WTRD can be generated for the count read operation. More specifically, the command delay circuit 113 can delay the precharge command PCG-BK by a first delay period to generate a set signal SET, and the column control signal generation circuit 121 can generate the column control signal BYP-PRAC for the column selection operation of the row access counting operation when the set signal SET is generated. In addition, the write-read signal generation circuit 128 can generate the write-read signal WTRD when the precharge command PCG-BK is generated, so that the count read operation is executed.

[0063] Next, as Figure 6 and Figure 8As shown, the column selection operation and count read operation in the row access counting operation can be performed based on the column control signal BYP-PRAC and the write / read signal WTRD. More specifically, when the column control signal BYP-PRAC is generated at time point T12, the counting column selection signal generation circuit 151 can generate the counting column selection signal YI-PRAC during the period T12-T15 when the column selection operation for the row access counting operation is performed, and the column selection switch 155 can connect the bit line pair BL / BLB to the segment input / output line pair SIO / SIOB during the period T12-T15 when the counting column selection signal YI-PRAC is generated. Furthermore, when the write / read signal WTRD is generated for the count read operation, the input / output control circuit 153 can generate the input / output line switch activation signal IOSWEN at time point T13. When the count read operation is executed and the sense amplifier activation signal LSAEN is generated, the sense amplifier 157 can sense and amplify the row count value output from the memory bank 124 that can be transmitted via the segment input / output line pair SIO / SIOB during the count read operation, and can output the row count value to the local input / output line pair LIO / LIOB. In summary, when the column selection operation and the count read operation for the row access count operation are executed, the row count value output from the memory bank 124 can be transmitted from the bit line pair BL / BLB to the segment input / output line pair SIO / SIOB via the column selection switch 155, and the row count value transmitted via the segment input / output line pair SIO / SIOB can be sensed, amplified and output to the local input / output line pair LIO / LIOB by the sense amplifier 157.

[0064] Next, as Figure 9 As shown, when the write signal WT-PRAC is generated in the command delay circuit 113, the write-read signal generation circuit 128 can generate the write-read signal WTRD for the count write operation.

[0065] Next, as Figure 6 and Figure 10As shown, the count write operation can be performed based on the column control signal BYP-PRAC and the write / read signal WTRD. More specifically, the input / output control circuit 153 can generate the input / output line switch activation signal IOSWEN at the time point T14 when the write / read signal WTRD is generated for the count write operation, and the input / output line switch 159 can connect the segment input / output line pair SIO / SIOB and the local input / output line pair LIO / LIOB based on the input / output line switch activation signal IOSWEN, such that: when the count write operation is performed, the updated row count value received through the local input / output line pair LIO / LIOB is transmitted to the segment input / output line pair SIO / SIOB. When the count write operation is performed, the column selection switch 155 can transmit the updated row count value transmitted through the segment input / output line pair SIO / SIOB to the bit line pair BL / BLB based on the count column selection signal YI-PRAC, so as to store the updated row count value in the memory bank 124. In summary, when the count write operation in the row access count operation is executed, the updated row count value received through the local input / output line pair LIO / LIOB can be transmitted via the column selection switch 155 and the input / output line switch 159 via the bit line pair BL / BLB and can be stored in the memory bank 124.

[0066] When a row access counting operation based on the precharge command PCG-BK is performed in the storage device 110 discussed above to update the row count value, a count read operation of the row count value in the output storage bank 124 and a count write operation of storing the updated row count value in the storage bank 124 can be performed during the period when the column selection operation for the row access counting operation is executed. Therefore, the counting column selection signal YI-PRAC does not need to be generated separately for the count read operation and the count write operation, and it is not necessary to precharge the local input / output lines LIO / LIOB, thereby reducing current consumption.

[0067] Figure 11 , Figure 12 and Figure 13 This illustrates an embodiment of the present disclosure. Figure 2 A diagram showing the alarm signal generation operation performed in the storage device 110.

[0068] First, such as Figure 11 and Figure 12As shown, command decoder 111 can decode command address CA to generate activation command ACT-BK to perform an activation operation on the memory cell accessed by activation address ACT-ADD in memory bank 124 (S101). Command decoder 111 can generate precharge command PCG-BK for precharge operation after activation operation (S102). When precharge command PCG-BK is delayed in command delay circuit 113 and latch pulse LPUL is generated, counter adder 115 can increment the row count value output from memory bank 124 by 1 through count read operation to generate update count signal CNT-A with updated row count value (S103). Based on update count signal CNT-A, threshold code TH-CD and activation address ACT-ADD, alarm signal generation circuit 117 can generate alarm signal ALERT.

[0069] Next, as Figure 11 and Figure 12 As shown, the alarm signal generation circuit 117 can determine whether the row count value corresponding to the update count signal CNT-A has reached the threshold corresponding to the threshold code TH-CD (S104) to generate an alarm signal ALERT. When the row count value has not reached the threshold, the row control circuit 123 can perform a precharge operation to release the word line accessed in the activation operation (S105).

[0070] like Figure 11 , Figure 12 and Figure 13 As shown, the code comparison circuit 141 compares the threshold corresponding to the threshold code TH-CD with the row count value corresponding to the update count signal CNT-A to generate an update signal Q-UP. More specifically, since the row count value corresponding to the update count signal CNT-A is set to binary bit group '111' and reaches binary bit group '111' (which is the threshold corresponding to the threshold code TH-C), the code comparison circuit 141 can generate an update signal Q-UP activated at logic "high" level 'H'. When the update signal Q-UP is activated, the address storage circuit 143 can sequentially store the activation address ACT-ADD in queues 147-1 to 147-N (S106). When it is determined that the activation address ACT-ADD is stored in all queues 147-1 to 147-N (S107), the address storage circuit 143 can activate the alarm signal ALERT at logic "high" level 'H' (S108). The line control circuit 123 can perform a precharge operation (S105) after storing the activation address ACT-ADD or generating the activation alarm signal ALERT.

[0071] According to the aforementioned storage device 110, during the row access counting operation, when the updated row count value reaches the threshold and the activation address ACT-ADD is stored in the address storage circuit 143, an alarm signal ALERT can be generated when the address storage circuit 143 is full, thereby managing charge loss from the storage cell.

[0072] The concepts have been disclosed in conjunction with the various embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed in this specification should not be considered from a restrictive but illustrative perspective. The scope of this disclosure is not limited to the foregoing description, and all distinguishing features within the equivalent scope should be understood to be included in this disclosure.

Claims

1. A storage device, comprising: A storage unit that stores a row count value, the row count value corresponding to the number of times each word line is accessed when an activation operation is performed; as well as The column control circuit performs count read and count write operations during the period when the column selection operation set by the precharge command is executed. The column control circuit includes: When the count read operation is performed, the row count value stored in the memory is output to the local input / output line pair, and When the count write operation is performed, the updated row count value transmitted via the local input / output line is stored in the memory.

2. The storage device according to claim 1, wherein, The precharge command is generated after the activation operation to perform the precharge operation.

3. The storage device according to claim 1, wherein, The precharge command is generated after a read or write operation is performed to perform the precharge operation, which is performed after the activation operation.

4. The storage device according to claim 1, wherein, The precharge command is generated to perform a precharge operation, which is performed together with a read operation or a write operation, and the precharge operation and the read operation or the precharge operation and the write operation are performed after the activation operation.

5. The storage device according to claim 1, wherein, The column control circuit includes: The counting column selection signal generation circuit generates the counting column selection signal based on the column control signal generated by the precharge command; An input / output control circuit that generates a sense amplifier activation signal when a write / read signal for the count read operation is generated; and generates an input / output line switch activation signal when the write / read signal for the count write operation is generated. A column selection switch that connects a bit line pair to a segment input / output line pair during the period in which the column selection operation is performed based on the counted column selection signal; A sensing amplifier, which: senses and amplifies a line count value transmitted through the segment input / output line pair based on the sensing amplifier activation signal, and outputs the amplified line count value to the segment input / output line pair; and An input / output line switch, which: based on the input / output line switch activation signal, transmits the updated line count value received through the local input / output line pair to the segment input / output line pair.

6. The storage device of claim 1, further comprising row control circuitry, the row control circuitry: accessing at least one word line based on the activation address when the activation operation is performed; and releasing the word line accessed in the activation operation when a precharge operation is performed.

7. The storage device according to claim 1, further comprising an alarm signal generation circuit, wherein the alarm signal generation circuit generates an alarm signal based on whether the activation address can be stored when the updated row count value reaches a threshold.

8. The storage device according to claim 7, wherein, The alarm signal generation circuit includes: A code comparison circuit compares an update count signal corresponding to the updated row count value with a threshold code corresponding to the threshold to generate an update signal; and An address storage circuit includes multiple queues, wherein the address storage circuit: sequentially stores the activation address based on the update signal; and generates the alarm signal when the activation address is stored in all of the multiple queues.

9. A storage device, comprising: The command delay circuit delays the precharge command to generate a set signal, a write signal, and a reset signal in sequence. A column control signal generation circuit generates a column control signal for column selection operation based on the set signal and the reset signal; A write / read signal generation circuit generates write / read signals based on the precharge command and the write signal; as well as Column control circuit, Specifically: During the period when the column selection operation is performed based on the column control signal and the write / read signal, a count read operation and a count write operation are performed. The column control circuit includes: When the count read operation is performed, the row count value stored in the memory is output to the local input / output line pair; as well as When the count write operation is performed, the updated row count value transmitted via the local input / output line is stored in the memory.

10. The storage device according to claim 9, wherein, The command delay circuit: The precharge command is delayed by a first delay period to generate the set signal; Delaying the set signal by a second delay period to generate the write signal; and The write signal is delayed by a third delay period to generate the reset signal.

11. The storage device according to claim 9, wherein, The column control signal generation circuit generates the column control signal during the period in which the column selection operation is performed, the period being set from the time the set signal is generated until the time the reset signal is generated.

12. The storage device according to claim 9, wherein, The write / read signal generation circuit: When the precharge command is generated, the write-read signal is generated to execute the count read operation; as well as When the write signal is generated, the write-read signal is generated to perform the count write operation.

13. The storage device according to claim 9, wherein, The column control circuit includes: A counting column selection signal generation circuit generates a counting column selection signal based on the column control signal; An input / output control circuit that: generates a sense amplifier activation signal when the write / read signal for the count read operation is generated; and generates an input / output line switch activation signal when the write / read signal for the count write operation is generated; A column selection switch that connects a bit line pair to a segment input / output line pair during the period in which the column selection operation is performed based on the counted column selection signal; A sensing amplifier, which: senses and amplifies a line count value transmitted through the segment input / output line pair based on the sensing amplifier activation signal; and outputs the amplified line count value to the segment input / output line pair; and An input / output line switch, which transmits the updated line count value received through the local input / output line pair to the segment input / output line pair based on the input / output line switch activation signal.

14. The storage device according to claim 9, wherein, The command delay circuit delays the set signal to sequentially generate the input / output sense amplifier control signal, latch pulse, and write driver control signal.

15. The storage device of claim 14, further comprising an input / output sensing amplifier, said input / output sensing amplifier: sensing and amplifying the row count value received through the local input / output line based on the input / output sensing amplifier control signal to output the row count value as read data.

16. The storage device of claim 15, further comprising an error correction circuit, wherein the error correction circuit: Receive the read data; The output is a count signal generated by correcting errors included in the read data; Receive update count signal; and The output is corrected data generated by correcting errors included in the update count signal.

17. The storage device of claim 16, further comprising a counting adder, wherein the counting adder: Receive the counting signal; The row count value is updated by incrementing the row count value corresponding to the count signal by one value; Generate the update count signal corresponding to the updated row count value; and The update count signal is latched based on the latch pulse.

18. The storage device of claim 16, further comprising a write driver, wherein the write driver drives the local input / output pair based on the correction data when the write driver control signal is generated.

19. The storage device of claim 9, further comprising an alarm signal generation circuit, wherein the alarm signal generation circuit generates an alarm signal based on whether the activation address can be stored when the updated row count value reaches a threshold.

20. The storage device according to claim 19, wherein, The alarm signal generation circuit includes: A code comparison circuit compares an update count signal corresponding to the updated row count value with a threshold code corresponding to the threshold to generate an update signal; and An address storage circuit includes multiple queues, wherein the address storage circuit: stores the activation address sequentially based on the update signal; and generates the alarm signal when the activation address is stored in all of the multiple queues.

21. A method for performing a row access counting operation, the method comprising: A column control signal for column selection operation is generated when the first delay period has elapsed since the precharge command was generated; In the column selection operation, a count read operation is performed to output the row count value stored in the memory. Update the row count value output during the count read operation; as well as When the second delay period has elapsed since the precharge command was generated, a count write operation is performed, which stores the updated row count value back into the memory.

22. The method of claim 21, further comprising: Based on the column control signal, the column selection operation is performed to connect the bit line pairs to the segment input / output line pairs.

23. The method of claim 21, further comprising: When the count read operation is performed, the row count value transmitted through the segment input / output line pair is sensed and amplified to output the row count value to the local input / output line pair.

24. The method of claim 21, further comprising: When the count write operation is performed, the updated row count value received through the local input / output line pair is transmitted to the segment input / output line pair.

25. The method of claim 21, further comprising: An alarm signal is generated based on whether the activation address can be stored when the updated row count value reaches a threshold.

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