Method of processing metadata and memory device performing the same

Abstract

The invention relates to a method of processing metadata and a memory device performing the same. A memory device includes a plurality of memory cores and a plurality of cell storage circuits, each of the plurality of cell storage circuits corresponding to a different memory core of the plurality of memory cores. In an embodiment, when a meta write operation is performed, data received via an external line is stored in a plurality of memory cores based on a column address, and metadata received via a meta line is stored in a meta storage circuit selected by the column address among the plurality of meta storage circuits.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0065480, filed on May 20, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a method for processing metadata and a memory device for performing the method. Background Technology

[0004] Typically, memory devices store metadata for efficient management and manipulation of data. Metadata includes detailed information about the characteristics and structure of the data. Metadata may include the physical and logical addresses of the memory, as well as information about the size and type of the data. Memory devices may include storage devices for storing metadata and may include various circuitry for controlling the storage or output of metadata. Summary of the Invention

[0005] In one embodiment, a memory device may include a plurality of memory cores and a plurality of meta-storage circuits, each of the meta-storage circuits corresponding to a different memory core among the plurality of memory cores. In one embodiment, when a meta-write operation is performed, data received via an external line may be stored in the plurality of memory cores based on column addresses, and metadata received via a meta-line may be stored in a meta-storage circuit selected by column address among the plurality of meta-storage circuits.

[0006] In one embodiment of this disclosure, when a meta-read operation is performed, data stored in multiple memory cores can be output to an external line based on column addresses. When a meta-read operation is performed, metadata stored in multiple meta-storage circuits selected by column addresses can be output to the meta line.

[0007] In embodiments of this disclosure, when an internal metadata write operation is performed, metadata stored in multiple metadata storage circuits can be output to the read metadata line based on column addresses. When an internal metadata write operation is performed, metadata received via the read metadata line can be stored in multiple memory cores based on column addresses.

[0008] In one embodiment of this disclosure, when an internal metadata read operation is performed, metadata stored in multiple memory cores can be output to the write metadata line based on column addresses. When an internal metadata read operation is performed, metadata received via the write metadata line can be stored in multiple metadata storage circuits based on column addresses.

[0009] In an embodiment of the disclosure, when a meta parallel write operation is performed, a test voltage can be stored in a plurality of meta storage circuits. When the meta parallel write operation is performed, the test voltage stored in the plurality of meta storage circuits can be stored in a plurality of memory cores. When a meta parallel read operation is performed, the test voltage stored in the plurality of memory cores can be output to an external line.

[0010] In an embodiment, a method of processing meta data can include, when a meta write operation is performed, storing data received via an external line in a plurality of memory cores based on a column address, and storing meta data received via a meta line in at least one meta storage circuit of the plurality of meta storage circuits selected by the column address.

[0011] In an embodiment, a method of processing meta data can include, when a meta read operation is performed, outputting data stored in a plurality of memory cores to an external line based on a column address, and outputting meta data stored in a meta storage circuit of the plurality of meta storage circuits selected by the column address to a meta line.

[0012] In an embodiment, a method of processing meta data can include, when an internal meta write operation is performed, outputting meta data stored in a plurality of meta storage circuits to a read meta line based on a column address, and storing meta data received via the read meta line in a plurality of memory cores based on the column address.

[0013] In an embodiment, a method of processing meta data can include, when an internal meta read operation is performed, outputting meta data stored in a plurality of memory cores to a write meta line based on a column address, and storing meta data received via the write meta line in a plurality of meta storage circuits based on the column address.

[0014] In an embodiment, a method of processing meta data can include, when a meta parallel write operation is performed, storing a test voltage in a plurality of meta storage circuits, when the meta parallel write operation is performed, storing the test voltage stored in the plurality of meta storage circuits in a plurality of memory cores, and when a meta parallel read operation is performed, outputting the test voltage stored in the plurality of memory cores to an external line. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 A memory system according to an example of the disclosure is illustrated.

[0016] Figure 2 A memory device according to an example of the disclosure is illustrated.

[0017] Figure 3 A meta control circuit and a meta storage circuit according to an example of the disclosure are illustrated.

[0018] Figure 4 An example of a meta storage circuit is shown in accordance with the present disclosure.

[0019] Figure 5 Circuitry of a meta register is shown in accordance with examples of the present disclosure.

[0020] Figure 6 A meta data driver is shown in accordance with examples of the present disclosure.

[0021] Figure 7 An input output line driver is shown in accordance with examples of the present disclosure.

[0022] Figure 8 A table including data used in meta mode operations performed based on column addresses is shown in accordance with examples of the present disclosure.

[0023] Figure 9 A memory device during operations including storing data and meta data during a meta write operation is shown in accordance with embodiments of the present disclosure.

[0024] Figure 10 A timing diagram during a meta write operation including storing meta data based on column addresses is shown in accordance with embodiments of the present disclosure.

[0025] Figure 11 A path in a memory device along which data and meta data are stored during a meta write operation is shown in accordance with embodiments of the present disclosure.

[0026] Figure 12 A meta data driver during a meta write operation including outputting received meta data to a write meta line is shown in accordance with embodiments of the present disclosure.

[0027] Figure 13 Circuitry of a meta register during a meta write operation including storing received meta data in a data latch is shown in accordance with embodiments of the present disclosure.

[0028] Figure 14 An input output line driver during a meta write operation including outputting received data to an internal line is shown in accordance with embodiments of the present disclosure.

[0029] Figure 15 A memory device during a meta read operation including outputting data and meta data is shown in accordance with embodiments of the present disclosure.

[0030] Figure 16 A timing diagram during a meta read operation including outputting meta data stored in a meta register based on column addresses is shown in accordance with embodiments of the present disclosure.

[0031] Figure 17 A path followed by outputting data and meta data during a meta read operation in a memory device according to an embodiment of the disclosure is shown.

[0032] Figure 18 Circuitry of a meta register during a meta read operation including outputting meta data stored in a data latch to a read meta line according to an embodiment of the disclosure is shown.

[0033] Figure 19 A meta data driver during an operation including outputting meta data received through a read meta line to a meta line according to an embodiment of the disclosure is shown.

[0034] Figure 20 An input / output line driver during a meta read operation including outputting data received through an internal line to an external line BGIO according to an embodiment of the disclosure is shown.

[0035] Figure 21 A memory device during an internal meta write operation including storing meta data output by a meta storage circuit in a memory core according to an embodiment of the disclosure is shown.

[0036] Figure 22 A timing diagram during an internal meta write operation including outputting and storing meta data based on a column address according to an embodiment of the disclosure is shown.

[0037] Figure 23 A path followed by outputting meta data from a meta storage circuit during an internal meta write operation in a memory device and a path followed by storing meta data in a memory core according to an embodiment of the disclosure is shown.

[0038] Figure 24 Circuitry of a meta register during an internal meta write operation including outputting meta data stored in a meta register to a read meta line according to an embodiment of the disclosure is shown.

[0039] Figure 25 An input / output line driver during an internal meta write operation including outputting meta data received through a read meta line to an internal line according to an embodiment of the disclosure is shown.

[0040] Figure 26 A memory device during an internal meta read operation including storing meta data output by a memory core in a meta storage circuit according to an embodiment of the disclosure is shown.

[0041] Figure 27 A timing diagram during an internal meta read operation including outputting meta data by a memory core and storing the meta data in a meta storage circuit based on a column address according to an embodiment of the disclosure is shown.

[0042] Figure 28 A path followed by a memory core to output test voltages stored in the memory core during a meta-parallel read operation in a memory device is shown in accordance with an embodiment of the present disclosure.

[0043] Figure 29 A circuit of a meta register during a meta-parallel write operation including outputting test voltages stored in the meta register to a read meta line is shown in accordance with an embodiment of the present disclosure.

[0044] Figure 30 A circuit of a meta register during a meta-parallel write operation including outputting test voltages stored in the meta register to a read meta line is shown in accordance with an embodiment of the present disclosure.

[0045] Figure 31 An example of a meta data driver for a meta-parallel write operation is shown in accordance with an embodiment of the present disclosure.

[0046] Figure 32 A path followed by a meta storage circuit to output test voltages during a meta-parallel write operation in a memory device and a path followed by storing test voltages in a memory core is shown in accordance with an embodiment of the present disclosure.

[0047] Figure 33 A circuit of a meta register during a meta-parallel write operation including outputting test voltages stored in the meta register to a read meta line is shown in accordance with an embodiment of the present disclosure.

[0048] Figure 34 An input-output line driver during a meta-parallel write operation including outputting meta data received through a read meta line to an internal line is shown in accordance with an embodiment of the present disclosure.

[0049] Figure 35 A path followed by a memory core to output test voltages stored in the memory core during a meta-parallel read operation in a memory device is shown in accordance with an embodiment of the present disclosure.

[0050] Figure 36 An input-output line driver during a meta-parallel read operation including outputting data received through an internal line to an external line is shown in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] The term “meta” is an abbreviation for “metadata” when used in conjunction with other terms such as “meta mode,” “meta read,” and “meta write” in the present disclosure.

[0052] Terms such as "first" and "second" used to distinguish a variety of components do not imply the size, order, priority, number, or importance of the components. For example, a first component can be referred to as a second component, and vice versa.

[0053] When a component is referred to as being "connected" to another component, the two components can be directly connected to each other or connected to each other through an intermediate component. When a component is referred to as being "directly connected" to another component, the two components are directly connected to each other without an intermediate component.

[0054] "Logic high level" and "logic low level" are used to describe the logic level of a signal. A signal of a logic high level is different from a signal of a logic low level. For example, when a signal at a first voltage corresponds to a signal of a logic high level, a signal at a second voltage corresponds to a signal of a logic low level. According to an embodiment, the voltage of a logic high level is a voltage higher than the voltage of a logic low level. According to an embodiment, the logic level of a signal can be set to a different logic level or the opposite logic level. For example, a signal of a logic high level can be at a logic low level in some embodiments, and a signal of a logic low level can be at a logic high level in some embodiments.

[0055] "A bit group" includes a combination of the logic levels of the bits included in a signal. When the logic level of each bit included in a signal changes, the bit group of the signal also changes. For example, if two bits are included in a signal, when the logic levels of the two bits included in the signal are a logic low level and a logic low level, the bit group of the signal includes a first bit group, and when the logic levels of the two bits included in the signal are a logic low level and a logic high level, the bit group of the signal includes a second bit group.

[0056] The present disclosure is described in detail below by way of examples. The examples are provided only for illustrating the present disclosure, and the scope of the present disclosure is not limited by the examples.

[0057] Figure 1 A memory system 1 according to examples of the present disclosure is shown. As Figure 1 shown, in an embodiment, the memory system 1 includes a memory controller 11, a first memory device 13-1, and a second memory device 13-2.

[0058] The memory controller 11 controls a write operation, a read operation, and a meta mode operation to be performed to the first memory device 13-1 through, for example, the first sub-channel S-CH1. The meta mode operation includes, for example, a meta write operation, a meta read operation, an internal meta write operation, and an internal meta read operation. When the write operation is performed, the memory controller 11 transmits data to the first memory device 13-1 through the first sub-channel S-CH1, while when the read operation is performed, the memory controller 11 receives data from the first memory device 13-1 through the first sub-channel S-CH1. When the meta write operation is performed, the memory controller 11 transmits data and meta data to the first memory device 13-1 through the first sub-channel S-CH1, while when the meta read operation is performed, the memory controller 11 receives data and meta data from the first memory device 13-1 through the first sub-channel S-CH1. When the write operation is performed, the memory controller 11 transmits data to the second memory device 13-2 through the second sub-channel S-CH2, while when the read operation is performed, the memory controller 11 receives data from the second memory device 13-2 through the second sub-channel S-CH2. When the meta write operation is performed, the memory controller 11 transmits data and meta data to the second memory device 13-2 through the second sub-channel S-CH2, while when the meta read operation is performed, the memory controller 11 receives data and meta data from the second memory device 13-2 through the second sub-channel S-CH2. In this example, each of the first sub-channel S-CH1 and the second sub-channel S-CH2 can communicate thirty-two bits in parallel, but the present disclosure is not limited to this example.

[0059] For example, when the write operation is performed, the first memory device 13-1 stores data received from the memory controller 11 in the memory core, for example, MC0 to MC31 in the memory core 14-1. For example, when the read operation is performed, the first memory device 13-1 transmits data stored in the memory core to the memory controller 11. For example, when the meta write operation is performed, the first memory device 13-1 stores data received from the memory controller 11 in the memory core and stores meta data in the first meta storage circuit (META STG) 15-1. For example, when the meta read operation is performed, the first memory device 13-1 transmits data stored in the memory core and meta data stored in the first meta storage circuit 15-1 to the memory controller 11. For example, when the internal meta write operation is performed, the first memory device 13-1 stores meta data stored in the first meta storage circuit 15-1 in the memory core. For example, when the internal meta read operation is performed, the first memory device 13-1 stores meta data stored in the memory core in the first meta storage circuit 15-1. Figure 2

[0060] ​For example, when a write operation is performed, the second memory device 13-2 stores data received from the memory controller 11 in the memory core. The memory core of the second memory device 13-2 and the memory core of the first memory device 13-1 are distinguished from or different from each other. When a read operation is performed, the second memory device 13-2 transfers data stored in the memory core to the memory controller 11. For example, when a meta write operation is performed, the second memory device 13-2 stores data received from the memory controller 11 in the memory core and stores meta data received from the memory controller 11 in the second meta storage circuit (META STG) 15-2. For example, when a meta read operation is performed, the second memory device 13-2 transfers data stored in the memory core and meta data stored in the second meta storage circuit 15-2 to the memory controller 11. For example, when an internal meta write operation is performed, the second memory device 13-2 stores meta data stored in the second meta storage circuit 15-2 in the memory core. For example, when an internal meta read operation is performed, the second memory device 13-2 stores meta data stored in the memory core in the second meta storage circuit 15-2.

[0061] Figure 2 A memory device according to an example of the present disclosure is shown. Figure 2 The memory device shown in FIG. 1 is Figure 1 An example of implementation of the first memory device 13-1 and / or the second memory device 13-2 shown in FIG. 2 is shown. As shown in FIG. 2, in an embodiment, the memory device includes memory cores MC0 to MC31, sub word lines SWD, column decoders YDEC0 to YDEC31, write drivers WTDRV0 to WTDRV31, input / output sense amplifiers IOSA0 to IOSA31, input / output line drivers BIODRV0 to BIODRV31, meta storage circuits META STG0 to META STG31, and meta lines BGIO-MD<0:7> and BGIO-MD<0:8>. The memory device can perform meta mode operations based on a column address (e.g., BYAC<4:9>) in FIG. 1. The meta write operation, the meta read operation, the internal meta write operation, and the internal meta read operation included in the meta mode operations of the memory device are described as follows. Figure 3

[0062] When the meta write operation is performed based on the column address, data is stored in the memory core via the external line (e.g., BGIO-MD<0:7> in FIG. 1) and the meta data is stored in the second meta storage circuit 15-2 via the meta line (e.g., BGIO-MD<0:8> in FIG. 1). Figure 7 ​The data received via the meta lines BGIO-MD<0:7> and BGIO-MD<8:15> is stored in the memory cores MC0 to MC31 via the input / output line drivers BIODRV0 to BIODRV31, the write drivers WTDRV0 to WTDRV31, and the column decoders YDEC0 to YDEC31. For example, when a sub write operation is performed, 256 bits of data are stored in the memory cores MC0 to MC31 based on a column selection signal selected or identified by a column address (e.g., YI0 of YI0 to YI59), with 8 bits stored in each of the 32 memory cores MC0 to MC31. For example, when a sub write operation is performed based on a column address, the sub data received via the meta lines BGIO-MD<0:7> and BGIO-MD<8:15> is stored in two of the meta storage circuits METASTG0 to METASTG31 selected by the column address. For example, when the meta storage circuits METASTG0 and METASTG1 (hereinafter denoted as “METASTG0 / 1”) are selected by a column address during a sub write operation, the sub data received via the meta lines BGIO-MD<0:7> and BGIO-MD<8:15> is driven by the input / output line drivers BIODRV0 and BIODRV1 such that 16 bits of sub data are stored in the meta storage circuits METASTG0 / 1, with 8 bits stored in each of the meta storage circuits METASTG0 / 1.

[0063] When a sub read operation is performed based on a column address, the data stored in the memory cores MC0 to MC31 is output via the column decoders YDEC0 to YDEC31, the input / output sense amplifiers IOSA0 to IOSA31, and the input / output line drivers BIODRV0 to BIODRV31 through the external lines (e.g., Figure 7For example, when a meta read operation is performed, a total of 256 bits of data (8 bits each in the memory cores MC0 to MC31) stored in the memory cores MC0 to MC31 can be output via the external lines based on a column selection signal (e.g., YI0 in YI0 to YI59) selected by the column address. For example, when a meta read operation is performed based on the column address, meta data stored in two of the meta storage circuits METASTG0 to METASTG31 is output via the meta lines BGIO-MD<0:7> and BGIO-MD<8:15>. For example, when the meta storage circuits METASTG0 / 1 are selected by the column address during a meta read operation, a total of 16 bits of meta data (including 8 bits stored in each of the meta storage circuits METASTG0 / 1) can be driven by the input / output line drivers BIODRV0 and BIODRV1 and output via the meta lines BGIO-MD<0:7> and BGIO-MD<8:15>.

[0064] For example, when an internal meta write operation is performed based on the column address, meta data stored in the meta storage circuits METASTG0 to METASTG31 can be driven by the input / output line drivers BIODRV0 and BIODRV1 and output, and stored in the memory cores MC0 to MC31 by the column decoders YDEC0 to YDEC31 and the write drivers WTDRV0 to WTDRV31, respectively. For example, during an internal meta write operation, a total of 256 bits of meta data stored in the meta storage circuits METASTG0 / 1 can be stored in the memory cores MC0 to MC31 based on a column selection signal (e.g., YI60 in YI60 to YI63) selected by the column address, with 8 bits stored in each of the 32 memory cores MC0 to MC31.

[0065] For example, when an internal meta read operation is performed based on the column address, meta data stored in the memory cores MC0 to MC31 is output by the column decoders YDEC0 to YDEC31 and the input / output sense amplifiers IOSA0 to IOSA31, driven by the input / output line drivers BIODRV0 and BIODRV1, and stored in the meta storage circuits METASTG0 to METASTG31, respectively. For example, during an internal meta read operation, a total of 256 bits (8 bits each in the memory cores MC0 to MC31) of meta data output by the memory cores MC0 to MC31 based on a column selection signal (e.g., YI60 in YI60 to YI63) selected by the column address is stored in the meta storage circuits METASTG0 to METASTG31, respectively.

[0066] Figure 3 A meta-control circuit MCTR 101 and a meta-storage circuit META STG 103 according to examples of the present disclosure are shown.

[0067] The meta control circuit 101 generates a latch input signal MS-WR, a latch output signal MS-RD, an internal meta write pulse WGIO-ENP-MR, and an internal meta read pulse RGIO-ENP-MR based on a column bank signal CBANK, a column address BYAC, an address latch pulse ADDLATP, a write pulse WGIO-ENP, a meta write pulse WGIO-ENP-MD, a read pulse RGIO-ENP, a meta read pulse RGIO-ENP-MD, and a meta mode signal META-M. The column bank signal CBANK is generated for each bit of meta data input and output when a meta mode operation is performed based on the column address BYAC for each bank. The column address BYAC is generated to select a memory core inputting and outputting data or to select a memory core and a meta storage circuit inputting and outputting meta data during the meta mode operation. The address latch pulse ADDLATP is sequentially generated in synchronization with the column bank signal CBANK to latch the column address BYAC during the meta mode operation. The write pulse WGIO-ENP and the meta write pulse WGIO-ENP-MD are generated when a meta write operation is performed during the meta mode operation. The write pulse WGIO-ENP and the meta write pulse WGIO-ENP-MD can be generated after the column bank signal CBANK and the address latch pulse ADDLATP are generated. The internal meta write pulse WGIO-ENP-MR is generated when an internal meta write operation is performed during the meta mode operation. The internal meta write pulse WGIO-ENP-MR can be generated after the column bank signal CBANK and the address latch pulse ADDLATP are generated. The read pulse RGIO-ENP and the meta read pulse RGIO-ENP-MD are generated when a meta read operation is performed during the meta mode operation. The read pulse RGIO-ENP and the meta read pulse RGIO-ENP-MD can be generated after the column bank signal CBANK and the address latch pulse ADDLATP are generated. The internal meta read pulse RGIO-ENP-MR is generated when an internal meta read operation is performed during the meta mode operation. The internal meta read pulse RGIO-ENP-MR can be generated after the column bank signal CBANK and the address latch pulse ADDLATP are generated. The latch input signal MS-WR is generated when a meta write operation or an internal meta read operation is performed during the meta mode operation. The latch input signal MS-WR can be generated after the column bank signal CBANK and the address latch pulse ADDLATP are generated. The latch output signal MS-RD is generated when a meta read operation or an internal meta write operation is performed during the meta mode operation. The latch output signal MS-RD can be generated after the column bank signal CBANK and the address latch pulse ADDLATP are generated.The meta control circuit 101 is electrically connected to the meta storage circuit 103 and outputs the latch input signal MS-WR, the latch output signal MS-RD, the write pulse WGIO-ENP, the meta write pulse WGIO-ENP-MD, the internal meta write pulse WGIO-ENP-MR, the read pulse RGIO-ENP, the meta read pulse RGIO-ENP-MD, and the internal meta read pulse RGIO-ENP-MR to the meta storage circuit 103.

[0068] The meta storage circuit 103 stores and outputs meta data based on the latch input signal MS-WR, the latch output signal MS-RD, the write pulse WGIO-ENP, the meta write pulse WGIO-ENP-MD, the internal meta write pulse WGIO-ENP-MR, the read pulse RGIO-ENP, the meta read pulse RGIO-ENP-MD, and the internal meta read pulse RGIO-ENP-MR. For example, when a meta write operation is performed during the meta mode operation, the meta storage circuit 103 stores meta data received via the meta line in a meta register selected by the latch input signal MS-WR in the meta register META REG in, for example, Figure 4 For example, when a meta read operation is performed during the meta mode operation, the meta storage circuit 103 outputs meta data stored in a meta register selected by the latch output signal MS-RD in the meta register META REG in, for example, Figure 4 For example, when an internal meta write operation is performed during the meta mode operation, the meta storage circuit 103 outputs meta data stored in a meta register selected by the latch output signal MS-RD in the meta register META REG in, for example, Figure 4 For example, when an internal meta read operation is performed during the meta mode operation, the meta storage circuit 103 stores meta data output by the memory core in a meta register selected by the latch input signal MS-WR in the meta register META REG in, for example, Figure 4

[0069] Figure 4 An example of the meta storage circuit 103 is shown.

[0070] As Figure 4 ​As shown, in one embodiment, the meta storage circuit 103 includes thirty-two meta registers META REG and eight meta data drivers METADATA DRV selected by the first to fourth meta group signals MRG<0:3>. For example, the meta storage circuit 103 includes eight meta registers META REG and two meta data drivers METADATA DRV selected by the first meta group signal MRG<0>, eight meta registers META REG and two meta data drivers METADATA DRV selected by the second meta group signal MRG<1>, eight meta registers META REG and two meta data drivers METADATA DRV selected by the third meta group signal MRG<2>, and eight meta registers META REG and two meta data drivers METADATA DRV selected by the fourth meta group signal MRG<3>. The eight meta registers META REG selected by the first meta group signal MRG<0> are grouped into two groups of four meta registers META REG, and each of the two meta data drivers METADATA DRV is assigned four meta registers META REG. Meta data of 8 bits (4 bits per meta data driver METADATA DRV) driven by the two meta data drivers METADATA DRV can be stored in the eight meta registers META REG or can be output. The eight meta registers META REG selected by the second meta group signal MRG<1> are grouped into two groups of four meta registers META REG, and each of the two meta data drivers METADATA DRV is assigned four meta registers META REG. Meta data of 8 bits (4 bits per meta data driver METADATA DRV) driven by the two meta data drivers METADATA DRV can be stored in the eight meta registers META REG or can be output. The eight meta registers META REG selected by the third meta group signal MRG<2> are grouped into two groups of four meta registers META REG, and each of the two meta data drivers METADATA DRV is assigned four meta registers META REG. Meta data of 8 bits (4 bits per meta data driver METADATA DRV) driven by the two meta data drivers METADATA DRV can be stored in the eight meta registers META REG or can be output. The eight meta registers META REG selected by the fourth meta group signal MRG<3> are grouped into two groups of four meta registers META REG, and each of the two meta data drivers METADATA DRV is assigned four meta registers META REG. Meta data of 8 bits (4 bits per meta data driver METADATA DRV) driven by the two meta data drivers METADATA DRV can be stored in the eight meta registers META REG or can be output.Eight-bit meta data (four-bit per meta data driver METADATA DRV) driven by two meta data drivers METADATA DRV can be stored in eight meta registers META REG or can be output.

[0071] Figure 5 A circuit of a meta register according to an example of the present disclosure is shown.

[0072] As shown in Figure 5 In an embodiment, the meta register comprises a data latch 111, a latch input circuit 113 and a latch output circuit 115.

[0073] For example, when a meta write operation or an internal meta read operation is performed, the latch input circuit 113 stores meta data input via the write meta line BGIO-MDD-WR in the data latch 111 based on a latch input signal MS-WR generated at a logic high level and an inverted latch input signal MS-WRB generated at a logic low level.

[0074] For example, when a meta write operation or an internal meta read operation is performed, the data latch 111 stores meta data received via the latch input circuit 113. The data latch 111 can be implemented, for example, in a single-latch type and stores meta data of one bit. The type of the data latch 111 and the number of bits of the meta data stored can be different from that described in the present example. The data latch 111 can be selected by a column address.

[0075] For example, when a meta read operation or an internal meta write operation is performed, the latch output circuit 115 outputs meta data stored in the data latch 111 via the read meta line BGIO-MDD-RD based on a latch output signal MS-RD generated at a logic high level and an inverted latch output signal MS-RDB generated at a logic low level.

[0076] Figure 6 A meta data driver according to an example of the present disclosure is shown.

[0077] As shown in Figure 6 In an embodiment, the meta data driver comprises selectors (SEL) 121 and 123, latches (LAT) 125 and a read driver (RD DRV) 127.

[0078] When a meta write operation is performed, the selector 121 outputs meta data received via the meta line BGIO-MD based on a generated meta write pulse WGIO-ENP-MD. For example, when an internal meta read operation is performed, the selector 123 outputs meta data output by the memory core and received via the internal line EIOD based on an internal meta read pulse RGIO-ENP-MR.

[0079] Latch 125 is electrically connected to selectors 121 and 123, latches the metadata output by selectors 121 and 123, and outputs the latched metadata to write global line BGIO-MDD-WR. For example, when a global write operation is performed, latch 125 latches the metadata output by selector 121 and outputs the latched metadata to write global line BGIO-MDD-WR. For example, when an internal global read operation is performed, latch 125 latches the metadata output by selector 123 and outputs the latched metadata to write global line BGIO-MDD-WR.

[0080] When a global read operation is performed, read driver 127 outputs the metadata output by the global register and received via read global line BGIO-MDD-RD to global line BGIO-MD based on global read pulse RGIO-ENP-MD.

[0081] When a global write operation is performed, the metadata driver outputs the metadata received via global line BGIO-MD to write global line BGIO-MDD-WR. When an internal global read operation is performed, the metadata driver outputs the metadata output by the memory core and received via internal line EIOD to write global line BGIO-MDD-WR. When a global read operation is performed, the metadata driver outputs the metadata output by the global register and received via read global line BGIO-MDD-RD to global line BGIO-MD.

[0082] Figure 7 An input / output line driver according to an example of the present disclosure is shown.

[0083] As Figure 7 shown, in one embodiment, the input / output line driver includes selectors (SEL) 131 and 133, latch (LAT) 135, and read driver (RD DRV) 137.

[0084] Selector 131 outputs data received via external line BGIO based on write pulse WGIO-ENP generated when a global write operation is performed. For example, when an internal global write operation is performed, selector 133 outputs the metadata output by the global register and received via read global line BGIO-MDD-RD based on internal global write pulse WGIO-ENP-MR.

[0085] The latch 135 is electrically connected to the selectors 131, 133, latches data output by the selector 131 and outputs the latched data to the internal line EIOD, and latches metadata output by the selector 133 and outputs the latched metadata to the internal line EIOD. For example, when a meta write operation is performed, the latch 135 latches data output by the selector 131 and outputs the latched data to the internal line EIOD. For example, when an internal meta write operation is performed, the latch 135 latches metadata output by the selector 133 and outputs the latched metadata to the internal line EIOD.

[0086] For example, when a meta read operation is performed, the read driver 137 outputs data output by the memory core and received via the internal line EIOD to the external line BGIO based on a read pulse RGIO-ENP.

[0087] For example, when a meta write operation is performed, the input / output line driver outputs data received via the external line BGIO to the internal line EIOD. For example, when an internal meta write operation is performed, the input / output line driver outputs metadata output by the meta register and received via the read meta line BGIO-MDD-RD to the internal line EIOD. For example, when a meta read operation is performed, the input / output line driver outputs data output by the memory core and received via the internal line EIOD to the external line BGIO.

[0088] Figure 8 A table including data used in a meta mode operation performed based on a column address according to an example of the present disclosure is shown.

[0089] As Figure 8As shown, when the meta write operation is performed during the period when the column address BYAC<9:4> is in the bit group "000000", a total of 32 bytes 32B or 256 bits of data are stored in the memory cores MC0 to MC31 (1 byte 1B or 8 bits in each of the memory cores MC0 to MC31), and a total of 2 bytes 2B or 16 bits of meta data are stored in the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1 (1 byte 1B or 8 bits in each of the meta storage circuits META STG0 / 1). Since the column selection signal YI0 for each of the memory cores MC0 to MC31 is selected based on the bit group "0000" of the column address BYAC<7:4>, a total of 32 bytes 32B or 256 bits of data are stored in the memory cells belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI0, 1 byte 1B or 8 bits for each of the memory cores MC0 to MC31. Since the memory cores MC0 / 1 are selected based on the bit group "0000" of the column address BYAC<7:4> and the first meta group signal MRG<0> is selected based on the bit group "00" of the column address BYAC<9:8>, a total of 16 bits of meta data are stored in the meta registers belonging to each of the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1 and selected by the first meta group signal MRG<0>, 8 bits for each of the meta storage circuits META STG0 / 1.

[0090] As Figure 8As shown, when the meta read operation is performed with the column address BYAC<9:4> in the state of the bit group "000000", 1 byte 1B or 8 bits of data stored in each of the memory cores MC0 to MC31 (a total of 32 bytes 32B or 256 bits of data) can be output, and 1 byte 1B or 8 bits of meta data stored in each of the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1 (a total of 2 bytes 2B or 16 bits of meta data) can be output. Since the column selection signal YI0 for each of the memory cores MC0 to MC31 is selected based on the bit group "0000" of the column address BYAC<7:4>, 1 byte 1B or 8 bits of data stored in each memory cell belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI0 (a total of 32 bytes 32B or 256 bits of data) can be output. Since the memory cores MC0 / 1 are selected based on the bit group "0000" of the column address BYAC<7:4> and the first meta group signal MRG<0> is selected based on the bit group "00" of the column address BYAC<9:8>, a total of 2 bytes 2B or 16 bits of meta data stored in the meta registers selected by the first meta group signal MRG<0> and belonging to each of the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1 (8 bits per meta storage circuit META STG0 / 1) can be output.

[0091] As Figure 8As shown, when the meta write operation is performed with the column address BYAC<9:4> being in the state of the bit group "000001", a total of 32 bytes 32B or 256 bits of data can be stored in the memory cores MC0 to MC31, each of 1 byte 1B or 8 bits, and a total of 2 bytes 2B or 16 bits of meta data are stored in the meta storage circuits META STG2 / 3 assigned to the memory cores MC2 / 3, each of 1 byte 1B or 8 bits. Since the column selection signal YI1 for each of the memory cores MC0 to MC31 is selected based on the bit group "0001" of the column address BYAC<7:4>, a total of 32 bytes 32B or 256 bits of data can be stored in the memory cells belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI1, each of 1 byte 1B or 8 bits. Since the memory cores MC2 / 3 are selected based on the bit group "0001" of the column address BYAC<7:4> and the first meta group signal MRG<0> is selected based on the bit group "00" of the column address BYAC<9:8>, a total of 2 bytes 2B or 16 bits (8 bits per meta storage circuit META STG2 / 3) of meta data can be stored in the meta registers belonging to each of the meta storage circuits META STG2 / 3 assigned to the memory cores MC2 / 3 and selected by the first meta group signal MRG<0>.

[0092] As Figure 8As shown, when the meta read operation is performed with the column address BYAC<9:4> in the state of the bit group "000001", 1 byte 1B or 8 bits of data stored in each of the memory cores MC0 to MC31 (totaling 32 bytes 32B or 256 bits of data) can be output, and 1 byte 1B or 8 bits of meta data stored in each of the meta storage circuits META STG0 / 1 assigned to the memory cores MC2 / 3 (totaling 2 bytes 2B or 16 bits of meta data) can be output. Since the column selection signal YI16 for each of the memory cores MC0 to MC31 is selected based on the bit group "0001" of the column address BYAC<7:4>, 1 byte 1B or 8 bits of data stored in each memory cell belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI1 (totaling 32 bytes 32B or 256 bits of data) can be output. Since the memory cores MC2 / 3 are selected based on the bit group "0001" of the column address BYAC<7:4> and the first meta group signal MRG<0> is selected based on the bit group "00" of the column address BYAC<9:8>, 2 bytes 2B or 16 bits of meta data stored in the meta registers belonging to each of the meta storage circuits META STG2 / 3 assigned to the memory cores MC2 / 3 and selected by the first meta group signal MRG<0> (8 bits per meta storage circuit META STG2 / 3) can be output.

[0093] As Figure 8As shown, when the meta write operation is performed with the column address BYAC<9:4> being in the state of the bit group "010000", a total of 32 bytes 32B or 256 bits of data can be stored in the memory cores MC0 to MC31, 1 byte 1B or 8 bits for each of the memory cores MC0 to MC31, and a total of 2 bytes 2B or 16 bits of meta data can be stored in the meta storage circuits METASTG0 / 1 assigned to the memory cores MC0 / 1, 1 byte 1B or 8 bits for each of the meta storage circuits METASTG0 / 1. Since the column selection signal YI1 for each of the memory cores MC0 to MC31 is selected based on the bit group "0000" of the column address BYAC<7:4>, a total of 32 bytes 32B or 256 bits of data can be stored in the memory cells belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI16, 1 byte 1B or 8 bits for each of the memory cores MC0 to MC31. Since the memory cores MC0 / 1 are selected based on the bit group "0000" of the column address BYAC<7:4> and the second meta group signal MRG<1> is selected based on the bit group "01" of the column address BYAC<9:8>, a total of 2 bytes 2B or 16 bits of meta data (8 bits for each of the meta storage circuits METASTG0 / 1) can be stored in the meta registers belonging to each of the meta storage circuits METASTG0 / 1 assigned to the memory cores MC0 / 1 and selected by the second meta group signal MRG<1>.

[0094] As Figure 8As shown, when the meta read operation is performed with the column address BYAC<9:4> being in the state of the bit group "010000", 1 byte 1B or 8 bits of data stored in each of the memory cores MC0 to MC31 (totaling 32 bytes 32B or 256 bits of data) can be output, and 1 byte 1B or 8 bits of meta data stored in each of the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1 (totaling 2 bytes 2B or 16 bits of meta data) can be output. Since the column selection signal YI16 of each of the memory cores MC0 to MC31 is selected based on the bit group "0000" of the column address BYAC<7:4>, 1 byte 1B or 8 bits of data stored in each memory cell belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI16 (totaling 32 bytes 32B or 256 bits of data) can be output. Since the memory cores MC0 / 1 are selected based on the bit group "0000" of the column address BYAC<7:4> and the second meta group signal MRG<1> is selected based on the bit group "01" of the column address BYAC<9:8>, 2 bytes 2B or 16 bits of meta data stored in the meta registers selected by the second meta group signal MRG<1> and belonging to each of the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1 (8 bits per meta storage circuit META STG0 / 1) can be output.

[0095] As Figure 8As shown, when the meta write operation is performed with the column address BYAC<9:4> being in the state of the bit group "100000", a total of 32 bytes 32B or 256 bits of data can be stored in the memory cores MC0 to MC31, each of 1 byte 1B or 8 bits, and a total of 2 bytes 2B or 16 bits of meta data are stored in the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1, each of 1 byte 1B or 8 bits. Since the column selection signal YI32 for each of the memory cores MC0 to MC31 is selected based on the bit group "0000" of the column address BYAC<7:4>, a total of 32 bytes 32B or 256 bits of data can be stored in the memory cells belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI32, each of 1 byte 1B or 8 bits. Since the memory cores MC0 / 1 are selected based on the bit group "0000" of the column address BYAC<7:4> and the third meta group signal MRG<2> is selected based on the bit group "10" of the column address BYAC<9:8>, a total of 2 bytes 2B or 16 bits of meta data can be stored in the meta registers belonging to each of the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1 and selected by the third meta group signal MRG<2>, each of 8 bits.

[0096] As Figure 8As shown, when the meta read operation is performed with the column address BYAC<9:4> being in the state of the bit group "100000", 1 byte 1B or 8 bits of data stored in each of the memory cores MC0 to MC31 (a total of 32 bytes 32B or 256 bits of data) can be output, and 1 byte 1B or 8 bits of meta data stored in each of the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1 (a total of 2 bytes 2B or 16 bits of meta data) can be output. Since the column selection signal YI32 for each of the memory cores MC0 to MC31 is selected based on the bit group "0000" of the column address BYAC<7:4>, 1 byte 1B or 8 bits of data stored in each memory cell belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI32 (a total of 32 bytes 32B or 256 bits of data) can be output. Since the memory cores MC0 / 1 are selected based on the bit group "0000" of the column address BYAC<7:4> and the third meta group signal MRG<2> is selected based on the bit group "10" of the column address BYAC<9:8>, a total of 2 bytes 2B or 16 bits of meta data (8 bits per meta storage circuit META STG0 / 1) stored in the meta registers belonging to each of the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1 and selected by the third meta group signal MRG<2> can be output.

[0097] As Figure 8As shown, when the meta write operation is performed with the column address BYAC<9:4> in the state of the bit group "110000", a total of 32 bytes 32B or 256 bits of data can be stored in the memory cores MC0 to MC31, 1 byte 1B or 8 bits for each of the memory cores MC0 to MC31, and a total of 2 bytes 2B or 16 bits of meta data can be stored in the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1, 1 byte 1B or 8 bits for each of the meta storage circuits META STG0 / 1. Since the column selection signal YI48 for each of the memory cores MC0 to MC31 is selected based on the bit group "0000" of the column address BYAC<7:4>, a total of 32 bytes 32B or 256 bits of data can be stored in the memory cells belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI48, 1 byte 1B or 8 bits for each of the memory cores MC0 to MC31. Since the memory cores MC0 / 1 are selected based on the bit group "0000" of the column address BYAC<7:4> and the fourth meta group signal MRG<3> is selected based on the bit group "11" of the column address BYAC<9:8>, a total of 2 bytes 2B or 16 bits of meta data can be stored in the meta registers belonging to each of the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1 and selected by the fourth meta group signal MRG<3>, 8 bits for each of the meta storage circuits META STG0 / 1.

[0098] As Figure 8As shown, when the meta read operation is performed with the column address BYAC<9:4> in the state of the bit group "110000", 1 byte 1B or 8 bits of data stored in each of the memory cores MC0 to MC31 (totaling 32 bytes 32B or 256 bits of data) can be output, and 1 byte 1B or 8 bits of meta data stored in each of the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1 (totaling 2 bytes 2B or 16 bits of meta data) can be output. Since the column selection signal YI48 for each of the memory cores MC0 to MC31 is selected based on the bit group "0000" of the column address BYAC<7:4>, 1 byte 1B or 8 bits of data stored in each memory cell belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI48 (totaling 32 bytes 32B or 256 bits of data) can be output. Since the memory cores MC0 / 1 are selected based on the bit group "0000" of the column address BYAC<7:4> and the fourth meta group signal MRG<3> is selected based on the bit group "11" of the column address BYAC<9:8>, 2 bytes 2B or 16 bits of meta data stored in the meta registers belonging to each of the meta storage circuits META STG0 / 1 assigned to the memory cores MC0 / 1 and selected by the fourth meta group signal MRG<3> (8 bits per meta storage circuit META STG0 / 1) can be output.

[0099] As Figure 8As shown, when the internal meta write operation is performed with the column address BYAC<9:4> in the state of the bit group "111011", a total of 32 bytes 32B or 256 bits of data can be stored in the memory cores MC0 to MC31, 1 byte 1B or 8 bits per memory core MC0 to MC31, and a total of 2 bytes 2B or 16 bits of meta data can be stored in the meta storage circuits META STG22 / 23 assigned to the memory cores MC22 / 23, 1 byte 1B or 8 bits per meta storage circuit META STG22 / 23. Since the column selection signal YI59 for each memory core MC0 to MC31 is selected based on the bit group "1011" of the column address BYAC<7:4>, a total of 32 bytes 32B or 256 bits of data can be stored in the memory cells belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI59, 1 byte 1B or 8 bits per memory core MC0 to MC31. Since the memory cores MC22 / 23 are selected based on the bit group "1011" of the column address BYAC<7:4> and the fourth meta group signal MRG<3> is selected based on the bit group "11" of the column address BYAC<9:8>, a total of 2 bytes 2B or 16 bits of meta data (8 bits per meta storage circuit META STG22 / 23) can be stored in the meta registers belonging to each meta storage circuit META STG22 / 23 assigned to the memory cores MC22 / 23 and selected by the fourth meta group signal MRG<3>.

[0100] As Figure 8As shown, when the meta read operation is performed with the column address BYAC<9:4> in the state of the bit group "111011", 1 byte 1B or 8 bits of data stored in each of the memory cores MC0 to MC31 (a total of 32 bytes 32B or 256 bits of data) can be output, and 1 byte 1B or 8 bits of meta data stored in each of the meta storage circuits META STG22 / 23 assigned to the memory cores MC22 / 23 (a total of 2 bytes 2B or 16 bits of meta data) can be output. Since the column selection signal YI59 for each of the memory cores MC0 to MC31 is selected based on the bit group "1011" of the column address BYAC<7:4>, 1 byte 1B or 8 bits of data stored in each memory cell belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI59 (a total of 32 bytes 32B or 256 bits of data) can be output. Since the memory cores MC22 / 23 are selected based on the bit group "1011" of the column address BYAC<7:4> and the fourth meta group signal MRG<3> is selected based on the bit group "11" of the column address BYAC<9:8>, a total of 2 bytes 2B or 16 bits of meta data (8 bits per meta storage circuit META STG22 / 23) stored in the meta registers belonging to each of the meta storage circuits META STG22 / 23 assigned to the memory cores MC22 / 23 and selected by the fourth meta group signal MRG<3> can be output.

[0101] As Figure 8As shown, when an internal meta write operation is performed with column address BYAC<9:4> in the bit group "111100", it can output 1 byte (1B) or 8 bits of data stored in each meta storage circuit META STG0 to META STG31 (a total of 32 bytes (32B) or 256 bits of data), and a total of 32 bytes (32B) of data can be stored in memory cores MC0 to MC31. Since memory cores MC0 to MC31 and meta storage circuits META STG0 to META STG31 are selected based on the bit group "1111" of column address BYAC<9:6>, and the first byte signal MRG... <0> The column selection signal YI60 is selected based on the bit group "00" of the column address BYAC<5:4>. Therefore, the data stored in each element storage circuit META STG0 to META STG31 and transmitted via the first tuple signal MRG... <0> The total 32 bytes (32B or 256 bits) of metadata in the selected meta register (8 bits for each meta storage circuit META STG0 to META STG31) can be output and stored in the memory cells belonging to the memory cores MC0 to MC31 and accessed via the column select signal YI60.

[0102] like Figure 8 As shown, when the internal meta-read operation is executed with column address BYAC<9:4> in the bit group "111100", it can output 1 byte (1B) or 8 bits of data (a total of 32 bytes (32B) or 256 bits) stored in each memory core MC0 to MC31, and the total of 32 bytes (32B) of data can be stored in the meta-storage circuits META STG0 to META STG31. Since memory cores MC0 to MC31 and meta-storage circuits META STG0 to META STG31 are selected based on the bit group "1111" of column address BYAC<9:6>, and the first tuple signal MRG... <0> The column select signal YI60 is selected based on the bit group "00" of the column address BYAC<5:4>, thus it can output 1 byte (1B) or 8 bits of metadata (totaling 32 bytes (32B) or 256 bits of metadata) stored in each memory cell belonging to each memory core MC0 to MC31 and accessed via the column select signal YI60. This total of 32 bytes (32B) of metadata can be stored in each metadata circuit META STG0 to META STG31 and accessed via the first tuple signal MRG. <0> In the selected meta register.

[0103] like Figure 8As shown, when an internal meta-write operation is performed with column address BYAC<9:4> in the bit group "111101", it can output 1 byte (1B) or 8 bits of metadata stored in each meta-storage circuit META STG0 to META STG31 (a total of 32 bytes (32B) or 256 bits of metadata), and the total of 32 bytes (32B) of metadata can be stored in memory cores MC0 to MC31. Since memory cores MC0 to MC31 and meta-storage circuits META STG0 to META STG31 are selected based on the bit group "1111" of column address BYAC<9:6>, and the second tuple signal MRG... <1> The column selection signal YI61 is selected based on the bit group "01" of the column address BYAC<5:4>. Therefore, the data stored in each element storage circuit META STG0 to META STG31 and transmitted via the second tuple signal MRG is selected. <1> The total 32 bytes (32B or 256 bits) of metadata in the selected meta register (8 bits for each meta storage circuit META STG0 to META STG31) can be output and stored in the memory cells belonging to each memory core MC0 to MC31 and accessed via the column select signal YI61.

[0104] like Figure 8 As shown, when the internal metadata read operation is performed with column address BYAC<9:4> in the bit group "111101", it can output 1 byte (1B) or 8 bits of metadata stored in each memory core MC0 to MC31 (a total of 32 bytes of metadata, 32B or 256 bits of metadata), and the total of 32 bytes of metadata can be stored in the metadata storage circuits META STG0 to META STG31. Since memory cores MC0 to MC31 and metadata storage circuits META STG0 to META STG31 are selected based on the bit group "1111" of column address BYAC<9:6>, and the second tuple signal MRG... <1> The column select signal YI61 is selected based on the bit group "01" of the column address BYAC<5:4>, thus it can output 1 byte (1B) or 8 bits of metadata (totaling 32 bytes (32B) or 256 bits of metadata) stored in each memory cell belonging to each memory core MC0 to MC31 and accessed via the column select signal YI61. This total of 32 bytes (32B) of metadata can be stored in each memory cell belonging to each memory core META STG0 to META STG31 and accessed via the second tuple signal MRG. <1> In the selected meta register.

[0105] like Figure 8As shown, when the internal meta write operation is performed with the column address BYAC<9:4> being in the state of the bit group "111110", 1 byte 1B or 8 bits of meta data stored in each of the meta storage circuits META STG0 to META STG31 (a total of 32 bytes 32B or 256 bits of meta data) can be output, and the total of 32 bytes 32B of meta data can be stored in the memory cores MC0 to MC31. Since the memory cores MC0 to MC31 and the meta storage circuits META STG0 to META STG31 are selected based on the bit group "1111" of the column address BYAC<9:6>, and the third meta group signal MRG<2> and the column selection signal YI62 are selected based on the bit group "10" of the column address BYAC<5:4>, 32 bytes 32B or 256 bits of meta data (8 bits for each of the meta storage circuits META STG0 to META STG31) stored in the meta registers belonging to each of the meta storage circuits META STG0 to META STG31 and selected by the third meta group signal MRG<2> can be output and stored in the memory cells belonging to the memory cores MC0 to MC31 and selected by the column selection signal YI62.

[0106] As shown, Figure 8 As shown, when the internal meta write operation is performed with the column address BYAC<9:4> being in the state of the bit group "111110", 1 byte 1B or 8 bits of meta data stored in each of the meta storage circuits META STG0 to META STG31 (a total of 32 bytes 32B or 256 bits of meta data) can be output, and the total of 32 bytes 32B of meta data can be stored in the memory cores MC0 to MC31. Since the memory cores MC0 to MC31 and the meta storage circuits META STG0 to META STG31 are selected based on the bit group "1111" of the column address BYAC<9:6>, and the third meta group signal MRG<2> and the column selection signal YI62 are selected based on the bit group "10" of the column address BYAC<5:4>, 32 bytes 32B or 256 bits of meta data (8 bits for each of the meta storage circuits META STG0 to META STG31) stored in the meta registers belonging to each of the meta storage circuits META STG0 to META STG31 and selected by the third meta group signal MRG<2> can be output and stored in the memory cells belonging to the memory cores MC0 to MC31 and selected by the column selection signal YI62.

[0107] As shown, Figure 8As shown, when the internal meta write operation is performed in a state where the bit group of the column address BYAC<9:4> is "111111", 1 byte 1B or 8 bits of meta data (total 32 bytes 32B or 256 bits of meta data) stored in each of the meta storage circuits META STG0 to META STG31 can be output, and the total 32 bytes 32B of meta data can be stored in the memory cores MC0 to MC31. Since the memory cores MC0 to MC31 and the meta storage circuits META STG0 to META STG31 are selected based on the bit group "1111" of the column address BYAC<9:6>, and the fourth group signal MRG<3> and the column selection signal YI63 are selected based on the bit group "11" of the column address BYAC<5:4>, the total 32 bytes 32B or 256 bits of meta data stored in the meta register belonging to each of the meta storage circuits META STG0 to META STG31 and selected by the fourth group signal MRG<3> (8 bits per meta storage circuit META STG0 to META STG31) can be output in units of 8 bits and stored in the memory cells belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI63.

[0108] As shown, Figure 8 As shown, when the internal meta write operation is performed in a state where the bit group of the column address BYAC<9:4> is "111111", 1 byte 1B or 8 bits of meta data (total 32 bytes 32B or 256 bits of meta data) stored in each of the meta storage circuits META STG0 to META STG31 can be output, and the total 32 bytes 32B of meta data can be stored in the memory cores MC0 to MC31. Since the memory cores MC0 to MC31 and the meta storage circuits META STG0 to META STG31 are selected based on the bit group "1111" of the column address BYAC<9:6>, and the fourth group signal MRG<3> and the column selection signal YI63 are selected based on the bit group "11" of the column address BYAC<5:4>, the total 32 bytes 32B or 256 bits of meta data stored in the meta register belonging to each of the meta storage circuits META STG0 to META STG31 and selected by the fourth group signal MRG<3> (8 bits per meta storage circuit META STG0 to META STG31) can be output in units of 8 bits and stored in the memory cells belonging to the memory cores MC0 to MC31 and accessed by the column selection signal YI63.

[0109] Figure 9 A memory device including during an operation of storing data and meta data during a meta write operation is shown. As shown,Figure 9 As shown, when a metadata write operation is performed with the column selection signal YI0 selected based on the column address BYAC in each column decoder YDEC0 to YDEC31, a total of 32 bytes (32B) or 256 bits of data can be stored in memory cores MC0 to MC31 as 1 byte (1B) or 8 bits. When a metadata write operation is performed with memory core MC0 / 1 selected via the column address BYAC, a total of 2 bytes (2B) or 16 bits of metadata can be stored in the metadata storage circuit META STG0 / 1, with each metadata storage circuit META STG0 / 1 being 1 byte (1B) or 8 bits.

[0110] Figure 10 A timing diagram is shown during a metadata write operation that includes storing metadata based on column address BYAC<9:4>. (See diagram for example.) Figure 10 As shown, for example, when the column bank signal CBANK is generated sequentially during a meta-write operation, the column address BYAC<9:4> is latched based on the address latch pulse ADDLATP. Since memory core MC0 / 1 is selected based on the bit group "0000" of column address BYAC<7:4>, and the first tuple signal MRG... <0> The selection is based on the bit group "00" of the column address BYAC<9:8>, therefore the metadata is stored, for example, in the metadata register of the metadata storage circuit META STG0 / 1 corresponding to the memory core MC0 / 1. For example, metadata with logic levels "H", "H", "L", "H" that is sequentially input via the metadata line BGIO-MD in sync with the metadata write pulse WGIO-ENP-MD is output to the write metadata line BGIO-MDD-WR. Furthermore, for example, metadata with logic levels "H", "H", "L", "H" that is input via the write metadata line BGIO-MDD-WR in sync with the latch input signal MS-WR is stored in the metadata belonging to the metadata storage circuit META STG0 / 1 and transmitted via the first tuple signal MRG. <0> In the selected meta register.

[0111] Figure 11 This illustrates the path taken in a memory device during a metadata write operation to store data and metadata. For example... Figure 10 and Figure 11As shown, since the memory core MC0 / 1 is selected based on the bit group "0000" of the column address BYAC<7:4> and the first meta group signal MRG<0> is selected based on the bit group "00" of the column address BYAC<9:8>, the meta data of a total of 2 bytes 2B or 16 bits received via the meta line BGIO-MD is stored in the meta register belonging to each meta storage circuit META STG0 / 1 assigned to the memory core MC0 / 1 and selected by the first meta group signal MRG<0>. Since the column selection signal YI0 for each memory core MC0 to MC31 is selected in the column decoder YDEC based on the bit group "0000" of the column address BYAC<7:4>, the data of a total of 32 bytes 32B or 256 bits received via the external line BGIO<0:7> is sequentially transferred to the internal line EIOD<0:7> and the local line LIO<0:7> by the input / output line driver BIODRV and the write driver WTDRV and stored in the memory cell belonging to each memory core MC0 to MC31 and accessed by the column selection signal YI0 selected via the column decoder YDEC. Although the memory core MC0 to MC31, the column decoder YDEC, the input / output line driver BIODRV, and the write driver WTDRV are each represented as one block in Figure 11 , the column decoder YDEC, the input / output line driver BIODRV, and the write driver WTDRV can be separate components for each memory core MC0 to MC31. Although the meta storage circuit META STG0 / 1 is represented as one block in Figure 11 , the meta storage circuit META STG0 / 1 can be a separate meta storage circuit META STG0 / 1.

[0112] Figure 12 The meta data driver during the meta write operation including outputting the received meta data to the write meta line BGIO-MDD-WR (as shown by the dotted line) is shown. As shown in Figure 12 , for example, when the meta write operation is performed, the meta data received via the meta line BGIO-MD is stored in the latch 125 via the selector 121 when the meta write pulse WGIO-ENP-MD is generated as a logic high "H". The meta data stored in the latch 125 is output to the write meta line BGIO-MDD-WR.

[0113] Figure 13 The circuit of the meta register during the meta write operation including storing the meta data received via the write meta line BGIO-MDD-WR in the data latch 111 (as shown by the dotted line) is shown. As shown in Figure 13As shown, for example, when a meta write operation is performed, the meta data received via the write meta line BGIO-MDD-WR is stored in the data latch 111 when the latched input signal MS-WR is generated at a logic high "H" and the inverted latched input signal MS-WRB is generated at a logic low "L".

[0114] Figure 14 The input / output line driver during a meta write operation including outputting the received data to the internal line EIOD (as shown by the dotted line) is shown. As Figure 14 As shown, for example, when a meta write operation is performed, the data received via the external line BGIO is stored in the latch 135 by the selector 131 when the write pulse WGIO-ENP is generated at a logic high "H". The meta data stored in the latch 135 is output to the internal line EIOD.

[0115] Figure 15 The memory device during a meta read operation including outputting data and meta data is shown. As Figure 15 As shown, when a meta read operation is performed in a state where the column select signal YI0 is selected in the column decoders YDEC0 to YDEC31 based on the column address BYAC, 1 byte IB or 8 bit of data stored in each of the memory cores MC0 to MC31 (totaling 32 bytes 32B or 256 bits of data) can be output. When a meta read operation is performed in a state where the memory core MC0 / 1 is selected by the column address BYAC, 1 byte IB or 8 bit of meta data stored in each of the meta storage circuits META STG0 / 1 (totaling 2 bytes 2B or 16 bits of meta data) can be output.

[0116] Figure 16 The timing diagram during a meta read operation including outputting the meta data stored in the meta register based on the column address BYAC<9:4> is shown. As Figure 16As shown, for example, when the column bank signal CBANK is sequentially generated while the meta read operation is performed, the column address BYAC<9:4> is latched based on the address latch pulse ADDLATP. For example, since the memory core MC0 / 1 is selected based on the bit group "0000" of the column address BYAC<7:4>, and the first meta group signal MRG<0> is selected based on the bit group "00" of the column address BYAC<9:8>, the meta data stored in the meta registers belonging to the meta storage circuitry META STG0 / 1 and selected by the first meta group signal MRG<0> is output to the read meta line BGIO-MDD-RD. More specifically, for example, the meta data stored in the meta registers belonging to the meta storage circuitry META STG0 / 1 and selected by the first meta group signal MRG<0> in synchronization with the latch output signal MS-RD and having logical levels of "H", "H", "L", "H" is output to the read meta line BGIO-MDD-RD. For example, the meta data having logical levels of "H", "H", "L", "H" sequentially input via the read meta line BGIO-MDD-RD in synchronization with the meta read pulse RGIO-ENP-MD is output to the meta line BGIO-MD.

[0117] Figure 17 The path along which data and meta data is output during a meta read operation in a memory device is shown. As shown in FIG. 6, for example, the column address BYAC<9:4> is latched based on the address latch pulse ADDLATP when the column bank signal CBANK is sequentially generated while the meta read operation is performed. For example, since the memory core MC0 / 1 is selected based on the bit group "0000" of the column address BYAC<7:4>, and the first meta group signal MRG<0> is selected based on the bit group "00" of the column address BYAC<9:8>, the meta data stored in the meta registers belonging to the meta storage circuitry META STG0 / 1 and selected by the first meta group signal MRG<0> is output to the read meta line BGIO-MDD-RD. Figure 16 and Figure 17 As shown, for example, since the memory core MC0 / 1 is selected based on the bit group "0000" of the column address BYAC<7:4>, and the first meta group signal MRG<0> is selected based on the bit group "00" of the column address BYAC<9:8>, the meta data stored in the meta registers belonging to the meta storage circuitry META STG0 / 1 and selected by the first meta group signal MRG<0> is output to the read meta line BGIO-MDD-RD. More specifically, for example, the meta data stored in the meta registers belonging to the meta storage circuitry META STG0 / 1 and selected by the first meta group signal MRG<0> in synchronization with the latch output signal MS-RD and having logical levels of "H", "H", "L", "H" is output to the read meta line BGIO-MDD-RD. For example, the meta data having logical levels of "H", "H", "L", "H" sequentially input via the read meta line BGIO-MDD-RD in synchronization with the meta read pulse RGIO-ENP-MD is output to the meta line BGIO-MD. Figure 17The memory core MC0 to MC31, the column decoder YDEC, the input / output sense amplifier IOSA, and the input / output line driver BIODRV are each represented as one block, but the column decoder YDEC, the input / output sense amplifier IOSA, and the input / output line driver BIODRV can be separate components for each memory core MC0 to MC31. Although the memory core MC0 to MC31 is represented as one block in Figure 17 The meta storage circuitry META STG0 / 1 is represented as one block, but the meta storage circuitry META STG0 / 1 can be separate meta storage circuitry META STG0 / 1.

[0118] Figure 18 The circuit of the meta register during a meta read operation including outputting the meta data stored in the data latch 111 to the read meta line BGIO-MDD-RD is shown. As shown, for example, when the meta read operation is performed, the meta data stored in the data latch 111 is output to the read meta line BGIO-MDD-RD when the latch output signal MS-RD is generated at a logic high level “H” and the inverted latch output signal MS-RDB is generated at a logic low level “L”. Figure 18

[0119] Figure 19 The meta data driver during an operation including outputting the meta data received via the read meta line BGIO-MDD-RD to the meta line BGIO-MD (as shown by the dotted line) is shown. As shown, for example, when the meta read operation is performed, the meta data received via the read meta line BGIO-MDD-RD is output to the meta line BGIO-MD via the read driver 127 when the meta read pulse RGIO-ENP-MD is generated at a logic high level “H”. Figure 19

[0120] Figure 20 The input / output line driver during a meta read operation including outputting the data received via the internal line EIOD to the external line BGIO (as shown by the dotted line) is shown. As shown, for example, when the meta read operation is performed, the data received via the internal line EIOD is output to the external line BGIO via the read driver 137 when the read pulse RGIO-ENP is generated at a logic high level “H”. Figure 20

[0121] Figure 21 The memory device during an internal meta write operation including storing the meta data output by the meta storage circuitry in the memory core is shown. As shown, for example, when the internal meta write operation is performed, the meta data output by the meta storage circuitry is stored in the memory core when the meta write pulse RGIO-ENP-MD is generated at a logic high level “H”. Figure 21 ​​​As shown, the 1-byte (1B) or 8-bit metadata stored in each of the META STG0 to META STG31 (totaling 32 bytes (32B) or 256 bits) can be output and stored in each memory core MC0 to MC31 based on the column address BYAC.

[0122] Figure 22 A timing diagram is shown during internal metadata write operations, including column address-based BYAC<9:4> output and storage metadata. (See diagram for details.) Figure 22 As shown, for example, when an internal meta-write operation is performed, the column address BYAC<9:4> is latched based on the address latch pulse ADDLATP during the sequential generation of the column memory bank signal CBANK. Since the memory cores MC0 to MC31 and the meta-storage circuits META STG0 to META STG31 are selected based on the bit group "1111" of the column address BYAC<9:6>, and the first tuple signal MRG... <0> The column selection signal YI60 is selected based on the bit group "00" of the column address BYAC<5:4>, therefore belonging to each element storage circuit META STG0 to META STG31 and via the first tuple signal MRG. <0> The metadata with logic levels "H", "H", "L", and "H" stored in the selected metadata register is synchronized with the latch output signal MS-RD and output to the read metadata line BGIO-MDD-RD. When the internal metadata write pulse WGIO-ENP-MR is generated, the metadata with logic levels "H", "H", "L", and "H" received via the read metadata line BGIO-MDD-RD is output to the internal line EIOD and stored in the memory cells belonging to the memory cores MC0 to MC31 and accessed via the column select signal YI60.

[0123] Figure 23 This illustrates the paths along which metadata is output from the metadata storage circuitry during an internal metadata write operation in a memory device, and the paths along which metadata is stored in the memory core. For example... Figure 22 and Figure 23As shown, since the memory cores MC0 to MC31 and the meta storage circuits META STG0 to META STG31 are selected based on the bit group "1111" of the column address BYAC<9:6> and the first meta group signal MRG<0> and the column selection signal YI60 are selected based on the bit group "00" of the column address BYAC<5:4>, the meta data stored in the meta register belonging to each of the meta storage circuits META STG0 to META STG31 and selected by the first meta group signal MRG<0> is output to the read meta line BGIO-MDD-RD via the input / output driver BIODRV. The meta data output to the read meta line BGIO-MDD-RD is sequentially transferred to the internal lines EIOD<0:7> and the local lines LIO<0:7> via the input / output line driver BIODRV and the write driver WTDRV and stored in the memory cells belonging to each of the memory cores MC0 to MC31 and accessed by the column selection signal YI60 selected via the column decoder YDEC. Although the memory cores MC0 to MC31, the column decoder YDEC, the write driver WTDRV, the input / output line driver BIODRV, and the meta storage circuits META STG0 to META STG31 are each represented as one block in Figure 23

[0124] Figure 24 The circuit of the meta register during the internal meta write operation including outputting the meta data stored in the data latch 111 to the read meta line BGIO-MDD-RD is shown. As shown, for example, when the internal meta write operation is performed, the meta data stored in the data latch 111 is output to the read meta line BGIO-MDD-RD when the latch output signal MS-RD is generated at the logic high "H" and the inverted latch output signal MS-RDB is generated at the logic low "L". Figure 24

[0125] Figure 25 The input / output line driver during the internal meta write operation including outputting the meta data received via the read meta line BGIO-MDD-RD to the internal line EIOD (as shown by the dotted line) is shown. As shown, for example, when the internal meta write operation is performed, the meta data received via the read meta line BGIO-MDD-RD is output to the internal line EIOD when the latch output signal MS-RD is generated at the logic high "H" and the inverted latch output signal MS-RDB is generated at the logic low "L". Figure 25 ​​As shown, for example, when an internal metadata write operation is performed, when the internal metadata write pulse WGIO-ENP-MR is generated at a logic high level "H", the metadata received via the read metadata line BGIO-MDD-RD is stored in latch 135 via selector 133. The metadata stored in latch 135 is output to the internal line EIOD.

[0126] Figure 26 The diagram illustrates a memory device during an internal metadata read operation, including storing metadata output from the memory core in the metadata storage circuitry. (Example) Figure 26 As shown, 1 byte (1B) or 8 bits) of metadata stored in each memory core MC0 to MC31 (a total of 32 bytes (32B) or 256 bits) can be output based on the column address BYAC and stored in each metadata circuit META STG0 to META STG31.

[0127] Figure 27 The timing diagram shows the internal metadata read operations, including metadata output from the memory core and metadata stored in the metadata storage circuitry based on column address BYAC<9:4>. (See diagram for details.) Figure 27 As shown, when an internal meta-read operation is performed, the column address BYAC<9:4> is latched based on the address latch pulse ADDLATP during the sequential generation of the column memory bank signal CBANK. Since the memory cores MC0 to MC31 and the meta-storage circuits META STG0 to META STG31 are selected based on the bit group "1111" of the column address BYAC<9:6>, and the first tuple signal MRG... <0> The column select signal YI60 is selected based on the bit group "00" of the column address BYAC<5:4>. Therefore, metadata with logic levels "H", "H", "L", "H" stored in memory cells belonging to memory cores MC0 to MC31 and accessed via column select signal YI60 is output to the internal line EIOD. Metadata with logic levels "H", "H", "L", "H" received via internal line EIOD in sync with the internal meta write pulse WGIO-ENP-MR is output to the write meta line BGIO-MDD-WR. Metadata with logic levels "H", "H", "L", "H" input via write meta line BGIO-MDD-WR in sync with latch input signal MS-WR is stored in the meta storage circuits META STG0 to META STG31 and accessed via the first tuple signal MRG. <0> In the selected meta register.

[0128] Figure 28 This illustrates the path along which the memory core outputs metadata during an internal metadata read operation in a memory device, and the metadata is stored in the metadata storage circuitry. For example...Figure 27 and Figure 28 As shown in FIG. 12, since the memory core MC0 to MC31 and the meta storage circuit META STG0 to META STG31 are selected based on the bit group "1111" of the column address BYAC<9:6>, and the first meta group signal MRG<0> and the column selection signal YI60 are selected based on the bit group "00" of the column address BYAC<5:4>, the meta data stored in the memory cells belonging to each of the memory cores MC0 to MC31 and accessed by the column selection signal YI60 selected via the column decoder YDEC is output to the local lines LIO<0:7>. The meta data output to the local lines LIO<0:7> is sequentially output to the internal lines EIOD<0:7> and the write meta lines BGIO-MDD-WR<0:7> via the input-output sense amplifier IOSA and the input-output line driver BIODRV. The meta data output to the write meta lines BGIO-MDD-WR<0:7> is stored in the meta registers belonging to the meta storage circuits META STG0 to META STG31 and selected in synchronization with the latched input signal MS-WR by the first meta group signal MRG<0>. Although the memory core MC0 to MC31, the column decoder YDEC, the input-output sense amplifier IOSA, the input-output line driver BIODRV, and the meta storage circuit META STG0 to META STG31 are each represented as one block in FIG. 12, the column decoder YDEC, the input-output sense amplifier IOSA, the input-output line driver BIODRV can be separate components for each of the memory cores MC0 to MC31 and for each of the meta storage circuits META STG0 to META STG31. Figure 28 Although the memory core MC0 to MC31, the column decoder YDEC, the input-output sense amplifier IOSA, the input-output line driver BIODRV, and the meta storage circuit META STG0 to META STG31 are each represented as one block in FIG. 12, the column decoder YDEC, the input-output sense amplifier IOSA, the input-output line driver BIODRV can be separate components for each of the memory cores MC0 to MC31 and for each of the meta storage circuits META STG0 to META STG31.

[0129] Figure 29 The meta data driver during the internal meta read operation including outputting the meta data received via the internal line EIOD to the write meta line BGIO-MDD-WR (as shown by the dotted line) is shown. As shown in FIG. 13, for example, when the internal meta read operation is performed, the meta data received via the internal line EIOD is stored in the latch 125 via the selector 123 when the internal meta write pulse WGIO-ENP-MR is generated at the logic high "H". The meta data stored in the latch 125 is output to the write meta line BGIO-MDD-WR. Figure 29

[0130] Figure 30 The circuit of the meta register during the internal meta read operation including storing the meta data received via the write meta line BGIO-MDD-WR in the data latch 111 (as shown by the dotted line) is shown. As shown in FIG. 14, for example, when the internal meta read operation is performed, the meta data received via the write meta line BGIO-MDD-WR is stored in the data latch 111 when the internal meta read pulse WGIO-ENP-MR is generated at the logic high "H". The meta data stored in the data latch 111 is output to the internal line EIOD. Figure 30 ​As shown, for example, when the internal meta read operation is performed, the meta data received via the write meta line BGIO-MDD-WR is stored in the data latch 111 when the latch input signal MS-WR is generated at a logic high "H" and the inverted latch input signal MS-WRB is generated at a logic low "L".

[0131] Figure 31 An example of a meta data driver for a meta parallel write operation is shown. As shown, in one embodiment, the meta data driver includes selectors (SEL) 140, 141 and 143, a latch (LAT) 145 and a read driver (RDDRV) 147. Figure 31

[0132] The selector 140 outputs a test voltage PAT based on a meta parallel test pulse WGIO-ENP-TPARA generated when the meta parallel write operation is performed. The selector 123 outputs the test voltage PAT as either the supply voltage VDD or the ground voltage VSS when the meta parallel write operation is performed. The selector 141 outputs the meta data received via the meta line BGIO-MD based on a meta write pulse WGIO-ENP-MD generated when the meta parallel write operation is performed. The selector 143 outputs the meta data output by the memory core and received via the internal line EIOD based on an internal meta read pulse RGIO-ENP-MR when the internal meta read operation is performed. For example, when the meta parallel write operation is performed, the selectors 141 and 143 can not operate while only the selector 140 can operate and output the test voltage PAT to the latch 145.

[0133] The latch 145 is electrically connected to the selectors 140, 141 and 143, latches the meta data output by the selectors 140, 141 and 143 and outputs the latched meta data to the write meta line BGIO-MDD-WR. For example, when the meta parallel write operation is performed, the latch 145 latches the test voltage PAT output by the selector 140 and outputs the latched test voltage PAT to the write meta line BGIO-MDD-WR. For example, when the meta write operation is performed, the latch 145 latches the meta data output by the selector 141 and outputs the latched meta data to the write meta line BGIO-MDD-WR. For example, when the internal meta read operation is performed, the latch 145 latches the meta data output by the selector 143 and outputs the latched meta data to the write meta line BGIO-MDD-WR. For example, when the meta parallel write operation is performed, the test voltage PAT output to the write meta line BGIO-MDD-WR is stored in the meta storage circuitry META STG in synchronization with the latch input signal MS-WR. The latch input signal MS-WR can be generated when the meta parallel test operation is performed. Reference is made to Figure 5 ​The operation of storing the test voltage PAT of the write bitline BGIO-MDD-WR in the bit storage circuit META-STG in synchronization with the latch input signal MS-WR is described in detail.

[0134] When the bit read operation is performed, the read driver 147 outputs the bit data output from the bit register and received via the read bitline BGIO-MDD-RD to the bitline BGIO-MD based on the bit read pulse RGIO-ENP-MD.

[0135] When the bit parallel write operation is performed, the bit data driver outputs the test voltage PAT to the write bitline BGIO-MDD-WR. The test voltage PAT output to the write bitline BGIO-MDD-WR is stored in the bit storage circuit META-STG in synchronization with the latch input signal MS-WR.

[0136] Figure 32 The path along which the test voltage PAT is output by the bit storage circuit during the bit parallel write operation in the memory device and the path along which the test voltage PAT is stored in the memory core are shown. As shown in Figure 32 As all of the column selection signals YI0 to YI31 for each memory core MC0 to MC31 are selected in the column decoder YDEC when the bit parallel write operation is performed, the test voltage PAT stored in the memory cells belonging to each bit storage circuit META-STG0 to META-STG31 and accessed by the column selection signals YI0 to YI31 is output to the read bitline BGIO-MDD-RD<0:7> via the input / output line driver BIODRV. The output test voltage PAT is sequentially output to the internal line EIOD<0:7> and the local line LIO<0:7> via the input / output line driver BIODRV and the write driver WTDRV. The test voltage PAT output via the local line LIO<0:7> is stored in all of the memory cells belonging to each memory core MC0 to MC31 and accessed by the column selection signals YI0 to YI63 selected by the column decoder YDEC. For example, when the bit parallel write operation is performed, the test voltage PAT output by each bit storage circuit META-STG0 to META-STG31 is stored in all of the memory cells included in each memory core MC0 to MC31. Although the test voltage PAT is sequentially output to the internal line EIOD<0:7> and the local line LIO<0:7> in the above-described embodiment, the test voltage PAT can be output to the internal line EIOD<0:7> and the local line LIO<0:7> in parallel. Figure 32The memory core MC0 to MC31, the column decoder YDEC, the write driver WTDRV, the input / output line driver BIODRV, and the meta storage circuit META STG0 to META STG31 are each represented as one block, but the column decoder YDEC, the write driver WTDRV, and the input / output line driver BIODRV can be separate components for each of the memory cores MC0 to MC31 and for each of the meta storage circuits META STG0 to META STG31.

[0137] Figure 33 The circuit of the meta register during a meta parallel write operation including outputting the test voltage PAT stored in the data latch 111 to the meta parallel read operation is shown. As shown, for example, when the meta parallel write operation is performed, the latch output signal MS-RD is generated at a logic high level "H" and the inverted latch output signal MS-RDB is generated at a logic low level "L", and the test voltage PAT stored in the data latch 111 is output to the read meta line BGIO-MDD-RD. Figure 33

[0138] Figure 34 The input / output line driver during a meta parallel write operation including outputting the meta data received via the read meta line BGIO-MDD-RD to the internal line EIOD is shown. As shown, for example, when the meta parallel write operation is performed, the meta data received via the read meta line BGIO-MDD-RD is stored in the latch 135 via the selector 133 when the internal meta write pulse WGIO-ENP-MR is generated at a logic high level "H". The meta data stored in the latch 135 is output to the internal line EIOD. Figure 34

[0139] The path along which the test voltage PAT stored in the memory core is output during a meta parallel read operation in the memory device is shown. As shown, for example, when the meta parallel read operation is performed, the test voltage PAT stored in all memory cells belonging to each of the memory cores MC0 to MC31 and accessed by the column selection signal YI0 to YI63 selected in the column decoder YDEC is output to the local line LIO<0:7>. The test voltage PAT output to the local line LIO<0:7> is sequentially output to the internal line EIOD<0:7> and the external line BGIO<0:7> via the input / output sense amplifier IOSA and the input / output line driver BIODRV. Although in the example shown in FIG. 10, the test voltage PAT is output to the local line LIO<0:7> and the internal line EIOD<0:7> via the input / output sense amplifier IOSA and the input / output line driver BIODRV, the test voltage PAT can be output to the local line LIO<0:7> and the internal line EIOD<0:7> via the input / output sense amplifier IOSA and the input / output line driver BIODRV without the input / output sense amplifier IOSA and the input / output line driver BIODRV. Figure 35 Figure 35 Figure 35 ​​​The memory cores MC0 to MC31, the column decoder YDEC, the input / output sense amplifier IOSA, and the input / output line driver BIODRV are each represented as one block, but the column decoder YDEC, the input / output sense amplifier IOSA, and the input / output line driver BIODRV can be separate components for each memory core MC0 to MC31.

[0140] Figure 36 The input / output line driver during a meta-parallel read operation including outputting data received via the internal line EIOD to the external line BGIO (as shown by the dotted line) is shown. As shown, when the meta-parallel read operation is performed, the data received via the internal line EIOD is output to the external line BGIO via the read driver 137 when the read pulse RGIO-ENP is generated at a logic high "H". Figure 36

[0141] Embodiments of the present disclosure are described. It will be understood by those of ordinary skill in the art that various modifications, additions and substitutions can be made without departing from the scope and technical concept of the present disclosure. Accordingly, the disclosed embodiments are to be considered as illustrative and not restrictive, and the scope of the present disclosure is not to be limited to the descriptions set forth herein. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.​

Claims

1. A memory device comprising: a plurality of memory cores; and a plurality of meta storage circuits, each of the plurality of meta storage circuits corresponding to a different memory core of the plurality of memory cores; wherein, when a meta write operation is performed, data received via an external line is stored in the plurality of memory cores based on a column address, and meta data received via a meta line is stored in a meta storage circuit of the plurality of meta storage circuits selected by the column address.

2. The memory device of claim 1, wherein, When the meta write operation is performed, a column selection signal is selected by the column address, and the data is stored in memory cells belonging to the plurality of memory cores and accessed by the selected column selection signal.

3. The memory device of claim 2, further comprising: an input-output line driver that outputs the data to an internal line when the meta write operation is performed; a write driver that outputs the data received via the internal line to a local line when the meta write operation is performed; and a column decoder that generates the column selection signal based on the column address when the meta write operation is performed.

4. The memory device of claim 1, wherein, each of the meta storage circuits includes a plurality of meta data drivers and a plurality of meta registers; wherein each of the plurality of meta data drivers corresponds to at least one of the plurality of meta registers; and wherein at least one of the plurality of meta data drivers and at least one of the plurality of meta registers are selected by a meta group signal.

5. The memory device of claim 1, wherein, each of the meta storage circuits includes: a meta data driver that outputs the meta data to the write meta line when the meta write operation is performed; and a meta register that stores the meta data received via the write meta line in a data latch selected by the column address when the meta write operation is performed.

6. The memory device of claim 1, wherein: when a meta read operation is performed, the data stored in the plurality of memory cores is output to the external line based on the column address; and when the meta read operation is performed, the meta data stored in the meta storage circuit selected by the column address is output to the meta line.

7. The memory device of claim 6, wherein, When the meta read operation is performed, a column selection signal is selected by the column address, and data stored in memory cells belonging to the plurality of memory cores and accessed by the selected column selection signal is output.

8. The memory device of claim 7, further comprising: a column decoder that generates the column selection signal based on the column address when the meta read operation is performed; an input-output sense amplifier that receives the data output by the plurality of memory cores via a local line based on the column selection signal and outputs the data to an internal line when the meta read operation is performed; and an input / output line driver to output the data received via the internal line to the external line when the cell read operation is performed.

9. The memory device of claim 6, wherein, Each of the cell storage circuits further includes: a cell register to output the cell data stored in a data latch selected by the column address to a read cell line when the cell read operation is performed; and a cell data driver to output the cell data received via the read cell line to the cell line when the cell read operation is performed.

10. The memory device of claim 1, wherein: when an internal cell write operation is performed, the cell data stored in the plurality of cell storage circuits is output to a read cell line based on the column address, and when the internal cell write operation is performed, the cell data received via the read cell line is stored in the plurality of memory cores based on the column address.

11. The memory device of claim 10, wherein, Each of the cell storage circuits includes a cell register to output the cell data stored in a data latch selected by the column address to the read cell line when the internal cell write operation is performed.

12. The memory device of claim 11, wherein, when the internal cell write operation is performed, a column selection signal is selected by the column address and the cell data is stored in a memory cell belonging to the plurality of memory cores and accessed by the selected column selection signal.

13. The memory device of claim 12, further comprising: an input / output line driver to output the cell data received via the read cell line to an internal line when the internal cell write operation is performed; a write driver to output the cell data received via the internal line to a local line when the internal cell write operation is performed; and a column decoder to generate the column selection signal based on the column address when the cell write operation is performed.

14. The memory device of claim 1, wherein: when an internal cell read operation is performed, the cell data stored in the plurality of memory cores is output to a write cell line based on the column address, and when the internal cell read operation is performed, the cell data received via the write cell line is stored in the plurality of cell storage circuits based on the column address.

15. The memory device of claim 14, wherein, when the internal cell read operation is performed, a column selection signal is selected by the column address and the cell data stored in a memory cell belonging to the plurality of memory cores and accessed by the selected column selection signal is output.

16. The memory device of claim 15, further comprising: a column decoder to generate the column selection signal based on the column address when the internal cell read operation is performed; an input / output sense amplifier to receive the cell data output by the plurality of memory cores via a local line based on the column selection signal and output the cell data to an internal line when the internal cell read operation is performed; and an input-output line driver that outputs the data received via the internal line to the write cell line when the internal cell read operation is performed.

17. The memory device of claim 14, wherein, each of the cell storage circuits stores the cell data received via the write cell line in a data latch selected by the column address when the internal cell read operation is performed.

18. A memory device, comprising: a plurality of memory cores; and a plurality of cell storage circuits, each of the plurality of cell storage circuits corresponding to a different one of the plurality of memory cores; wherein, when a cell read operation is performed, data stored in the plurality of memory cores is output to an external line based on a column address, and wherein, when the cell read operation is performed, cell data stored in a cell storage circuit selected by the column address among the plurality of cell storage circuits is output to a cell line.

19. The memory device of claim 18, wherein, a column selection signal is selected by the column address when the cell read operation is performed, and data stored in memory cells belonging to the plurality of memory cores and accessed by the selected column selection signal is output.

20. The memory device of claim 19, further comprising: a column decoder that generates the column selection signal based on the column address when the cell read operation is performed; an input-output sense amplifier that receives the data output by the plurality of memory cores via a local line based on the column selection signal and outputs the data to an internal line when the cell read operation is performed; and an input-output line driver that outputs the data received via the internal line to the external line when the cell read operation is performed.

21. The memory device of claim 18, wherein, each of the cell storage circuits further comprises: a cell register that outputs the cell data stored in a data latch selected by the column address to a read cell line when the cell read operation is performed; and a cell data driver that outputs the cell data received via the read cell line to the cell line when the cell read operation is performed.

22. A memory device, comprising: a plurality of memory cores; and a plurality of cell storage circuits, each of the plurality of cell storage circuits corresponding to a different one of the plurality of memory cores; wherein, when an internal cell write operation is performed, cell data stored in the plurality of cell storage circuits is output to a read cell line based on a column address; and wherein, when the internal cell write operation is performed, the cell data received via the read cell line is stored in the plurality of memory cores based on the column address.

23. The memory device of claim 22, wherein, each of the cell storage circuits comprises a cell register that outputs the cell data stored in a data latch selected by the column address to a read cell line when the internal cell write operation is performed.

24. The memory device of claim 23, wherein, When the internal meta write operation is performed, a column selection signal is selected by the column address, and the meta data stored in a memory cell belonging to the plurality of memory cores and accessed by the selected column selection signal is stored.

25. A memory device comprising: a plurality of memory cores; and a plurality of meta storage circuits, each of the plurality of meta storage circuits corresponding to a different memory core of the plurality of memory cores; wherein, when an internal meta read operation is performed, meta data stored in the plurality of memory cores is output to a write meta line based on a column address; and wherein, when the internal meta read operation is performed, the meta data received via the write meta line is stored in the plurality of meta storage circuits based on the column address.

26. The memory device of claim 25, wherein, When the internal meta read operation is performed, a column selection signal is selected by the column address, and the meta data stored in a memory cell belonging to the plurality of memory cores and accessed by the selected column selection signal is output.

27. The memory device of claim 26, further comprising: a column decoder that, when the internal meta read operation is performed, generates the column selection signal based on the column address; an input-output sense amplifier that, when the internal meta read operation is performed, receives the meta data output by the plurality of memory cores via a local line based on the column selection signal, and outputs the meta data to an internal line; and an input-output line driver that, when the internal meta read operation is performed, outputs the meta data received via the internal line to the write meta line.

28. The memory device of claim 25, wherein, When the internal meta read operation is performed, each of the meta storage circuits stores the meta data received via the write meta line in a data latch selected by the column address.

29. A memory device comprising: a plurality of memory cores; and a plurality of meta storage circuits, each of the plurality of meta storage circuits corresponding to a different memory core of the plurality of memory cores; wherein, when a meta parallel write operation is performed, a test voltage is stored in the plurality of meta storage circuits, when the meta parallel write operation is performed, the test voltage stored in the plurality of meta storage circuits is stored in the plurality of memory cores, and when a meta parallel read operation is performed, the test voltage stored in the plurality of memory cores is output to an external line.

30. The memory device of claim 29, wherein, The test voltage is a power supply voltage or a ground voltage.

31. The memory device of claim 29, wherein, Each of the plurality of meta storage circuits comprises: a meta data driver that, when the meta parallel write operation is performed, outputs the test voltage to a write meta line; and a meta register that, when the meta parallel write operation is performed, stores the test voltage received via the write meta line in a data latch.

32. The memory device of claim 29, wherein: when the cell parallel read operation is performed, the test voltage stored in the memory cell selected by the column address among the plurality of memory cores is output to the external line. when the cell parallel read operation is performed, the test voltage stored in the memory cell selected by the column address among the plurality of memory cores is output to the external line.

33. The memory device of claim 32, wherein, when the cell parallel read operation is performed, all of the column selection signals are selected, and the test voltage stored in the memory cell belonging to the plurality of memory cores and accessed by all of the column selection signals is output.

34. The memory device of claim 29, wherein, when the cell parallel read operation is performed, all of the column selection signals are selected, and the test voltage stored in the memory cell belonging to the plurality of memory cores and accessed by all of the column selection signals is output.

35. The memory device of claim 34, further comprising: a column decoder that, when the cell parallel read operation is performed, selects all of the column selection signals; an input / output sense amplifier that, when the cell parallel read operation is performed, receives the test voltage output by the plurality of memory cores via the local line based on the column selection signals, and outputs the test voltage to the internal line; and an input / output line driver that, when the cell parallel read operation is performed, outputs the test voltage received via the internal line to the external line.

36. A method of processing cell data, the method comprising: when a cell write operation is performed, storing data received via an external line in a plurality of memory cores based on a column address; and when the cell write operation is performed, storing cell data received via a cell line in a cell storage circuit selected by the column address among a plurality of cell storage circuits.

37. A method of processing cell data, the method comprising: when a cell read operation is performed, outputting data stored in a plurality of memory cores to an external line based on a column address; and when the cell read operation is performed, outputting cell data stored in a cell storage circuit selected by the column address among a plurality of cell storage circuits to a cell line.

38. A method of processing cell data, the method comprising: when an internal cell write operation is performed, outputting cell data stored in a plurality of cell storage circuits to a read cell line based on a column address; and when the internal cell write operation is performed, storing the cell data received via the read cell line in a plurality of memory cores based on the column address.

39. A method of processing cell data, the method comprising: when an internal cell read operation is performed, outputting cell data stored in a plurality of memory cores to a write cell line based on a column address; and when the internal cell read operation is performed, storing cell data received via the write cell line in a plurality of cell storage circuits based on the column address.

40. A method of processing cell data, the method comprising: when a cell parallel write operation is performed, storing a test voltage in a plurality of cell storage circuits; when the cell parallel read operation is performed, the test voltage stored in the memory cell selected by the column address among the plurality of memory cores is output to the external line. when the meta-parallel read operation is performed, the test voltage stored in the plurality of memory cores is output to an external line. and when the meta-parallel read operation is performed, the test voltage stored in the plurality of memory cores is output to an external line.

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