Semiconductor device using shape memory alloy structure and manufacturing method

Abstract

The invention relates to a semiconductor device using a shape memory alloy structure and a manufacturing method. The semiconductor device has an interposer. A shape metal alloy (SMA) structure is disposed over the interposer. The SMA structure is formed of nickel-titanium. Solder bumps and electrical components are disposed over the interposer. An interposer is disposed over the substrate with the SMA structures, solder bumps, and electrical components between the interposer and the substrate. And reflowing the solder bump.

Description

Technical Field

[0001] This invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods of fabrication using shape memory alloy (SMA) structures. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, power conversion, optoelectronics, and creating visual images for television displays. Semiconductor devices are used in communications, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Semiconductor device manufacturers are constantly striving to create smaller and more advanced semiconductor packages to meet the shared needs of electronic device manufacturers and consumers. Substrate and interposer warpage is a major problem in advanced semiconductor packaging. Smaller devices with thinner substrates and interposers are more susceptible to warpage during manufacturing. Therefore, there is a need for advanced packages manufactured using shape memory alloy (SMA) structures. Attached Figure Description

[0004] Figures 1a-1c The illustration shows a semiconductor wafer with multiple semiconductor dies separated by saw tracks;

[0005] Figures 2a-2p The diagram illustrates the process of forming a semiconductor package with a shape memory alloy (SMA) structure; and

[0006] Figure 3a and Figure 3b The illustration shows the integration of semiconductor packages into electronic devices. Detailed Implementation

[0007] In the following description, the invention will be described in one or more embodiments with reference to the figures, wherein similar reference numerals denote the same or similar elements. While the invention is described with regard to the best mode for carrying out the objectives of the invention, those skilled in the art will appreciate that the invention is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and figures. Features shown in the figures are not necessarily drawn to scale. Elements assigned the same reference numerals in the figures have similar functions to each other. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0008] Semiconductor devices are generally manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components (such as transistors and diodes) have the ability to control the flow of current. Passive electrical components (such as capacitors, inductors, and resistors) create the voltage and current relationships necessary for the electrical circuit to function.

[0009] Back-end manufacturing refers to the process of dicing or isolating finished wafers into individual semiconductor dies and packaging these dies for structural support, electrical interconnection, and environmental isolation. To isolate a semiconductor die, the wafer is scribed and broken along non-functional regions (known as serrations or scribing lines). This is done using laser cutting tools or saw blades. After isolation, the individual semiconductor dies are deployed onto a packaging substrate that includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to contact pads within the semiconductor package. Electrical connections can be made using conductive layers, bumps, pillar bumps, conductive paste, or wiring bonding. A sealant or other molding material is deposited on the semiconductor package to provide physical support and electrical isolation. The completed semiconductor package is then inserted into an electrical system, enabling the semiconductor device to function for other system components.

[0010] Figure 1a A semiconductor wafer 100 is shown, having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100, separated by non-active, inter-die wafer regions or saw tracks 106. The saw tracks 106 provide dicing areas to individualize the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0011] Figure 1bA cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back surface or passive surface 108 and an active surface 110, which contains analog or digital circuitry, including active devices, passive devices, conductive layers, and dielectric layers, implemented as formed on or within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, power devices, or other signal processing circuitry. The semiconductor die 104 may also include IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

[0012] A conductive layer 112 is formed on the active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as contact pads of a circuit on the active surface 110.

[0013] Conductive bump material is deposited on conductive layer 112 using evaporation, electroplating, electroless plating, droplet, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, combinations thereof, and optionally, flux solutions. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 114. In one embodiment, bumps 114 are formed on under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesion layer. Bumps 114 can also be compression bonded or thermocompressed bonded to conductive layer 112. Bumps 114 represent one type of interconnect structure that can be formed on conductive layer 112. The interconnect structure can also utilize bonded wiring, conductive paste, column bumps, microbumps, or other electrical interconnects.

[0014] exist Figure 1c In this process, a saw blade or laser cutting tool 118 is used to monomerize the semiconductor wafer 100 into individual semiconductor dies 104 through the saw groove 106. After monomerization, the individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies (KGD) or known good cells (KGU).

[0015] Figures 2a-2pThe illustration shows the process of forming a semiconductor package with a shape memory alloy (SMA) structure. Figure 2a A cross-sectional view of a multilayer interconnect substrate or interposer 120, including a conductive layer 122 and an insulating layer 124, is shown. Although only a single interposer 120 is shown, hundreds or thousands of interposers are typically fabricated together in a single sheet or panel before being monomerized.

[0016] The conductive layer 122 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer can be formed using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer 122 provides horizontal electrical interconnects across the substrate 120 and vertical electrical interconnects between the top and bottom surfaces. Depending on the design and function of the semiconductor die 104 and other electrical components, portions of the conductive layer 122 can be electrically shared or electrically isolated.

[0017] The insulating layer 124 comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The insulating layer can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, or thermal oxidation. The insulating layer 124 provides isolation and structural support between the conductive layers 122. In other embodiments, any other suitable type of substrate or interlayer is used for the interlayer 120.

[0018] Solder bumps 125 are formed on the contact pads of conductive layer 122, as described above for bump 114, for example, using stencil printing or a ball drop process. Discrete passive components 126, such as resistors, inductors, or capacitors, are picked up and placed or otherwise mounted on interposer 120. Components 126 are electrically and physically coupled to interposer 120 using solder or solder paste. Any desired electrical components, including semiconductor die 104, other semiconductor dies, semiconductor packages, and discrete active components, can be mounted on interposer 120 as needed to achieve the intended electrical function of the formed semiconductor package.

[0019] SMA pillars 130 are deployed near the edges, corners, or ends of each interposer 120 unit. In some embodiments, the interposer 120 is square or rectangular, and four SMA pillars 130 are deployed at each corner of the interposer. SMA is an alloy that can deform in a cold state but recovers its original shape (“memory”) upon heating. In one embodiment, the SMA pillars 130 are formed of nickel-titanium (NiTi), also known as nitinol. The transition temperature of nitinol can be adjusted during the manufacturing process to suit specific applications, including those involving solder reflow temperatures typically between 183 and 260°C. Other SMA materials are used in other embodiments, such as copper-aluminum-nickel, Fe-Mn-Si, Cu-Zn-Al, and Cu-Al-Ni, as well as other alloys of zinc, copper, gold, or iron.

[0020] The SMA pillars 130 are formed by depositing the desired material into mask openings on the interposer layer 120. Alternatively, another substrate is used to form the SMA pillars 130 in the mask openings, and then the SMA pillars are picked up and placed on the interposer layer 120. In another embodiment, the SMA pillars 130 are cut from a sheet of material.

[0021] SMA pillars 130 are typically attached to the contact pads of conductive layer 122 using solder or solder paste. SMA pillars 130 may be dipped in solder paste before being deployed onto the interposer layer 120. In one embodiment, the contact pads of conductive layer 122 on which the SMA pillars 130 are mounted are electrically isolated from all portions of the conductive layer 122 that are electrically operable in the final package being formed; that is, the SMA pillars 130 have no internal electrical interconnection with the package being formed. Alternatively, SMA pillars 130 may be optionally formed in the kerf of the package being formed, such that the pillars are cut out and removed when the final package is individualized.

[0022] Figures 2b-2d The illustration shows a plan view of an interposer layer 120 in an exemplary embodiment. A conductive layer 122 forms a redistribution layer (RDL) pattern 122a in the middle of the interposer layer footprint and isolated contact pads 122b in the corners. The RDL pattern 122a is depicted as square only to illustrate the approximate area occupied by the RDL pattern. In practice, the RDL pattern 122a will consist of contact pads, conductive traces, and similar structures, not just a large conductive plane. The contact pads 122b are formed for mounting SMA pillars 130. In one embodiment, the contact pads 122b are formed in both the length and width dimensions of the interposer layer 120 so as not to overlap with the RDL pattern 122a at all. This allows for complete removal of the contact pads 122b by individualizing only in two vertical directions without removing any portion of the RDL pattern 122a.

[0023] Figure 2c An SMA post 130 is shown deployed on contact pad 122b. The SMA post 130 is rectangular with an aspect ratio of approximately 2:1. Each SMA post 130 at all four corners may be oriented parallel to each other. Alternatively, the posts may be tilted to face the center of the interposer layer 120, or deployed in any other suitable orientation. In other embodiments, the SMA post 130 is square, circular, or other suitable shape. Figure 2d Another embodiment is shown, wherein each corner contact pad 122b has two SMA posts 130a and 130b deployed thereon. Each SMA post 130a and 130b is deployed adjacent to an edge of the interposer layer 120 and is oriented parallel to the adjacent edge of the interposer layer. Thus, each edge of the interposer layer 120 has two SMA posts parallel to that edge orientation, one at each end. In other embodiments, additional contact pads 122b and SMA posts 130 can be formed and deployed along the edges between corners in any suitable number and distribution.

[0024] exist Figure 2e In this embodiment, multiple interposers 120 are deployed on a packaging substrate 140, with bumps 125, components 126, and SMA pillars 130 oriented toward the substrate, i.e., between the substrate 140 and the interposers 120. The substrate 140 has a structure similar to that of the interposers 120, wherein the formation and operation of the conductive layer 142 are similar to those of the conductive layer 122, and the formation and operation of the insulating layer 144 are similar to those of the insulating layer 124. Optionally, components 126 and any other desired electrical components, such as those mentioned that might be mounted on the interposers 120, are mounted on the substrate 140, in addition to being mounted on the interposers or, alternatively, on the interposers. In some embodiments, the SMA pillars 130 are mounted on the substrate 140 instead of the interposers 120.

[0025] Intermediate layer 120 is provided with bumps 125 and SMA pillars 130 aligned with the contact pads of conductive layer 142. Solder paste is applied to the ends of the SMA pillars 130 opposite to the intermediate layer 120 for attaching the pillars to the substrate 140. Alternatively, solder paste is printed on the contact pads of conductive layer 142 for attaching the SMA pillars 130. The contact pads of conductive layer 142 are isolated and do not overlap with the RDL pattern of the conductive layer, such as... Figure 2b The conductive layer 122 is shown in the figure. Figure 2f An interposer 120 is shown on substrate 140, which is prepared for reflow of the solder paste to attach pillars 130, and an RDL pattern for reflow of bumps 125 to electrically connect conductive layers 122 and 142.

[0026] Figure 2gThe typical temperature profile for solder reflow of SAC305 solder is shown at 150°C. The oven temperature begins to rise at 0 seconds and reaches 250°C at 300 seconds. At 300 seconds, the oven is shut off, and the temperature begins to drop until it reaches its original temperature of approximately 25°C at about 480 seconds.

[0027] At point 152, after approximately 235 seconds, SMA column 130 reaches the austenite initiation temperature. After approximately 300 seconds, before the temperature is allowed to drop further, the austenite termination temperature is reached at point 154. The temperature remains within the austenite zone until it drops back below the austenite initiation temperature at point 156. The region between points 152 and 156 is called the dwell zone because the temperature remains within the austenite zone.

[0028] Austenite is the high-temperature phase of SMA and typically has a cubic crystal structure with high symmetry. The austenitic phase in the SMA structure increases the structural height of the SMA pillar 130. This increased height of the SMA pillar 130 during solder reflow has several benefits, as described below.

[0029] At point 160, approximately 350 seconds into the process, temperature profile 150 cools to the martensitic initiation temperature. The temperature profile remains within the martensitic zone until point 162, approximately 425 seconds later, when the temperature reaches the martensitic termination temperature. The region between points 160 and 162 is called the cooling zone or martensitic zone. Martensite is a low-temperature phase and is generally characterized by lower symmetry. Within the martensitic zone, the SMA pillar 130 contracts from or recovers to its original shape before reaching the austenitic zone. The start and end temperatures of the austenitic and martensitic zones can be configured by modifying the ratio of Ni to Ti or other components or by controlling the amount of oxygen or carbon bonded to titanium atoms.

[0030] Figures 2h-2j The illustration shows one benefit of SMA column 130 correcting warpage. Figure 2h In this configuration, an interposer 120 has been deposited on a substrate 140, but solder bumps 125 have not yet been reflowed. The interposer 120 has edges or ends that are warped upwards, such that inner bumps 125a remain on the substrate 140, but outer bumps 125b have a gap 170 between the bumps and the substrate 140. If the bumps 125b are not properly wetted onto the conductive layer 142 due to separation, the gap 170 may cause undesirable electrical discontinuities after reflow. SMA pillars 130 are attached to the interposer 120 using solder paste 172, but fail to make physical contact with solder paste 174 on the substrate 140.

[0031] Figure 2iThe substrate 140 and interposer 120 in the austenitic zone are shown. SMA pillars 130 have been grown as indicated by arrow 176. The austenitic growth of the SMA pillars 130 increases the pillar height, allowing the pillars to physically contact the solder paste 174 on the substrate 140. The solder paste 174 is reflowed and wetted onto the SMA pillars 130.

[0032] Figure 2j The SMA pillar 130, which shrinks again in the martensitic phase, is shown. Arrow 178 illustrates the shrinkage of the SMA pillar 130 pulling down the interposer 120. The force exerted by the shrinkage of the SMA pillar 130 corrects the warpage of the interposer 120, resulting in a substantially flat interposer. Gap 170 is closed, allowing solder bumps 125b to flow properly back onto the contact pads of the conductive layer 142. The SMA pillar 130 pulls the corners, edges, or ends of the interposer 120 down toward the substrate 140.

[0033] exist Figure 2k In this process, a sealant or molding compound 180 is deposited on and between the substrate 140 and the interposer 120, including around the SMA pillars 130, bumps 125, and assembly 126, using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. The sealant 180 can be a liquid or particulate polymer composite, such as epoxy resin, epoxy acrylate, or another suitable polymer, with or without suitable fillers. The sealant 180 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external components and contaminants.

[0034] In some embodiments, the SMA pillars 130 are regrown during the molding process, which can be performed at high temperatures. The growth of the SMA pillars 130 provides additional support for the interposer layer 120 above the substrate 140 to reduce the collapse of the solder bumps 125.

[0035] exist Figure 2l In this configuration, additional electrical components are mounted on interposer 120, opposite component 126. For example, discrete component 182 and semiconductor package 184 are mounted on interposer 120. In one embodiment, semiconductor package 184 includes semiconductor die 104. In some embodiments, semiconductor package 184 may be a system-in-package module or a chiplet, wherein multiple components are packaged together.

[0036] The semiconductor package 184 includes solder bumps 186 on the bottom surface of the package, which will be flowed back to the contact pads of the conductive layer 122 to make the semiconductor package electrically and physically contact the interposer 120. Figure 2mThe package 184 is shown stacked on the interposer 120 and ready for reflow. As described above with respect to bump 114, bump 187 is formed on the bottom of the substrate 140. The kerf 188 is drawn to illustrate how, in some embodiments, the post 130 is positioned within the kerf.

[0037] A common problem with stacked packages is that the reflow solder bumps 186 used to attach package 184 to interposer 120 also reflow the bumps 125 between the interposer and substrate 140. Because stacked packages can be quite heavy, especially where multiple packages or chips are stacked on each interposer 120, the reflow of bumps 125 can cause the interposer 120 to collapse toward the substrate 140. This collapse problem exists in all embodiments, but is exacerbated in embodiments where package 184 is mounted before molding with sealant 180. One problem caused by the collapse of bumps 125 is that component 126 may unintentionally short-circuit with conductive layer 142, resulting in defective cells.

[0038] Figure 2n Arrow 190 illustrates the tendency for the reflow bump 125 to collapse due to gravity. Arrow 192 illustrates the expansion of the SMA pillar 130 in the austenitic zone. The expansion of the SMA pillar 130 provides additional support during reflow to counteract the collapse of the bump 125 under the weight of the package 184. A typical manufacturing process involves a total of four reflows. During the four reflow cycles, the height of the bump 125 gradually decreases from the target value. The SMA pillar 130 expands to reverse the collapse of the bump 125. From the first reflow, each reflow step provides the same anti-collapse benefit, but this benefit becomes more significant with each subsequent reflow. For smaller bumps 125, without correction using the SMA pillar 130, collapse might begin to cause noticeable defects as early as the second reflow.

[0039] exist Figure 2o In this process, a saw blade or laser cutting tool 194 is used to monolithize the packaged panel through saw grooves 188. If SMA pillars 130 are deployed within saw grooves 188, the SMA pillars are removed through monolithization. Figure 2p A complete semiconductor package 196 after monomerization is shown. The semiconductor package 196 has a package substrate 140 and an interposer 120, wherein warpage is reduced due to the use of SMA pillars 130 during manufacturing. The use of SMA pillars 130 also reduces the possibility of solder bump 125 collapse and accidental short circuits. In some embodiments, the SMA pillars 130 are retained in the final package.

[0040] Figure 3a and Figure 3b The figure illustrates the integration of the aforementioned semiconductor package and device (e.g., semiconductor package 196) into a larger electronic device 200. Figure 3a The figure shows a partial cross-section of a semiconductor package 196 mounted on a printed circuit board (PCB) or other substrate 202, which is part of an electronic device 200. Bumps 187 are flowed back onto the conductive layer 204 of the PCB 202 to physically attach and electrically connect the semiconductor package 196 to the PCB. In other embodiments, thermocompression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between the semiconductor package 196 and the PCB 202. Components of the package 196, such as semiconductor die 104 and package 184, are electrically coupled to the conductive layer 204 via bumps 187, substrate 140, bumps 125, and interposer 120.

[0041] Figure 3b The figure illustrates an electronic device 200 having a chip carrier substrate or PCB 202, wherein multiple semiconductor packages, including semiconductor package 196, are deployed on the surface of the PCB 202. Depending on the application, the electronic device 200 may have one type of semiconductor package or multiple types of semiconductor packages.

[0042] Electronic device 200 can be a standalone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electronic device 200 can be a sub-component of a larger system. For example, electronic device 200 can be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Alternatively, electronic device 200 can be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packages can include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are crucial for product market acceptance. The distance between semiconductor devices can be reduced to achieve higher density. PCB 202 can have more irregular shapes to easily fit into more ergonomic and smaller device housings.

[0043] exist Figure 3b In this design, PCB 202 provides a common substrate for the structural support and electrical interconnection of semiconductor packages deployed on the PCB. Conductive signal traces 204 are formed on the surface or within the layers of PCB 202 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 204 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. Trace 204 also provides power and ground connections for each semiconductor package.

[0044] In some embodiments, the semiconductor device has two packaging levels. The first-level packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first-level package, where the die is directly mechanically and electrically deployed to the PCB.

[0045] For illustrative purposes, several types of first-level packages are shown on PCB 202, including a bonding wiring package 246 and a flip chip 248. Additionally, several types of second-level packages deployed on PCB 202 are shown, including a ball grid array (BGA) 250, a bump chip carrier (BCC) 252, a contact grid array (LGA) 256, a multi-chip module (MCM) or SIP module 258, a quad flat package (QFN) 260, a quad flat package 262, and an embedded die-level ball grid array (eWLB) 264. In one embodiment, eWLB 264 is a fan-out die-level package (Fo-WLP) or a fan-in die-level package (Fi-WLP).

[0046] Depending on system requirements, any combination of semiconductor packages configured with first-level and second-level packaging styles, along with any combination of other electrical components, can be connected to PCB 202. In some embodiments, electronic device 200 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can integrate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less prone to failure and less expensive to manufacture, thus reducing costs for consumers.

[0047] While one or more embodiments of the invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations can be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Provide an intermediary layer; A shape metal alloy (SMA) structure is deployed on the intermediary layer, wherein the SMA structure is formed of nickel-titanium; Solder bumps are deployed on the intermediate layer; Electrical components are deployed on top of the intermediary layer; The interposer is deployed on the substrate, wherein the SMA structure, solder bumps and electrical components are between the interposer and the substrate; as well as The solder bumps are reflowed.

2. The method of claim 1, wherein reflowing the solder bumps causes the SMA structure to expand.

3. The method of claim 2, wherein the SMA structure shrinks upon cooling after reflow.

4. The method of claim 1, further comprising deploying a semiconductor package on the interposer layer opposite to the substrate.

5. The method of claim 4, further comprising a second reflow of the solder bumps after the semiconductor package is deployed on the interposer layer.

6. The method of claim 1, wherein a gap exists between the solder bumps and the substrate prior to reflow.

7. A method for manufacturing a semiconductor device, comprising: Provide an intermediary layer; A shape metal alloy (SMA) structure is deployed on top of the intermediary layer; as well as The interposer is deployed on the substrate, wherein the SMA structure is located between the interposer and the substrate.

8. The method of claim 7, further comprising reflowing solder bumps after deploying the semiconductor package on the interposer layer.

9. The method of claim 8, wherein reflowing the solder bumps causes the SMA structure to expand.

10. The method of claim 9, wherein the SMA structure shrinks upon cooling after reflow.

11. A semiconductor device, comprising: Intermediate layer; Substrate; as well as Shaped metal alloy (SMA) structures are deployed between the interlayer and the substrate.

12. The semiconductor device of claim 11, further comprising a semiconductor package disposed on the interposer layer opposite the substrate.

13. The semiconductor device of claim 11, further comprising an electrical component disposed between the interposer and the substrate.

14. The semiconductor device of claim 11, further comprising solder bumps disposed between the interposer and the substrate.

15. The semiconductor device of claim 11, further comprising a plurality of SMA structures deployed between the interposer and the substrate, wherein one of the plurality of SMA structures is deployed at each corner of the interposer.

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