Formation method and packaging method of semiconductor structure

Abstract

A semiconductor structure forming method and a semiconductor structure packaging method are provided, and the semiconductor structure forming method comprises the following steps: providing a substrate which comprises a to-be-bonded surface; forming a bonding pad in the substrate on one side of the to-be-bonded surface, wherein the to-be-bonded surface is exposed out of the top surface of the bonding pad; forming a protective layer covering the bonding pad and exposing the to-be-bonded surface; and performing surface activation treatment on the to-be-bonded surface. According to the invention, the bonding effect of the semiconductor structure is improved, so that the packaging yield is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a method for forming and packaging a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, the feature size of integrated circuits continues to shrink. Correspondingly, the packaging requirements for integrated circuits are also increasing. Based on the two-dimensional packaging in the X and Y planes of multi-chip modules (MCMs), 3D packaging technology stacked along the Z direction has been fully developed, and the 3D packaging technology has higher density.

[0003] Three-dimensional integrated circuits (3D ICs) are fabricated using advanced chip stacking technology, which stacks chips with different functions into an integrated circuit with a three-dimensional structure. Compared to two-dimensional integrated circuits, the stacking technology of 3D ICs not only shortens the signal transmission path but also increases the operating speed, thereby meeting the demands of semiconductor devices for higher performance, smaller size, lower power consumption, and more functions.

[0004] Hybrid bonding, as a novel packaging technology, is currently widely used. It achieves stacking technology through hybrid bonding of metals to metals and inorganic materials to inorganic materials. The bonding interface directly determines whether wafers can form a connected structure to allow current to pass through. Since wafer thinning processes continue after bonding, if the wafer bonding is not tight enough, wafer peeling may occur. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming and packaging a semiconductor structure, which is beneficial to improving the bonding effect of the semiconductor structure and thus improving the packaging yield.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a bonding surface; forming bonding pads in the substrate on one side of the bonding surface, with the bonding surface exposed above the top surface of the bonding pads; forming a protective layer covering the bonding pads and exposing the bonding surface; and performing surface activation treatment on the bonding surface.

[0007] Optionally, in the step of providing the substrate, the substrate includes a substrate and a dielectric layer located on the substrate, and the bonding surface is the surface of the dielectric layer exposed; in the step of forming bonding pads in the substrate on one side of the bonding surface, bonding pads are formed in the dielectric layer, and the dielectric layer exposes the top surface of the bonding pads; in the step of performing surface activation treatment on the bonding surface, the dielectric layer is subjected to surface activation treatment.

[0008] Optionally, in the step of providing the substrate, the material of the dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

[0009] Optionally, in the step of providing the substrate, an interconnect layer is formed in the dielectric layer; in the step of forming bonding pads in the substrate on one side of the bonding surface, the bonding pads penetrate the dielectric layer on the interconnect layer, and a portion of the bonding pads are electrically connected to the interconnect layer.

[0010] Optionally, the step of forming bonding pads in the dielectric layer includes: patterning the dielectric layer to form multiple grooves, with some grooves exposed above the top surface of the interconnect layer; and forming bonding pads in the grooves.

[0011] Optionally, the step of patterning the dielectric layer to form multiple grooves includes: forming a mask layer covering the dielectric layer; patterning the mask layer to form multiple mask openings exposing the top surface of the dielectric layer; patterning the dielectric layer along the mask openings to form multiple grooves; and after forming the grooves, the forming method further includes: removing the mask layer.

[0012] Optionally, the step of forming bonding pads in the groove includes: forming an interconnect material layer that fills the groove and covers the top surface of the dielectric layer; planarizing the interconnect material layer; removing the interconnect material layer above the top surface of the dielectric layer; and retaining the interconnect material layer located in the groove as a bonding pad.

[0013] Optionally, a selective atomic layer deposition process can be used to form a protective layer that covers the bonding pads and exposes the surfaces to be bonded.

[0014] Optionally, in the step of forming a protective layer that covers the bonding pads and exposes the bonding surface, the protective layer is a self-assembled single-layer structure.

[0015] Optionally, after performing surface activation treatment on the bonding surfaces, the formation method may further include: removing the protective layer.

[0016] Optionally, a plasma activation process can be used to activate the surface of the bonding surfaces.

[0017] Optionally, the method may further include removing the protective layer in the step of surface activation treatment of the bonding surfaces.

[0018] Optionally, in the step of forming bonding pads in the substrate on one side of the bonding surface, the material of the bonding pads includes copper.

[0019] Accordingly, embodiments of the present invention provide a packaging method, comprising: providing a first wafer and a second wafer, both the first wafer and the second wafer comprising a semiconductor structure formed by the formation method provided in embodiments of the present invention; bonding the first wafer and the second wafer with their surfaces to be bonded facing each other, wherein the bonding pads of the first wafer and the second wafer are in contact.

[0020] Optionally, after bonding the first wafer and the second wafer with their surfaces facing each other, the packaging method further includes: thermally expanding the bonding pads.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0022] In the semiconductor structure formation method provided by the embodiments of the present invention, a protective layer is formed that covers the bonding pads and exposes the bonding surface, and the bonding surface is subjected to surface activation treatment. In the embodiments of the present invention, surface activation treatment of the bonding surface is beneficial to improving the bonding performance of the bonding surface. The protective layer covers the bonding pads and exposes the bonding surface, so that when the bonding surface is surface activated, it plays a protective role for the bonding pads, reducing damage to the bonding pads. At the same time, it can expose and activate the bonding surface, and will not accidentally sputter the material of the bonding pads onto the bonding surface, making the bonding surface less susceptible to contamination, which is beneficial to improving the bonding performance of the bonding surface. This makes it beneficial to improve the bonding effect of the semiconductor structure when bonding is performed through the bonding surface.

[0023] In the packaging method provided in this embodiment of the invention, a first wafer and a second wafer are provided. Both the first wafer and the second wafer include a semiconductor structure formed by the formation method provided in this embodiment of the invention. The bonding surfaces of the first wafer and the second wafer are aligned to bond the first wafer and the second wafer. In this embodiment of the invention, surface activation treatment is performed on the bonding surfaces, which is beneficial to improving the bonding performance of the bonding surfaces. The protective layer covers the bonding pads and exposes the bonding surfaces, so that when the surface activation treatment is performed on the bonding surfaces, the bonding surfaces can be exposed and activated simultaneously, and the material of the bonding pads will not be accidentally sputtered onto the bonding surfaces, making the bonding surfaces less susceptible to contamination. This is beneficial to improving the bonding performance of the bonding surfaces, and when the first wafer and the second wafer are bonded through the bonding surfaces, the bonding effect is improved, thereby improving the packaging yield. Attached Figure Description

[0024] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0025] Figures 4 to 14This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0026] Figures 15 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the packaging method of the present invention. Detailed Implementation

[0027] As the background technology shows, the bonding effect and packaging yield of semiconductor structures currently need improvement. This paper analyzes the reasons why the bonding effect and packaging yield of semiconductor structures need improvement, using a semiconductor structure formation method as an example.

[0028] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0029] refer to Figure 1 A substrate 10 is provided, the substrate 10 having a bonding surface 10a, and a bonding pad 20 is formed in the substrate 10 on one side of the bonding surface 10a.

[0030] Reference Figure 2 and Figure 3 Surface activation treatment was performed on the bonding surface 10a.

[0031] Surface activation treatment is performed on the bonding surface 10a to activate the surface of the substrate 10. This is typically done by plasma bombardment of the bonding surface 10a, which exposes the bonding pad 20 surface. However, during bombardment, material from the bonding pad 20 can easily sputter onto the surface of the bonding surface 10a on the substrate 10 (e.g.,...). Figure 3 As shown, this affects the bonding performance of the bonding surface 10a, thereby affecting the bonding effect of the semiconductor structure and the packaging yield of the package structure obtained by subsequent semiconductor structure bonding.

[0032] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a bonding surface; forming bonding pads in the substrate on one side of the bonding surface, with the bonding surface exposed above the top surface of the bonding pads; forming a protective layer covering the bonding pads and exposing the bonding surface; and performing surface activation treatment on the bonding surface.

[0033] In the semiconductor structure formation method provided by the embodiments of the present invention, a protective layer is formed that covers the bonding pads and exposes the bonding surface, and the bonding surface is subjected to surface activation treatment. In the embodiments of the present invention, surface activation treatment of the bonding surface is beneficial to improving the bonding performance of the bonding surface. The protective layer covers the bonding pads and exposes the bonding surface, so that when the bonding surface is surface activated, it plays a protective role for the bonding pads, reducing damage to the bonding pads. At the same time, it can expose and activate the bonding surface, and will not accidentally sputter the material of the bonding pads onto the bonding surface, making the bonding surface less susceptible to contamination, which is beneficial to improving the bonding performance of the bonding surface. This makes it beneficial to improve the bonding effect of the semiconductor structure when bonding is performed through the bonding surface.

[0034] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figures 4 to 14 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention.

[0036] refer to Figure 4 A substrate 100 is provided, the substrate 100 including a bonding surface 100a.

[0037] The substrate 100 is used to provide a process operation platform for the formation of semiconductor structures.

[0038] In this embodiment, the substrate 100 includes a bonding surface 100a.

[0039] Subsequently, the semiconductor structure is bonded to other structures by bonding the bonding surface 100a.

[0040] In this embodiment, in the step of providing the substrate 100, the substrate 100 includes a substrate 110 and a dielectric layer 120 located on the substrate 110, and the bonding surface 100a is the surface of the dielectric layer 120 exposed.

[0041] As an example, substrate 110 is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0042] The bonding surface 100a is the surface exposed by the dielectric layer 120, and the bonding of the semiconductor structure is subsequently achieved through the surface exposed by the dielectric layer 120.

[0043] The dielectric layer 120 is used to provide a process operation platform for the subsequent formation of bonding pads, and also to achieve electrical isolation between bonding pads.

[0044] In this embodiment, the material of the dielectric layer 120 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0045] As an example, in this embodiment, the material of the dielectric layer 120 in the step of providing the substrate 100 is silicon oxide.

[0046] In this embodiment, during the step of providing the substrate 100, an interconnect layer 130 is formed in the dielectric layer 120.

[0047] The interconnect layer 130 is used to realize the basic circuit functions of the semiconductor structure. After the semiconductor structure is bonded, the interconnect layer 130 is electrically connected to the outside, realizing the electrical connection between the circuit structures of the semiconductor structure, thereby realizing the normal function of the package structure.

[0048] Reference Figures 5 to 10 A bonding pad 220 is formed in the substrate 100 on one side of the bonding surface 100a, and the top surface of the bonding pad 220 is exposed on the bonding surface 100a.

[0049] The bonding pad 220 is used to contact the bonding pads of other structures to achieve bonding of the semiconductor structure during subsequent bonding of the semiconductor structure.

[0050] In this embodiment, in the step of forming bonding pads 220 in the substrate 100 on one side of the bonding surface 100a, the material of the bonding pads 220 includes one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, which is beneficial to obtaining better conductivity.

[0051] As an example, in this embodiment, the bonding pad 220 is made of copper. Copper has good diffusion properties, so when the bonding pad 220 is heated during the subsequent bonding of the semiconductor structure, the material of the bonding pad 220 is easy to diffuse, thus the bonding performance of the bonding pad 220 is good during the subsequent bonding of the semiconductor structure.

[0052] In this embodiment, in the step of forming bonding pad 220 in the substrate 100 on one side of the bonding surface 100a, bonding pad 220 is formed in the dielectric layer 120, and the dielectric layer 120 exposes the top surface of the bonding pad 220.

[0053] The dielectric layer 120 exposes the top surface of the bonding pad 220, enabling subsequent bonding of the semiconductor structure through the exposed surface of the bonding pad 220.

[0054] In this embodiment, hybrid bonding is subsequently used to bond the semiconductor structure. Specifically, when bonding different semiconductor structures through the bonding surface 100a, the stacking technology is achieved through hybrid bonding, which involves contact between metals (i.e., bonding pads 220 and bonding pads 220) and between inorganic materials (i.e., contact between dielectric layers 120 and dielectric layers 120).

[0055] In this embodiment, in the step of forming bonding pads 220 in the substrate 100 on one side of the bonding surface 100a, the bonding pads 220 penetrate the dielectric layer 120 on the interconnect layer 130, and a portion of the bonding pads 220 are electrically connected to the interconnect layer 130.

[0056] The bonding pad 220 penetrates the dielectric layer 120 on the interconnect layer 130, so that the dielectric layer 120 can expose the top surface of the bonding pad 220.

[0057] In this process, the partial bonding pad 220 is electrically connected to the interconnect layer 130. Correspondingly, the partial bonding pad 220 is also used to electrically connect to the interconnect layer 130, serving as an interconnect pad to realize the electrical connection between the interconnect layer 130 and the outside after the bonding of the semiconductor structure is achieved.

[0058] Reference Figures 5 to 7 The step of forming bonding pads 220 in the substrate 100 on one side of the bonding surface 100a includes: patterning the dielectric layer 120, forming a plurality of grooves 200, with some grooves 200 exposed above the top surface of the interconnect layer 130.

[0059] The groove 200 is used to provide space for the formation of the bonding pad 220. Part of the groove 200 exposes the top surface of the interconnect layer 130 to prepare for the formation of the bonding pad 220 that is electrically connected to the interconnect layer 130.

[0060] Specifically, refer to Figure 5 The step of forming a plurality of grooves 200 in the patterned dielectric layer 120 includes forming a mask layer 300 covering the dielectric layer 120.

[0061] The mask layer 300 is used as an etching mask for the patterning medium layer 120.

[0062] In this embodiment, the material of the mask layer 300 is photoresist.

[0063] refer to Figure 6 A patterned mask layer 300 is formed to create multiple mask openings 310 that expose the top surface of the dielectric layer 120.

[0064] The mask opening 310 is used to pattern the dielectric layer 120 along the mask opening 310.

[0065] refer to Figure 7A plurality of grooves 200 are formed by patterning the dielectric layer 120 along the mask opening 310.

[0066] Patterning the dielectric layer 120 along the mask opening 310 forms multiple grooves 200, which helps to improve the dimensional accuracy of the grooves 200.

[0067] refer to Figure 8 After forming the groove 200, the forming method also includes: removing the mask layer 300.

[0068] Remove the mask layer 300 to prepare for the formation of the bonding pad 220.

[0069] Reference Figure 9 and Figure 10 A bonding pad 220 is formed in the groove 200.

[0070] Specifically, refer to Figure 9 The step of forming bonding pads 220 in the groove 200 includes forming an interconnect material layer 210 that fills the groove 200 and covers the top surface of the dielectric layer 120.

[0071] Interconnect material layer 210 is used to form bonding pads 220.

[0072] Accordingly, in this embodiment, in the step of forming the interconnect material layer 210 that fills the groove 200 and covers the top surface of the dielectric layer 120, the material of the interconnect material layer 210 is copper.

[0073] refer to Figure 10 The interconnect material layer 210 is planarized, the interconnect material layer 210 above the top surface of the dielectric layer 120 is removed, and the interconnect material layer 210 located in the groove 200 is retained as a bonding pad 220.

[0074] The planarization of the interconnect material layer 210 removes the interconnect material layer 210 that is higher than the top surface of the dielectric layer 120, so that the top surface of the bonding pad 220 and the dielectric layer 120 has better flatness. In other words, the flatness of the bonding surface 100a is better, which is beneficial to improving the bonding performance of the bonding surface 100a.

[0075] In this embodiment, a chemical mechanical polishing (CMP) process is used to planarize the interconnect material layer 210 and remove the interconnect material layer 210 above the top surface of the dielectric layer 120.

[0076] Chemical mechanical polishing combines the advantages of chemical polishing and mechanical polishing, ensuring the simultaneous and efficient removal of material from the interconnect material layer 210 above the top surface of the dielectric layer 120, and obtaining a better surface of the bonding surface 100a.

[0077] Reference Figure 11 and Figure 12 , Figure 12 yes Figure 11 The top view shows a protective layer 400 that covers the bonding pads 220 and exposes the bonding surface 100a.

[0078] The protective layer 400 is used to cover the surface of the bonding pad 220, so that the bonding pad 220 is protected during the subsequent surface activation treatment of the bonding surface 100a, reducing damage and oxidation to the bonding pad 220, and also reducing the probability of sputtering material from the bonding pad 220 onto the surface of the dielectric layer 120.

[0079] In this embodiment, subsequent surface activation treatment of the bonding surface 100a is beneficial to improving the bonding performance of the bonding surface 100a. The protective layer 400 covers the bonding pad 220 and exposes the bonding surface 100a, so that when the bonding surface 100a is surface activated, it plays a protective role for the bonding pad 220, reducing damage to the bonding pad 220. At the same time, it can expose the bonding surface 100a to be activated, and will not accidentally sputter the material of the bonding pad 220 onto the bonding surface 100a, making the bonding surface 100a less susceptible to contamination. This is beneficial to improving the bonding performance of the bonding surface 100a, and thus improving the bonding effect of the semiconductor structure when bonding is performed through the bonding surface 100a.

[0080] In this embodiment, a protective layer 400 is formed by selective atomic layer deposition (SALD) that covers the bonding pads 220 and exposes the bonding surface 100a.

[0081] The selective atomic layer deposition (ALD) process can selectively deposit the protective layer 400 on the surface of the bonding pad 220, exposing the bonding surface 100a on the side of the bonding pad 220.

[0082] In this embodiment, in the step of forming a protective layer 400 that covers the bonding pad 220 and exposes the bonding surface 100a, the protective layer 400 is a self-assembled single-layer structure.

[0083] Specifically, the process of forming the protective layer 400 with a self-assembled monolayer (SAM) structure is as follows: the bonding pad 220 is made of a metallic material. Based on the affinity of the organic chemical chains suspended in a special solution for the metal, these molecular chains will adsorb onto the metal surface and self-assemble into an organized region. Over time, this region will adsorb a large number of molecules and form nuclei, which will continue to grow and thicken until the metal surface is covered by a monolayer. At this point, due to the presence of van der Waals forces, i.e., the weak net attraction between neutral organic solids, this monolayer material is tightly wrapped and deposited on the metal surface, thus forming a protective layer 400 that selectively covers the surface of the bonding pad 220.

[0084] Reference Figure 13 and Figure 14 Surface activation treatment is performed on the bonding surface 100a.

[0085] Surface activation treatment is performed on the bonding surface 100a to activate the surface material of the bonding surface 100a and improve the bonding force of the bonding surface 100a.

[0086] Accordingly, in this embodiment, in the step of performing surface activation treatment on the bonding surface 100a, the dielectric layer 120 is subjected to surface activation treatment.

[0087] In this embodiment, the protective layer 400 covers the bonding pad 220. Therefore, only the dielectric layer 120 can be surface activated, which not only improves the bonding force of the bonding surface 100a, but also protects the bonding pad 220.

[0088] In this embodiment, a plasma activation process is used to activate the surface of the bonding surface 100a.

[0089] Plasma activation process can activate the bonding surface 100a, making it easier to achieve bonding of semiconductor structures through the bonding surface 100a.

[0090] Specifically, in this embodiment, a plasma activation process is used to perform surface activation treatment on the dielectric layer 120. Through surface excitation, H and O bonds can be formed on the dielectric layer 120 of the bonding surface 100a, which increases the hydroxyl density on the surface and enables hydrophilic pre-bonding at room temperature, thereby improving the bonding force of the bonding surface 100a.

[0091] Specifically, refer to Figure 14 In this embodiment, the method for performing surface activation treatment on the bonding surface 100a further includes removing the protective layer 400.

[0092] Remove the protective layer 400 to expose the bonding surface 100a, preparing for the subsequent bonding of the semiconductor structure.

[0093] In this embodiment, the excitation force of plasma is relatively strong. Through high-energy excitation, the protective layer 400 on the bonding pad 220 can be removed. Thus, in this embodiment, the protective layer 400 can be removed simultaneously during the surface activation treatment of the bonding surface 100a, which helps to simplify the process flow and improve process efficiency.

[0094] In other embodiments, after performing surface activation treatment on the bonding surfaces, the method may further include removing the protective layer.

[0095] It should be noted that in this embodiment, the plasma activation treatment also removes part of the dielectric layer 120, which helps to better expose the bonding pads 220 on the bonding surface 100a, thereby improving the bonding yield when the semiconductor structure is bonded through the bonding surface 100a in the future.

[0096] Figures 15 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the packaging method of the present invention.

[0097] refer to Figure 15 Provide the first wafer 10A (e.g.) Figure 15 (a) shown) and the second wafer 10B (as shown) Figure 15 (b) As shown, both the first wafer 10A and the second wafer 10B include a semiconductor structure formed by the formation method of the aforementioned embodiment.

[0098] The first wafer 10A and the second wafer 10B are used to implement wafer-level packaging for the packaging structure.

[0099] refer to Figure 16 The bonding surfaces 100a of the first wafer 10A and the second wafer 10B are aligned so that the first wafer 10A and the second wafer 10B are bonded together, and the bonding pads 220 of the first wafer 10A and the second wafer 10B are in contact.

[0100] In this embodiment, surface activation treatment of the bonding surface 100a is beneficial to improving the bonding performance of the bonding surface 100a. The protective layer covers the bonding pad 220 and exposes the bonding surface 100a, so that when the bonding surface 100a is surface activated, the bonding surface 100a can be exposed and activated at the same time, and the material of the bonding pad 220 will not be accidentally sputtered onto the bonding surface 100a, making the bonding surface 100a less susceptible to contamination. This is beneficial to improving the bonding performance of the bonding surface 100a, and when the first wafer 10A and the second wafer 10A are bonded through the bonding surface 100a, the bonding effect is improved, thereby improving the packaging yield.

[0101] In this embodiment, after the bonding surfaces 100a of the first wafer 10A and the second wafer 10B are aligned and bonded together, the packaging method further includes: thermally expanding the bonding pads 220.

[0102] Thermal expansion treatment of bonding pad 220 allows for more complete contact between the bonding surfaces 100a of the first wafer 10A and the second wafer 10B, which is beneficial to enhancing the bonding strength of the packaging structure.

[0103] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a bonding surface; A bonding pad is formed in the substrate on one side of the surface to be bonded, with the surface to be bonded exposing the top surface of the bonding pad; A protective layer is formed that covers the bonding pads and exposes the surfaces to be bonded; The surface to be bonded is subjected to surface activation treatment.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the substrate includes a substrate and a dielectric layer located on the substrate, and the bonding surface is the exposed surface of the dielectric layer; In the step of forming a bonding pad in the substrate on one side of the bonding surface, the bonding pad is formed in the dielectric layer, and the dielectric layer exposes the top surface of the bonding pad; In the step of performing surface activation treatment on the bonding surface, the dielectric layer is subjected to surface activation treatment.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the step of providing the substrate, the material of the dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the step of providing the substrate, an interconnect layer is formed in the dielectric layer; In the step of forming bonding pads in the substrate on one side of the bonding surface, the bonding pads penetrate the dielectric layer on the interconnect layer, and a portion of the bonding pads are electrically connected to the interconnect layer.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The step of forming the bonding pads in the dielectric layer includes: patterning the dielectric layer to form a plurality of grooves, with a portion of the grooves exposed above the top surface of the interconnect layer; The bonding pad is formed in the groove.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The step of patterning the dielectric layer to form multiple grooves includes: forming a mask layer covering the dielectric layer; The mask layer is patterned to form multiple mask openings that expose the top surface of the dielectric layer; The dielectric layer is patterned along the mask opening to form a plurality of the grooves; After forming the groove, the forming method further includes removing the mask layer.

7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The step of forming the bonding pad in the groove includes: forming an interconnect material layer that fills the groove and covers the top surface of the dielectric layer; The interconnect material layer is planarized, the interconnect material layer above the top surface of the dielectric layer is removed, and the interconnect material layer located in the groove is retained as the bonding pad.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, A protective layer is formed by selective atomic layer deposition (SLD) to cover the bonding pads and expose the bonding surfaces.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of forming a protective layer that covers the bonding pads and exposes the bonding surface, the protective layer is a self-assembled single-layer structure.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, After performing surface activation treatment on the bonding surface, the forming method further includes removing the protective layer.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The surfaces to be bonded are activated using a plasma activation process.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of performing surface activation treatment on the surface to be bonded, the forming method further includes: removing the protective layer.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming bonding pads in the substrate on one side of the bonding surface, the material of the bonding pads includes one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium.

14. A packaging method, characterized in that, include: A first wafer and a second wafer are provided, each of the first wafer and the second wafer comprising a semiconductor structure formed by the formation method according to any one of claims 1 to 13; The bonding surfaces of the first wafer and the second wafer are brought together so that the first wafer and the second wafer are bonded together, and the bonding pads of the first wafer and the second wafer are in contact.

15. The packaging method as described in claim 14, characterized in that, After bonding the first wafer and the second wafer with their surfaces facing each other, the packaging method further includes: thermally expanding the bonding pads.

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