Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The substrate comprises first regions used for forming semiconductor fins and second regions located between the first regions; forming a plurality of semiconductor fins on the substrate in the first region; forming an isolation layer covering the plurality of semiconductor fins, wherein the isolation layer encloses an isolation groove between the semiconductor fins in the second region; filling a dielectric layer in the isolation groove; removing a part of the dielectric layer in the isolation groove, the isolation layer below the dielectric layer and a part of the substrate to form an interconnection groove; forming a bottom connecting line located at the bottom of the interconnection groove; forming a pseudo vertical connecting line located above the bottom connecting line in the interconnection groove; forming a source-drain doping layer on the semiconductor fin at the two sides of the pseudo vertical connecting line; forming a gate structure crossing the plurality of semiconductor fins; removing pseudo vertical connecting lines; filling a conductive material in the interconnection groove to form an interconnection conductive layer on the bottom connecting line; the embodiment of the invention is favorable for improving the manufacturing yield of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Semiconductor chips are mainly composed of a silicon substrate and field-effect transistors. A dense network of power rails is distributed above the field-effect transistors to provide power signals.

[0003] With the increasing demand for advanced semiconductor technology nodes, the reduction in spacing between traditional field-effect transistors (FETs) is achieved by decreasing the power rail linewidth and spacing. However, as power rail linewidth and spacing have become extremely narrow, the metal resistance of the power rails has increased significantly, exacerbating the voltage drop problem. To ensure lower voltage drop, designers have proposed Buried Power Rails (BPRs) to reduce voltage drop. In this technology, the power rails are buried within the silicon substrate and connected to the FETs via vias to provide signals.

[0004] However, the process of embedding power rails is relatively complex, and the manufacturing process can easily lead to a decrease in the yield of semiconductor structures. Summary of the Invention

[0005] The technical problem solved by the present invention is to improve the yield of semiconductor bulk devices by providing a semiconductor structure and a method for forming the same.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure formation method, comprising: providing a substrate; the substrate including a first region for forming semiconductor fins and a second region located between the first regions; forming a plurality of semiconductor fins located on the substrate in the first region; forming an isolation layer covering the plurality of semiconductor fins, the isolation layer forming an isolation trench between the semiconductor fins in the second region; filling the isolation trench with a dielectric layer; removing a portion of the dielectric layer in the isolation trench and the isolation layer and a portion of the substrate located below the dielectric layer to form an interconnect trench; forming a bottom connection line located at the bottom of the interconnect trench; forming a pseudo-vertical connection line located above the bottom connection line in the interconnect trench; forming source / drain doped layers on the semiconductor fins on both sides of the pseudo-vertical connection line; forming a gate structure spanning the plurality of semiconductor fins; removing the pseudo-vertical connection line; and filling the interconnect trench with a conductive material to form an interconnect conductive layer located on the bottom connection line.

[0007] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate; the substrate including a first region for forming semiconductor fins and a second region located between the first regions; a plurality of semiconductor fins located in the first region of the substrate; a gate structure spanning the semiconductor fins in the first region; source and drain doped layers on the semiconductor fins on both sides of the gate structure; an isolation layer covering the plurality of semiconductor fins, the surface of the isolation layer being lower than the top surface of the semiconductor fins; an interconnect trench located in the second region of the substrate, the interconnect trench being surrounded by the isolation layer; the bottom of the interconnect trench being located within the substrate; a bottom connection line located at the bottom of the interconnect trench; and an interconnect conductive layer located within the interconnect trench and connected to the bottom connection line of the interconnect trench.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure formation method of this invention, firstly, the isolation trench is surrounded by an isolation layer and filled with a dielectric layer. In the step of removing part of the dielectric layer in the isolation trench, the isolation layer below the dielectric layer, and part of the substrate to form an interconnect trench, the dielectric layer can protect the isolation layer at the interconnect trench, reducing the probability of semiconductor fins being damaged due to the destruction of the isolation layer, thereby improving the semiconductor device fabrication yield. Secondly, if the interconnect trench is formed before the source / drain doped layer is formed, the process of forming the interconnect trench is less likely to damage the source / drain doped layer, which also improves the semiconductor structure fabrication yield. Thirdly, a pseudo-vertical interconnect line is formed above the bottom interconnect line in the interconnect trench. The pseudo-vertical interconnect line is located between the second regions. When the source / drain doped layer is formed on the semiconductor fin in the first region, the pseudo-vertical interconnect line can act as a barrier to the source / drain doped layer, reducing the merge defect between the source / drain doped layers of adjacent first regions, which also improves the semiconductor device fabrication yield. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0011] Figures 1 to 9 This is a schematic diagram of the structure corresponding to each step in a semiconductor structure formation method;

[0012] Figures 10 to 2 6 is a schematic diagram of the structure corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] As described in the background section, existing semiconductor fabrication processes can lead to reduced semiconductor structure yield. The following section will combine... Figures 1 to 9 The semiconductor structure formation method is shown, and the reasons for the reduced semiconductor structure yield due to the fabrication process are analyzed. This semiconductor structure formation method mainly includes the following steps:

[0015] refer to Figure 1 A substrate 100 is provided, and a plurality of semiconductor fins 102 are formed on the substrate 100 by photolithography using a first mask 101.

[0016] refer to Figure 2 and Figure 3 An isolation layer 103 covering the semiconductor fin 102 and the first mask 101 is formed on the substrate 100.

[0017] The first trench 106 is formed by exposure, development and etching processes using the second mask 104 and the third mask 105.

[0018] refer to Figure 4 An isolation layer 107 is formed, covering the surface of the isolation layer 103 and the bottom and sidewalls of the first trench 106.

[0019] refer to Figure 5 Remove the insulating layer 107 located on the surface of the insulating layer 103 to form a second trench 108.

[0020] Continue to refer to Figure 5 A power track line 109 is formed at the bottom of the second trench 108.

[0021] refer to Figure 6 An isolation medium layer 110 is formed by chemical vapor deposition, which fills the second trench 108 and covers the surface of the isolation layer 103.

[0022] refer to Figure 7 A portion of the thickness of the isolation dielectric layer 110 and the isolation layer 103 is removed by a dry etching process, so that the surface of the remaining portion of the isolation dielectric layer 110 and the isolation layer 103 is lower than the top surface of the semiconductor fin 102.

[0023] Continue to refer to Figure 7The process of removing a portion of the thickness of the isolation medium layer 110 and the isolation layer 103 also includes removing the first mask 101.

[0024] refer to Figure 8 An interlayer dielectric layer 111 is formed on the isolation layer 103, and the interlayer dielectric layer 111 covers the surface of the isolation dielectric layer 110 at the second trench 108; the isolation dielectric layer 110 and the interlayer dielectric layer 111 are not distinguished at the superimposed film layer 113.

[0025] Continue to refer to Figure 8 Source and drain doped layers 112 are formed on semiconductor fin 102.

[0026] refer to Figure 9 By using processes such as exposure, development, and etching, the isolation dielectric layer 110 and the interlayer dielectric layer 111 at the superimposed film layer 113 are removed to form the third trench 114 and expose the surface of the power track line 109.

[0027] Continue to refer to Figure 9 A conductive connection layer (not shown) is formed in the third trench 114 to connect with the power track line 109; the conductive connection layer is used to connect the source / drain doped layer, the power track line and the common electrode line, etc.

[0028] In existing semiconductor structure formation methods, firstly, when etching to form the first trench 106, the distance between the first trench 106 and the semiconductor fin 102 is small, and the isolation layer 103 covering the semiconductor fin 102 at region A1 is at risk of being damaged, increasing the probability of the semiconductor fin being exposed and damaged, thereby reducing the semiconductor structure fabrication yield; secondly, the step of etching to form the third trench 114 is prone to damaging the source and drain doped layer A2 located near the third trench 114, which also reduces the semiconductor structure fabrication yield.

[0029] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure. The method includes: providing a substrate; the substrate including a first region for forming semiconductor fins and a second region located between the first regions; forming a plurality of semiconductor fins on the substrate in the first region; forming an isolation layer covering the plurality of semiconductor fins, the isolation layer forming an isolation trench between the semiconductor fins in the second region; filling the isolation trench with a dielectric layer; removing a portion of the dielectric layer in the isolation trench and the isolation layer and a portion of the substrate located below the dielectric layer to form an interconnect trench; forming a bottom connection line at the bottom of the interconnect trench; forming a pseudo-vertical connection line above the bottom connection line in the interconnect trench; forming source / drain doped layers on the semiconductor fins on both sides of the pseudo-vertical connection line; forming a gate structure spanning the plurality of semiconductor fins; removing the pseudo-vertical connection line; and filling the interconnect trench with a conductive material to form an interconnect conductive layer on the bottom connection line.

[0030] In the semiconductor structure formation method of this invention, firstly, the isolation trench is surrounded by an isolation layer and filled with a dielectric layer. In the step of removing part of the dielectric layer in the isolation trench, the isolation layer below the dielectric layer, and part of the substrate to form an interconnect trench, the dielectric layer can protect the isolation layer at the interconnect trench, reducing the probability of semiconductor fins being damaged due to the destruction of the isolation layer, thereby improving the semiconductor device manufacturing yield. Secondly, since the interconnect trench is formed before the source / drain doping layer is formed, the process of forming the interconnect trench is less likely to damage the source / drain doping layer, which also improves the semiconductor structure manufacturing yield. Thirdly, a pseudo-vertical interconnect line is formed above the bottom interconnect line in the interconnect trench. The pseudo-vertical interconnect line is located between the second regions. When the source / drain doping layer is formed on the semiconductor fin in the first region, the pseudo-vertical interconnect line can act as a barrier to the source / drain doping layer, reducing the merge defect between the source / drain doping layers of adjacent first regions, which also improves the semiconductor device manufacturing yield.

[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] refer to Figures 10 to 2 6 is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention. Wherein, Figure 19c It is along Figure 19b The top view captured by the dashed lines X10-X11; Figure 22b It is along Figure 22a The top view captured by the dashed lines X20-X21; Figure 23b yes Figure 23a Top view; Figure 26b yes Figure 26a Top view.

[0033] refer to Figure 10 A substrate 200 is provided; the substrate 200 includes a first region Q1 for forming semiconductor fins and a second region Q2 located between the first regions Q1.

[0034] In this embodiment, the substrate 200 is used to provide a process platform for the formation of a semiconductor structure; the substrate 200 is a silicon substrate, and the material of the substrate 200 is single-crystal silicon; in other embodiments, the material of the substrate 200 may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, and the substrate 200 may also be other types of substrates such as silicon on insulator or germanium on insulator; in other embodiments, an epitaxial layer (not shown) with the same crystal structure as the substrate 200 is formed on the surface of the substrate 200 to improve the pattern transfer quality.

[0035] In this embodiment, the first region Q1 is used to form a fin field-effect transistor; a portion of the second region Q2 is used to form a via plug (VBPR, Via contact to BPR metal) for a buried power track, wherein the VBPR includes a bottom connection line and an interconnect conductive layer located on the bottom connection line; a portion of the second region Q2 is used to form a dielectric layer isolation structure.

[0036] refer to Figure 11 Multiple semiconductor fins 201 are formed on the substrate 200 in the first region Q1, and the multiple semiconductor fins 201 are mainly used to form the channel of the semiconductor device.

[0037] In this embodiment, the semiconductor fin 201 is formed by patterning the substrate 200. The material of the semiconductor fin 201 is the same as that of the substrate 200, which is silicon; in other embodiments, the material of the semiconductor fin 201 may be different from that of the substrate 200, for example, it may be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide and indium gallium nitride.

[0038] It should be noted that, for the sake of brevity and clarity in the accompanying drawings, all embodiments of the present invention are illustrated using three first regions Q1, each first region Q1 forming two semiconductor fins 201, for a total of six semiconductor fins 201, and this is not intended to limit the present invention.

[0039] refer to Figure 12 An isolation layer 202 is formed covering the plurality of semiconductor fins 201, and the isolation layer 202 forms an isolation trench 203 between the semiconductor fins in the second region Q2; the isolation trench 203 is used to provide location space for subsequent formation of interconnect trenches.

[0040] In this embodiment, the spacing d0 between the semiconductor fins 201 in the first region Q1 is small, while the spacing d1 between the spaced semiconductor fins 201 in the second region Q2 is large. The thickness of the isolation layer 202 can be set to fill the spacing between the semiconductor fins 201 in the first region Q1, but not yet fill the second region Q2. Therefore, the way the semiconductor fins 201 are covered in the second region Q2 is conformal coverage, thereby forming an isolation trench 203 located between the semiconductor fins 201.

[0041] It should be noted that if the thickness d2 of the isolation layer 202 is too large, it will not only increase the fabrication cycle of the isolation layer 202, but also affect the conformal coverage effect of the second region Q2. If the thickness d2 of the isolation layer 202 is too small, it will easily increase the probability of the semiconductor fin 201 being exposed and damaged. In this embodiment, the thickness of the isolation layer 202 is in the range of 10 nanometers to 100 nanometers.

[0042] The material of the isolation layer 202 includes one or more of Si3N4, SiCON, SiON, SiCO, and SiCN; in this embodiment, the material of the isolation layer 202 can be SiCO.

[0043] The atomic layer deposition method has advantages such as thin and uniform film, dense structure, and good adhesion to the semiconductor fins. In this embodiment, the atomic layer deposition process is used to form an isolation layer 202 covering the multiple semiconductor fins 201.

[0044] It should be noted that by using atomic layer deposition to form the isolation layer 202, the thickness d3 of the isolation layer 202 between the edge of the isolation trench 203 and the adjacent semiconductor fin 201 can be the same or close, which can reduce the problem of electrical differences in semiconductor devices caused by the different thicknesses of the isolation layer 202 on both sides of the interconnect trench.

[0045] refer to Figure 13 A dielectric layer 204 is filled in the isolation trench 203. The dielectric layer 204 can not only form physical or electrical isolation between semiconductor fins 201, but also reduce the probability of semiconductor fins 201 being exposed and damaged due to etching of the isolation layer 202 at the interconnect trench during the interconnect trench formation process, thereby improving the semiconductor device manufacturing yield.

[0046] The material of the dielectric layer 204 is different from that of the isolation layer 202. The step of forming the interconnect trench has a large etching selectivity for the dielectric layer 204 and the isolation layer 202, thereby reducing the damage to the isolation layer 202 caused by this step.

[0047] Specifically, the dielectric layer material includes one or more of Si3N4, SiCON, SiON, SiCO, and SiCN; in this embodiment, the dielectric layer 204 can be made of Si3N4.

[0048] In this embodiment, a dielectric layer 204 is formed in the isolation trench 203 by chemical vapor deposition.

[0049] Continue to refer to Figure 13 In this embodiment, the dielectric layer 204 is not only filled in the isolation trench 203, but also formed on the surface of the isolation layer 202.

[0050] refer to Figure 14 and Figure 15 The dielectric layer 204 within the isolation trench 203, the isolation layer 202 below the dielectric layer 204, and part of the substrate are removed to form an interconnect trench 205; the interconnect trench 205 is used to provide space for the subsequent formation of bottom connection lines and interconnect conductive layers.

[0051] It should be noted that if the interconnect trench 205 is formed before the source and drain doped layers are formed, the process of forming the interconnect trench 205 is less likely to damage the source and drain doped layers, thereby improving the fabrication yield of the semiconductor structure.

[0052] In this embodiment, the specific steps for forming the interconnect trench 205 include: removing part of the dielectric layer 204 in the isolation trench 203, the isolation layer 202 located below the dielectric layer 204, and part of the substrate by etching process to form the interconnect trench 205.

[0053] Continue to refer to Figure 14 Photoresist J1 is coated on the surface of the dielectric layer 204. Through exposure and development processes, an opening K1 located at the second region Q2 of the substrate is formed on the photoresist J1, exposing the dielectric layer 204.

[0054] Continue to refer to Figure 15 The interconnect trench 205 is formed by using a dry etching process to remove the dielectric layer 204 located in the isolation trench 203 below the opening K1, the isolation layer 202 located below the dielectric layer 204, and part of the substrate.

[0055] It should be noted that during the etching of dielectric layer 204, since the materials of the isolation layer 202 forming the isolation trench 203 are different from those of dielectric layer 204, even if there is an alignment deviation between opening K1 and isolation trench 203 during exposure and development, the isolation layer 202 is not easily damaged due to the selectivity of the etching process for the dielectric layer 204 material. Therefore, a self-aligned process is used to form interconnect trench 205 during the etching process. This process reduces the risk of damage to the isolation layer 202 at the isolation trench by dry etching, thereby reducing the probability of semiconductor fins being exposed and damaged due to the damage to the isolation layer 202, and improving the yield of semiconductor device fabrication.

[0056] It should be noted that interconnect trenches are formed in part of the second region Q2; the dielectric layer filled in part of the second region Q2 is not removed, and is used to form a dielectric layer isolation structure.

[0057] refer to Figure 16 and Figure 17 A bottom connection line 206 is formed at the bottom of the interconnect trench 205; the bottom connection line 206 is used to transmit external electrical signals to the semiconductor device, for example, to transmit external electrical signals to the gate structure of the semiconductor device, so as to control the turn-on and turn-off of the semiconductor device.

[0058] The step of forming the bottom connection line 206 includes: filling the interconnect trench with a bottom connection line material layer.

[0059] In this embodiment, the material of the bottom connecting wire 206 includes tungsten or ruthenium.

[0060] The process for forming the bottom interconnect material layer includes one or more of chemical vapor deposition, physical vapor deposition, and electroplating. In this embodiment, the bottom interconnect material layer (not shown) is filled in the interconnect trench 205 by physical vapor deposition, and the bottom interconnect material layer also covers the surface of the dielectric layer 204.

[0061] Continue to refer to Figure 16 and Figure 17 The step of forming the bottom connecting line further includes: using the dielectric layer 204 as a stop layer, performing chemical mechanical polishing on the bottom connecting line material layer.

[0062] And the bottom connecting line material layer after chemical mechanical polishing is etched back to form the bottom connecting line 206.

[0063] In this embodiment, the etching back can be performed using a dry etching process.

[0064] Continue to refer to Figure 17It should be noted that if the thickness d4 of the bottom connection line 206 after the etch-back is too small, it will easily cause the resistance of the bottom connection line 206 to increase, which is not conducive to the transmission of electrical signals and increases the power consumption of the semiconductor device; if it is too large, the contact area between the bottom connection line 206 and the isolation layer 202 will increase, and the probability of the bottom connection line 206 being oxidized by oxygen atoms escaping from the isolation layer will increase accordingly; in this embodiment, the thickness of the bottom connection line 206 after the etch-back is in the range of 10 nanometers to 100 nanometers.

[0065] refer to Figures 18 to 20 A pseudo-vertical interconnect line 207 is formed in the interconnect trench 205 above the bottom interconnect line 206. The pseudo-vertical interconnect line 207 is located between the second regions Q2. When the source and drain doped layers are formed on the semiconductor fins of the first region Q1, the pseudo-vertical interconnect line can block the source and drain doped layers, reduce the fusion defects between the source and drain doped layers of adjacent first regions Q1, and thus improve the yield of semiconductor device fabrication.

[0066] The pseudo-vertical connector 207 is made of one or more of the following materials: aluminum oxide, titanium oxide, titanium carbide, and titanium nitride; in this embodiment, the pseudo-vertical connector 207 can be made of aluminum oxide.

[0067] In this embodiment, the step of forming the pseudo-vertical connector 207 includes:

[0068] Continue to refer to Figure 18 A plug material layer 208 is formed within the interconnect trench 205, located above the bottom connection line 206. The plug material layer 208 also covers the surface of the dielectric layer 204. The plug material layer 208 is used to prevent oxidation by oxygen atoms escaping from the isolation layer 202 on the surface of the bottom connection line 206 (the oxygen atoms may come from the isolation layer material itself or oxygen atom impurities in the isolation layer), thereby reducing the risk of electrical connection failure between the subsequent interconnect conductive layer and the bottom connection line and improving the reliability of the semiconductor device.

[0069] The plug material layer 208 includes one or more of Si3N4, SiCON, SiON, SiCO, and SiCN; in this embodiment, the plug material layer 208 can be Si3N4.

[0070] In this embodiment, the plug material layer 208 is formed using a chemical vapor deposition process.

[0071] Continuing to refer to Figure 19, Figure 19 includes Figure 19a , Figure 19b and Figure 19c A self-aligned process is used to remove the plug material layer 208 inside and above the interconnect trench 205, exposing the surface SF1 of the bottom connection line 206.

[0072] The specific steps for removing the plug material layer 208 inside and above the interconnect trench 205 include: coating the surface of the plug material layer 208 with photoresist (not shown), and forming an opening (not shown) at the second region Q2 of the substrate 200 on the photoresist through processes such as exposure and development.

[0073] Referring to Figure 19, the plug material layer 208 inside and above the interconnect trench 205 is removed using a dry etching process, exposing the surface SF1 of the bottom connection line 206.

[0074] It should be noted that when removing the plug material layer 208 inside and above the interconnect trench 205, since the isolation layer 202 surrounding the interconnect trench 205 is made of a different material than the plug material layer 208, even if there is an alignment deviation between the opening (not shown) during exposure and development and the interconnect trench 205, the isolation layer 202 at the interconnect trench 205 is not easily damaged due to the material selectivity of the etching process for the plug material layer 208. Therefore, a self-aligned etching process is used to remove the plug material layer 208 inside and above the interconnect trench 205 during the etching process. This process reduces the risk of damage to the isolation layer 202 at the interconnect trench by dry etching, thereby reducing the risk of semiconductor fins being exposed and damaged due to the damage to the isolation layer 202, and improving the yield of semiconductor device fabrication.

[0075] Using a chemical vapor deposition process, a pseudo-vertical connector material layer C1 is formed on the surface SF1 of the exposed bottom connector 206; the pseudo-vertical connector layer C1 also covers the surface of the plug material layer 208.

[0076] Continue to refer to Figure 20 Using the isolation layer 202 located on the semiconductor fin 201 as a stop layer, the pseudo-vertical interconnect material layer C1 is chemically and mechanically polished to form the pseudo-vertical interconnect 207 and the dielectric layer isolation structure 204a; the surface of the formed pseudo-vertical interconnect 207 is flush with the surface of the isolation layer 202 and the dielectric layer isolation structure 204a.

[0077] It should be noted that the formed dielectric layer isolation structure 204a can not only be used to physically or electrically isolate the semiconductor fins, but also to block the source and drain doped layers, reducing the fusion defects between the source and drain doped layers of adjacent first regions Q1, thereby improving the yield of semiconductor device fabrication.

[0078] refer to Figures 21 to 24 Source / drain doped layers 209 are formed on the semiconductor fins 201 on both sides of the pseudo-vertical connection line 207.

[0079] Continue to refer to Figure 21After forming the pseudo vertical connection line 207 and before forming the source / drain doped layer 209, a dry etching process is used to remove part of the thickness of the isolation layer 202 so that the surface of the isolation layer 202 is lower than the top of the semiconductor fin 201.

[0080] Continuing to refer to Figure 22, Figure 22 includes Figure 22a , Figure 22b A pseudo-gate structure 210 is formed on the semiconductor fins 201 exposed by the isolation layer 202 using a chemical vapor deposition process.

[0081] An epitaxial growth process is used to form source and drain doped layers 209 on the semiconductor fins 201 on both sides of the pseudo-gate structure 210.

[0082] Referring again to Figure 22, it should be noted that the pseudo-vertical connection line 207 is located in the interconnect trench between the second regions Q2. When the source and drain doped layers 209 are formed on the semiconductor fins 201 on both sides of the pseudo gate structure 210, the pseudo-vertical connection line 207 can block the source and drain doped layers 209, reduce the fusion defects between the source and drain doped layers 209 of the adjacent first regions Q1, and improve the yield of semiconductor device fabrication.

[0083] Continue referring to Figure 23, which includes... Figure 23a , Figure 23b Before forming the step of the semiconductor fin gate structure spanning multiple semiconductors, the method further includes: forming an interlayer dielectric layer 211 covering the source / drain doped layer 209 and the dummy gate structure 210; the interlayer dielectric layer 211 is used to isolate adjacent semiconductor devices and adjacent metal trace layers (not shown), and can also be used to support the sidewalls (not shown) of the dummy gate structure 210 during the subsequent removal of the dummy gate structure 210.

[0084] In this embodiment, an interlayer dielectric layer 211 covering the source / drain doped layer 209 and the pseudo-gate structure 210 is formed by chemical vapor deposition.

[0085] Referring again to Figure 23, a gate structure 212 is formed that spans multiple semiconductor fins 201; the gate structure 212 is used to control the turn-on and turn-off of the semiconductor device.

[0086] In this embodiment, the step of forming a gate structure 212 spanning multiple semiconductor fins 201 further includes: using a dry etching process to remove the dummy gate structure 210 and the interlayer dielectric layer 211 on the dummy gate structure 210, exposing the semiconductor fins 201.

[0087] A gate structure 212 is formed on the exposed semiconductor fin 201 using a chemical vapor deposition process.

[0088] Continue to refer to Figure 24After the step of forming the gate structure 212, the method further includes patterning the interlayer dielectric layer 211 to form an opening K2, which provides location space for the subsequent formation of the interconnect conductive layer.

[0089] In this embodiment, a portion of the interlayer dielectric layer 211 is removed by a dry etching process so that the surface of the interlayer dielectric layer 211 is lower than the top of the source / drain doped layer 209, the mass layer isolation structure 204a, and the pseudo-vertical interconnect 207.

[0090] refer to Figure 25 Remove the pseudo vertical connection line 207 to provide space for the subsequent formation of the interconnect conductive layer.

[0091] In this embodiment, after the patterned interlayer dielectric layer 211, a wet etching process is used to remove the pseudo vertical interconnects 207.

[0092] It should be noted that when removing the pseudo-vertical interconnects 207 in the interconnect trench 205, by setting the material of the pseudo-vertical interconnects 207, a gentler wet etching process can be used to remove them, which is less likely to damage the source / drain doped layers 209 and improves the semiconductor structure fabrication yield. Specifically, a wet etching process using an etching solution including deionized water (Di-water) or NH4OH is used to remove the pseudo-vertical interconnects 207.

[0093] Referring to Figure 26, Figure 26 includes Figure 26a , Figure 26b The interconnect trench 205 is filled with a conductive material (not shown), which is also formed in the opening K2; an interconnect conductive layer 213 is formed on the bottom connection line 206 and in the opening K2; the interconnect conductive layer 213 is used to transmit external electrical signals to the semiconductor device through the bottom connection line 206, for example, to transmit external electrical signals to the gate structure 212, source / drain doped layer 209 and common electrode (not shown) of the semiconductor device.

[0094] The material of the interconnect conductive layer 213 includes one or more of tungsten, ruthenium, or cobalt; in this embodiment, the material of the interconnect conductive layer 213 can be cobalt.

[0095] The process for forming the interconnect conductive layer 213 includes one or more of chemical vapor deposition, physical vapor deposition, and electroplating. In this embodiment, a conductive material is formed in the interconnect trench 205 and the opening K2 by physical vapor deposition. The conductive material is etched by wet etching to form the interconnect conductive layer 213 located on the bottom connection line 206 and in the opening K2.

[0096] To address the aforementioned technical problems, the present invention also provides a semiconductor structure; Figure 26 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0097] Referring to Figure 26, Figure 26 includes Figure 26a , Figure 26b The semiconductor structure of this embodiment includes: a substrate 200; the substrate 200 includes a first region Q1 for forming semiconductor fins and a second region Q2 located between the first regions Q1; a plurality of semiconductor fins 201 located in the first region Q1 of the substrate 200; a gate structure 212 spanning the semiconductor fins 201 in the first region Q1; source / drain doped layers 209 located on both sides of the gate structure 212 on the semiconductor fins; an isolation layer 202 covering the plurality of semiconductor fins 201, the surface of the isolation layer 202 being lower than the top surface of the semiconductor fins 201; an interconnect trench 205 located in a portion of the second region Q2 of the substrate 200, the interconnect trench 205 being surrounded by the isolation layer 202; the bottom of the interconnect trench 205 being located within the substrate 200; a bottom connection line 206 located at the bottom of the interconnect trench 205; and an interconnect conductive layer 213 located within the interconnect trench 205 and connected to the bottom connection line 206 of the interconnect trench 205.

[0098] The semiconductor structure of this invention includes: First, an isolation layer 202 covering the plurality of semiconductor fins 201, the surface of which is lower than the top surface of the semiconductor fins 201. This structure increases the contact area between the source / drain doped layers 209 and the gate structure 212 and the semiconductor fins 201, thereby improving the on-state current of the semiconductor device. Second, the bottom of the interconnect trench 205 is located within the substrate 200, and a bottom connection line 206 is located at the bottom of the interconnect trench 205. This structure reduces the contact area between the bottom connection line 206 and the isolation layer 202, reducing the risk of oxygen atoms escaping from the isolation layer oxidizing the bottom connection line 206 and causing semiconductor device failure, thus improving the reliability of the semiconductor device. Third, an interconnect conductive layer 213 located within the interconnect trench 205 and connected to the bottom connection line 206 of the interconnect trench 205 has an isolation layer 202 designed between the interconnect conductive layer 213 and the semiconductor fins 201. This reduces the probability that the interconnect conductive layer 213 will affect the electrical properties of adjacent semiconductor devices when transmitting electrical signals.

[0099] Substrate 200; the substrate 200 includes a first region Q1 for forming semiconductor fins 201 and a second region Q2 located between the first regions Q1; the substrate 200 is used to provide a process platform for forming semiconductor structures; the first region Q1 is used to provide location space for forming the semiconductor fins 201; the second region Q2 is used to provide location space for forming interconnect trenches 205, bottom connection lines 206, interconnect conductive layers 213, and dielectric isolation structures 204a.

[0100] In this embodiment, the substrate 200 is a silicon substrate, and the material of the substrate 200 is single-crystal silicon. In other embodiments, the material of the substrate 200 may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen nitride. The substrate 200 may also be other types of substrates such as silicon-on-insulator or germanium-on-insulator. In other embodiments, an epitaxial layer (not shown) with the same crystal structure as the substrate 200 is formed on the surface of the substrate 200 to improve the pattern transfer quality.

[0101] Multiple semiconductor fins 201 are located in a first region Q1 of the substrate 200; the semiconductor fins 201 are used to form channels for semiconductor devices.

[0102] A gate structure 212 spans the semiconductor fin 201 of the first region Q1; the gate structure 212 is used to control the turn-on and turn-off of the semiconductor device.

[0103] The source / drain doped layer 209 is located on the semiconductor fins 201 on both sides of the gate structure 212; the source / drain doped layer 209 is used to provide a low resistivity path in the source and drain regions of the semiconductor device to improve the current transmission efficiency.

[0104] An isolation layer 202 covers the plurality of semiconductor fins 201, and the surface of the isolation layer 202 is lower than the top surface of the semiconductor fins 201; the isolation layer 202 is used to form an interconnect trench 205; the isolation layer 202 is also used to prevent external impurities from entering the semiconductor structure through the bottom of the substrate 200 and causing semiconductor transistor failure.

[0105] The material of the isolation layer 202 includes one or more of Si3N4, SiCON, SiON, SiCO, and SiCN; in this embodiment, the material of the isolation layer 202 can be SiCO.

[0106] Interconnect trench 205 is located in the second region Q2 of substrate 200; the interconnect trench 205 is surrounded by the isolation layer 202, and the bottom of the interconnect trench 205 is located within the substrate 200; the interconnect trench 205 provides space for subsequent formation of bottom connection line 206 and interconnect conductive layer 213.

[0107] Bottom connection line 206 is located at the bottom of the interconnect trench 205; the bottom connection line 206 is used to transmit external electrical signals to the semiconductor device, for example, to transmit external electrical signals to the gate structure 212 of the semiconductor device, so as to control the turn-on and turn-off of the semiconductor device.

[0108] The material layer of the bottom connecting line 206 includes tungsten or ruthenium; in this embodiment, the material layer of the bottom connecting line 206 can be tungsten.

[0109] An interconnect conductive layer 213 is located within the interconnect trench 205 and is electrically connected to the bottom connection line 206 of the interconnect trench 205. The interconnect conductive layer 213 is also located on the isolation layer 202 and is connected to the source / drain doped layer 209. The interconnect conductive layer 213 is used to transmit external electrical signals to the semiconductor device via the bottom connection line 206, for example, to transmit external electrical signals to the gate structure 212, the source / drain doped layer 209, and the common electrode (not shown) of the semiconductor device.

[0110] The material of the interconnect conductive layer 213 includes one or more of tungsten, ruthenium, or cobalt; in this embodiment of the invention, the material of the interconnect conductive layer 213 may be cobalt.

[0111] A dielectric layer isolation structure 204a is located in a portion of the second region Q2; the dielectric layer isolation structure 204a is used to form physical or electrical isolation between semiconductor fins 201.

[0112] It should be noted that the semiconductor structure of this embodiment can be formed using the formation method of the foregoing embodiments, or it can be formed using other formation methods. For further specific descriptions of the semiconductor structure of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0113] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a base; The substrate includes a first region for forming semiconductor fins and a second region located between the first regions; Multiple semiconductor fins are formed on the substrate of the first region; An isolation layer is formed covering the plurality of semiconductor fins, the isolation layer forming an isolation trench located between the semiconductor fins in the second region; A medium layer is filled into the isolation trench; Remove part of the dielectric layer in the isolation trench, as well as the isolation layer and part of the substrate located below the dielectric layer, to form an interconnect trench; Form a bottom connection line located at the bottom of the interconnect trench; A pseudo-vertical connection line is formed above the bottom connection line within the interconnect trench; Source and drain doped layers are formed on the semiconductor fins on both sides of the pseudo-vertical interconnect. A gate structure spanning multiple semiconductor fins is formed; Remove the pseudo-vertical connector; The interconnect trench is filled with conductive material to form an interconnect conductive layer located on the bottom connection line.

2. The forming method as described in claim 1, characterized in that, The isolation layer is formed using an atomic layer deposition process.

3. The forming method as described in claim 1, characterized in that, The materials of the dielectric layer and the isolation layer are different.

4. The forming method as described in claim 1, characterized in that, The insulating layer material includes one or more of the following: Si3N4, SiCON, SiON, SiCO, and SiCN.

5. The forming method as described in claim 1, characterized in that, The dielectric layer is also formed on the surface of the isolation layer; The step of forming the interconnect trench includes: The interconnect trench is formed by removing part of the dielectric layer in the isolation trench, the isolation layer below the dielectric layer, and part of the substrate through photolithography.

6. The forming method as described in claim 1, characterized in that, The dielectric layer material includes one or more of Si3N4, SiCON, SiON, SiCO, and SiCN.

7. The forming method as described in claim 1, characterized in that, The steps for forming the bottom connecting line include: A bottom connecting wire material layer is filled into the interconnect trench; Using the dielectric layer as a stop layer, the bottom connecting wire material layer is subjected to chemical mechanical polishing; The bottom connector material layer after chemical mechanical polishing is etched back to form the bottom connector.

8. The forming method as described in claim 1, characterized in that, The bottom connecting wire is made of tungsten or ruthenium.

9. The forming method as described in claim 1, characterized in that, The steps for forming the pseudo-vertical connector include: A plug material layer is formed within the interconnect trench above the bottom connection line; Using a self-aligned process, the plug material layer inside and above the interconnect trench is removed to expose the surface of the bottom interconnect wire; A pseudo-vertical connector material layer is formed on the exposed bottom connector surface; Using the isolation layer located on the fin as a stop layer, the pseudo-vertical connector material layer is chemically and mechanically polished to form the pseudo-vertical connector.

10. The forming method as described in claim 1, characterized in that, The materials of the pseudo-vertical interconnect include one or more of the following: aluminum oxide, titanium oxide, titanium carbide, and titanium nitride.

11. The forming method as described in claim 1, characterized in that, Prior to the step of forming a multi-semiconductor fin gate structure, the method further includes: forming an interlayer dielectric layer covering the source and drain doped layers; After the gate structure formation step, the method further includes: patterning the interlayer dielectric layer to form an opening; Remove the pseudo-vertical connection lines after the graphical interlayer dielectric layer is rendered; In the step of filling the interconnect trench with conductive material, the conductive material is also formed in the opening.

12. The forming method as described in claim 1, characterized in that, The pseudo-vertical interconnects were removed using a wet etching process.

13. The forming method as described in claim 12, characterized in that, The etching solution used in the wet etching process includes deionized water or NH4OH.

14. The forming method as described in claim 1, characterized in that, The interconnect conductive layer material includes one or more of tungsten, ruthenium, or cobalt.

15. A semiconductor structure, characterized in that, include: The substrate includes a first region for forming semiconductor fins and a second region located between the first regions; Multiple semiconductor fins located in the first region of the substrate; Gate structure spanning the semiconductor fin of the first region; Source and drain doped layers are located on the semiconductor fins on both sides of the gate structure; An isolation layer is applied over the plurality of semiconductor fins, the surface of which is lower than the top surface of the semiconductor fins; An interconnect trench located in the second region of the substrate portion, the interconnect trench being surrounded by the isolation layer, the bottom of the interconnect trench being located within the substrate; The bottom connection line located at the bottom of the interconnect trench; An interconnect conductive layer located within the interconnect trench and connected to the bottom connection line of the interconnect trench.

16. The semiconductor structure as described in claim 15, characterized in that, The interconnect conductive layer is also located on the isolation layer and is connected to the source / drain doped layer.

17. The semiconductor structure as described in claim 15, characterized in that, A dielectric layer isolation structure is formed in part of the second region.

18. The semiconductor structure as described in claim 15, characterized in that, The insulating layer material includes one or more of the following: Si3N4, SiCON, SiON, SiCO, and SiCN.

19. The semiconductor structure as described in claim 15, characterized in that, The bottom connecting wire material layer includes tungsten or ruthenium.

20. The semiconductor structure as described in claim 15, characterized in that, The interconnect conductive layer material includes one or more of tungsten, ruthenium, or cobalt.

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