Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application provides a semiconductor device preparation method and a semiconductor device. The method comprises the following steps: providing a semiconductor initial structure; forming a groove in the semiconductor initial structure, wherein the groove penetrates an epitaxial layer; forming a first through hole in a first insulating layer at the bottom of the groove, wherein the first through hole is communicated with the groove, and the first through hole penetrates to a first metal layer; forming a conductive layer on a side of the groove, the first through hole and a second insulating layer away from the first metal layer, wherein the conductive layer is connected with the first metal layer through the first through hole; forming a second through hole in the conductive layer at the bottom of the groove to disconnect the conductive layer, thereby forming a first conductive structure and a second conductive structure, wherein the orthographic projection of the second through hole towards the first metal layer is located between the orthographic projection of the first through hole towards the first metal layer and the orthographic projection of a first side wall towards the first metal layer. The method can simplify the preparation process of the semiconductor device, reduce the preparation difficulty and improve the preparation efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor preparation, in particular to a semiconductor device preparation method and a semiconductor device. BACKGROUND

[0002] With the development and progress of semiconductor technology, the application scenarios of semiconductor devices are more and more extensive, and the requirements for the preparation efficiency of semiconductor devices are gradually increasing. In the existing semiconductor devices, for the semiconductor devices formed with FSI (Front Side Illumination) metal layer and BSI (Back Side Illumination) metal layer, a metal interconnection structure is usually formed in advance after the FSI metal layer is formed and before the BSI metal layer is formed, so that the metal interconnection structure can form an electrical connection with the FSI metal layer, so that the FSI metal layer and the BSI metal layer can form an electrical connection through the metal interconnection structure when the BSI metal layer is formed.

[0003] However, the existing semiconductor devices usually need to form two conductive layers, which are respectively used for grounding of the device and metal interconnection between the FSI metal layer and the BSI metal layer, thereby causing the preparation process of the semiconductor device to be complicated, the preparation difficulty to be increased, and the preparation efficiency to be reduced. SUMMARY

[0004] Therefore, the semiconductor device preparation method and the semiconductor device provided in the embodiments of the present application can simplify the preparation process of the semiconductor device, reduce the preparation difficulty, and improve the preparation efficiency.

[0005] In a first aspect, the present application provides a semiconductor device preparation method, comprising:

[0006] providing a semiconductor initial structure, wherein the semiconductor initial structure comprises a first metal layer, a first insulating layer, an epitaxial layer, a dielectric layer, and a second insulating layer, and the first metal layer, the first insulating layer, the epitaxial layer, the dielectric layer, and the second insulating layer are sequentially stacked in the thickness direction of the epitaxial layer;

[0007] forming a trench exposing part of the top surface of the first insulating layer in the semiconductor initial structure;

[0008] forming a first via in the first insulating layer at the bottom of the trench, wherein the first via is in communication with the trench, and the first via penetrates to the first metal layer;

[0009] forming a conductive layer on the side of the trench, the first via, and the second insulating layer away from the first metal layer, wherein the conductive layer is connected with the first metal layer through the first via;

[0010] forming a second via hole in the conductive layer at the bottom of the trench to break the conductive layer, to form a first conductive structure and a second conductive structure, wherein the first conductive structure comprises the conductive layer on the first sidewall surface of the trench, and the second conductive structure comprises the conductive layer in the first via hole and the conductive layer on the second sidewall surface of the trench, and a projection of the second via hole on the first metal layer is between a projection of the first via hole on the first metal layer and a projection of the first sidewall on the first metal layer.

[0011] In one of the embodiments, the projection of the trench on the first metal layer comprises a ring shape.

[0012] The projection of the second via hole on the first metal layer comprises a ring shape.

[0013] In one of the embodiments, the trench penetrates the epitaxial layer.

[0014] In one of the embodiments, before the step of forming the conductive layer on the side of the trench, the first via hole and the second insulating layer away from the first metal layer, the method further comprises:

[0015] forming a barrier layer on the side of the trench and the second insulating layer away from the first metal layer, wherein the conductive layer is formed on the side of the barrier layer away from the first metal layer.

[0016] In one of the embodiments, the method for manufacturing the semiconductor device further comprises:

[0017] forming a third insulating layer on the side of the conductive layer away from the first metal layer;

[0018] etching the third insulating layer, the first conductive structure and the barrier layer to form a grid isolated by the grid trench, wherein the grid comprises the barrier layer, the first conductive structure and the third insulating layer stacked in sequence in the direction away from the first metal layer.

[0019] In one of the embodiments, the method for manufacturing the semiconductor device further comprises:

[0020] forming a third insulating layer on the side of the conductive layer away from the first metal layer;

[0021] etching the third insulating layer on the second conductive structure to form a fourth via hole exposing part of the second conductive structure.

[0022] In one of the embodiments, the method for manufacturing the semiconductor device further comprises:

[0023] forming a fourth conductive structure in the fourth via hole, wherein the fourth conductive structure is connected to the second conductive structure.

[0024] In one of the embodiments, forming the third insulating layer on the side of the conductive layer away from the first metal layer comprises:

[0025] Forming, in the trench, a first sub-insulating structure, a second sub-insulating structure and a second insulating structure which are sequentially stacked from outside to inside; wherein the first sub-insulating structure fills the second via hole, the materials of the first sub-insulating structure and the second sub-insulating structure are different, and the materials of the second sub-insulating structure and the second insulating structure are different.

[0026] In a second aspect, the application provides a semiconductor device prepared by the method of preparing a semiconductor device according to any one of the first aspect.

[0027] In one of the embodiments, the epitaxial layer comprises a first fork structure, the dielectric layer comprises a second fork structure, the first fork structure cooperates with the second fork structure to form an electrostatic collection structure, and the electrostatic collection structure is located between the first conductive structure and the epitaxial layer.

[0028] The unexpected effects of the embodiments of the application include: by forming a trench penetrating the epitaxial layer, further forming a first via hole, forming a conductive layer on the sidewall of the trench, the first via hole and the surface of the second insulating layer, and then isolating the conductive layer through the second via hole to form two conductive structures insulated from each other, the dielectric layer between the first conductive structure and the first insulating layer can be connected through the first conductive structure, and in the process of adsorbing the electrostatic charge inside the semiconductor device by the epitaxial layer, the first conductive structure can conduct the adsorbed electrostatic charge to the epitaxial layer in contact, thereby forming the ground of the semiconductor device. At the same time, the second conductive structure covers the second sidewall surface of the trench and fills in the first via hole, and the second conductive structure can be electrically connected with the first metal layer, and in the case that the second conductive structure forms a metal layer on the side away from the second insulating layer, the newly formed metal layer can be electrically connected with the first metal layer, thereby realizing the metal interconnection across layers of the semiconductor device. Therefore, the ground and the metal interconnection of the semiconductor device can be realized by one conductive layer, thereby simplifying the preparation process of the semiconductor device, reducing the preparation difficulty and improving the preparation efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the application or the related art, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the application or the related art. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0030] Figure 1 A schematic structural diagram of a semiconductor device obtained by a preparation method of a semiconductor device according to a comparative embodiment of the application is provided.

[0031] Figure 2A schematic flowchart of a method for manufacturing a semiconductor device is provided for an embodiment of the present application.

[0032] Figure 3 A schematic structural diagram of a semiconductor initial structure obtained by a method for manufacturing a semiconductor device is provided for an embodiment of the present application.

[0033] Figure 4 A schematic structural diagram of a trench obtained by a method for manufacturing a semiconductor device is provided for an embodiment of the present application.

[0034] Figure 5 A schematic structural diagram of a first via obtained by a method for manufacturing a semiconductor device is provided for an embodiment of the present application.

[0035] Figure 6 A schematic structural diagram of a conductive layer obtained by a method for manufacturing a semiconductor device is provided for an embodiment of the present application.

[0036] Figure 7 A schematic structural diagram of a second via obtained by a method for manufacturing a semiconductor device is provided for an embodiment of the present application.

[0037] Figure 8 A schematic structural diagram of a first via obtained by another method for manufacturing a semiconductor device is provided for an embodiment of the present application.

[0038] Figure 9 A schematic top view of a structure obtained by a method for manufacturing a semiconductor device is provided for an embodiment of the present application.

[0039] Figure 10 A schematic structural diagram of a barrier layer obtained by a method for manufacturing a semiconductor device is provided for an embodiment of the present application.

[0040] Figure 11a A schematic structural diagram of a third insulating layer obtained by a method for manufacturing a semiconductor device is provided for an embodiment of the present application.

[0041] Figure 11b A schematic structural diagram of a third insulating layer including a stack obtained by a method for manufacturing a semiconductor device is provided for another embodiment of the present application.

[0042] Figure 12 A schematic structural diagram of a grid obtained by a method for manufacturing a semiconductor device is provided for an embodiment of the present application.

[0043] Figure 13 A schematic structural diagram of a fourth via obtained by a method for manufacturing a semiconductor device is provided for an embodiment of the present application.

[0044] Figure 14A schematic structural diagram of a fourth conductive structure obtained by a preparation method of a semiconductor device provided in an embodiment of the present application.

[0045] Explanation of reference signs:

[0046] 100-semiconductor initial structure, 101-first metal layer, 102-first insulating layer, 103-epitaxial layer, 104-dielectric layer, 105-second insulating layer, 106-oxide layer, 107-conductive pad, T0-conductive pillar, 200-conductive layer, 201-first conductive structure, 202-second conductive structure, 300-barrier layer, 400-third insulating layer, Gd-grid, ma-protection layer, 600-fourth conductive structure, T1-trench, T2-first via, T3-second via, T4-grid trench, T5-fourth via, J1-first insulating structure, J11-first sub-insulating structure, J12-second sub-insulating structure, J2-second insulating structure, 700-electrostatic collection structure, S1-first sidewall, S2-second sidewall, S3-trench bottom, A1-orthographic projection of the semiconductor device toward the first metal layer, A2-orthographic projection of the first conductive structure toward the first metal layer, A3-orthographic projection of the second via toward the first metal layer, A4-orthographic projection of the first via toward the first metal layer, A5-orthographic projection of the second conductive structure toward the first metal layer, A6-orthographic projection of the epitaxial layer and the dielectric layer between the second conductive structure and the first insulating layer toward the first metal layer. DETAILED DESCRIPTION

[0047] For the purpose of facilitating the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. In the drawings, embodiments of the present application are shown. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present application is more thorough and complete.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the description of the present application herein only for the purpose of describing the specific embodiments of the present application and is not intended to limit the present application.

[0049] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0050] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0051] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0052] Please refer to Figure 1 In a comparative embodiment of the semiconductor device, the conductive pad 107 is electrically connected to the first metal layer 101 fabricated by a front-side illumination (FSI) process via a conductive post T0 penetrating the first insulating layer 102. The first conductive structure 201 for connecting the grid and ground, and the conductive pad 107, are different conductive layers fabricated using different processes, resulting in complex fabrication processes, high costs, and increased complexity of the conductive layers. Furthermore, since the conductive pad 107 is embedded within the epitaxial layer 103, a trench needs to be formed first, penetrating the second insulating layer 105, the dielectric layer 104, the oxide layer 106, and the epitaxial layer 103, exposing a portion of the top surface of the first insulating layer 102. Figure 1 (Not shown), and then a conductive pad 107 embedded inside the epitaxial layer 103 is formed in the trench. Therefore, the fabrication process of the conductive pad 107 is complex, and it increases the probability of current leakage channels between the conductive pad 107 and the epitaxial layer 103, reducing the reliability of the fabricated structure.

[0053] like Figure 1 As shown, in the comparative embodiment of the semiconductor device, the first conductive structure 201 and the second conductive structure 202 used for grounding need to be formed separately. Moreover, the formation of the first conductive structure 201 and the second conductive structure 202 typically requires multiple patterning and mask fabrication processes. Therefore, the fabrication method of the semiconductor device in the comparative embodiment usually leads to an increase in the number of fabrication steps, an increase in the number of photomasks used, increased process complexity, increased fabrication difficulty, and reduced fabrication efficiency.

[0054] Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figure 2 As shown, a first aspect of this application provides a method for fabricating a semiconductor device, comprising:

[0055] Step S110: Provide an initial semiconductor structure. The initial semiconductor structure includes a first metal layer, a first insulating layer, an epitaxial layer, a dielectric layer, and a second insulating layer, wherein the first metal layer, the first insulating layer, the epitaxial layer, the dielectric layer, and the second insulating layer are stacked sequentially in the thickness direction of the epitaxial layer.

[0056] like Figure 3 As shown, the initial semiconductor structure 100 includes a first metal layer 101, a first insulating layer 102, an epitaxial layer 103, a dielectric layer 104, a second insulating layer 105, and an oxide layer 106.

[0057] For example, such as Figure 3As shown, the first metal layer 101 can be an FSI metal layer, the first insulating layer 102 can include an oxide film, a silicon nitride film, and an oxide film, the epitaxial layer 103 can include an epitaxial substrate, the dielectric layer 104 can include a high dielectric constant material film, such as hafnium dioxide, aluminum oxide, and tantalum pentoxide, etc., and the second insulating layer 105 can include an oxide layer. In the case where the semiconductor device includes a BSI metal layer, the second insulating layer 105 can be used as an oxide layer of the BSI metal layer. The dielectric layer 104 can adsorb static charges inside the semiconductor device. The oxide layer 106 can include silicon oxide.

[0058] Step S120: A trench is formed within the initial semiconductor structure to expose a portion of the top surface of the first insulating layer.

[0059] like Figure 4 As shown, the trench T1 penetrates the second insulating layer 105, the dielectric layer 104, the oxide layer 106, and the epitaxial layer 103, exposing part of the top surface of the first insulating layer 102.

[0060] For example, such as Figure 4 As shown, the second insulating layer 105 and the dielectric layer 104 can be etched sequentially using an etching process to obtain a trench T1. The shape of the trench T1 can be annular, etc. The etching depth of the trench T1 is greater than or equal to the sum of the thicknesses of the second insulating layer 105, the dielectric layer 104, the oxide layer 106, and the epitaxial layer 103, thereby allowing the conductive layer formed within the trench T1 to simultaneously contact the epitaxial layer 103 and the first insulating layer 102, thus achieving grounding of the semiconductor device.

[0061] refer to Figure 4 The first sidewall S1 and the second sidewall S2 of the trench T1 are located on opposite sides of the trench T1 in the direction perpendicular to the thickness of the epitaxial layer 103.

[0062] Step S130: A first through hole is formed in the first insulating layer at the bottom of the trench, wherein the first through hole is connected to the trench and extends through to the first metal layer.

[0063] like Figure 5 As shown, the first through hole T2 penetrates the first insulating layer 102, and the orthographic projection edge of the first through hole T2 toward the first metal layer 101 falls into the orthographic projection edge of the trench T1 toward the first metal layer 101.

[0064] In step S140, a conductive layer is formed on the side of the trench, the first through hole, and the second insulating layer away from the first metal layer, wherein the conductive layer is connected to the first metal layer through the first through hole.

[0065] like Figure 6As shown, the conductive layer 200 covers the first sidewall S1, the second sidewall S2 and the bottom S3 of the trench T1, and the conductive layer 200 can fill the first through hole T2.

[0066] For example, the conductive layer 200 may include a metallic material, such as aluminum.

[0067] Step S150: A second through hole is formed in the conductive layer at the bottom of the trench to disconnect the conductive layer and form a first conductive structure and a second conductive structure. The first conductive structure includes a conductive layer located on the surface of the first sidewall of the trench, and the second conductive structure includes a conductive layer located in the first through hole and a conductive layer located on the surface of the second sidewall of the trench. The orthographic projection of the second through hole toward the first metal layer is located between the orthographic projection of the first through hole toward the first metal layer and the orthographic projection of the first sidewall toward the first metal layer.

[0068] like Figure 7 As shown, the conductive layer includes a first conductive structure 201 and a second conductive structure 202. A second through-hole T3 is located on the surface of the bottom S3 of the trench and is connected to the trench T1. The first conductive structure 201 is used for grounding the semiconductor device, and the second conductive structure 202 is used for metal interconnection between the first metal layer 101 and other metal layers.

[0069] For example, please continue to refer to Figure 7 The second via T3 can be located at the bottom S3 of the trench T1. The minimum distance between the second via T3 and the first metal layer 101 is less than the distance between the surface of the epitaxial layer 103 near the first metal layer 101 and the first metal layer 101. When the trench T1 is annular, the second via T3 can be formed within the second conductive structure 202 located on the surface of the second insulating layer 105 to isolate the second conductive structure 202 and form a first sub-conductive structure and a second sub-conductive structure. The first sub-conductive structure is used for metal interconnection of the first metal layer 101, and the second sub-conductive structure can be used to meet other conductivity requirements.

[0070] The semiconductor device fabrication method provided in this application involves forming a trench T1 that penetrates the epitaxial layer 103 and exposes part of the top surface of the first insulating layer 102, and further forming a first via T2. After forming a conductive layer 200 on the sidewall of the trench T1, the first via T2, and the surface of the second insulating layer 105, the conductive layer 200 is isolated through the second via T3 to form two mutually insulated conductive structures. This allows the dielectric layer 104 between the first conductive structure 201 and the first insulating layer 102, and the epitaxial layer 103 to be connected through the first conductive structure 201. During the process of the epitaxial layer 103 adsorbing static charges inside the semiconductor device, the first conductive structure 201 can conduct the adsorbed static charges to the contacting epitaxial layer 103, thereby forming a grounding of the semiconductor device. Simultaneously, the second conductive structure 202 covers the surface of the second sidewall S2 of the trench T1 and fills the first through-hole T2, enabling an electrical connection between the second conductive structure 202 and the first metal layer 101. When a metal layer is formed on the side of the second conductive structure 202 away from the second insulating layer 105, the newly formed metal layer can be electrically connected to the first metal layer 101, achieving cross-layer metal interconnection in the semiconductor device. Therefore, grounding and metal interconnection of the semiconductor device can be achieved through a single conductive layer 200, thereby simplifying the semiconductor device fabrication process, reducing fabrication difficulty, and improving fabrication efficiency.

[0071] like Figure 8 As shown, in some feasible embodiments, the orthographic projection of the trench T1 toward the first metal layer 101 includes an annular shape; the orthographic projection of the second through hole T3 toward the first metal layer 101 also includes an annular shape.

[0072] like Figure 9 As shown, from a top-down view, A1 represents the orthographic projection of the semiconductor device toward the first metal layer 101, A2 represents the orthographic projection of the first conductive structure 201 toward the first metal layer 101, A3 represents the orthographic projection of the second via T3 toward the first metal layer 101, A4 represents the orthographic projection of the first via T2 toward the first metal layer 101, A5 represents the orthographic projection of the second conductive structure 202 toward the first metal layer 101, and A6 represents the orthographic projection of the epitaxial layer 103 and the dielectric layer 104 between the second conductive structure 202 and the first insulating layer 102 toward the first metal layer 101.

[0073] The semiconductor device fabrication method provided in this application embodiment can form an independent epitaxial layer 103 and dielectric layer 104 through an annular trench T1 and an annular second via T3. Furthermore, during the formation of the conductive layer 200, a second conductive structure 202 can be formed on the surface of the independent structure within the semiconductor device. This increases the surface area of ​​the second conductive structure 202, improves the metal interconnect performance of the second conductive structure 202, reduces the failure risk of the second conductive structure 202, and improves the stability and reliability of the semiconductor device.

[0074] like Figure 8 As shown, in some feasible embodiments, the trench T1 penetrates the epitaxial layer 103.

[0075] The semiconductor device fabrication method provided in this application increases the surface area of ​​the first conductive structure 201 on the surface of the first sidewall S1 by increasing the depth of the trench T1. This increases the contact area between the first conductive structure 201 and the epitaxial layer 103, enhances the electrostatic charge transport capability of the first conductive structure 201, improves the grounding effect of the semiconductor device, and further improves the reliability and stability of the semiconductor device.

[0076] like Figure 10 As shown, in some feasible embodiments, before the step of forming a conductive layer on the side of the trench T1, the first through hole T2, and the second insulating layer 105 away from the first metal layer 101, the method further includes: forming a barrier layer 300 on the side of the trench T1 and the second insulating layer 105 away from the first metal layer 101, wherein the conductive layer is formed on the side of the barrier layer 300 away from the first metal layer 101.

[0077] For example, before forming the first through hole T2, a barrier structure (not shown) can be formed on the surfaces of the first sidewall S1, the second sidewall S2, and the bottom S3 of the trench T1, as well as on the side of the second insulating layer 105 away from the first metal layer 101. The barrier structure and the first insulating layer 102 are simultaneously etched to form the barrier layer 300 and the first through hole T2.

[0078] It should be noted that the barrier layer 300 is a conductive film layer, and the barrier layer 300 has low permeability to metal atoms. The material of the barrier layer 300 may include titanium nitride.

[0079] The semiconductor device fabrication method provided in this application provides a barrier layer 300 formed between the conductive layer 200 and the epitaxial layer 103. This barrier layer 300 can block electron migration between the conductive layer 200 and the epitaxial layer 103, preventing metal atoms in the conductive layer 200 from migrating to the epitaxial layer 103 and affecting the surface morphology of the conductive layer 200. This can improve the reliability and stability of the conductive layer 200 and extend the service life of the semiconductor device.

[0080] like Figure 11a , Figure 12 As shown, in some feasible embodiments, the method for fabricating a semiconductor device further includes:

[0081] In step S210, a third insulating layer 400 is formed on the side of the conductive layer 200 away from the first metal layer 101.

[0082] For example, a third insulating layer 400 is formed on the side of the conductive layer 200 away from the first metal layer 101 and inside the second via T3. The third insulating layer 400 may include an oxide film layer and / or a nitride film layer, etc.

[0083] In step S220, the third insulating layer 400, the first conductive structure 201, and the barrier layer 300 are etched to form a grid Gd isolated by the grid trench T4.

[0084] Please refer to Figure 11b In some feasible embodiments, step S210 involves forming a third insulating layer 400 on the side of the conductive layer 200 away from the first metal layer 101, including:

[0085] In step S410, a first insulating structure J1 is formed on the side of the conductive layer 200 away from the first metal layer 101. The first insulating structure J1 includes a first sub-insulating structure J11 and a second sub-insulating structure J12. The first sub-insulating structure J11 is formed in the trench T1, and the second sub-insulating structure J12 is formed on the surface of the first sub-insulating structure J11 away from the trench T1.

[0086] For example, a first sub-insulating structure J11 may be formed on the side of the conductive layer 200 away from the first metal layer 101 and within the second via T3, wherein the first sub-insulating structure J11 includes an oxide film layer and defines a groove (not shown).

[0087] In step S420, a second sub-insulation structure J12 is formed on the surface of the first sub-insulation structure J11 away from the trench T1.

[0088] For example, an insulating material layer can be formed on the side of the first sub-insulating structure J11 away from the trench T1. Part of the insulating material layer can be removed by photolithography and etching processes to obtain a second sub-insulating structure J12, which defines a recess (not shown). The second sub-insulating structure J12 includes a nitride film layer and is formed on the surface of the recess in the first sub-insulating structure J11.

[0089] Step S430: A second insulating structure J2 is formed within the second sub-insulating structure J12, wherein the third insulating layer 400 includes a first sub-insulating structure J11, a second sub-insulating structure J12, and a second insulating structure J2 stacked sequentially from the outside to the inside.

[0090] Please continue to refer to this. Figure 11b After forming the second insulating structure J2, the first sub-insulating structure J11 on the top surface of the conductive layer 200 can be used as the etching stop layer to planarize the top surface of the third insulating layer 400, resulting in the first sub-insulating structure J11 and the second insulating structure J2 with their top surfaces flush.

[0091] For example, the second insulating structure J2 may include an oxide film layer. The third insulating layer 400 protects the conductive layer 200, preventing it from contacting the external water and oxygen environment and affecting the electrical performance of the first conductive structure 201 and the second conductive structure 202, thereby improving the reliability and stability of the semiconductor device. In the following embodiment, using... Figure 11a The example of the third insulating layer 400 as a whole film layer is used to illustrate the specific implementation principle of the embodiments of this application. Those skilled in the art can undoubtedly determine that, in Figure 11a , Figure 11b Inspired by this, any changes to the number and material of the third insulating layer 400 should fall within the scope of protection of this application.

[0092] For example, such as Figure 12 As shown, the grid groove T4 may include multiple grooves, and the grid groove T4 penetrates the third insulating layer 400, the first conductive structure 201 and the barrier layer 300.

[0093] For example, please continue to refer to Figure 13 In step S230, a protective layer ma is formed on the outer surface of the grid Gd.

[0094] For example, please continue to refer to Figure 13 The grid Gd includes a barrier layer 300, a first conductive structure 201, and a third insulating layer 400 sequentially stacked along a direction away from the first metal layer 101. A protective layer ma can be formed on the outer surface of the grid Gd using a deposition process. The material of the protective layer ma can be, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or combinations thereof in the grid trench.

[0095] For example, please continue to refer to Figure 13 After the protective layer ma is formed, the third insulating layer 400 and the protective layer ma above the second insulating layer 105 between adjacent trenches T1 can be etched to obtain a fourth through hole T5 that exposes part of the second conductive structure 202. The exposed second conductive structure 202 can be used to form a conductive pad.

[0096] For example, please continue to refer to Figure 13 The semiconductor device fabrication method provided in this application embodiment protects the conductive layer 200 with a third insulating layer 400, preventing the conductive layer 200 from contacting the external water and oxygen environment and affecting the electrical performance of the first conductive structure 201 and the second conductive structure 202, thereby improving the reliability and stability of the semiconductor device. Simultaneously, the grid Gd and the first conductive structure 201 used for grounding can be formed within the same conductive layer 200, further simplifying the semiconductor device fabrication process, reducing fabrication difficulty, and improving fabrication efficiency.

[0097] For example, please continue to refer to Figure 13 The orthographic projection of the fourth through hole T5 toward the first metal layer 101 falls inside the orthographic projection edge of the epitaxial layer 103 toward the first metal layer 101.

[0098] like Figures 13-14 As shown, in some feasible embodiments, the method for fabricating a semiconductor device further includes: forming a fourth conductive structure 600 within a fourth through-hole T5, wherein the fourth conductive structure 600 is connected to the second conductive structure 202.

[0099] For example, please continue to refer to Figures 13-14 The semiconductor device fabrication method provided in this application provides that by forming a fourth conductive structure 600 in the fourth via T5, a metal layer can be directly formed on the side of the fourth conductive structure 600 away from the first metal layer 101. Through the fourth conductive structure 600 and the second conductive structure 202, cross-layer metal interconnection inside the semiconductor device is realized, so that electrical signals on different conductive film layers inside the semiconductor device can be transmitted to each other, thereby improving the reliability of the semiconductor device.

[0100] like Figure 14 As shown, in a second aspect of this application, a semiconductor device is provided, fabricated using any of the semiconductor device fabrication methods described in the first aspect above. The semiconductor device includes: a semiconductor initial structure 100, a conductive layer 200, and a barrier layer 300. The semiconductor initial structure 100 includes a first metal layer 101, a first insulating layer 102, an epitaxial layer 103, a dielectric layer 104, and a second insulating layer 105. The conductive layer 200 includes a first conductive structure 201 and a second conductive structure 202.

[0101] like Figure 14As shown, the semiconductor device provided in this application embodiment forms a trench T1 that extends through the epitaxial layer 103, and further forms a first via T2. After forming a conductive layer 200 on the sidewall of the trench T1, the first via T2, and the surface of the second insulating layer 105, the conductive layer 200 is isolated by the second via T3 to form two mutually insulated conductive structures. This allows the dielectric layer 104 and the epitaxial layer 103 between the first conductive structure 201 and the first insulating layer 102 to be connected through the first conductive structure 201. During the process of the epitaxial layer 103 adsorbing static charges inside the semiconductor device, the first conductive structure 201 can conduct the adsorbed static charges to the contacting epitaxial layer 103, thereby forming a grounding of the semiconductor device. Simultaneously, the second conductive structure 202 covers the surface of the second sidewall S2 of the trench T1 and fills the first through-hole T2, enabling an electrical connection between the second conductive structure 202 and the first metal layer 101. When a metal layer is formed on the side of the second conductive structure 202 away from the second insulating layer 105, the newly formed metal layer can be electrically connected to the first metal layer 101, achieving cross-layer metal interconnection in the semiconductor device. Therefore, grounding and metal interconnection of the semiconductor device can be achieved through a single conductive layer 200, thereby simplifying the semiconductor device fabrication process, reducing fabrication difficulty, and improving fabrication efficiency.

[0102] like Figure 14 As shown, in some feasible embodiments, the epitaxial layer 103 includes a first forked structure, and the dielectric layer 104 includes a second forked structure. The first forked structure and the second forked structure cooperate to obtain an electrostatic collection structure 700, which is located between the first conductive structure 201 and the epitaxial layer 103.

[0103] like Figure 14 As shown, the area indicated by the dashed box includes the electrostatic collection structure 700.

[0104] Please continue to refer to this. Figure 14 The semiconductor device provided in this application embodiment can improve the electrostatic collection capability of the dielectric layer 104 through the electrostatic collection structure 700, thereby improving the grounding effect of the semiconductor device and improving the reliability and stability of the semiconductor device.

[0105] Please continue to refer to this. Figures 2-14The unexpected effects that can be produced by the embodiments of this application include: by forming a trench T1 that penetrates to the epitaxial layer 103, a first through hole T2 is further formed. After forming a conductive layer 200 on the sidewall of the trench T1, the first through hole T2 and the surface of the second insulating layer 105, the conductive layer 200 is isolated through the second through hole T3 to form two mutually insulated conductive structures. This allows the dielectric layer 104 and the epitaxial layer 103 between the first conductive structure 201 and the first insulating layer 102 to be connected through the first conductive structure 201. During the process of the epitaxial layer 103 adsorbing the static charge inside the semiconductor device, the first conductive structure 201 can conduct the adsorbed static charge to the contacting epitaxial layer 103, thereby forming the grounding of the semiconductor device. Simultaneously, the second conductive structure 202 covers the surface of the second sidewall S2 of the trench T1 and fills the first through-hole T2, enabling an electrical connection between the second conductive structure 202 and the first metal layer 101. When a metal layer is formed on the side of the second conductive structure 202 away from the second insulating layer 105, the newly formed metal layer can be electrically connected to the first metal layer 101, achieving cross-layer metal interconnection in the semiconductor device. Therefore, grounding and metal interconnection of the semiconductor device can be achieved through a single conductive layer 200, thereby simplifying the semiconductor device fabrication process, reducing fabrication difficulty, and improving fabrication efficiency.

[0106] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0107] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor initial structure is provided, wherein the semiconductor initial structure includes a first metal layer, a first insulating layer, an epitaxial layer, a dielectric layer and a second insulating layer, wherein the first metal layer, the first insulating layer, the epitaxial layer, the dielectric layer and the second insulating layer are sequentially stacked in the thickness direction of the epitaxial layer; A trench is formed within the initial semiconductor structure to expose a portion of the top surface of the first insulating layer; the trench's orthogonal projection toward the first metal layer includes an annular shape; A first through hole is formed in the first insulating layer at the bottom of the trench, wherein the first through hole is connected to the trench and extends through the first metal layer; A conductive layer is formed on the side of the trench, the first through hole, and the second insulating layer away from the first metal layer, wherein the conductive layer is connected to the first metal layer through the first through hole; An annular second through-hole is formed within the conductive layer at the bottom of the annular trench to disconnect the conductive layer, forming a first conductive structure electrically connected to the epitaxial layer for grounding and a second conductive structure disconnected from the first conductive structure. The first conductive structure includes the conductive layer located on the surface of the first sidewall of the trench, and the second conductive structure includes the conductive layer located within the first through-hole and the conductive layer located on the surface of the second sidewall of the trench. The orthographic projection of the second through-hole toward the first metal layer is located between the orthographic projection of the first through-hole toward the first metal layer and the orthographic projection of the first sidewall toward the first metal layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The orthographic projection of the second through-hole toward the first metal layer includes an annular shape.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The trench penetrates the epitaxial layer.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, Prior to the step of forming a conductive layer on the side of the trench, the first through-hole, and the second insulating layer away from the first metal layer, the method further includes: A barrier layer is formed on the side of the trench and the second insulating layer away from the first metal layer, wherein the conductive layer is formed on the side of the barrier layer away from the first metal layer.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, Also includes: A third insulating layer is formed on the side of the conductive layer away from the first metal layer; The third insulating layer, the first conductive structure, and the barrier layer are etched to form a grid isolated by grid trenches. The grid includes a barrier layer, a first conductive structure, and a third insulating layer stacked sequentially in a direction away from the first metal layer.

6. The method for fabricating a semiconductor device according to claim 4, characterized in that, Also includes: A third insulating layer is formed on the side of the conductive layer away from the first metal layer; The third insulating layer on the second conductive structure is etched to form a fourth via that exposes a portion of the second conductive structure.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, Also includes: A fourth conductive structure is formed within the fourth through hole, wherein the fourth conductive structure is connected to the second conductive structure.

8. The method for fabricating a semiconductor device according to claim 5 or 6, characterized in that, The formation of a third insulating layer on the side of the conductive layer away from the first metal layer includes: A first sub-insulating structure, a second sub-insulating structure, and a second insulating structure are formed in the trench, stacked sequentially from the outside to the inside; wherein the first sub-insulating structure fills the second through hole; the first sub-insulating structure and the second sub-insulating structure are made of different materials, and the second sub-insulating structure and the second insulating structure are made of different materials.

9. A semiconductor device, characterized in that, It is prepared by the method of preparing a semiconductor device as described in any one of claims 1 to 8.

10. The semiconductor device according to claim 9, characterized in that, The epitaxial layer includes a first forked structure, and the dielectric layer includes a second forked structure. The first forked structure and the second forked structure cooperate to obtain an electrostatic collection structure, which is located between the first conductive structure and the epitaxial layer.

Images