Fan-out wafer level packaging unit
By forming grooves on the dielectric layer and filling them with metal paste to form conductive lines, the problems of high cost of conductive lines and poor bare die connection in the prior art are solved, realizing low-cost, environmentally friendly, thin and small packaging units, improving electrical connection efficiency and product diversification.
Patent Information
- Application Number
- CN202410626921.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-20
- Publication Date
- 2025-11-21
AI Technical Summary
In existing fan-out wafer-level packaging technologies, the manufacturing cost of conductive lines is high and not environmentally friendly. In multi-chip packaging, there is a lack of effective electrical connection between bare dies, which limits product functionality and market applications.
The process involves forming grooves on the dielectric layer and filling them with metal paste to create conductive lines. The bare dies are then connected by wire bonding, and openings are made on the outer sheath to form pads, thus achieving electrical connections between the bare dies. This simplifies the manufacturing process and reduces costs.
This achieves low-cost and environmentally friendly manufacturing processes for conductive lines, improves the thinness and compactness of packaging units and electrical connection efficiency, and enhances the diversified applications and market competitiveness of products.
Smart Images
Figure CN120998885A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a packaging unit, in particular to a fan-out wafer level packaging unit. BACKGROUND
[0002] A packaging technology with light, thin, short and high efficiency and high reliability is a development trend of the semiconductor industry, and the fan-out wafer level packaging (FOWLP) is an existing packaging technology.
[0003] In the advanced FOWLP, the redistribution layer (RDL) is the most critical, because the redistribution layer (RDL) can make the multiple pads on the die have XY plane electrical extension and interconnection effect to form multiple pads around the die, so as to effectively improve the design space and reliability of the redistribution layer (RDL), but how to make the redistribution layer (RDL) have XY plane electrical extension and interconnection effect while also maintaining or achieving a certain degree of light, thin, short and small effect, the redistribution layer (RDL) is the most critical. However, the redistribution layer (RDL) in the existing FOWLP packaging technology is formed by electroplating or electroplating, so that the material cost and manufacturing cost are relatively high, and the process in the existing technology does not meet or is not conducive to the requirements of environmental protection.
[0004] In addition, when the FOWLP provides products with higher performance or more functions, at least two or more dies are generally arranged in the FOWLP, and the redistribution layer (RDL) is used to integrate the fan-out wafer level packaging unit in the form of a multi-chip, at this time the design space of the redistribution layer (RDL) in the FOWLP will be relatively increased, and the manufacturing technology of the redistribution layer (RDL) is relatively more critical.
[0005] Furthermore, in the existing fan-out wafer level packaging unit in the form of a multi-chip, the at least two or more dies arranged inside lack effective electrical connection between each other, so that the existing product has the disadvantage of limited use function, which is not conducive to the diversified market demand in the future. SUMMARY
[0006] The main purpose of the present application is to provide a fan-out wafer level packaging unit, which comprises a carrier plate, at least two dies, a first dielectric layer, a second dielectric layer, a plurality of via lines, at least two first solder pads, at least one first wire and an outer protective layer; wherein each die is electrically connected to each other through each first wire; wherein each via line is formed by metal paste filled in each first recess of the first dielectric layer and each second recess of the second dielectric layer, and a second solder pad is formed in each opening of the outer protective layer; wherein each die can be externally electrically connected by each second solder pad located around the chip area on the second surface of each die, effectively solving the problem of high manufacturing cost and environmental pollution in the existing fan-out packaging technology when manufacturing each via line.
[0007] To achieve the above object, the present application provides a fan-out wafer level packaging unit, which comprises a carrier plate, at least two dies, a first dielectric layer, a second dielectric layer, a plurality of conductive lines, at least two first pads, at least one first wire and an outer protective layer; wherein each of the dies is cut from the same wafer or different wafers, each of the dies is parallel and spaced side by side on the carrier plate, each of the dies has a first surface and an opposite second surface, the first surface of each of the dies is fixed on the carrier plate, the second surface of each of the dies has a plurality of die pads, and the vertical chip region of the second surface is defined as a chip region; wherein the first dielectric layer is arranged on the carrier plate and the second surface of each of the dies, the first dielectric layer has a plurality of first grooves extending horizontally, wherein each of the die pads of each of the dies is exposed outside by the plurality of first grooves; wherein the second dielectric layer is arranged on the first dielectric layer, the second dielectric layer has a plurality of second grooves extending horizontally, and the plurality of second grooves are communicated with the plurality of first grooves; wherein each of the conductive lines is composed of a metal paste filled in the plurality of first grooves and the plurality of second grooves, and each of the conductive lines is electrically connected with each of the die pads of each of the dies; wherein each of the first pads is formed on two corresponding conductive lines in each of the dies; wherein each of the first wires is formed by a wire bonding operation to form a first pad and a second pad on each of the first pads in each of the dies, so that each of the dies can be electrically connected by each of the first wires; wherein the outer protective layer is arranged on the second dielectric layer and covers each of the first pads and each of the first wires, the outer protective layer has a plurality of openings, and at least two of the openings are located around the chip region on the second surface of each of the dies, wherein each of the conductive lines can be exposed outside through each of the openings, wherein each of the conductive lines forms a second pad in each of the openings for external exposure, and wherein each of the dies can be externally electrically connected in sequence through the die pad, the conductive line and the second pad located around the chip region on the second surface of the die, thereby forming the fan-out wafer level packaging unit; wherein each of the dies in the fan-out wafer level packaging unit is electrically connected to each other by each of the first wires; and a manufacturing method of the fan-out wafer level packaging unit comprises the following steps: step S1: providing a carrier plate; step S2: arranging a plurality of dies cut from the same wafer or different wafers parallel and spaced side by side on the carrier plate, wherein each of the dies has a first surface and an opposite second surface, the first surface of each of the dies is arranged on the carrier plate, the second surface of each of the dies has a plurality of die pads, and the vertical chip region of the second surface is defined as a chip region.Step S3: a first dielectric layer is disposed on the carrier and the second surface of each of the dies; Step S4: a plurality of first grooves are horizontally formed on the first dielectric layer, and each of the die pads of each of the dies is exposed outside by the plurality of first grooves; Step S5: a second dielectric layer is disposed on the first dielectric layer; Step S6: a plurality of second grooves are horizontally formed on the second dielectric layer, and the plurality of second grooves are in communication with the plurality of first grooves; Step S7: a metal paste is filled in the plurality of first grooves and the plurality of second grooves, and the thickness of the metal paste is higher than the surface of the second dielectric layer; Step S8: the metal paste higher than the surface of the second dielectric layer is ground, so that the surface of the metal paste is flush with the surface of the second dielectric layer to form a plurality of conductive lines; Step S9: a first solder pad is formed on each of the conductive lines in each of the dies, and each of the first solder pads is disposed on each of the conductive lines in a corresponding manner; Step S10: a wire bonding operation is performed, so that at least one first wire forms a first solder joint and a second solder joint on each of the first solder pads in each of the dies through each of the first wires; wherein each of the dies is electrically connected through each of the first wires; Step S11: an outer protective layer is disposed on the second dielectric layer, and the outer protective layer covers each of the first solder pads and each of the first wires; Step S12: a plurality of openings are formed in the outer protective layer, and at least one of the openings is formed around the chip region on the second surface of each of the dies, so that each of the conductive lines is exposed outside through each of the openings to form a second solder pad in each of the openings; and Step S13: a separation operation is performed, and a package having at least two of the dies is separated as a unit to form a plurality of fan-out wafer level packaging units.
[0008] In a preferred embodiment of the present application, each of the dies can be electrically connected to the first solder pads of other dies in sequence through the die pad, the conductive line, and the first wire on the first solder pad around the chip region on the second surface of the die.
[0009] In a preferred embodiment of the present application, each of the dies is separated from the same or different wafer.
[0010] In a preferred embodiment of the present application, the horizontal height of each of the second surfaces of each of the dies on the carrier is the same.
[0011] In a preferred embodiment of the present application, the carrier includes a silicon (Si) carrier, a glass carrier, or a ceramic carrier.
[0012] In a preferred embodiment of the present application, the metal paste includes a silver paste, a nano-silver paste, a copper paste, or a nano-copper paste.
[0013] In a preferred embodiment of the present application, the first surface of each of the dies is further disposed on the carrier substrate by a die attach film (DAF).
[0014] In a preferred embodiment of the present application, each of the openings is further provided with a solder ball, and each of the solder balls is electrically connected to each of the second pads in each of the openings.
[0015] In a preferred embodiment of the present application, the fan-out wafer level package unit is electrically connected to an electronic component by each of the solder balls. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 is a side view cross-sectional schematic diagram of the fan-out wafer level package unit of the present application disposed on a printed circuit board.
[0017] Figure 2 is a side view cross-sectional schematic diagram of a die of the present application disposed on a carrier substrate.
[0018] Figure 3 is a side view cross-sectional schematic diagram of a first dielectric layer of the present application disposed on a carrier substrate and a second surface of a die.
[0019] Figure 4 is a side view cross-sectional schematic diagram of a second dielectric layer of the present application disposed on a first dielectric layer.
[0020] Figure 5 is a side view cross-sectional schematic diagram of a first recess and a second recess of the present application filled with a metal paste.
[0021] Figure 6 is Figure 5 is a side view cross-sectional schematic diagram of the metal paste above the surface of the second dielectric layer being polished.
[0022] Figure 7 is a side view cross-sectional schematic diagram of the present application being wire bonded.
[0023] Figure 8 is a side view cross-sectional schematic diagram of the present application of an outer protective layer forming a plurality of openings.
[0024] Figure 9 is a side view cross-sectional schematic diagram of the fan-out wafer level package unit of the present application.
[0025] Figure 10 is a side view cross-sectional schematic diagram of another embodiment of the fan-out wafer level package unit of the present application.
[0026] Explanation of reference numerals in the attached figures: 1-Fan-out wafer-level packaging unit; 1a-Chip area; 10-Carrier board; 20-Bare die; 20a-First bare die; 20b-Second bare die; 21-First side; 22-Second side; 23-Die pad; 30-First dielectric layer; 31-First groove; 40-Second dielectric layer; 41-Second groove; 50-Conductive line; 50a-Metal paste; 51-Second solder pad; 60-First solder pad; 70-First bonding wire; 71-First solder joint; 72-Second solder joint; 80-Outer sheath; 81-Opening; 90-Chip bonding film; 100-Solder ball; 2-Electronic component. Detailed Implementation
[0027] The structure and technical features of the present invention are described in detail below with reference to the illustrations. The illustrations are only used to illustrate the structural relationships and related functions of the present invention. Therefore, the dimensions of the components in the illustrations are not drawn to actual scale and are not intended to limit the present invention.
[0028] refer to Figure 8 The present invention provides a fan-out wafer-level packaging unit 1, which includes a carrier 10, at least two dies 20, a first dielectric layer 30, a second dielectric layer 40, multiple conductive lines 50, at least two first bonding pads 60, at least one first bonding wire 70 and an outer sheath 80.
[0029] The carrier 10 may be a silicon (Si) carrier, a glass carrier, or a ceramic carrier, but is not limited thereto. Figure 2 As shown.
[0030] Each bare die 20 is cleaved from the same wafer or different wafers. The bare dies 20 are arranged parallel and spaced apart on the carrier substrate 10. Each bare die 20 has a first surface 21 and an opposing second surface 22. The first surface 21 of each bare die 20 is fixedly disposed on the carrier substrate 10. The second surface 22 of each bare die 20 has multiple die pads 23, and the vertical chip region of the second surface 22 defines a chip region 1a. Figure 2 As shown. In Figure 2 The example of each bare die 20 having a crystal pad 23 is given with two crystal pads 23, but it is not intended to limit the present invention.
[0031] Furthermore, in order to illustrate the structural relationships and related functions of the present invention, the present invention... Figures 1 to 9 In the embodiment shown, each bare die 20 on the carrier 10 further includes a first bare die 20a and a second bare die 20b, but this is not a limitation. That is, each bare die 20 is illustrated by example with two, but it is not intended to limit the present invention.
[0032] The first dielectric layer 30 is disposed on the second surface 22 of the carrier plate 10 and the dies 20 (the first die 20a and the second die 20b), and has a plurality of first grooves 31 extending horizontally, as shown in Figure 3 Each die pad 23 of each die 20 (the first die 20a and the second die 20b) is exposed outside by each first groove 31, as shown in Figure 3 .
[0033] The second dielectric layer 40 is disposed on the first dielectric layer 30, and has a plurality of second grooves 41 extending horizontally, each second groove 41 being in communication with each first groove 31, as shown in Figure 4 .
[0034] Each conductive line 50 is composed of a metal paste 50a filled in each first groove 31 and each second groove 32, and is electrically connected to each die pad 23 of each die 20 (the first die 20a and the second die 20b), as shown in Figure 6 . The metal paste 50a includes silver paste, nano-silver paste, copper paste or nano-copper paste, but is not limited thereto. The nano-silver paste material has the characteristics of low cost, high conductivity and low-temperature sintering, but since the nano-silver paste material is a common material, further description is omitted.
[0035] Each first solder pad 60 is formed on each conductive line 50 in each die 20 (the first die 20a and the second die 20b) by two corresponding processes, as shown in Figure 7 . Each first solder pad 60 further bears the positive pressure generated during wire bonding or soldering, so that the internal lines (such as each conductive line 50) can be arranged below each first solder pad 60.
[0036] Each first wire 70 is formed on each first solder pad 60 in each die 20 (the first die 20a and the second die 20b) by a wire bonding process to form a first solder joint 71 and a second solder joint 72, so that each die 20 (the first die 20a and the second die 20b) can be electrically connected through each first wire 70, as shown in Figure 7 .
[0037] In addition, in order to illustrate the structural relationship and related functions of the present application, in the embodiment shown in Figure 1 , the solder joint on the first die 20a is the first solder joint 71, but is not limited thereto, and the solder joint on the second die 20b is the second solder joint 72, but is not limited thereto. Each first wire 70 is described by taking one wire as an example, but is not intended to limit the present application.
[0038] The outer protective layer 80 is disposed on the second dielectric layer 40 and covers the first bonding pads 60 and the first bonding wires 70. The outer protective layer 80 has a plurality of openings 81, and at least two of the openings 81 are located around the chip region 1a on the second surface 22 of each die 20 (the first die 20a and the second die 20b), as shown in Figure 8 The via lines 50 can be exposed outside through the openings 81, as shown in Figure 8 The via lines 50 are exposed outside through the openings 81, and a second bonding pad 51 is formed in each opening 81, as shown in Figure 8 The dies 20 (the first die 20a and the second die 20b) can be sequentially electrically connected outside through the pads 23, the via lines 50, and the second bonding pads 51 located around the chip region 1a on the second surface 22 of each die 20 (the first die 20a and the second die 20b), thereby forming the fan-out wafer level package unit 1, as shown in Figure 8 .
[0039] The dies 20 (the first die 20a and the second die 20b) in the fan-out wafer level package unit 1 are electrically connected to each other through the first bonding wires 70, as shown in Figure 8 .
[0040] The manufacturing method of the fan-out wafer level package unit 1 includes the following steps:
[0041] Step S1: providing a carrier plate 10, as shown in Figure 2 .
[0042] Step S2: parallelly and spacedly arranging a plurality of dies 20 cut from the same wafer or different wafers on the carrier plate 10, as shown in Figure 2 The dies 20 have a first surface 21 and an opposite second surface 22. The first surface 21 of each die 20 is disposed on the carrier plate 10. The second surface 22 of each die 20 has a plurality of pads 23, and the vertical chip region of the second surface 22 is defined as a chip region 1a, as shown in Figure 2 .
[0043] Step S3: laying a first dielectric layer 30 on the carrier plate 10 and the second surface 22 of each die 20, as shown in Figure 3 .
[0044] Step S4: horizontally extending a plurality of first grooves 31 on the first dielectric layer 30, and exposing each pad 23 of each die 20 outside through each first groove 31, as shown in Figure 3 .
[0045] Step S5: A second dielectric layer 40 is disposed on the first dielectric layer 30, as shown. Figure 4
[0046] Step S6: A plurality of second grooves 41 are formed horizontally on the second dielectric layer 40, and each of the second grooves 41 is in communication with each of the first grooves 31, as shown. Figure 4
[0047] Step S7: A metal paste 50a is filled in each of the first grooves 31 and each of the second grooves 41, and the thickness of the metal paste 50a is higher than the surface of the second dielectric layer 40, as shown. Figure 5
[0048] Step S8: The metal paste 50a higher than the surface of the second dielectric layer 40 is ground, so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form a plurality of conductive lines 50, as shown. Figure 6
[0049] Step S9: A first solder pad 60 is formed on each of the conductive lines 50 in each of the dies 20, and each of the first solder pads 60 is disposed on each of the conductive lines 50 in a corresponding manner, as shown. Figure 7
[0050] Step S10: A wire bonding operation is performed, so that at least one first wire 70 forms a first bonding point 71 and a second bonding point 72 on each of the first solder pads 60 in each of the dies 20, as shown; wherein each of the dies 20 is electrically connected through each of the first wires 70, as shown. Figure 7 Figure 7
[0051] Step S11: An outer protective layer 80 is disposed on the second dielectric layer 40, and the outer protective layer 80 covers each of the first solder pads 60 and each of the first wires 70, as shown. Figure 8
[0052] Step S12: A plurality of openings 81 are formed in the outer protective layer 80, and at least one of the openings 81 is formed around the chip region 1a on the second surface 22 of each of the dies 20, so that each of the conductive lines 50 is exposed outside through each of the openings 81 to form a second solder pad 51 in each of the openings, as shown. Figure 8
[0053] Step S13: A singulation operation is performed, and a package having at least two of the dies 20 is singulated to form a plurality of fan-out wafer level packaging units 1, as shown. Figure 8
[0054] The processes of steps S3 to S9 and S12 in the manufacturing method of the fan-out wafer level package unit 1 can be regarded as key steps for making the redistribution layer (RDL) of the fan-out wafer level package unit 1. In step S4, a plurality of first grooves 31 are formed horizontally on the first dielectric layer 30. In step S6, a plurality of second grooves 41 are formed horizontally on the second dielectric layer 40. In step S7, a metal paste 50a is filled into each of the first grooves 31 and the second grooves 41. In step S8, the metal paste 50a is polished to be flush with the surface of the second dielectric layer 40, thereby forming a plurality of conductive lines 50. Since steps S4 to S8 are easy to implement precisely, the processes are simplified. The conductive lines 50 in the redistribution layer can be extended and interconnected in the XY plane, and the fan-out wafer level package unit 1 can still be made to be light, thin, and short, and the fan-out wafer level package unit 1 with at least two dies 20 can still be made to be light, thin, and short.
[0055] Referring to Figure 10 , each die 20 can be electrically connected to other dies 20 through the die pads 23, the conductive lines 50, and the first wire bonds 70 on the first pads 60. However, the first die 20a can be electrically connected to the second die 20b through the first wire bonds 70, for example.
[0056] Referring to Figure 2 , when the dies 20 are cut from the same wafer, the dies 20 can be dies with the same specifications, performance, or functions. However, the dies 20 can not be dies with the same specifications, performance, or functions.
[0057] Referring to Figure 2 , when the dies 20 are cut from different wafers, the dies 20 can be dies with different specifications, performance, or functions. For example, the first die 20a in Figure 2 may have a smaller size than the second die 20b.
[0058] Referring to Figure 2The horizontal height of each second surface 22 between each die 20 on the carrier plate 10 is the same, but not limited, so that the first recess 31 of the first dielectric layer 30 and the second recess 41 of the second dielectric layer 40 formed by the RDL technology can be flatly extended, which helps to keep the structure on each die 20 better and increase the reliability of the product.
[0059] Reference Figure 2 The first surface 21 of each die 20 is further provided on the carrier plate by a die attach film (DAF) 90, but not limited.
[0060] Reference Figure 9 Each opening 81 is further provided with a solder ball 100, but not limited, which can be electrically connected with each second pad 51 in each opening 81; wherein the fan-out wafer level package unit 1 can be electrically connected to an electronic element 2 by the solder ball 100, but not limited, as shown in Figure 1 ; wherein the electronic element 2 is a printed circuit board (PCB), but not limited, as shown in Figure 1 .
[0061] The fan-out wafer level package unit 1 of the present application has the following advantages compared with the existing fan-out wafer level package unit:
[0062] (1) The steps S3 to S9 and S12 in the manufacturing method of the fan-out wafer level package unit 1 of the present application are compared with the related manufacturing technology of the existing fan-out wafer level package unit. The present application makes the interconnection of each interconnection line in RDL in the state of XY plane electrical extension and interconnection, while also maintaining or achieving a certain degree of thinness, which is a simple and easy to implement step, especially beneficial to reducing the thickness of the package unit. Therefore, the process of the present application is not only simplified to save cost, but also can effectively improve the use efficiency and reliability of the fan-out wafer level package unit 1.
[0063] (2) The forming method of each interconnection line 50 is to fill the metal paste 50a into each first recess 31 and each second recess 41, and the thickness of the metal paste 50a is higher than the surface of the second dielectric layer 40, as shown in Figure 5 , and then the metal paste 50a higher than the surface of the second dielectric layer 40 is ground, so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40 to form each interconnection line 50, as shown in Figure 6Therefore, the present application can effectively solve the problem of high manufacturing cost and environmental pollution in the prior art fan-out packaging technology.
[0064] (3) Each bare die 20 can be electrically connected to the outside in sequence through the die pad 23, the RDL-formed interconnection 50, and the first solder pad 60 on the periphery of the chip region 1a on the second surface 22 of the bare die 20, that is, the interconnection in the RDL can extend and interact in the XY plane, and at the same time, the fan-out wafer level packaging unit of the multi-chip type can be kept or achieved to a certain extent of the integration effect of lightness, thinness, and smallness, so as to provide a product with higher performance (for example, each bare die 20 is a bare die with the same specification, performance, or desired function) or more functions (for example, each bare die 20 is a bare die with different specifications, performance, or desired functions), and increase the market competitiveness of the product.
[0065] (4) Each bare die 20 can be electrically connected to the first solder pad 60 of other bare dies 20 in sequence through the die pad 23, the interconnection 50, and the first solder wire 70 on the first solder pad 60 on the periphery of the chip region 1a on the second surface 22 of the bare die 20, but not limited to, for example, the first bare die 20a can be electrically connected to the second bare die 20b through the first solder wire 70, effectively solving the problem of lack of effective electrical connection between the bare dies in the prior art fan-out wafer level packaging unit of the multi-chip type, increasing the diversified application of the product, and being beneficial to increasing the market competitiveness of the product.
[0066] The above is only the preferred embodiment of the present application, which is only illustrative but not limiting to the present application; those skilled in the art understand that many changes, modifications, and even equivalent changes can be made to the present application within the spirit and scope defined by the claims of the present application, but all will fall within the protection scope of the present application.
Claims
1. A fan-out wafer level package unit, characterized by, Comprising: a carrier plate; at least two dies, each of the dies being separated from the same wafer or different wafers, each of the dies being parallel and spaced apart on the carrier plate, each of the dies having a first surface and an opposite second surface, the first surface of each of the dies being fixed on the carrier plate, the second surface of each of the dies having a plurality of die pads, and a vertical chip region of the second surface being defined as a chip region; a first dielectric layer disposed on the carrier plate and the second surface of each of the dies, the first dielectric layer having a plurality of first grooves horizontally extending formed thereon; wherein each of the die pads of each of the dies is exposed outside by the plurality of the first grooves; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer having a plurality of second grooves horizontally extending formed thereon, the plurality of the second grooves being communicated with the plurality of the first grooves; a plurality of conductive lines, each of the conductive lines being composed of a metal paste filled in the plurality of the first grooves and the plurality of the second grooves, each of the conductive lines being electrically connected with each of the die pads of each of the dies; at least two first pads, each of the first pads being formed on two corresponding conductive lines in each of the dies; at least one first wire, each of the first wires being formed by a wire bonding operation to form a first pad and a second pad on each of the first pads in each of the dies, respectively, so that each of the dies can be electrically connected by each of the first wires; and an outer protective layer disposed on the second dielectric layer and covering each of the first pads and each of the first wires, the outer protective layer having a plurality of openings and at least two of the openings being located around the chip region on the second surface of each of the dies; wherein each of the conductive lines can be exposed outside by each of the openings; wherein each of the conductive lines forms a second pad in each of the openings for being exposed outside by each of the openings; wherein each of the dies can be electrically connected outside in sequence through the die pad, the conductive line, and the second pad located around the chip region on the second surface of the die, thereby forming the fan-out wafer level package unit; wherein each of the dies in the fan-out wafer level package unit is electrically connected to each other by each of the first wires; wherein a manufacturing method of the fan-out wafer level package unit comprises the following steps: Step S1: providing a carrier plate; Step S2: parallel and spaced apart arranging a plurality of dies separated from the same wafer or different wafers on the carrier plate; wherein each of the dies has a first surface and an opposite second surface, the first surface of each of the dies is disposed on the carrier plate, the second surface of each of the dies has a plurality of die pads, and a vertical chip region of the second surface is defined as a chip region; Step S3: laying a first dielectric layer on the carrier plate and the second surface of each of the dies; Step S4: horizontally extending forming a plurality of first grooves on the first dielectric layer, and enabling each of the die pads of each of the dies to be exposed outside by the plurality of the first grooves; Step S5: laying a second dielectric layer on the first dielectric layer; Step S6: forming a plurality of second grooves horizontally on the second dielectric layer, and making the plurality of second grooves communicate with the plurality of first grooves; Step S7: filling a metal paste into the plurality of first grooves and the plurality of second grooves, and making the thickness of the metal paste higher than the surface of the second dielectric layer; Step S8: grinding the metal paste higher than the surface of the second dielectric layer to make the surface of the metal paste flush with the surface of the second dielectric layer to form a plurality of conductive lines; Step S9: forming a first solder pad on each of the conductive lines in each of the dies, respectively, and each of the first solder pads is disposed on each of the conductive lines in a corresponding manner; Step S10: performing a wire bonding operation to form a first solder joint and a second solder joint on each of the first solder pads in each of the dies by at least one first wire, respectively; wherein each of the dies is electrically connected by each of the first wires; Step S11: disposing an outer protective layer on the second dielectric layer, and making the outer protective layer cover each of the first solder pads and each of the first wires; Step S12: forming a plurality of openings in the outer protective layer, and making at least one of the openings formed around the chip region on the second surface of each of the dies, so that each of the conductive lines can be exposed outside through each of the openings to form a second solder pad in each of the openings; and Step S13: performing a singulation operation to singulate a plurality of fan-out wafer level packaging units with at least two of the dies as a unit.
2. The fan-out wafer level package unit of claim 1, wherein, Each of the dies can be electrically connected to the first solder pads of other dies in sequence through the die pad, the conductive line, and the first wire on the first solder pad around the chip region on the second surface of the die.
3. The fan-out wafer level packaging unit of claim 1, wherein, Each of the dies is singulated from the same or different wafer.
4. The fan-out wafer level packaging unit of claim 1, wherein, The horizontal height of each of the second surfaces between each of the dies on the carrier plate is the same.
5. The fan-out wafer level packaging unit of claim 1, wherein, The carrier plate includes a silicon carrier plate, a glass carrier plate, or a ceramic carrier plate.
6. The fan-out wafer level packaging unit of claim 1, wherein, The metal paste includes a silver paste, a nano-silver paste, a copper paste, or a nano-copper paste.
7. The fan-out wafer level package unit of claim 1, wherein, The first surface of each of the dies is disposed on the carrier plate by a chip bonding film.
8. The fan-out wafer level package unit of claim 1, wherein, Each of the openings is further provided with a tin ball, and each of the tin balls can be electrically connected to each of the second solder pads in each of the openings.
9. The fan-out wafer level packaging unit of claim 8, wherein, The fan-out wafer level packaging unit is electrically connected to an electronic element by each of the tin balls.