Packaging structure, packaging method and electronic equipment

Abstract

The invention discloses a packaging structure, a packaging method and electronic equipment, and the packaging structure comprises a first packaging body which comprises a first substrate and a first chip which are electrically connected, and the first chip is located on the first surface of the first substrate; the second packaging body is stacked on the first packaging body, and the second packaging body and the first chip are located on the same side of the first substrate; the second packaging body comprises a second substrate and a second chip which are electrically connected, the second chip is located on the second surface of the second substrate, and the second surface faces the first surface; the heat conduction structure penetrates through the second substrate at the side part of the second chip; the heat dissipation cover is located on the second face and covers the second chip, the heat dissipation cover comprises a side cover and a top cover which are connected, the top cover is in heat conduction connection with the second chip and the first chip, and the side cover is in heat conduction connection with the heat conduction structure. According to the packaging structure, the heat conduction path formed by the heat dissipation cover and the heat conduction structure can be obtained, heat generated by the second chip and the first chip can be dissipated through the heat dissipation cover and the heat conduction structure, and therefore the heat dissipation performance of the packaging structure is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor packaging, and in particular, to a packaging structure, a packaging method and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, semiconductor packaging tends to develop in the direction of high density, multi-function, low power consumption and miniaturization. Therefore, it is necessary to integrate chips with different functions in a single packaging structure, and to integrate more chips in a limited space.

[0003] At the same time, the performance of chips is continuously improved with the development of technology, and the power consumption and heat of chips are correspondingly continuously increased. If the chip cannot be cooled in time when it is working, the problem of chip failure due to high temperature is prone to occur.

[0004] Therefore, how to improve the heat dissipation performance of the packaging structure in the case of integrating more chips in the packaging structure has become a problem to be solved. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a packaging structure, a packaging method and an electronic device to improve the heat dissipation performance of the packaging structure.

[0006] To solve the above problem, an embodiment of the present application provides a packaging structure, comprising: a first packaging body comprising a first substrate and a first chip, the first chip being located on a first surface of the first substrate and electrically connected to the first substrate; a second packaging body stacked on the first packaging body, the second packaging body and the first chip being located on the same side of the first substrate; the second packaging body comprising: a second substrate; a second chip located on a second surface of the second substrate and electrically connected to the second substrate, the second surface facing the first surface; a heat conduction structure penetrating the second substrate on the side of the second chip; a heat dissipation cover located on the second surface of the second substrate and covering the second chip, the heat dissipation cover comprising a side cover located on the side of the second chip and a top cover connected to the side cover, the top cover being in thermal connection with the second chip and the first chip, and the side cover being in thermal connection with the heat conduction structure.

[0007] Correspondingly, an embodiment of the present application also provides an electronic device comprising the packaging structure provided by any embodiment of the present application.

[0008] Correspondingly, the embodiment of the present application also provides a packaging method, comprising: disposing a first chip on a first surface of a first substrate, the first chip being electrically connected to the first substrate; obtaining a second substrate provided with a heat conduction structure, the heat conduction structure being located at a side of a chip mounting area of the second substrate and penetrating through the second substrate, the chip mounting area being used for disposing a second chip; disposing the second chip on a second surface of the second substrate, the second chip being located in the chip mounting area and being electrically connected to the second substrate; disposing a heat dissipation cover covering the second chip on the second surface of the second substrate, the heat dissipation cover comprising a side cover located at a side of the second chip and a top cover connected to the side cover, the top cover being in heat conduction connection with the second chip, and the side cover being in heat conduction connection with the heat conduction structure; oppositely disposing the first surface and the second surface, and disposing the top cover on the first chip, so as to stack the second substrate and the first substrate, and the top cover is in heat conduction connection with the first chip.

[0009] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0010] In the packaging structure provided by the embodiment of the present application, the second packaging body is stacked on the first packaging body, the first packaging body comprises a first chip located on a first substrate, the second packaging body comprises a second chip and a heat dissipation cover located on a second substrate, the second substrate is provided with a heat conduction structure located at a side of the second chip, the heat dissipation cover covers the second chip, the top cover of the heat dissipation cover is in heat conduction connection with the second chip and the first chip, and the side cover of the heat dissipation cover is in heat conduction connection with the heat conduction structure. Therefore, the packaging structure can obtain a heat conduction path composed of the heat dissipation cover and the heat conduction structure, and the heat generated by the second chip and the first chip can be dissipated through the heat dissipation cover and the heat conduction structure, thereby improving the heat dissipation performance of the packaging structure.

[0011] In the packaging method provided by the embodiment of the present application, the first chip is disposed on the first surface of the first substrate, the second chip located in the chip mounting area and the heat dissipation cover covering the second chip are disposed on the second surface of the second substrate, the top cover of the heat dissipation cover is in heat conduction connection with the second chip, the side cover of the heat dissipation cover is in heat conduction connection with the heat conduction structure, the second substrate is provided with the heat conduction structure located at a side of the chip mounting area and penetrating through the second substrate, then the first surface and the second surface are oppositely disposed, and the top cover is disposed on the first chip, so as to stack the second substrate and the first substrate, and the top cover is in heat conduction connection with the first chip. Therefore, through the packaging method, the packaging structure can obtain a heat conduction path composed of the heat dissipation cover and the heat conduction structure, and the heat generated by the second chip and the first chip can be dissipated through the heat dissipation cover and the heat conduction structure, thereby improving the heat dissipation performance of the packaging structure.

[0012] The electronic device provided by the embodiment of the present application comprises the packaging structure provided by the embodiment of the present application, and the packaging structure has good heat dissipation performance, so that the working performance of the electronic device comprising the packaging structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a structural schematic diagram of a packaging structure;

[0014] Figure 2 is a structural schematic diagram of another packaging structure;

[0015] Figure 3 is a structural schematic diagram of an embodiment of the packaging structure of the present application;

[0016] Figure 4 is a flow chart of a packaging method of an embodiment of the present application; Figure 3 is a plan view of an embodiment of the second substrate, the second chip, the heat conduction structure and the side cover in the direction from the first substrate to the second substrate;

[0017] Figure 5 is a structural schematic diagram of another embodiment of the packaging structure of the present application;

[0018] Figure 6 is a structural schematic diagram of still another embodiment of the packaging structure of the present application;

[0019] Figure 7 is a flow chart of a packaging method of an embodiment of the present application;

[0020] Figures 8 to 20 is a schematic diagram of each step in the packaging method of an embodiment of the present application;

[0021] Figure 21 is a schematic diagram of part of the steps in the packaging method of another embodiment of the present application;

[0022] Figures 22 to 24 is a schematic diagram of part of the steps in the packaging method of still another embodiment of the present application. DETAILED DESCRIPTION

[0023] As known from the background, in the case of integrating more chips in the packaging structure, how to improve the heat dissipation performance of the packaging structure becomes a problem to be solved urgently.

[0024] Reference Figure 1 , Figure 1 is a structural schematic diagram of a packaging structure.

[0025] The packaging structure comprises: a substrate 10 comprising a first surface 10A and a second surface 10B arranged oppositely; a plurality of chips 11 located on the first surface 10A of the substrate 10; a first conductive connecting member 12 located between the chip 11 and the first surface 10A, the first conductive connecting member 12 electrically connecting the chip 11 and the substrate 10; and a second conductive connecting member 13 located on the second surface 10B of the substrate 10, the second conductive connecting member 13 electrically connecting the substrate 10.

[0026] In the field of advanced semiconductor packaging, in order to realize the interconnection of multiple flip chips, multiple flip chips are usually tiled on the surface of the substrate 10, and the flip chips are interconnected through the wiring in the substrate 10. However, when the number of chips 11 increases, the area of the substrate 10 needs to be increased, thereby increasing the packaging area, which is not conducive to the miniaturization of the packaging structure.

[0027] Therefore, in order to reduce the packaging area, another packaging structure has also been proposed. Figure 2 FIG. 2 is a structural schematic diagram of another packaging structure.

[0028] The packaging structure comprises: a substrate 20 comprising a first surface 20A and a second surface 20B arranged oppositely; a first chip 21 located on the first surface 20A of the substrate 20, the first chip 21 being provided with a conductive via structure 26 penetrating the first chip 21; a first conductive connecting member 22 located between the conductive via structure 26 and the first surface 20A, the first conductive connecting member 22 electrically connecting the conductive via structure 26 and the substrate 20; a second chip 25 vertically stacked on the first chip 21; a second conductive connecting member 24 located between the second chip 25 and the conductive via structure 26, the second conductive connecting member 24 electrically connecting the second chip 25 and the conductive via structure 26; and a third conductive connecting member 23 located on the second surface 20B of the substrate 20, the third conductive connecting member 23 electrically connecting the substrate 20.

[0029] In this packaging structure, multiple flip chips are vertically stacked on the surface of the substrate 20, and the interconnection is realized through the conductive via structure 26. The vertically stacked mode of multiple flip chips is conducive to reducing the packaging area. For example, the conductive via structure 26 can be a through silicon via (TSV) structure. However, the preparation technology of the conductive via structure 26 has a high cost, thereby increasing the packaging cost.

[0030] In order to balance the packaging area and the packaging cost, the Package On Package (POP) technology has been paid more and more attention as one of the important packaging methods for realizing high-density integration. The POP structure is conducive to obtaining higher integration, smaller packaging size, and higher signal transmission rate.

[0031] The POP structure usually includes a plurality of vertically stacked packages, for example, taking 2 packages as an example, the POP structure includes a bottom package and a top package which are stacked. However, the stacked manner of the plurality of packages can cause heat accumulation problem, thereby causing the package structure to have poor heat dissipation performance.

[0032] To solve the technical problem, the package structure provided by the embodiment of the present application includes a first package and a second package which are stacked, the first package includes a first substrate and a first chip located on a first surface of the first substrate, the first chip is electrically connected to the first substrate, the second package is located on the same side of the first chip on the first substrate, the second package includes a second substrate, the second substrate is provided with a heat conduction structure penetrating through the second substrate, the second package further includes a second chip located on a second surface of the second substrate and a heat dissipation cover, the heat dissipation cover covers the second chip, the second surface of the second substrate faces the first surface of the first substrate, the top cover of the heat dissipation cover is in thermal conduction connection with the second chip and the first chip, and the side cover of the heat dissipation cover is in thermal conduction connection with the heat conduction structure. Therefore, the package structure can obtain a heat conduction path composed of the heat dissipation cover and the heat conduction structure, the heat generated by the second chip and the first chip can be dissipated through the heat dissipation cover and the heat conduction structure, thereby improving the heat dissipation performance of the package structure.

[0033] In order to make the above-mentioned purpose, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0034] Figure 3 And Figure 4 is a schematic diagram of an embodiment of the package structure of the present application. Among them, Figure 3 is a structural schematic diagram of an embodiment of the package structure of the present application, Figure 4 is based on Figure 3 , along the direction from the first substrate to the second substrate, the plan view of an embodiment of the second substrate, the second chip, the heat conduction structure and the side cover.

[0035] Combined with reference Figure 3 and Figure 4The package structure includes: a first package 109 including a first substrate 101 and a first chip 102, the first chip 102 being located on a first surface 101A of the first substrate 101 and electrically connected to the first substrate 101; and a second package 209 stacked on the first package 109, the second package 209 being located on the same side of the first chip 102 as the first substrate 101. The second package 209 includes: a second substrate 201; a second chip 202 located on a second surface 201A of the second substrate 201 and electrically connected to the second substrate 201, the second surface 201A facing the first surface 101A; a heat conduction structure 2011 penetrating through the second substrate 201 on a side of the second chip 202; and a heat dissipation cover 208 located on the second surface 201A of the second substrate 201 and covering the second chip 202, the heat dissipation cover 208 including a side cover 2081 located on the side of the second chip 202 and a top cover 2082 connected to the side cover 2081, the top cover 2082 being in thermal conduction connection with the second chip 202 and the first chip 102, and the side cover 2081 being in thermal conduction connection with the heat conduction structure 2011.

[0036] The first substrate 101 serves as a package carrier for obtaining the first package 109, and is configured to provide support for the first chip 102 and provide an electrical connection path for the first chip 102, thereby realizing package integration and electrical integration of the first chip 102.

[0037] In some embodiments, the first substrate 101 has a first metal wiring layer (not shown in the figure) therein, thereby providing the electrical connection path.

[0038] In some embodiments, the first substrate 101 can include a package substrate, an interposer layer, or a re-distribution layer (RDL). As an example, the first substrate 101 is a package substrate.

[0039] The type of the first chip 102 is determined according to actual functional requirements or application scenarios. For example, the first chip 102 can include one or more of a radio frequency chip, a memory chip, an ASIC (Application-Specific Integrated Circuit) chip, a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip, and an FPGA (Field-Programmable Gate Array) chip. In other embodiments, the first chip can also be other chips according to actual process requirements.

[0040] In the embodiment, the first chip 102 is soldered to the first substrate 101 by a flip chip process. Accordingly, the packaging structure further comprises a third conductive connecting member 103 located between the first chip 102 and the first substrate 101, and the third conductive connecting member 103 electrically connects the first chip 102 and the first substrate 101.

[0041] By the flip chip process, efficient signal transmission can be achieved, signal delay and loss can be reduced, and thus the performance of the packaging structure can be improved.

[0042] The third conductive connecting member 103 is used as a soldering connecting member to solder the first chip 102 to the first substrate 101, and in addition, the third conductive connecting member 103 is used to achieve electrical connection between the first chip 102 and the first substrate 101.

[0043] In some embodiments, a bonding surface of the first chip 102 is formed with a first chip pad (not shown in the figure). Accordingly, the third conductive connecting member 103 connects the first chip pad of the first chip 102. Wherein, the bonding surface of the first chip 102 faces the first substrate 101.

[0044] In the embodiment, the third conductive connecting member 103 is a conductive bump. For example, the third conductive connecting member 103 can include a micro bump (μBump) or a C2 bump. Wherein, the C2 bump generally refers to a copper pillar bump (Copper Pillar Bump) with a solder cap on the top surface.

[0045] The material of the third conductive connecting member 103 includes one or more of copper, aluminum, gold, nickel, silver, palladium and tin.

[0046] As an example, the third conductive connecting member 103 is a micro bump, and the material of the third conductive connecting member 103 is tin.

[0047] In some embodiments, the packaging structure further comprises a first underfill layer 104. The first underfill layer 104 is located between the first chip 102 and the first substrate 101, and also fills the gap between the third conductive connecting members 103.

[0048] The first underfill layer 104 can reduce the influence of the mismatch of the thermal expansion coefficients between the first chip 102 and the first substrate 101, can perform stress and strain redistribution, can reduce the probability of failure of the third conductive connecting members 103, can help to improve the reliability of the soldering between the first chip 102 and the first substrate 101, and thus can help to improve the reliability of the packaging structure.

[0049] As an example, the material of the first underfill layer 104 includes epoxy. In other embodiments, the first underfill layer material can also employ other thermosetting materials.

[0050] In this embodiment, the second package 209 is located on the same side of the first substrate 101 as the first chip 102, so that the first package 109 and the second package 209 are stacked, thereby obtaining a POP structure.

[0051] In some embodiments, the first package 109 is a lower package in the POP structure, and the second package 209 is an upper package in the POP structure. In other embodiments, the first package is an upper package in the POP structure, and the second package is a lower package in the POP structure.

[0052] The second substrate 201 serves as a packaging carrier for obtaining the second package 209, and is used to provide support for the second chip 202 and provide an electrical connection path for the second chip 202, thereby realizing the packaging integration and electrical integration of the second chip 202.

[0053] In some embodiments, the second substrate 201 has a second metal wiring layer (not shown in the figure), thereby providing an electrical connection path.

[0054] In some embodiments, the second substrate 201 can include a packaging substrate, an interposer, or a redistribution layer. As an example, the second substrate 201 is a packaging substrate.

[0055] The type of the second chip 202 depends on the actual functional needs or application scenarios, for example, the second chip 202 can include one or more of a radio frequency chip, a memory chip, an ASIC chip, a CPU chip, a GPU chip, and an FPGA chip. In other embodiments, the second chip can also be other chips according to actual process requirements.

[0056] In this embodiment, the second chip 202 is soldered to the second substrate 201 by flip-chip packaging technology. Correspondingly, the packaging structure further includes a fourth conductive connecting member 203 located between the second chip 202 and the second substrate 201, and the fourth conductive connecting member 203 electrically connects the second chip 202 and the second substrate 201.

[0057] In some embodiments, the bonding surface of the second chip 202 is formed with a second chip pad (not shown in the figure). Correspondingly, the fourth conductive connecting member 203 connects the second chip pad of the second chip 202. The bonding surface of the second chip 202 faces the second substrate 201.

[0058] The fourth conductive connecting member 203 is used as a soldering connecting member to solder the second chip 202 to the second substrate 201, and is also used to realize electrical connection between the second chip 202 and the second substrate 201.

[0059] In this embodiment, the fourth conductive connecting member 203 is a conductive bump. For example, the fourth conductive connecting member 203 can include a micro bump or a C2 bump.

[0060] The material of the fourth conductive connecting member 203 includes one or more of copper, aluminum, gold, nickel, silver, palladium and tin.

[0061] As an example, the fourth conductive connecting member 203 is a micro bump, and the material of the fourth conductive connecting member 203 is tin.

[0062] In some embodiments, the packaging structure further includes a second underfill layer 204. The second underfill layer 204 is located between the second chip 202 and the second substrate 201, and also fills the gap between the fourth conductive connecting members 203.

[0063] The second underfill layer 204 can reduce the influence of the mismatch of the thermal expansion coefficients between the second chip 202 and the second substrate 201, can perform stress and strain redistribution, can reduce the probability of failure of the fourth conductive connecting members 203, can help to improve the reliability of the soldering between the second chip 202 and the second substrate 201, and thus can help to improve the reliability of the packaging structure.

[0064] As an example, the material of the second underfill layer 204 includes epoxy resin. In other embodiments, the material of the second underfill layer can also use other thermosetting materials.

[0065] In some embodiments, the second face 201A of the second substrate 201 faces the first face 101A of the first substrate 101, and the second chip 202 is located on the second face 201A of the second substrate 201, which is beneficial to improve the utilization rate of the third face 201B of the second substrate 201, and the third face 201B is arranged opposite to the second face 201A. For example, chips can be continuously stacked on the third face 201B of the second substrate 201 to improve the integration of the packaging structure; or a heat sink can be arranged on the third face 201B of the second substrate 201 to improve the heat dissipation performance of the packaging structure.

[0066] In some embodiments, the heat-conducting structure 2011 penetrates the second substrate 201 on the side of the second chip 202, so as to be able to guide the heat generated by the first chip 102 and the second chip 202 to the third face 201B of the second substrate 201, and dissipate heat through the third face 201B.

[0067] It should be noted that in some embodiments, the heat conduction structure 2011 is located at the side of the second chip 202, so as to be in heat conduction connection with the side cover 2081 of the heat dissipation cover 208.

[0068] It should also be noted that in some embodiments, the heat conduction structure 2011 is arranged away from the second metal wiring layer in the second substrate 201, so as to reduce the influence on the second metal wiring layer in the second substrate 201.

[0069] The heat conduction structure 2011 is made of a material with good heat conduction effect, so as to facilitate the rapid conduction of heat from the inside of the packaging structure to the outside. In some embodiments, the material of the heat conduction structure 2011 includes one or more of copper, aluminum, iron, tungsten, molybdenum, diamond and graphene.

[0070] As an example, the material of the heat conduction structure 2011 is a metal heat conduction material, which has high heat conduction performance.

[0071] In some embodiments, the heat conduction structure 2011 is prepared in the second substrate 201 in advance. Specifically, in the process of preparing the second substrate 201, the second metal wiring layer is often formed at the same time, so as to obtain the second substrate 201 with the second metal wiring layer. Therefore, the heat conduction structure 2011 can be formed at the same time in the process of forming the second metal wiring layer, which is beneficial to control the relative position between the heat conduction structure 2011 and other second metal wiring layers in the second substrate 201, and facilitate the heat conduction structure 2011 to avoid other second metal wiring layers. Correspondingly, in some embodiments, the heat conduction structure 2011 can be stacked by multiple metal heat conduction layers.

[0072] In other embodiments, the heat conduction structure can also be a solid heat sink structure embedded in the second substrate. This is beneficial to increase the volume of the heat conduction structure, so as to improve the heat dissipation capacity of the heat conduction structure.

[0073] The heat dissipation cover 208 covers the second chip 202, so that the top cover 2082 of the heat dissipation cover 208 is in heat conduction connection with the second chip 202 and the first chip 102, and the side cover 2081 of the heat dissipation cover 208 is located at the side of the second chip 202, so that the side cover 2081 of the heat dissipation cover 208 is in heat conduction connection with the heat conduction structure 2011. Correspondingly, the heat generated by the second chip 202 and the first chip 102 is conducted to the side cover 2081 through the top cover 2082, and then conducted to the heat conduction structure 2011 through the side cover 2081, so as to be dissipated through the heat conduction structure 2011 on the side of the second substrate 201 away from the first substrate 101.

[0074] Therefore, under the joint action of the heat dissipation cover 208 and the heat conduction structure 2011, the packaging structure can obtain a heat conduction path formed by the heat dissipation cover 208 and the heat conduction structure 2011, and the heat generated by the second chip 202 and the first chip 102 can be dissipated via the heat conduction path, thereby improving the heat dissipation performance of the packaging structure.

[0075] It should be noted that the heat generated by the first chip 102 is conducted via the top cover 2082, which is conducive to reducing the requirement for the alignment accuracy of the second chip 202 and the first chip 102.

[0076] In some embodiments, the second chip 202 and the first chip 102 are aligned up and down along the normal direction of the first surface 101A, thereby saving the overall area occupied by the second chip 202 and the first chip 102.

[0077] The material of the heat dissipation cover 208 is a heat-conducting material, so that the heat dissipation cover 208 has a good heat conduction coefficient, which is conducive to quickly conducting heat from the inside of the packaging structure to the outside. In some embodiments, the material of the heat dissipation cover 208 includes one or more of stainless steel, copper, aluminum, iron, tungsten, molybdenum, diamond, and graphene.

[0078] As an example, the material of the heat dissipation cover 208 is a metal heat-conducting material, thereby facilitating the processing and forming of the heat dissipation cover 208. For example, the heat dissipation cover 208 can be formed by a stamping process.

[0079] In some embodiments, the heat dissipation cover 208 and the heat conduction structure 2011 are separate structures, thereby reducing the difficulty of obtaining the second substrate 201 provided with the heat conduction structure 2011.

[0080] The side cover 2081 is used to fix the heat dissipation cover 208 on the second substrate 201, and the side cover 2081 is also used to conduct heat between the top cover 2082 and the heat conduction structure 2011.

[0081] In some embodiments, the packaging structure further includes a heat-conducting connection layer 2083 located between the side cover 2081 and the heat conduction structure 2011, and the heat-conducting connection layer 2083 includes a solder layer or a heat-conducting adhesive layer. The heat-conducting connection layer 2083 is used to fix the side cover 2081 on the heat conduction structure 2011, and also used to conduct heat between the side cover 2081 and the heat conduction structure 2011.

[0082] It should be noted that the appropriate heat-conducting connection layer 2083 can be selected according to the materials of the side cover 2081 and the heat conduction structure 2011.

[0083] In some embodiments, the heat dissipation cover 208 and the heat conduction structure 2011 are both made of metal heat conduction material, so that the side cover 2081 and the heat conduction structure 2011 can be combined by welding, and the heat conduction connecting layer 2083 is a solder layer. By selecting the solder layer, the bonding strength between the side cover 2081 and the heat conduction structure 2011 can be improved, and in addition, the electrical connection requirement of the heat dissipation cover 208 and the heat conduction structure 2011 can be met according to actual needs.

[0084] Reference Figure 4 In some embodiments, the side cover 2081 is an annular structure surrounding the side wall of the second core 202, and correspondingly, the side cover 2081 and the top cover 2082 form a cavity (not labeled) for accommodating the second core 202, so that the heat dissipation cover 208 can also protect the second core 202.

[0085] Continuing to refer to Figure 4 In some embodiments, the heat conduction structure 2011 is an annular structure surrounding the second chip 202 without being closed, so as to increase the heat dissipation area of the heat conduction structure 2011, thereby improving the heat dissipation efficiency of the packaging structure, and at the same time, the second metal circuit layer can be avoided to be arranged, so as to reduce the influence on the second metal circuit layer in the second substrate 201.

[0086] In this embodiment, the side cover 2081 is an annular structure surrounding the side wall of the second core 202, and the heat conduction structure 2011 is an annular structure surrounding the second chip 202 without being closed, and the side cover 2081 is aligned with the heat conduction structure 2011, so as to increase the contact area of the side cover 2081 and the heat conduction structure 2011, thereby further improving the heat dissipation efficiency.

[0087] It should be noted that in other embodiments, the number of side covers can also be multiple, and the multiple side covers are separately arranged on the side of the second chip. For example, the multiple side covers are separately arranged around the second chip.

[0088] It should be further noted that in other embodiments, the number of heat conduction structures is multiple, and the multiple heat conduction structures are separately arranged around the second chip. For example, in some other embodiments, the number of heat conduction structures and side covers is both multiple, and the side covers correspond to the heat conduction structures one by one and are heat conduction connected.

[0089] In some embodiments, in the direction parallel to the second surface 201A, the width W1 (as shown in Figure 4 of the heat conduction structure 2011 is greater than the width W2 (as shown in Figure 4As shown in the figure, this reduces the alignment accuracy requirements between the heat-conducting structure 2011 and the side cover 2081 when fixing the side cover 2081 to the heat-conducting structure 2011. Moreover, the larger width W1 of the heat-conducting structure 2011 also helps to increase the area of ​​the heat dissipation surface of the heat-conducting structure 2011 exposed on the third surface 201B.

[0090] In some embodiments, the packaging structure further includes a first thermal interface material (TIM) layer 107, located between the first chip 102 and the top cover 2082, and in contact with both the first chip 102 and the top cover 2082.

[0091] The first thermal interface material layer 107 is used to achieve a thermally conductive connection between the first chip 102 and the top cover 2082. Furthermore, the first thermal interface material layer 107 is used to fill the gap between the first chip 102 and the top cover 2082, thereby further improving the thermal conductivity between the first chip 102 and the top cover 2082. In some embodiments, the material of the first thermal interface material layer 107 is thermal grease.

[0092] In other embodiments, the packaging structure may not contain a first thermal interface material layer, and the side of the first chip facing away from the first substrate may be in direct contact with the top cover.

[0093] In some embodiments, the packaging structure further includes a second thermally conductive interface material layer 207, located between the second core 202 and the top cover 2082, and in contact with both the second core 202 and the top cover 2082.

[0094] The second thermal interface material layer 207 is used to achieve a thermally conductive connection between the second core 202 and the top cover 2082. Furthermore, the second thermal interface material layer 207 is used to fill the gap between the second core 202 and the top cover 2082, thereby further improving the thermal conductivity between the second core 202 and the top cover 2082. In some embodiments, the material of the second thermal interface material layer 207 is thermal grease.

[0095] In other embodiments, the packaging structure may also not contain a second thermal interface material layer, and the side of the second chip facing away from the second substrate and the top cover may be in direct contact.

[0096] In some embodiments, the packaging structure further includes a heat sink 206 located on the third surface 201B of the second substrate 201 and thermally connected to the thermally conductive structure 2011.

[0097] By providing a heat sink 206 on the third surface 201B of the second substrate 201, the heat dissipation effect of the packaging structure is further improved.

[0098] In some embodiments, the heat spreader 206 and the heat conducting structure 2011 are made of metal materials, and the heat spreader 206 and the heat conducting structure 2011 are eutectic bonded. Under the influence of high-temperature processing, the metal materials of the heat spreader 206 and the heat conducting structure 2011 are diffused at the interface, and accordingly, the packaging structure further comprises a eutectic layer (not shown in the figure) between the heat spreader 206 and the heat conducting structure 2011.

[0099] The heat spreader 206 and the heat conducting structure 2011 are bonded by the eutectic layer, which improves the bonding strength and the heat conduction efficiency between the heat spreader 206 and the heat conducting structure 2011.

[0100] In other embodiments, the packaging structure can also comprise a thermal adhesive layer (not shown in the figure) between the heat spreader 206 and the heat conducting structure 2011, and in contact with the heat spreader 206 and the heat conducting structure 2011. The thermal adhesive layer is used to fix the heat spreader 206 on the second substrate 201, and to realize the heat conduction between the heat spreader 206 and the heat conducting structure 2011. It should be noted that the thermal adhesive layer can also be located between the heat spreader 206 and the third surface 201B of the second substrate 201, thereby improving the stability of the heat spreader 206.

[0101] In some embodiments, the heat spreader 206 is a heat sink. Specifically, as shown in FIG. 1, the heat spreader 206 is a heat sink with heat dissipation fins, and the heat sink comprises a base (not labeled) and fins (not labeled) standing on the base. Figure 3

[0102] In other embodiments, the heat spreader can also contain a liquid cooling channel for the cooling liquid to pass through, and the liquid cooling channel comprises an inlet and an outlet to realize the circulation of the cooling liquid.

[0103] In some embodiments, the first package 109 further comprises a first conductive connecting piece 105 located on the first surface 101A of the side of the first chip 102 and electrically connected to the first substrate 101, and the second package 209 further comprises a second conductive connecting piece 205 located on the second surface 201A and on the side of the heat conducting structure 2011 away from the second chip 202, the second conductive connecting piece 205 is electrically connected to the second substrate 201, and the second conductive connecting piece 205 is connected to the first conductive connecting piece 105.

[0104] Specifically, the first conductive connecting piece 105 is electrically connected to the first metal wiring layer in the first substrate 101, and the second conductive connecting piece 205 is electrically connected to the second metal wiring layer in the second substrate 201.

[0105] ​The second conductive connecting member 205 is connected with the first conductive connecting member 105, so that the first substrate 101 and the second substrate 201 are electrically connected, and then the second chip 202 and the first substrate 101 are electrically connected.

[0106] It should be noted that the height of the second conductive connecting member 205 and the first conductive connecting member 105 is less than the distance between the first substrate 101 and the second substrate 201, so when the solder ball is used as the second conductive connecting member 205 or the first conductive connecting member 105, it is beneficial to reduce the transverse size of the solder ball, thereby reducing the probability of short circuit between adjacent solder balls, or when the conductive column is used as the second conductive connecting member 205 or the first conductive connecting member 105, it is beneficial to reduce the probability of inclination of the conductive column.

[0107] The material of the first conductive connecting member 105 includes one or more of copper, aluminum, gold, nickel, silver, palladium and tin, and the material of the second conductive connecting member 205 includes one or more of copper, aluminum, gold, nickel, silver, palladium and tin.

[0108] In some embodiments, the first conductive connecting member 105 is a conductive column, and the second conductive connecting member 205 is a solder ball. The conductive column is not prone to collapse, so it can support the solder ball, thereby improving the stability of the second conductive connecting member 205 and the first conductive connecting member 105. In addition, the second conductive connecting member 205 is selected as a solder ball, which is beneficial to ensure the connection effect between the second conductive connecting member 205 and the first conductive connecting member 105. As an example, the first conductive connecting member 105 is a copper column, and the second conductive connecting member 205 is a tin ball.

[0109] In other embodiments, the second conductive connecting member and the first conductive connecting member can also be solder balls.

[0110] In some embodiments, the first package 109 further includes a plastic encapsulation layer 106 located on the first surface 101A of the side of the first chip 102 and the first conductive connecting member 105. The plastic encapsulation layer 106 covers the side wall of the first chip 102 and the first conductive connecting member 105, and exposes the surface of the first conductive connecting member 105 away from the first substrate 101, the surface of the first chip 102 away from the first substrate 101, and the second conductive connecting member 205.

[0111] The plastic encapsulation layer 106 is used to protect the first chip 102 and the first conductive connecting member 105; the plastic encapsulation layer 106 is also used to improve the mechanical strength of the first package 109, thereby improving the stacking reliability of the second package 209 and the first package 109.

[0112] The material of the plastic sealing layer 106 is a plastic sealing material, for example, an epoxy resin. The epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical performance, and low cost. In other embodiments, other suitable packaging materials can also be selected for the plastic sealing layer.

[0113] In some embodiments, the packaging structure further includes a fifth conductive connecting member 1011 located on the fourth surface 101B of the first substrate 101 and electrically connected to the first substrate 101, the fourth surface 101B being opposite to the first surface 101A.

[0114] The first substrate 101 has a first metal circuit layer, so as to obtain the first substrate 101 with the first metal circuit layer, and the fifth conductive connecting member 1011 is electrically connected to the first metal circuit layer in the first substrate 101, so as to realize the electrical connection between the first substrate 101 and other circuits. For example, the first substrate 101 is assembled to a PCB (Printed Circuit Board) through the fifth conductive connecting member 1011.

[0115] The material of the fifth conductive connecting member 1011 includes one or more of copper, aluminum, gold, nickel, silver, palladium, and tin. In some embodiments, the fifth conductive connecting member 1011 is a solder ball. As an example, the fifth conductive connecting member 1011 is a tin ball.

[0116] Figure 5 FIG. 4 is a structural schematic diagram of another embodiment of the packaging structure of the present application.

[0117] The same as the foregoing embodiments, details are not repeated herein. The difference between the present embodiment and the foregoing embodiments is that, as shown in FIG. 4, the second substrate 401 has a ground interconnection layer 4012, the heat conduction structure 4011 and the heat dissipation cover 408 are both conductive materials, the heat conduction structure 4011 is electrically connected to the ground interconnection layer 4012, and the heat dissipation cover 408 is electrically connected to the heat conduction structure 4011. Figure 5

[0118] The heat conduction structure 4011 is electrically connected to the ground interconnection layer 4012, and the heat dissipation cover 408 is electrically connected to the heat conduction structure 4011, so that the heat dissipation cover 408 can be grounded, thereby enabling the heat dissipation cover 408 to also function as an electromagnetic shield, thereby reducing the interference between adjacent chips (for example, between the first chip 302 and the second chip 402).

[0119] ​In some embodiments, the heat dissipation cover 408 comprises a side cover 4081 located at the side of the second chip 402 and a top cover 4082 connected with the side cover 4081, and in the case that the heat dissipation cover 408 and the heat conduction structure 4011 are in a split structure, the heat conduction connection layer between the heat dissipation cover 408 and the heat conduction structure 4011 is a solder layer.

[0120] In some embodiments, the side cover 4081 is in a ring structure surrounding the side wall of the second chip 402, so as to further enhance the electromagnetic shielding effect of the heat dissipation cover 408.

[0121] For example, the side cover 4081 is in a ring structure surrounding the side wall of the second chip 402, and the heat conduction structure 4011 is in an open ring structure surrounding the second chip 402, and the side cover 4081 is aligned with the heat conduction structure 4011.

[0122] Figure 6 FIG. 7 is a structural schematic diagram of another embodiment of the packaging structure of the present application.

[0123] The same as the foregoing embodiments, which will not be repeated here. The difference between the present embodiment and the foregoing embodiments is that, as shown in FIG. 7, the number of the second chips 502 is multiple; and the heat conduction structure 5011 is also located between the adjacent second chips 502. Figure 6

[0124] The heat dissipation cover 508 comprises a side cover 5081 and a top cover 5082 connected with the side cover 5081, and correspondingly, the side cover 5081 is in heat conduction connection with each heat conduction structure 5011.

[0125] The heat conduction structure 5011 is also located between the adjacent second chips 502, and the side cover 5081 is in heat conduction connection with each heat conduction structure 5011, which is beneficial to shorten the length of the heat dissipation path of each second chip 502 and increase the number of the heat dissipation path, so as to improve the heat dissipation efficiency.

[0126] It should be noted that, in some embodiments, in the case that the side cover 5081 is in a ring structure surrounding the side wall of the second chip 502, according to the arrangement of the second chip 502, the side cover 5081 is in a grid shape.

[0127] It should be further noted that, Figure 6 The size relationship between the second chip 502 and the first chip in FIG. 6 is only for illustration.

[0128] Correspondingly, the present application also provides a packaging method. For a better understanding of the present application, reference should be made to the foregoing embodiments. Figures 7 to 20 , Figure 7 FIG. 8 is a flow chart of the packaging method of an embodiment of the present application, Figures 8 to 20 FIG. 9 is a schematic diagram of each step in the packaging method of an embodiment of the present application.

[0129] ​Reference Figure 7 And in combination with reference Figures 8 to 9 A first chip 602 is disposed on the first surface 601A of the first substrate 601, and the first chip 602 is electrically connected to the first substrate 601.

[0130] The first substrate 601 serves as a packaging carrier for obtaining a first package, and is configured to provide support for the first chip 602 and provide an electrical connection path for the first chip 602, thereby achieving packaging integration and electrical integration of the first chip 602.

[0131] In some embodiments, the first substrate 601 can include a packaging substrate, an interposer, or a redistribution layer. As an example, the first substrate 601 is a packaging substrate.

[0132] The type of the first chip 602 is determined according to actual functional needs or application scenarios. The description of the type of the first chip 602 can refer to the related content of the packaging structure, which will not be described here.

[0133] In some embodiments, the step of disposing the first chip 602 on the first surface 601A of the first substrate 601 includes: welding the first chip 602 on the first surface 601A of the first substrate 601 by flip-chip technology.

[0134] Specifically, the manner of welding the first chip 602 on the first surface 601A of the first substrate 601 by flip-chip technology includes: forming a third conductive connecting member 603 on a bonding surface (not shown) of the first chip 602, the third conductive connecting member 603 being electrically connected to the first chip 602, and the bonding surface of the first chip 602 being configured to bond with the first substrate 601; and welding the first chip 602 to the first surface 601A of the first substrate 601 by using the third conductive connecting member 603, and achieving electrical connection between the first chip 602 and the first substrate 601.

[0135] In some embodiments, the bonding surface of the first chip 602 is formed with a first chip pad (not shown). Correspondingly, the third conductive connecting member 603 is formed on the first chip pad of the first chip 602.

[0136] The third conductive connecting member 603 is configured to serve as a welding connecting member, thereby welding the first chip 602 to the first substrate 601.

[0137] In this embodiment, the third conductive connecting member 603 is a conductive bump. For example, the third conductive connecting member 603 can include a micro bump or a C2 bump.

[0138] The material of the third conductive connecting member 603 includes one or more of copper, aluminum, gold, nickel, silver, palladium, and tin.

[0139] As an example, the third conductive connectors 603 are micro-bumps, and the material of the third conductive connectors 603 is tin.

[0140] With reference to the foregoing Figure 9 After the first chip 602 is disposed on the first surface 601A of the first substrate 601, the packaging method further comprises: filling a first underfill layer 604 between the first chip 602 and the first substrate 601, and the first underfill layer 604 also fills the gaps between the third conductive connectors 603.

[0141] The first underfill layer 604 can reduce the influence of the mismatch of the coefficients of thermal expansion between the first chip 602 and the first substrate 601, can perform stress and strain redistribution, can reduce the probability of failure of the third conductive connectors 603, can help to improve the reliability of the soldering between the first chip 602 and the first substrate 601, and thus can help to improve the reliability of the packaging structure.

[0142] As an example, the material of the first underfill layer 604 comprises epoxy resin. In other embodiments, the first underfill layer material can also use other thermosetting materials.

[0143] With reference to the foregoing Figure 8 Before the top cover on the second substrate is subsequently disposed on the first chip 602, the packaging method further comprises: disposing a first conductive connector 605 on the first surface 601A of the first substrate 601, and the first conductive connector 605 is electrically connected to the first substrate 601.

[0144] Wherein, after the first chip 602 and the first conductive connector 605 are disposed on the first surface 601A of the first substrate 601, the first conductive connector 605 is located on the side of the first chip 602.

[0145] The first conductive connector 605 is used to realize the electrical connection between the first substrate 601 and the second substrate.

[0146] It should be noted that the height of the first conductive connector 605 is less than the spacing between the first substrate 601 and the second substrate, so that when a solder ball is used as the first conductive connector 605, it is beneficial to reduce the lateral size of the solder ball, thereby reducing the probability of short circuit between adjacent solder balls, or when a conductive pillar is used as the first conductive connector 605, it is beneficial to reduce the probability of inclination of the conductive pillar.

[0147] The material of the first conductive connector 605 comprises one or more of copper, aluminum, gold, nickel, silver, palladium, and tin,

[0148] In some embodiments, the first conductive connector 605 is a conductive pillar which is not prone to collapse, and is conducive to improving the stability of the second conductive connector and the first conductive connector 605. As an example, the first conductive connector 605 is a copper pillar. In other embodiments, the first conductive connector can also be a solder ball.

[0149] In some embodiments, the first conductive connector 605 can be welded on the first surface 601A of the first substrate 601.

[0150] In other embodiments, a sacrificial layer (not shown in the figure) can also be formed on the first surface 601A of the first substrate 601, and a via hole exposing the first substrate 601 is formed in the sacrificial layer, then the first conductive connector 605 is formed in the via hole, and the sacrificial layer is removed after the first conductive connector 605 is formed.

[0151] As an example, after the first conductive connector 605 is disposed on the first surface 601A of the first substrate 601, the first chip 602 is disposed on the first surface 601A of the first substrate 601, so as to reduce the influence of the process of disposing the first conductive connector 605 on the first chip 602. In other embodiments, the assembly sequence of the first chip and the first conductive connector on the first substrate can also be exchanged.

[0152] Reference Figure 10 , after the top cover on the second substrate is disposed on the first chip 602, the packaging method further comprises: after the first chip 602 and the first conductive connector 605 are disposed on the first surface 601A of the first substrate 601, a plastic encapsulation layer 606 is formed on the first surface 601A of the first substrate 601, the plastic encapsulation layer 606 covers the sidewalls of the first chip 602 and the first conductive connector 605, and exposes the surface of the first conductive connector 605 away from the first substrate 601 and the surface of the first chip 602 away from the first substrate 601.

[0153] The plastic encapsulation layer 606 is used to protect the first chip 602 and the first conductive connector 605.

[0154] After the plastic encapsulation layer 606 is formed, the first substrate 601, the first chip 602, the first conductive connector 605 and the plastic encapsulation layer 606 constitute a first package, and the plastic encapsulation layer 606 is also used to improve the mechanical strength of the first package, so as to improve the stacking reliability of the first package and the second package.

[0155] The plastic encapsulation layer 606 exposes the surface of the first chip 602 away from the first substrate 601, which is conducive to heat dissipation of the first chip 602.

[0156] The material of the plastic sealing layer 606 is a plastic sealing material, for example, an epoxy resin. The epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost. In other embodiments, other suitable packaging materials can also be selected for the plastic sealing layer.

[0157] In some embodiments, the step of forming the plastic sealing layer 606 on the first surface 601A of the first substrate 601 includes: forming a plastic sealing material layer on the first surface 601A of the first substrate 601, the plastic sealing material layer covering the first conductive connecting member 605 and the first chip 602; performing a planarization process on the plastic sealing material layer to expose the surface of the first conductive connecting member 605 on the side away from the first substrate 601 and the surface of the first chip 602 on the side away from the first substrate 601, and the remaining plastic sealing material layer serves as the plastic sealing layer 606.

[0158] Reference is made to Figure 7 in combination with reference to Figure 11 and Figure 12 , Figure 12 is Figure 11 FIG. 2 is a top view of an embodiment of the second substrate 701, the chip mounting area 702A, and the heat conduction structure 7011 in the second package 700, which is obtained by performing step S2, obtaining the second substrate 701 provided with the heat conduction structure 7011, the heat conduction structure 7011 being located on the side of the chip mounting area 702A of the second substrate 701 (as shown in FIG. 1) and penetrating through the second substrate 701, and the chip mounting area 702A being used for disposing the second chip. Figure 12

[0159] The second substrate 701 serves as a packaging carrier for obtaining the second package, is used for providing support for the second chip and providing an electrical connection path for the second chip, thereby realizing packaging integration and electrical integration of the second chip.

[0160] In some embodiments, the second substrate 701 can include a packaging substrate, an interposer, or a redistribution layer. As an example, the second substrate 701 is a packaging substrate.

[0161] In some embodiments, the heat conduction structure 7011 penetrates through the second substrate 701, so as to be able to guide the heat generated by the first chip 602 and the second chip to the third surface 701B of the second substrate 701 and dissipate the heat through the third surface 701B, the third surface 701B being disposed opposite to the second surface 701A.

[0162] It should be noted that the heat conduction structure 7011 is located on the side of the chip mounting area 702A, so that the side cover of the subsequent heat dissipation cover can be in thermal conduction connection with the heat conduction structure 7011.

[0163] ​The heat-conducting structure 7011 is made of a material with good heat-conducting effect, so as to facilitate the rapid conduction of heat from the inside of the packaging structure to the outside. In some embodiments, the material of the heat-conducting structure 7011 includes one or more of copper, aluminum, iron, tungsten, molybdenum, diamond and graphene.

[0164] As an example, the material of the heat-conducting structure 7011 is a metal heat-conducting material with high heat-conducting performance. For example, the material of the heat-conducting structure 7011 is copper.

[0165] In some embodiments, the step of obtaining the second substrate 701 provided with the heat-conducting structure 7011 includes providing the second substrate 701, and the heat-conducting structure 7011 is prepared in the second substrate 701 in advance.

[0166] Specifically, in the process of preparing the second substrate 701, a second metal circuit layer (not shown in the figure) is often formed at the same time, so as to obtain the second substrate 701 with the second metal circuit layer. Therefore, the heat-conducting structure 7011 can be formed at the same time in the process of forming the second metal circuit layer, which is beneficial to control the relative position between the heat-conducting structure 7011 and other second metal circuit layers in the second substrate 701, and facilitate the heat-conducting structure 7011 to avoid other second metal circuit layers. Correspondingly, in some embodiments, the heat-conducting structure 7011 can include multiple metal heat-conducting layers stacked, and the metal heat-conducting layers of adjacent layers are connected.

[0167] In other embodiments, the heat-conducting structure can also be a solid heat sink structure embedded in the second substrate.

[0168] As shown in Figure 12 In some embodiments, in the step of obtaining the second substrate 701 provided with the heat-conducting structure 7011, the heat-conducting structure 7011 is an open ring structure arranged around the chip mounting area 702A, so as to increase the heat dissipation area of the heat-conducting structure 7011, and further improve the heat dissipation efficiency of the packaging structure. In addition, the second metal circuit layer can be arranged to reduce the influence on the second metal circuit layer in the second substrate 701.

[0169] In other embodiments, in the step of obtaining the second substrate provided with the heat-conducting structure, the number of heat-conducting structures is multiple, and the heat-conducting structures are arranged separately on the side of the chip mounting area. For example, the heat-conducting structures can be arranged separately along the circumference of the chip mounting area.

[0170] Referring to Figure 7 and continuing to refer to Figure 11 and Figure 12 , step S3 is performed to arrange a second chip 702 on the second surface 701A of the second substrate 701, and the second chip 702 is located in the chip mounting area 702A (as shown in Figure 12The second chip 702 is electrically connected to the second substrate 701.

[0171] The type of the second chip 702 depends on actual functional requirements or application scenarios. The type of the second chip 702 can be described with reference to related content of the packaging structure, which is not described herein again.

[0172] In some embodiments, the step of disposing the second chip 702 on the second surface 701A of the second substrate 701 includes welding the second chip 702 on the first surface 701A of the second substrate 701 by a flip-chip process.

[0173] Specifically, the manner of welding the second chip 702 on the first surface 701A of the second substrate 701 by the flip-chip process includes forming a fourth conductive connecting member 703 on a bonding surface (not shown) of the second chip 702, the fourth conductive connecting member 703 being electrically connected to the second chip 702, and the bonding surface of the second chip 702 being used for bonding with the second substrate 701; and welding the second chip 702 to the second surface 701A of the second substrate 701 by the fourth conductive connecting member 703, and realizing electrical connection between the second chip 702 and the second substrate 701.

[0174] In some embodiments, the bonding surface of the second chip 702 is formed with a second chip pad (not shown). Accordingly, the fourth conductive connecting member 703 is formed on the second chip pad of the second chip 702.

[0175] The fourth conductive connecting member 703 is used as a welding connecting member to weld the second chip 702 to the second substrate 701.

[0176] In the embodiment, the fourth conductive connecting member 703 is a conductive bump. For example, the fourth conductive connecting member 703 can include a micro bump or a C2 bump.

[0177] The material of the fourth conductive connecting member 703 includes one or more of copper, aluminum, gold, nickel, silver, palladium, and tin.

[0178] As an example, the fourth conductive connecting member 703 is a micro bump, and the material of the fourth conductive connecting member 703 is tin.

[0179] It should be noted that in some embodiments, the second substrate 701 provided with the heat conduction structure 7011 is obtained, and then the second chip 702 is disposed on the second surface 701A of the second substrate 701, so as to reduce the process difficulty. In other embodiments, the second chip can also be disposed on the second surface of the second substrate, and then the heat conduction structure is disposed in the second substrate.

[0180] Continuing to refer to Figure 11After the second chip 702 is disposed on the second surface 701A of the second substrate 701, the packaging method further includes filling a second underfill layer 704 between the second chip 702 and the second substrate 701, and the second underfill layer 704 also fills the gaps between the fourth conductive connectors 703.

[0181] The second underfill layer 704 can reduce the influence of the mismatch of the coefficients of thermal expansion between the second chip 702 and the second substrate 701, can perform stress and strain redistribution, can reduce the probability of failure of the fourth conductive connectors 703, can help to improve the reliability of the soldering between the second chip 702 and the second substrate 701, and thus can help to improve the reliability of the packaging structure.

[0182] As an example, the material of the second underfill layer 704 includes epoxy resin. In other embodiments, the second underfill layer material can also use other thermosetting materials.

[0183] Reference Figure 13 The second conductive connector 705 is disposed on the second surface 701A of the second substrate 701, and the second conductive connector 705 is located on the side of the heat-conducting structure 7011 away from the chip assembly area 702A (as shown in Figure 12 The second conductive connector 705 is electrically connected to the second substrate 701.

[0184] The second conductive connector 705 is used to realize the electrical connection between the second substrate 701 and the first substrate 601.

[0185] It should be noted that the height of the second conductive connector 705 is less than the spacing between the first substrate 601 and the second substrate 701, so when the solder ball is used as the second conductive connector 705, it is beneficial to reduce the lateral size of the solder ball, thereby reducing the probability of short circuit between adjacent solder balls, or when the conductive pillar is used as the second conductive connector 705, it is beneficial to reduce the probability of inclination of the conductive pillar.

[0186] The material of the second conductive connector 705 includes one or more of copper, aluminum, gold, nickel, silver, palladium, and tin. In some embodiments, the second conductive connector 705 is a solder ball, thereby reducing the complexity of preparing the second conductive connector 705. As an example, the second conductive connector 705 is a tin ball.

[0187] It should be noted that the first conductive connector 605 is a conductive pillar, and the second conductive connector 705 is a solder ball. The conductive pillar is not prone to collapse, and thus can support the solder ball, thereby improving the stability of the second conductive connector 705 and the first conductive connector 605. Moreover, the second conductive connector 705 is selected to be a solder ball, which is beneficial to ensure the connection effect between the second conductive connector 705 and the first conductive connector 605.

[0188] Referring to Figure 14 , the subsequent step further comprises disposing a heat dissipation cover to cover the second chip 702 on the second surface 701A of the second substrate 701, and before disposing the heat dissipation cover, the packaging method further comprises: forming a second thermally conductive interface material layer 707 on the surface of the second chip 702 facing away from the second substrate 701.

[0189] The second thermally conductive interface material layer 707 is used to realize the thermally conductive connection between the second chip 702 and the top cover of the heat dissipation cover.

[0190] Specifically, the second thermally conductive interface material layer 707 is used to fill the gap between the second chip 702 and the top cover, thereby further improving the heat conduction efficiency between the second chip 702 and the top cover. In some embodiments, the material of the second thermally conductive interface material layer 707 is thermal silicone grease.

[0191] In other embodiments, the step of forming the second thermally conductive interface material layer can also be omitted, so that the surface of the second chip facing away from the second substrate and the top cover are in direct contact.

[0192] Referring to Figure 7 , in combination with referring to Figure 15 and Figure 16 , Figure 16 is based on Figure 15 , the top view of an embodiment of the second substrate 701, the second chip 702, the thermally conductive structure 7011 and the side cover 7081 in FIG. 8B, step S4 is performed to dispose a heat dissipation cover 708 to cover the second chip 702 on the second surface 701A of the second substrate 701, the heat dissipation cover 708 comprises a side cover 7081 located at the side of the second chip 702 and a top cover 7082 connected with the side cover 7081, the top cover 7082 is in thermally conductive connection with the second chip 702, and the side cover 7081 is in thermally conductive connection with the thermally conductive structure 7011.

[0193] Since the heat dissipation cover 708 covers the second chip 702, after the subsequent step of disposing the top cover 7082 on the first chip 602, the top cover 7082 of the heat dissipation cover 708 is in thermally conductive connection with both the second chip 702 and the first chip 602, and the side cover 7081 of the heat dissipation cover 708 is located at the side of the second chip 702, so that the side cover 7081 of the heat dissipation cover 708 is in thermally conductive connection with the thermally conductive structure 7011. Accordingly, the heat generated by the second chip 702 and the first chip 602 is conducted to the side cover 7081 via the top cover 7082, and then conducted to the thermally conductive structure 7011 via the side cover 7081, so as to realize heat dissipation through the thermally conductive structure 7011.

[0194] The side cover 7081 is used to realize the assembly of the heat dissipation cover 708 on the second substrate 701, and is also used to realize the heat conduction between the top cover 7082 and the thermally conductive structure 7011.

[0195] The material of the heat dissipation cover 708 is a heat conductive material, so that the heat dissipation cover 708 has a good heat conduction coefficient, which is beneficial to quickly conduct heat from the inside of the packaging structure to the outside. In some embodiments, the material of the heat dissipation cover 708 includes one or more of stainless steel, copper, aluminum, iron, tungsten, molybdenum, diamond and graphene.

[0196] As an example, the material of the heat dissipation cover 708 is a metal heat conductive material, thereby facilitating the processing and forming of the heat dissipation cover 708. For example, the heat dissipation cover 708 can be formed by a stamping process.

[0197] Specifically, in the step of arranging the heat dissipation cover 708 to cover the second chip 702 on the second surface 701A of the second substrate 701, the top cover 7082 is in contact with the second heat conductive interface material layer 707.

[0198] In some embodiments, the step of arranging the heat dissipation cover 708 to cover the second chip 702 on the second surface 701A of the second substrate 701 includes fixing the side cover 7081 on the heat conductive structure 7011 by the heat conductive connection layer 7083, and achieving heat conduction between the side cover 7081 and the heat conductive structure 7011. The heat conductive connection layer 7083 includes a solder layer or a heat conductive adhesive layer.

[0199] The heat conductive connection layer 7083 is used to achieve the assembly of the heat dissipation cover 708 on the second substrate 701, and also to achieve heat conduction between the side cover 7081 and the heat conductive structure 7011.

[0200] It should be noted that the heat dissipation cover 708 and the heat conductive structure 7011 are separate structures, thereby reducing the difficulty of obtaining the second substrate 701 provided with the heat conductive structure 7011.

[0201] It should be further noted that the appropriate heat conductive connection layer 7083 can be selected according to the materials of the side cover 7081 and the heat conductive structure 7011.

[0202] In some embodiments, the heat dissipation cover 708 and the heat conductive structure 7011 are both metal heat conductive materials, so that the step of arranging the heat dissipation cover 708 to cover the second chip 702 on the second surface 701A of the second substrate 701 includes welding the side cover 7081 of the heat dissipation cover 708 to the heat conductive structure 7011 by using a solder layer.

[0203] By selecting a solder layer, it is beneficial to improve the bonding strength between the side cover 7081 and the heat conductive structure 7011, and in addition, it is also possible to meet the electrical connection requirements of the heat dissipation cover 708 and the heat conductive structure 7011 according to actual needs.

[0204] In some embodiments, in the step of arranging the heat dissipation cover 708 to cover the second chip 702 on the second surface 701A of the second substrate 701, the side cover 7081 is an annular structure surrounding the side wall of the second chip 702.

[0205] Correspondingly, the side cover 7081 and the top cover 7082 form a cavity (not shown) to accommodate the second chip 702. Therefore, the heat sink 708 can also protect the second chip 702.

[0206] In other embodiments, there may be multiple side covers, and these side covers may be disposed separately on the sides of the second chip. For example, multiple side covers may be arranged separately around the second chip.

[0207] In this embodiment, the heat-conducting structure 7011 is arranged around the chip assembly area 702A (e.g., Figure 12 As shown, the side cover 7081 is an annular structure surrounding the side wall of the second core 702, and the side cover 7081 is aligned with the heat-conducting structure 7011, thereby increasing the contact area between the side cover 7081 and the heat-conducting structure 7011, thereby further improving the heat dissipation efficiency. At the same time, it can avoid the setting of the second metal circuit layer, thereby reducing the impact on the second metal circuit layer in the second substrate 701.

[0208] In other embodiments, there are multiple heat-conducting structures and side covers. In the step of setting a heat dissipation cover for the second chip on the second side of the second substrate, the side covers correspond one-to-one with the heat-conducting structures and are thermally connected.

[0209] like Figure 16 As shown, in some embodiments, in the direction parallel to the second surface 701A, the width W1 of the heat-conducting structure 7011 is greater than the width W2 of the side cover 7081, thereby reducing the alignment accuracy requirements between the heat-conducting structure 7011 and the side cover 7081 when fixing the side cover 7081 to the heat-conducting structure 7011. Furthermore, the larger width W1 of the heat-conducting structure 7011 also helps to increase the area of ​​the heat-dissipating surface of the heat-conducting structure 7011 exposed on the third surface 701B.

[0210] It should be noted that this embodiment uses a single second chip 702 as an example. In other embodiments, the number of second chips on the second substrate can be multiple; correspondingly, heat-conducting structures are also located between adjacent second chips, and the side covers of the heat sink are thermally connected to each heat-conducting structure.

[0211] The heat-conducting structure is also located between adjacent second chips, and the side cover is thermally connected to each heat-conducting structure, which helps to shorten the length of the heat dissipation path of each second chip and increase the number of heat dissipation paths, thereby improving heat dissipation efficiency.

[0212] It should also be noted that in some embodiments, when the side cover is an annular structure surrounding the sidewall of the second chip, the side cover may be in a grid shape depending on the arrangement of the second chip.

[0213] In addition, in some embodiments, the second substrate 701 provided with the heat conduction structure 7011, the second chip 702, the heat dissipation cover 708 and the second conductive connecting piece 705 are used to form a second package, and the top cover 7082 is subsequently arranged on the first chip 602 to realize the stacked packaging of the second package and the first package.

[0214] With reference to Figure 17 , the packaging method further comprises: forming a first heat conduction interface material layer 607 on the surface of the first chip 602 facing away from the first substrate 601 before arranging the top cover 7082 on the first chip 602.

[0215] The first heat conduction interface material layer 607 is used to realize the heat conduction connection between the first chip 602 and the top cover 7082.

[0216] The first heat conduction interface material layer 607 is used to fill the gap between the first chip 602 and the top cover 7082, thereby further improving the heat conduction efficiency between the first chip 602 and the top cover 7082. In some embodiments, the material of the first heat conduction interface material layer 607 is thermal silicone grease.

[0217] In other embodiments, the step of forming the first heat conduction interface material layer can also be omitted.

[0218] With reference to Figure 7 , and in combination with the reference Figure 18 , the step S15 is performed to arrange the first surface 601A and the second surface 701A in a relative manner, and arrange the top cover 7082 on the first chip 602 to stack the second substrate 701 and the first substrate 601, and to realize the heat conduction connection between the top cover 7082 and the first chip 602.

[0219] By arranging the top cover 7082 on the first chip 602 and realizing the heat conduction connection between the top cover 7082 and the first chip 602, the packaging structure can obtain a heat conduction path composed of the heat dissipation cover 708 and the heat conduction structure 7011, and the heat generated by the second chip 702 and the first chip 602 can be dissipated via the heat dissipation cover 708 and the heat conduction structure 7011, thereby improving the heat dissipation performance of the packaging structure.

[0220] Specifically, in the step of arranging the top cover 7082 on the first chip 602, the top cover 7082 is in contact with the first heat conduction interface material layer 607.

[0221] It should be noted that the heat generated by the first chip 602 is conducted via the top cover 7082, which is conducive to reducing the requirement for the alignment accuracy of the second chip 702 and the first chip 602. In some embodiments, the second chip 702 and the first chip 602 are aligned in an up-down manner along the normal direction of the first surface 701A, thereby saving the overall occupied area of the second chip 702 and the first chip 602.

[0222] In some embodiments, the second conductive connectors 705 are soldered to the corresponding first conductive connectors 605 in the step of disposing the top cover 7082 on the first chip 602.

[0223] The second conductive connectors 705 are connected to the first conductive connectors 605, so that the first substrate 601 and the second substrate 701 are electrically connected through the second conductive connectors 705 and the first conductive connectors 605.

[0224] Reference Figure 19 After the top cover 7082 is disposed on the first chip 602, the packaging method further comprises: disposing a heat sink 706 on the third surface 701B of the second substrate 701, the heat sink 706 being in thermal conductive connection with the heat conductive structure 7011, and the third surface 701B being disposed opposite to the second surface 701A.

[0225] By disposing the heat sink 706 on the third surface 701B of the second substrate 701, the heat dissipation effect of the packaging structure is further improved.

[0226] In some embodiments, when the heat sink 706 and the heat conductive structure 7011 are both metal materials, the heat sink 706 and the heat conductive structure 7011 can be combined through a eutectic process. Under the influence of high-temperature processing, the metal materials of the heat sink 706 and the heat conductive structure 7011 form a eutectic layer (not shown in the figure) at the interface due to mutual diffusion between materials.

[0227] The heat sink 706 and the heat conductive structure 7011 are combined through the eutectic layer, which improves the bonding strength and the heat conduction efficiency between the heat sink 706 and the heat conductive structure 7011.

[0228] In other embodiments, the heat sink 706 can be disposed on a heat conductive adhesive layer covering the heat conductive structure 7011 after the heat conductive adhesive layer is formed on the third surface 701B of the second substrate 701. It should be noted that the heat conductive adhesive layer can also cover the third surface 701B of the second substrate 701, thereby improving the stability of the heat sink 706.

[0229] In some embodiments, the heat sink 706 is a heat sink. Specifically, as shown in Figure 19 The heat sink 706 is a heat sink with heat dissipation fins. In other embodiments, the heat sink can also include a liquid cooling channel for passing cooling liquid, the liquid cooling channel including an inlet and an outlet to realize circulation of the cooling liquid.

[0230] Reference Figure 20After the top cover 7082 is arranged on the first chip 602, the packaging method further includes: forming a fifth conductive connecting piece 6011 electrically connecting the first substrate 601 on a fourth surface 601B of the first substrate 601, the fourth surface 601B being opposite to the first surface 601A.

[0231] The first substrate 601 has a first metal circuit layer (not shown in the figure), so as to obtain the first substrate 601 with the first metal circuit, and the fifth conductive connecting piece 6011 is electrically connected to the first metal circuit layer in the first substrate 601, so as to realize the electrical connection between the first substrate 601 and other circuits. For example, the first substrate 601 is assembled to a PCB board through the fifth conductive connecting piece 6011 subsequently.

[0232] The material of the fifth conductive connecting piece 6011 includes one or more of copper, aluminum, gold, nickel, silver, palladium and tin. In some embodiments, the fifth conductive connecting piece 6011 is a solder ball. As an example, the fifth conductive connecting piece 6011 is a tin ball.

[0233] Figure 21 FIG. 8 is a schematic diagram of part of steps in a packaging method according to another embodiment of the present application.

[0234] The same as the foregoing embodiments, details are not repeated herein. The difference between the present embodiment and the foregoing embodiments is that the step of obtaining the second substrate 801 provided with the heat conduction structure 8011 includes: providing the second substrate 801, the second substrate 801 having a ground interconnection layer 8012, and the second substrate 801 being previously prepared with the heat conduction structure 8011, the heat conduction structure 8011 being conductive material, and the heat conduction structure 8011 being electrically connected to the ground interconnection layer 8012.

[0235] In some embodiments, the second substrate 801 has a second metal circuit layer, the second metal circuit layer including the ground interconnection layer 8012, so that the heat conduction structure 8011 is electrically connected to the ground interconnection layer 8012 and avoids the rest of the second metal circuit layer.

[0236] Correspondingly, in the step of arranging the heat dissipation cover 808 of the cover 802 on the second surface (not labeled) of the second substrate 801, the heat dissipation cover 808 is conductive material, and the heat dissipation cover 808 is electrically connected to the heat conduction structure 8011.

[0237] The heat conduction structure 8011 is electrically connected to the ground interconnection layer 8012, and the heat dissipation cover 808 is electrically connected to the heat conduction structure 8011, so that the heat dissipation cover 808 can be grounded, so that the heat dissipation cover 808 can also play a role of electromagnetic shielding, thereby reducing the interference between adjacent chips (for example, between the first chip and the second chip 802).

[0238] In some embodiments, the heat dissipation cover 808 includes a side cover 8081 located at the side of the second chip 802, and a top cover 8082 connected with the side cover 8081. Correspondingly, the heat conduction connection layer (not shown) between the side cover 8081 and the heat conduction structure 8011 is a solder layer.

[0239] In some embodiments, the side cover 8081 is an annular structure surrounding the side wall of the second chip 802, so as to further enhance the electromagnetic shielding effect of the heat dissipation cover 808. For example, the side cover 8081 is an annular structure surrounding the side wall of the second chip 802, and the heat conduction structure 8011 is an annular structure surrounding the second chip 802. The side cover 8081 is aligned with the heat conduction structure 8011.

[0240] Figures 22 to 24 FIG. 8 is a schematic diagram of part of the packaging method according to another embodiment of the present application.

[0241] The same as the foregoing embodiments, details are not repeated here. The difference between the present embodiment and the foregoing embodiments is that, after forming the opening 9015 in the second substrate 901, the heat conduction structure 9011 is arranged in the opening 9015.

[0242] Referring to FIG. 8, the packaging method according to the present embodiment includes the following steps. Figure 22 Before arranging the heat conduction structure in the second substrate 901, the packaging method further includes: temporarily bonding the second substrate 901 to the temporary carrier 900, with the second surface 901A facing away from the temporary carrier 900; and after temporarily bonding the second substrate 901 to the temporary carrier 900, forming the opening 9015 penetrating through the second substrate 901, the opening 9015 being located at the side of the chip mounting area (not shown).

[0243] The opening 9015 is used to provide a space position for forming the heat conduction structure.

[0244] In some embodiments, the opening 9015 can be formed by an etching process. As an example, the second substrate 901 is etched by a laser etching process to form the opening 9015.

[0245] Referring to FIG. 8, the packaging method according to the present embodiment includes the following steps. Figure 23 The heat conduction structure 9011 is arranged in the opening 9015 to obtain the second substrate 901 provided with the heat conduction structure 9011.

[0246] In some embodiments, the step of disposing the heat-conductive structure 9011 in the opening 9015 comprises: filling a heat-conductive material in the opening 9015 to form the heat-conductive structure 9011. In some embodiments, after filling the heat-conductive material in the opening 9015, the heat-conductive material also covers the second surface 901A of the second substrate 901, thus the step of disposing the heat-conductive structure 9011 in the opening 9015 further comprises: performing a planarization process on the heat-conductive material to expose the second surface 901A of the second substrate 901 and retain the heat-conductive material in the opening 9015 as the heat-conductive structure 9011.

[0247] It should be noted that, by disposing the heat-conductive structure 9011 in the opening 9015, the volume of the heat-conductive structure 9011 can be increased, thus improving the heat dissipation capability of the heat-conductive structure 9011.

[0248] Reference is made to FIG. 9, which shows a flowchart of a packaging method according to an embodiment of the present application. Figure 24 In some embodiments, after disposing the heat-conductive structure 9011 in the opening 9015 (as shown in FIG. 9B), the packaging method further comprises: performing debonding to remove the temporary carrier 900 (as shown in FIG. 9C). Figure 22 Figure 22 It should be noted that, in some embodiments, the temporary carrier 900 is removed after disposing the second chip 902, so that the temporary carrier 900 plays a further supporting role in the process of disposing the second chip 902. In other embodiments, the second chip 902 can also be disposed after removing the temporary carrier 900.

[0249] Reference is made to FIG. 9, which shows a flowchart of a packaging method according to an embodiment of the present application. Figure 24 In some embodiments, after disposing the heat-conductive structure 9011 in the opening 9015 (as shown in FIG. 9B), the packaging method further comprises: disposing the second chip 902 on the second surface 901A of the second substrate 901 (as shown in FIG. 9D). Figure 22 Figure 22 It should be noted that, in some embodiments, the temporary carrier 900 is removed after disposing the second chip 902, so that the temporary carrier 900 plays a further supporting role in the process of disposing the second chip 902. In other embodiments, the second chip 902 can also be disposed after removing the temporary carrier 900.

[0250] It should be noted that, according to needs, in some embodiments, the temporary carrier 900 is removed after disposing the second chip 902, so that the temporary carrier 900 plays a further supporting role in the process of disposing the second chip 902. In other embodiments, the second chip 902 can also be disposed after removing the temporary carrier 900.

[0251] It should be noted that, the packaging structure of the embodiments of the present application can be obtained by the packaging method of the embodiments of the present application, or can also be obtained by other packaging methods.

[0252] Correspondingly, the embodiments of the present application also provide an electronic device, which comprises the packaging structure of any of the foregoing embodiments. Since the packaging structure has good heat dissipation performance, the working performance of the electronic device comprising the packaging structure is improved.

[0253] As an example, the electronic device can comprise any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a camera, a personal computer, a vehicle-mounted device, a wearable device, a virtual reality device, an augmented reality device, etc., or any intermediate product comprising the packaging structure.

[0254] ​​Although the present application has been disclosed with reference to the above embodiments, the application is not limited to the above embodiments. It will be apparent to those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the application. The scope of the application should be limited only by the appended claims.

Claims

1. A packaging structure, characterized in that, include: A first package includes a first substrate and a first chip, wherein the first chip is located on a first surface of the first substrate and is electrically connected to the first substrate. The second package is stacked on the first package, and the second package and the first chip are located on the same side of the first substrate; The second package includes: a second substrate; a second chip located on a second surface of the second substrate and electrically connected to the second substrate, the second surface facing the first surface; a thermally conductive structure penetrating the side portion of the second substrate; and a heat sink located on the second surface of the second substrate and covering the second chip, the heat sink including a side cover located on the side portion of the second chip and a top cover connected to the side cover, the top cover being thermally connected to both the second chip and the first chip, and the side cover being thermally connected to the thermally conductive structure.

2. The packaging structure as described in claim 1, characterized in that, The packaging structure further includes a thermally conductive connection layer located between the side cover and the thermally conductive structure, the thermally conductive connection layer comprising a solder layer or a thermally conductive adhesive layer.

3. The packaging structure as described in claim 1, characterized in that, The side cover is an annular structure surrounding the sidewall of the second chip; Alternatively, the heat-conducting structure may be a non-closed annular structure surrounding the second chip; Alternatively, the side cover is an annular structure surrounding the sidewall of the second chip, and the heat-conducting structure is a non-closed annular structure surrounding the second chip, with the side cover aligned with the heat-conducting structure. Alternatively, there may be multiple thermally conductive structures, arranged separately around the second chip; the side cover corresponds one-to-one with the thermally conductive structures and is thermally connected.

4. The packaging structure as described in any one of claims 1 to 3, characterized in that, The second substrate has a ground interconnect layer; Both the thermally conductive structure and the heat dissipation cover are made of conductive materials. The thermally conductive structure is electrically connected to the grounding interconnect layer, and the heat dissipation cover is electrically connected to the thermally conductive structure.

5. The packaging structure as described in any one of claims 1 to 3, characterized in that, The number of the second chips is multiple; the heat-conducting structure is also located between adjacent second chips; the side cover is thermally connected to each heat-conducting structure.

6. The packaging structure according to any one of claims 1 to 3, characterized in that, In a direction parallel to the second surface, the width of the heat-conducting structure is greater than the width of the side cover.

7. The packaging structure according to any one of claims 1 to 3, characterized in that, The packaging structure also includes one or more of the following: The first thermally conductive interface material layer is located between the first chip and the top cover, and is in contact with both the first chip and the top cover; The second thermal interface material layer is located between the second chip and the top cover, and is in contact with both the second chip and the top cover.

8. The packaging structure as described in any one of claims 1 to 3, characterized in that, The packaging structure further includes a heat sink, located on the third side of the second substrate and thermally connected to the thermally conductive structure, wherein the third side is disposed opposite to the second side.

9. The packaging structure as described in any one of claims 1 to 3, characterized in that, The second package satisfies one or more of the following: The heat sink is made of one or more of the following materials: stainless steel, copper, aluminum, iron, tungsten, molybdenum, diamond, and graphene. The material of the thermally conductive structure includes one or more of copper, aluminum, iron, tungsten, molybdenum, diamond, and graphene.

10. The packaging structure as described in claim 1, characterized in that, The first package further includes: a first conductive connector, located on the first surface of the first chip and electrically connected to the first substrate; The second package further includes: a second conductive connector located on the second surface and on the side of the thermally conductive structure away from the second chip; the second conductive connector is electrically connected to the second substrate; and the second conductive connector is connected to the first conductive connector.

11. The packaging structure as described in claim 10, characterized in that, The first package further includes a molding layer located on the first surface of the first chip and the first conductive connector, the molding layer covering the sidewalls of the first chip and the first conductive connector, and exposing the surface of the first conductive connector facing away from the first substrate, the surface of the first chip facing away from the first substrate, and the second conductive connector.

12. The packaging structure as described in claim 10, characterized in that, The first conductive connector is a conductive post, and the second conductive connector is a solder ball.

13. The packaging structure as described in claim 1, characterized in that, The packaging structure further includes: a third conductive connector located between the first chip and the first substrate, wherein the third conductive connector is electrically connected to the first chip and the first substrate; A fourth conductive connector is located between the second chip and the second substrate, and the fourth conductive connector is electrically connected to the second chip and the second substrate.

14. The packaging structure as described in claim 1, characterized in that, The packaging structure further includes a fifth conductive connector, located on the fourth side of the first substrate and electrically connected to the first substrate, wherein the fourth side is disposed opposite to the first side.

15. An electronic device, characterized in that, Includes the packaging structure as described in any one of claims 1 to 14.

16. A packaging method, characterized in that, include: A first chip is disposed on a first side of a first substrate, and the first chip is electrically connected to the first substrate. A second substrate with a thermally conductive structure is obtained. The thermally conductive structure is located on the side of the chip assembly area of ​​the second substrate and penetrates the second substrate. The chip assembly area is used to set a second chip. A second chip is disposed on the second side of the second substrate, and the second chip is located in the chip assembly area and is electrically connected to the second substrate. A heat dissipation cover for the second chip is provided on the second side of the second substrate. The heat dissipation cover includes a side cover located on the side of the second chip and a top cover connected to the side cover. The top cover is thermally connected to the second chip, and the side cover is thermally connected to the thermally conductive structure. The first and second surfaces are arranged opposite each other, and the top cover is placed on the first chip so that the second substrate and the first substrate are stacked, and the top cover is thermally connected to the first chip.

17. The packaging method as described in claim 16, characterized in that, The step of obtaining a second substrate with a thermally conductive structure includes: providing a second substrate, wherein a thermally conductive structure is pre-prepared in the second substrate; Alternatively, the step of obtaining a second substrate with a thermally conductive structure may include: providing a second substrate; and providing a thermally conductive structure in the second substrate.

18. The packaging method as described in claim 17, characterized in that, Before the thermally conductive structure is provided in the second substrate, the packaging method further includes: temporarily bonding the second substrate to a temporary carrier plate, with the second side facing away from the temporary carrier plate; after temporarily bonding the second substrate to the temporary carrier plate, forming an opening penetrating the second substrate, the opening being located on the side of the chip assembly area; The step of providing a heat-conducting structure in the second substrate includes: providing a heat-conducting structure in the opening; After providing a thermally conductive structure in the opening, the encapsulation method further includes: debonding to remove the temporary carrier.

19. The packaging method as described in claim 18, characterized in that, The step of setting a heat-conducting structure in the opening includes: filling the opening with a heat-conducting material to form a heat-conducting structure; After a heat-conducting structure is provided in the opening, the second chip is provided on the second side of the second substrate.

20. The packaging method as described in claim 16, characterized in that, After obtaining the second substrate having the thermally conductive structure, the second chip is disposed on the second side of the second substrate; The step of providing a heat dissipation cover for the second chip on the second side of the second substrate includes: fixing the side cover to the heat-conducting structure and achieving a heat-conducting connection with the heat-conducting structure through a heat-conducting connection layer, wherein the heat-conducting connection layer includes a solder layer or a heat-conducting adhesive layer.

21. The packaging method as described in claim 16, characterized in that, The packaging method further includes one or more of the following: before placing the top cover on the first chip, forming a first thermal interface material layer on the surface of the first chip facing away from the first substrate, and during the step of placing the top cover on the first chip, the top cover is in contact with the first thermal interface material layer; Before the heat dissipation cover covering the second chip is provided on the second side of the second substrate, a second thermally conductive interface material layer is formed on the side of the second chip facing away from the second substrate, and in the step of providing the heat dissipation cover covering the second chip on the second side of the second substrate, the top cover is in contact with the second thermally conductive interface material layer.

22. The packaging method as described in claim 16, characterized in that, Before placing the top cover on the first chip, the packaging method further includes: A first conductive connector is disposed on a first surface of the first substrate, and the first conductive connector is electrically connected to the first substrate. After the first conductive connector and the first chip are disposed on the first surface of the first substrate, the first conductive connector is located on the side of the first chip. A second conductive connector is provided on the second side of the second substrate. The second conductive connector is located on the side of the heat-conducting structure away from the chip assembly area. The second conductive connector is electrically connected to the second substrate. In the step of placing the top cover on the first chip, the second conductive connector is soldered to the corresponding first conductive connector.

23. The packaging method as described in claim 22, characterized in that, Before the top cover is disposed on the first chip, the packaging method further includes: after disposing the first chip and the first conductive connector on a first surface of the first substrate, forming a molding compound on the first surface of the first substrate, the molding compound covering the sidewalls of the first chip and the first conductive connector, and exposing the surface of the first conductive connector facing away from the first substrate and the surface of the first chip facing away from the first substrate.

24. The packaging method as described in claim 16, characterized in that, The step of setting the first chip on the first surface of the first substrate includes: soldering the first chip onto the first surface of the first substrate by a flip-chip bonding process; The step of setting the second chip on the second side of the second substrate includes: soldering the second chip onto the second side of the second substrate by flip-chip bonding process.

25. The packaging method as described in claim 16, characterized in that, In the step of obtaining a second substrate with a thermally conductive structure, the thermally conductive structure is a non-closed annular structure surrounding the chip assembly area. Alternatively, in the step of providing a heat dissipation cover for the second chip on the second side of the second substrate, the side cover is an annular structure surrounding the side wall of the second chip; Alternatively, in the step of obtaining a second substrate with a heat-conducting structure, the heat-conducting structure is a non-closed annular structure surrounding the chip assembly area, and in the step of providing a heat dissipation cover for the second chip on the second side of the second substrate, the side cover is an annular structure surrounding the side wall of the second chip, and the side cover is aligned with the heat-conducting structure. Alternatively, in the step of obtaining a second substrate with a heat-conducting structure, there are multiple heat-conducting structures, which are arranged separately around the chip assembly area, and in the step of providing a heat dissipation cover for the second chip on the second side of the second substrate, the side cover corresponds to each of the heat-conducting structures and is thermally connected.

26. The packaging method as described in claim 16 or 25, characterized in that, The step of obtaining a second substrate with a thermally conductive structure includes: providing a second substrate, the second substrate having a ground interconnect layer, and the second substrate having a pre-prepared thermally conductive structure, the thermally conductive structure being a conductive material, and the thermally conductive structure being electrically connected to the ground interconnect layer; In the step of providing a heat dissipation cover for the second chip on the second side of the second substrate, the heat dissipation cover is made of a conductive material and is electrically connected to the heat-conducting structure.

27. The packaging method as described in claim 16, characterized in that, In a direction parallel to the second surface, the width of the heat-conducting structure is greater than the width of the side cover.

28. The packaging method as described in claim 16, characterized in that, After the top cover is placed on the first chip, the packaging method further includes: placing a heat sink on the third side of the second substrate, wherein the heat sink is thermally connected to the thermally conductive structure, and the third side is disposed opposite to the second side.

29. The packaging method as described in claim 16, characterized in that, After the top cover is disposed on the first chip, the packaging method further includes: forming a fifth conductive connector electrically connected to the first substrate on a fourth surface of the first substrate, wherein the fourth surface is disposed opposite to the first surface.

30. The packaging method as described in claim 22, characterized in that, The first conductive connector is a conductive post, and the second conductive connector is a solder ball.

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