Semiconductor package and manufacturing method thereof

Abstract

The inventive concept relates to a semiconductor package and a method of manufacturing the same. The semiconductor package includes a first redistribution substrate, a first semiconductor chip on a first side of the first redistribution substrate, a first through pillar on a second side of the first redistribution substrate, a second redistribution substrate on the first semiconductor chip and the first through pillar, a second semiconductor chip on a second side of the second redistribution substrate, a semiconductor device includes a first redistribution substrate, a second semiconductor chip on a first side of the first redistribution substrate, a second through pillar on a first side of the second redistribution substrate, a third redistribution substrate on the second semiconductor chip and the second through pillar, a heat dissipation block on a second side of the third redistribution substrate, and a semiconductor device on a first side of the third redistribution substrate. The first side of the first redistribution substrate, the first side of the second redistribution substrate, and the first side of the third redistribution substrate are each spaced apart from a respective second side in a horizontal direction, and the first sides are each aligned in a vertical direction.

Description

Technical Field

[0001] The inventive concept relates to semiconductor packaging, and more specifically, to a semiconductor package comprising two logic chips and a method for manufacturing the same. Background Technology

[0002] Driven by the rapid development of the electronics industry and user demands, electronic devices are becoming smaller and lighter. As electronic devices become smaller and lighter, the semiconductor packages used within them are also becoming smaller and lighter, requiring high reliability, high performance, and high capacity. With higher performance and higher capacity, the power consumption of semiconductor packages also increases. Therefore, the importance of reducing the size of semiconductor packages, improving their performance, and enhancing their thermal characteristics has increased. Summary of the Invention

[0003] The inventive concept provides a semiconductor package and a method for manufacturing the same, which can achieve a small form factor, maximize or otherwise improve heat dissipation characteristics, and enhance reliability.

[0004] Furthermore, the problems that can be solved by the inventive concept are not limited to those described above, and other problems can be clearly understood by those skilled in the art from the following description.

[0005] According to an aspect of the inventive concept, a semiconductor package is provided, comprising: a first redistribution substrate having a first side and a second side spaced apart in a first horizontal direction; a first semiconductor chip on the first side of the first redistribution substrate; a first through-post on the second side of the first redistribution substrate; a second redistribution substrate on the first semiconductor chip and the first through-post, the second redistribution substrate having a first side and a second side spaced apart in a first horizontal direction; a second semiconductor chip on the second side of the second redistribution substrate; a second through-post on the first side of the second redistribution substrate; a third redistribution substrate on the second semiconductor chip and the second through-post, the third redistribution substrate having a first side and a second side spaced apart in a first horizontal direction, the first side of the first redistribution substrate, the first side of the second redistribution substrate, and the first side of the third redistribution substrate being aligned in a vertical direction perpendicular to the upper surface of the first redistribution substrate; a heat sink on the second side of the third redistribution substrate; and a semiconductor device on the first side of the third redistribution substrate.

[0006] According to other aspects of the inventive concept, a semiconductor package is provided, comprising: a first redistribution substrate having a first side and a second side spaced apart in a first horizontal direction; a first semiconductor chip on the first side of the first redistribution substrate; a first through post on the second side of the first redistribution substrate; a second through post on the first semiconductor chip; a second semiconductor chip on the first through post; a second redistribution substrate on the second semiconductor chip and the second through post, the second redistribution substrate having a first side and a second side spaced apart in a first horizontal direction, the first side of the second redistribution substrate and the first side of the first redistribution substrate being aligned in a vertical direction perpendicular to the upper surface of the first redistribution substrate; a heat sink on the second side of the second redistribution substrate; a semiconductor device on the first side of the second redistribution substrate; a sealant located between the first redistribution substrate and the second redistribution substrate, and covering the side surfaces of the first through post and the second through post, the side surface and the upper surface of the first semiconductor chip, and the side surface and the lower surface of the second semiconductor chip; and an external connection terminal on the lower surface of the first redistribution substrate.

[0007] According to other aspects of the inventive concept, a semiconductor package is provided, comprising: a first redistribution substrate having a first side and a second side spaced apart in a first horizontal direction; a first semiconductor chip on the first side of the first redistribution substrate; a first through post on the second side of the first redistribution substrate; a second through post on the first semiconductor chip; a second semiconductor chip on the first through post; a second redistribution substrate on the second semiconductor chip and the second through post, the second redistribution substrate having a first side and a second side spaced apart in a first horizontal direction, the first side of the second redistribution substrate and the first side of the first redistribution substrate being aligned in a vertical direction perpendicular to the upper surface of the first redistribution substrate; a heat sink on the second side of the second redistribution substrate; a semiconductor device on the first side of the second redistribution substrate; and a sealant located between the first redistribution substrate and the second redistribution substrate.

[0008] According to other aspects of the inventive concept, a method for manufacturing a semiconductor package is provided, the method comprising: forming a first redistribution substrate having a first side and a second side spaced apart in a first horizontal direction; forming a first through post on a second side of the first redistribution substrate; disposing a first semiconductor chip on a first side of the first redistribution substrate; forming a second redistribution substrate on the first through post and the first semiconductor chip, the second redistribution substrate having a first side and a second side spaced apart in a first horizontal direction; forming a second through post on a first side of the second redistribution substrate; disposing a second semiconductor chip on a second side of the second redistribution substrate; forming a third redistribution substrate on the second semiconductor chip and the second through post, the third redistribution substrate having a first side and a second side spaced apart in a first horizontal direction, the first side of the first redistribution substrate, the first side of the second redistribution substrate, and the first side of the third redistribution substrate being aligned in a vertical direction perpendicular to the upper surface of the first redistribution substrate; disposing a heat sink on a second side of the third redistribution substrate; and disposing a semiconductor device on a first side of the third redistribution substrate.

[0009] According to other aspects of the inventive concept, a method for manufacturing a semiconductor package is provided, the method comprising: forming a first redistribution substrate having a first side and a second side spaced apart in a first horizontal direction; forming a first through-post on the second side of the first redistribution substrate; disposing a first semiconductor chip on the first side of the first redistribution substrate; forming a lower sealant covering a side surface of the first through-post and a side surface and a top surface of the first semiconductor chip; forming a second through-post on the first semiconductor chip; disposing a second semiconductor chip on the first through-post and the lower sealant; forming an upper sealant covering a side surface of the second through-post and a side surface and a bottom surface of the second semiconductor chip; forming a second redistribution substrate on the second semiconductor chip and the upper sealant, the second redistribution substrate having a first side and a second side spaced apart in a first horizontal direction, the first side of the second redistribution substrate being aligned with the first side of the first redistribution substrate in a vertical direction; disposing a heat sink on the second side of the second redistribution substrate; and disposing a semiconductor device on the first side of the second redistribution substrate. Attached Figure Description

[0010] The exemplary embodiments will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 This is a cross-sectional view of a semiconductor package according to some example embodiments;

[0012] Figures 2A to 2C It is shown in detail Figure 1 A cross-sectional view of the structure of a semiconductor device in a semiconductor package;

[0013] Figures 3A to 3CThis is a cross-sectional view of a semiconductor package according to some example embodiments;

[0014] Figure 4A and Figure 4B This is a cross-sectional view of a semiconductor package according to some example embodiments;

[0015] Figure 5A and Figure 5B This is a cross-sectional view of a semiconductor package according to some example embodiments;

[0016] Figures 6A to 6N This is a cross-sectional view schematically illustrating the process of manufacturing a semiconductor package according to some example embodiments;

[0017] Figures 7A to 7E It is shown in detail Figure 6C A cross-sectional view of the operation; and

[0018] Figures 8A to 8D This is a cross-sectional view schematically illustrating a process for manufacturing a semiconductor package according to some example embodiments. Detailed Implementation

[0019] It will be understood that elements and / or properties (e.g., structure, surface, orientation, etc.) that can be described as "perpendicular", "parallel", "coplanar" with respect to other elements and / or their properties (e.g., structure, surface, orientation, etc.) can be "perpendicular", "parallel", "coplanar", etc., respectively with respect to other elements and / or their properties, or can be "substantially perpendicular", "substantially parallel", "substantially coplanar" with respect to other elements and / or their properties, respectively.

[0020] Components and / or properties that are “substantially perpendicular,” “substantially parallel,” or “substantially coplanar” relative to other components and / or their properties (e.g., structure, surface, orientation, etc.) will be understood to be “perpendicular,” “parallel,” or “coplanar” relative to other components and / or their properties, respectively, within manufacturing and / or material tolerances, and / or have deviations of equal to or less than 10% (e.g., ±10% tolerance) relative to other components and / or their properties in terms of magnitude and / or angle from “perpendicular,” “parallel,” or “coplanar”.

[0021] In the following description, some exemplary embodiments are described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same parts, and repeated descriptions thereof are omitted.

[0022] Figure 1 This is a cross-sectional view of a semiconductor package 1000 according to some example embodiments.

[0023] refer to Figure 1The semiconductor package 1000 of this example embodiment includes first to third redistribution substrates 100-1 to 100-3, a first semiconductor chip 200, a second semiconductor chip 300, a semiconductor device 400, a heat sink 500, a first through post 600-1 and a second through post 600-2, a first sealant 700-1 and a second sealant 700-2, and an external connection terminal 800.

[0024] The first redistribution substrate 100-1 may be disposed below the first semiconductor chip 200, the first through-post 600-1, and the first sealant 700-1. The first redistribution substrate 100-1 may redistribute the chip pads of the first semiconductor chip 200 to the external area of ​​the first semiconductor chip 200. The first redistribution substrate 100-1 may include a body insulating layer 101, redistribution lines 103, and vertical channels 105.

[0025] The bulk insulating layer 101 may be formed of an insulating material (e.g., a photoimageable dielectric (PID) or a photoimageable polyimide (PIP) resin) and may further include inorganic fillers. However, the material of the bulk insulating layer 101 is not limited to the materials described above. For example, the bulk insulating layer 101 may include polyimide isoindroquinazolindione (PIQ), polyimide (PI), polybenzoxazole (PBO), etc.

[0026] Based on the multilayer structure of the redistribution line 103, the bulk insulating layer 101 can have a multilayer structure. However, in Figure 1 For convenience, the body insulating layer 101 is shown as a single-layer structure. When the body insulating layer 101 has a multilayer structure, all layers of the body insulating layer 101 may include the same material, or at least one layer may include a different material.

[0027] The redistribution lines 103 can be arranged in multiple layers within the bulk insulating layer 101. Redistribution lines 103 arranged on different layers can be connected to each other via vertical pathways 105. Simultaneously, redistribution lines 103 having a horizontal difference between two or more layers can be connected to each other by stacking multiple vertical pathways 105. The stacked vertical pathways 105 can be referred to as stacked pathways. The redistribution lines 103 and vertical pathways 105 can include, for example, copper (Cu). However, the material of the redistribution lines 103 and vertical pathways 105 is not limited to Cu.

[0028] External connection terminals 800 may be disposed on the lower surface of the body insulating layer 101. External connection terminals 800 may be disposed on external connection pads disposed on the lower surface of the body insulating layer 101. External connection pads may be included as part of the redistribution line 103. However, in some embodiments, external connection pads may be considered as components separate from the redistribution line 103.

[0029] The first semiconductor chip 200 can be disposed on the first redistribution substrate 100-1 via the adhesive layer 230. The first semiconductor chip 200 can be disposed on the first redistribution substrate 100-1 to be offset to one side in the x-direction. For example, as... Figure 1 As shown, the first semiconductor chip 200 may be disposed on the first redistribution substrate 100-1 to be offset to the right in the x-direction. For example, the first semiconductor chip 200 may be offset to a first side of the first redistribution substrate 100-1 in the x-direction, such that a portion of the upper surface of the first redistribution substrate 100-1 is exposed through the first semiconductor chip 200 (e.g., the first semiconductor chip 200 does not overlap in the vertical direction (z-direction)).

[0030] The first semiconductor chip 200 can be a logic chip. Therefore, the first semiconductor chip 200 may include multiple logic devices. Here, logic devices are devices that perform various signal processing operations and may include, for example, AND, OR, NOT, flip-flops, etc. For example, the first semiconductor chip 200 may be a neural processing unit (NPU) chip. In some example embodiments, the first semiconductor chip 200 may be a modem chip that supports communication with the second semiconductor chip 300. However, the type of the first semiconductor chip 200 is not limited to an NPU chip or a modem chip. For example, the first semiconductor chip 200 may perform individual operations or may include various types of integrated devices to support the operation of the second semiconductor chip 300. The first semiconductor chip 200 may include a multi-channel input / output (I / O) interface for exchanging stored signals with the semiconductor device 400. Furthermore, the first semiconductor chip 200 may include static random access memory (SRAM) for temporary storage of data.

[0031] like Figure 1As shown, the first semiconductor chip 200 may include a substrate 201, an active layer 210, and a first connection terminal 220. The substrate 201 may constitute the body of the first semiconductor chip 200 and may be based on a silicon wafer. The active layer 210 may be disposed on the substrate 201. Strictly speaking, the active layer 210 may include an IC layer in which active elements such as transistors are disposed, and multiple interconnect layers disposed on the IC layer. Typically, the multiple interconnect layers occupy most of the active layer 210, and the IC layer may occupy only a portion of the active layer 210. Meanwhile, the multiple interconnect layers include multiple layers of interconnects, and the interconnects of different layers can be connected to each other through pathways. Chip pads connected to the interconnects of the multiple interconnect layers may be disposed on the upper surface of the active layer 210, and the first connection terminal 220 may be disposed on the chip pads.

[0032] In the first semiconductor chip 200, the upper surface can be the front side, which is the active surface, and the lower surface can be the rear side, which is the passive surface. In other words, the upper surface of the active layer 210 can correspond to the front side of the first semiconductor chip 200, and the lower surface of the substrate 201 can correspond to the rear side of the first semiconductor chip 200. Chip pads can be formed on the front side (which is the active surface), and first connection terminals 220 can be disposed on the chip pads. The first connection terminal 220 can include metal pillars or solder. In some example embodiments, the first connection terminal 220 can include both metal pillars and solder. Here, the metal pillars can include, for example, Cu. However, the material of the metal pillars is not limited to Cu. The first semiconductor chip 200 can be connected to the second redistribution substrate 100-2 via the first connection terminal 220.

[0033] The first through post 600-1 can be located between the first redistribution substrate 100-1 and the second redistribution substrate 100-2. Since the first sealant 700-1 is located between the first redistribution substrate 100-1 and the second redistribution substrate 100-2, the first through post 600-1 can have a structure extending through the first sealant 700-1 in the z-direction. The first through post 600-1 can electrically connect the first redistribution substrate 100-1 to the second redistribution substrate 100-2. For example, the first through post 600-1 can be connected to the redistribution line 103 of the first redistribution substrate 100-1, and can also be connected to the redistribution line of the second redistribution substrate 100-2. For example, the first through post 600-1 can be on a second side of the first redistribution substrate 100-1, which is spaced apart from the first side in the x-direction and exposed by the first semiconductor chip 200. For example, the first through post 600-1 can be on the upper surface of the first redistribution substrate 100-1 opposite to the first semiconductor chip 200.

[0034] In the semiconductor package 1000 of this exemplary embodiment, the first through-post 600-1 may, for example, be configured as a two-dimensional (2D) array structure on the left side of the first semiconductor chip 200 in the x-direction on the first redistribution substrate 100-1. The first through-post 600-1 can be connected to the second semiconductor chip 300 via the second redistribution substrate 100-2. Furthermore, the first through-post 600-1 can be connected to the semiconductor device 400 via the second redistribution substrate 100-2 and the second through-post 600-2.

[0035] The first through-post 600-1 may include, for example, Cu. Therefore, the first through-post 600-1 may be referred to as a Cu post. However, the material of the first through-post 600-1 is not limited to Cu. The first through-post 600-1 may be formed using a seed metal by electroplating. The seed metal may include various metallic materials, such as Cu, titanium (Ti), tantalum (Ta), titanium nitride (TiN), and / or tantalum nitride (TaN). In the semiconductor package 1000 of this example embodiment, the lower pad 610-1 of the first redistribution substrate 100-1 may be used as the seed metal. However, according to some example embodiments, the seed metal may be formed separately from the lower pad 610-1.

[0036] The second redistribution substrate 100-2 can be disposed on the first semiconductor chip 200, the first through-post 600-1, and the first sealant 700-1. The second redistribution substrate 100-2 may also include a body insulating layer, redistribution lines, and vertical pathways. The second redistribution substrate 100-2 may have a structure similar to that of the first redistribution substrate 100-1, but the thickness may be different. For example, the number of redistribution lines in the second redistribution substrate 100-2 may be less than the number of redistribution lines 103 in the first redistribution substrate 100-1. However, in some example embodiments, the number of redistribution lines in the second redistribution substrate 100-2 may be substantially the same as the number of redistribution lines 103 in the first redistribution substrate 100-1. Meanwhile, the redistribution lines of the second redistribution substrate 100-2 can be connected to an external connection terminal 800 through the first through-post 600-1 and the first redistribution substrate 100-1.

[0037] The second semiconductor chip 300 can be mounted on the second redistribution substrate 100-2 via the second connection terminal 320. The second semiconductor chip 300 can be disposed on the left side of the second redistribution substrate 100-2 in the x-direction, corresponding to the first through-post 600-1. Furthermore, the second semiconductor chip 300 and the first semiconductor chip 200 can at least partially overlap each other in the z-direction. For example, the second semiconductor chip 300 can be biased towards a second side of the second redistribution substrate 100-2 in the x-direction, such that a portion of the upper surface of the second redistribution substrate 100-2 is exposed through the second semiconductor chip 300 (e.g., the second semiconductor chip 300 does not overlap in the vertical direction (z-direction)). For example, the overlap region OLA of the second semiconductor chip 300 and the first semiconductor chip 200 can have an area less than 50% of the area of ​​each of the second semiconductor chip 300 and the first semiconductor chip 200. However, the area of ​​the overlap region OLA is not limited to the above numerical range. The second semiconductor chip 300 is connected to the first semiconductor chip 200 using a portion of the second redistribution substrate 100-2 corresponding to the overlapping region OLA, thereby minimizing or otherwise reducing the signal path between the first semiconductor chip 200 and the second semiconductor chip 300.

[0038] In some example embodiments, the second semiconductor chip 300 may also be mounted on the second redistribution substrate 100-2 via pad-to-pad bonding, hybrid bonding (HB), or bonding using anisotropic conductive film (ACF). For reference, because the pads may include Cu, pad-to-pad bonding is also referred to as Cu-to-Cu bonding. HB can refer to a combination of pad-to-pad bonding and insulator-to-insulator bonding. ACF is an anisotropic conductive film that conducts electricity in only one direction and can refer to a conductive film formed by mixing fine conductive particles with an adhesive resin to form a film.

[0039] The second semiconductor chip 300 can be a logic chip. Therefore, the second semiconductor chip 300 may include multiple logic devices. In the semiconductor package 1000 of this example embodiment, the second semiconductor chip 300 can be, for example, an application processor (AP) chip. Furthermore, depending on the function of the second semiconductor chip 300, it can be referred to as a control chip, a processing chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, etc. Meanwhile, in terms of integrated functions, the second semiconductor chip 300 can be referred to as a system-on-a-chip (SoC) together with or independently of the first semiconductor chip.

[0040] The second semiconductor chip 300 may include a substrate 301, an active layer 310, and a second connection terminal 320. The active layer 310 may include an integrated circuit (IC) layer and multiple interconnect layers. The IC layer may include multiple integrated devices. The multiple interconnect layers may be disposed below the IC layer and may include multiple layers of interconnects. In the second semiconductor chip 300, the lower surface may be the front side, which is the active surface, and the upper surface may be the rear side, which is the passive surface. In other words, the lower surface of the active layer 310 may correspond to the front side of the second semiconductor chip 300, and the upper surface of the substrate 301 may correspond to the rear side of the second semiconductor chip 300.

[0041] The second through post 600-2 can be located between the second redistribution substrate 100-2 and the third redistribution substrate 100-3. Since the second sealant 700-2 is located between the second redistribution substrate 100-2 and the third redistribution substrate 100-3, the second through post 600-2 can have a structure extending through the second sealant 700-2 in the z-direction. The second through post 600-2 can connect the second redistribution substrate 100-2 to the third redistribution substrate 100-3. For example, the second through post 600-2 can be connected to a redistribution line of the second redistribution substrate 100-2, and can also be connected to a redistribution line of the third redistribution substrate 100-3. For example, the second through post 600-2 can be on a first side of the second redistribution substrate 100-2, which is spaced apart from the second side and exposed by the second semiconductor chip 300. For example, the second through post 600-2 can be on the upper surface of the second redistribution substrate 100-2 opposite to the second semiconductor chip 300.

[0042] In the semiconductor package 1000 of this exemplary embodiment, the second through-post 600-2 may, for example, be a 2D array structure on the right side of the second semiconductor chip 300 along the x-direction on the second redistribution substrate 100-2. The second through-post 600-2 can be connected to the semiconductor device 400 via the third redistribution substrate 100-3. Furthermore, the second through-post 600-2 can be connected to the first semiconductor chip 200 and the second semiconductor chip 300 via the second redistribution substrate 100-2.

[0043] Furthermore, in the semiconductor package 1000 of this exemplary embodiment, left and right in the x-direction can be relative concepts. Therefore, the positions of the first semiconductor chip 200 and the first through-post 600-1 can be changed. For example, the first semiconductor chip 200 can be positioned biased to the left in the x-direction, and the first through-post 600-1 can be positioned to the right of the first semiconductor chip 200 in the x-direction. Additionally, the second semiconductor chip 300 can be positioned to the right in the x-direction corresponding to the first through-post 600-1, and the second through-post 600-2 and semiconductor device 400 can be positioned to the left in the x-direction.

[0044] The material or forming method of the second through-hole post 600-2 can be substantially the same as that of the first through-hole post 600-1. However, the number of first through-hole posts 600-1 can be greater than the number of second through-hole posts 600-2. For example, the number of first through-hole posts 600-1 can be 30% or more greater than the number of second through-hole posts 600-2 (e.g., between 30% and 100%). However, the difference in the number of first through-hole posts 600-1 and second through-hole posts 600-2 is not limited to the aforementioned numerical range.

[0045] The third redistribution substrate 100-3 can be disposed on the second semiconductor chip 300, the second through-post 600-2, and the second sealant 700-2. The third redistribution substrate 100-3 may also include a body insulating layer, redistribution lines, and vertical vias. The third redistribution substrate 100-3 may have a structure similar to that of the first redistribution substrate 100-1 or the second redistribution substrate 100-2, but may have a different thickness. For example, the number of redistribution lines in the third redistribution substrate 100-3 may differ from the number of redistribution lines in the first redistribution substrate 100-1 or the second redistribution substrate 100-2. Specifically, the number of redistribution lines in the third redistribution substrate 100-3 may be less than the number of redistribution lines 103 in the first redistribution substrate 100-1 and may be greater than the number of redistribution lines in the second redistribution substrate 100-2. However, the number of redistribution lines in the third redistribution substrate 100-3 is not limited to the above description. Meanwhile, the redistribution lines of the third redistribution substrate 100-3 can be connected to the first semiconductor chip 200 and the second semiconductor chip 300 through the second through post 600-2 and the second redistribution substrate 100-2.

[0046] Semiconductor device 400 can be mounted on third redistribution substrate 100-3 via third connection terminal 450. Semiconductor device 400 can be disposed on the right side of third redistribution substrate 100-3 in the x-direction, corresponding to second through post 600-2. For example, semiconductor device 400 can be on the first side of third redistribution substrate 100-3. Semiconductor device 400 can be a single chip or a package including multiple chips. For example, when semiconductor device 400 is a single chip, semiconductor device 400 can include a memory chip. When semiconductor device 400 is a package, semiconductor device 400 can include, for example, multiple memory chips. The memory chip of semiconductor device 400 can include, for example, volatile memory devices (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) or non-volatile memory devices (such as flash memory). In the semiconductor package 1000 of this example embodiment, the memory chip of semiconductor device 400 can be, for example, a DRAM chip. However, the type of memory chip of semiconductor device 400 is not limited to DRAM chips. Reference is made below. Figures 2A to 2C Describe in detail the single-chip structure or package structure of semiconductor device 400.

[0047] When the semiconductor device 400 is a package, the semiconductor package 1000 of this example embodiment can have a package-on-package (POP) structure. For example, in the semiconductor package 1000 of this example embodiment, the first to third redistribution substrates 100-1 to 100-3, the first semiconductor chip 200 and the second semiconductor chip 300, and the first through post 600-1 and the second through post 600-2 can constitute a lower package, and the semiconductor device 400 of the package structure can constitute an upper package. Therefore, the semiconductor package 1000 of this example embodiment can have a POP structure in which the upper package is stacked on the lower package.

[0048] The heat sink 500 can be mounted on the third redistribution substrate 100-3 via the adhesive layer 530. For example, the heat sink 500 can be mounted on a second side of the third redistribution substrate 100-3, which is spaced apart from a first side of the third redistribution substrate 100-3 in the x-direction. The heat sink 500 can be disposed on the left side of the third redistribution substrate 100-3 in the x-direction to correspond to the second semiconductor chip 300. That is, the heat sink 500 can be disposed on the left side of the semiconductor device 400 in the x-direction on the third redistribution substrate 100-3. The heat sink 500 may include, for example, a heat sink or a heatslug. According to some example embodiments, the heat sink 500 may be referred to as a thermal path block (HPB). Meanwhile, the adhesive layer 530 may include a material with high thermal conductivity. For example, the adhesive layer 530 may include a thermal interface material (TIM) or a thermally conductive resin. The TIM may include a material with high thermal conductivity (i.e., low thermal resistance), such as grease, tape, elastomeric pads, and / or phase transfer materials.

[0049] In some example embodiments, the first side of the first redistribution substrate 100-1, the first side of the second redistribution substrate 100-2, and the first side of the third redistribution substrate 100-3 can be aligned in the vertical direction (z-direction). In some example embodiments, the second side of the first redistribution substrate 100-1, the second side of the second redistribution substrate 100-2, and the second side of the third redistribution substrate 100-3 can be aligned in the vertical direction (z-direction).

[0050] The first sealant 700-1 may be located between the first redistribution substrate 100-1 and the second redistribution substrate 100-2. The first sealant 700-1 may cover and seal the side surface of the first through post 600-1 and the side and top surfaces of the first semiconductor chip 200. In some example embodiments, the first semiconductor chip 200 may be connected to the second redistribution substrate 100-2 via pad-to-pad bonding, HB, bonding using ACF, etc., and the first sealant 700-1 may cover the side surface of the first semiconductor chip 200.

[0051] The second sealant 700-2 may be located between the second redistribution substrate 100-2 and the third redistribution substrate 100-3. The second sealant 700-2 may cover and seal the side surface of the second through post 600-2 and the side and bottom surfaces of the second semiconductor chip 300. In some example embodiments, the second sealant 700-2 may cover the second through post 600-2 and the side surfaces of the second semiconductor chip 300.

[0052] The first sealant 700-1 and the second sealant 700-2 may include insulating materials, such as thermosetting resins (e.g., epoxy resins), thermoplastic resins (e.g., polyimide), or resins including reinforcing materials (e.g., inorganic fillers) mixed in with these materials. For example, the first sealant 700-1 and the second sealant 700-2 may include Ajinomoto deposited film (ABF), flame retardant (FR)-4, bismaleimide triazine (BT) resin, etc. Furthermore, the first sealant 700-1 and the second sealant 700-2 may include molding materials (e.g., epoxy molding compounds (EMC)) or photosensitive materials (e.g., photoimageable sealants (PIE)). However, the materials of the first sealant 700-1 and the second sealant 700-2 are not limited to the aforementioned materials.

[0053] External connection terminals 800 may be disposed on the lower surface of the first redistribution substrate 100-1. For example, external connection pads may be disposed on the lower surface of the first redistribution substrate 100-1, and external connection terminals 800 may be disposed on the external connection pads. External connection terminals 800 can connect the semiconductor package 1000 to the package substrate of an external system or the motherboard of an electronic device such as a mobile device. External connection terminals 800 can be electrically connected to the redistribution lines 103 of the first redistribution substrate 100-1 via external connection pads. Furthermore, external connection terminals 800 can be electrically connected to the first through-post 600-1 via the redistribution lines 103 of the first redistribution substrate 100-1.

[0054] The external connection terminal 800 may include a metal pillar 810 and solder 820. The metal pillar 810 may include, for example, Cu. However, the material of the metal pillar 810 is not limited to Cu. In some example embodiments, the external connection terminal 800 may include only solder.

[0055] Meanwhile, since the external connection terminal 800 is disposed on the lower surface of the first redistribution substrate 100-1, the external connection terminal 800 can be disposed in an area larger than the area of ​​the first semiconductor chip 200 or the second semiconductor chip 300. In this way, the package structure in which the external connection terminal 800 is disposed in an area larger than the area of ​​the first semiconductor chip 200 or the second semiconductor chip 300 is called a fan-out (FO) package structure.

[0056] In the semiconductor package 1000 of this example embodiment, for example, the first semiconductor chip 200 may have an area of ​​8.0 x 12.0 mm. 2 Or even smaller, the second semiconductor chip 300 can have an area of ​​5.0*11.0mm. 2 The semiconductor device 400 can have an area of ​​7.0*13.0mm or even smaller. 2Or even smaller, the total package area can be 17.0*14.0mm. 2 Or even smaller. Furthermore, the pitch / width of each of the first connection terminal 220 of the first semiconductor chip 200 and the second connection terminal 320 of the second semiconductor chip 300 can be, for example, 90 / 50 μm or smaller. However, in the semiconductor package 1000 of this example embodiment, the area of ​​the components or the pitch / width of the connection terminals are not limited to the numerical ranges described above.

[0057] Regarding references Figure 1 The area and positional relationship of the first to third redistribution substrates 100-1 to 100-3, the first semiconductor chip 200 and the second semiconductor chip 300, the first through-post 600-1 and the second through-post 600-2, and the semiconductor device 400 are shown in the plan view. Each of the first to third redistribution substrates 100-1 to 100-3 may have an area substantially the same as that of each of the first sealant 700-1 and the second sealant 700-2 in the plan view. Therefore, in the plan view, the first semiconductor chip 200 and the first through-post 600-1 may be located in the first redistribution substrate 100-1. Furthermore, in the plan view, the second semiconductor chip 300 and the second through-post 600-2 may be located in the second redistribution substrate 100-2. Simultaneously, in the plan view, the semiconductor device 400 and the heat sink 500 may be located in the third redistribution substrate 100-3.

[0058] The first semiconductor chip 200 and the second semiconductor chip 300 may at least partially overlap each other in the z-direction. For example, the first semiconductor chip 200 and the second semiconductor chip 300 may overlap each other in the z-direction by 50% or less of their respective areas. Furthermore, the heat sink 500 may overlap with the second semiconductor chip 300 in the z-direction. For example, the heat sink 500 may overlap with the second semiconductor chip 300 to cover 70% or more of the area of ​​the second semiconductor chip 300. However, the area of ​​the second semiconductor chip 300 covered by the heat sink 500 is not limited to the above numerical ranges. Simultaneously, the semiconductor device 400 may overlap with the first semiconductor chip 200.

[0059] The semiconductor package 1000 of this example embodiment can have a FO wafer-level package (FOWLP) structure to improve heat dissipation characteristics, achieve a small form factor, and improve reliability. Specifically, a heat sink 500 is disposed on the third redistribution substrate 100-3 with a structure that largely overlaps with the second semiconductor chip 300, and the second semiconductor chip 300, which contacts the second redistribution substrate 100-2, is connected to the first redistribution substrate 100-1 via a first through-post 600-1, thereby improving the heat dissipation effect of the second semiconductor chip 300. Furthermore, the first semiconductor chip 200 contacts the first redistribution substrate 100-1 and is connected to the second redistribution substrate 100-2 via a first connection terminal 220, thereby improving the heat dissipation effect of the first semiconductor chip 200.

[0060] By arranging the first semiconductor chip 200 and the second semiconductor chip 300 to overlap in the z-direction, the semiconductor package 1000 of this exemplary embodiment can achieve a small form factor. For example, compared to a package structure in which the first semiconductor chip 200 and the second semiconductor chip 300 are arranged side by side in the horizontal direction, the semiconductor package 1000 of this exemplary embodiment can reduce the area by 30% or more.

[0061] By shortening the connection path between the first semiconductor chip 200 and the second semiconductor chip 300, the semiconductor package 1000 of this example embodiment is implemented with improved signal integrity (SI) characteristics and reliability. Specifically, the first semiconductor chip 200 and the second semiconductor chip 300 are connected via a portion of the second redistribution substrate 100-2 corresponding to the overlapping area OLA, thereby shortening the connection path and correspondingly improving SI characteristics. For example, when the connection between the first semiconductor chip 200 and the second semiconductor chip 300 is achieved through the first redistribution substrate 100-1, the number of redistribution lines 103 layers within the first redistribution substrate 100-1 can increase, resulting in a longer connection path, which may degrade SI characteristics. Furthermore, to minimize the resistance of redistribution lines with many layers, connections via stacked pathways can be introduced; however, in the case of stacked pathways, reliability may be problematic due to damage such as cracks. Meanwhile, the connection between the first semiconductor chip 200 and the second semiconductor chip 300 can be achieved using a bridging chip. However, the use of bridging chips is disadvantageous in terms of process and cost, and if the bridging chip is placed on the lower surface of the first redistribution substrate 100-1, the area without external connection terminals 800 may increase, which may degrade the reliability of the entire semiconductor package.

[0062] Figures 2A to 2C To show in more detail Figure 1 A cross-sectional view of the structure of the semiconductor device in the semiconductor package 1000. (As referenced above...) Figure 1The given description is either brief or omitted.

[0063] refer to Figure 2A Semiconductor device 400 may include a memory chip. The memory chip may include, for example, volatile memory devices (such as DRAM or SRAM) or non-volatile memory devices (such as flash memory). In the semiconductor package 1000 of this example embodiment, the memory chip of semiconductor device 400 may include, for example, a DRAM chip. Semiconductor device 400 having a flip-chip bonding structure using a third connection terminal 450 may be mounted on a third redistribution substrate 100-3. The third connection terminal 450 may include metal pillars and solder, or may include only solder.

[0064] refer to Figure 2B Semiconductor device 400a may include a semiconductor package with a wire bonding structure. Specifically, semiconductor device 400a may include a package substrate 410 and a plurality of memory chips 420 stacked on the package substrate 410. The memory chips 420 have a wire bonding structure using an adhesive layer 425 and wires 430, and may be mounted on the package substrate 410. The memory chips 420 of semiconductor device 400a may include, for example, volatile memory devices (such as DRAM or SRAM) or non-volatile memory devices (such as flash memory). In the semiconductor package 1000 of this example embodiment, the memory chips 420 of semiconductor device 400a may include, for example, DRAM chips. Meanwhile, semiconductor device 400a may include an internal sealant sealing the memory chips 420 and wires 430 on the package substrate 410. However, in Figure 2B For convenience, the internal sealant has been omitted.

[0065] exist Figure 2B In this embodiment, four memory chips 420 are stacked on the packaging substrate 410, but the number of memory chips 420 is not limited to four. For example, three or fewer memory chips 420 or five or more memory chips 420 can be stacked on the packaging substrate 410. Furthermore, the memory chips 420 are not limited to a stepped structure, and can be stacked on the packaging substrate 410 in a Z-shaped structure or a combination of stepped and Z-shaped structures. A third connection terminal 450 can be disposed on the lower surface of the packaging substrate 410. Therefore, the semiconductor device 400a of the package structure can also be mounted on the third redistribution substrate 100-3 via the third connection terminal 450.

[0066] refer to Figure 2CThe semiconductor device 400b may include a high-bandwidth memory (HBM) package. Specifically, the semiconductor device 400b may include a substrate chip 410a, a plurality of core chips 420a stacked on the substrate chip 410a, and an internal sealant 440. Furthermore, the substrate chip 410a and the core chips 420a may include a through electrode 430a. However, the uppermost core chip 420a may not include the through electrode 430a.

[0067] The base chip 410a may include logic devices. Therefore, the base chip 410a can be a logic chip. The base chip 410a can be located below the core chip 420a, and can integrate signals from the core chip 420a and transmit the integrated signals externally. It can also transmit signals and power from external sources to the core chip 420a. Therefore, the base chip 410a can be referred to as a buffer chip or a control chip. Meanwhile, each core chip 420a can be a memory chip. For example, each core chip 420a can be a DRAM chip. Furthermore, the core chips 420a can be stacked on the base chip 410a or the lower core chip 420a via pad-to-pad bonding, HB bonding, bonding using connection terminals, or bonding using ACF. Figure 2C In this design, four core chips 420a are stacked on the base chip 410a, but the number of core chips 420a is not limited to four. For example, three or fewer, or five or more core chips 420a can be stacked on the base chip 410a.

[0068] The third connection terminal 450 can be disposed on the lower surface of the substrate chip 410a. Therefore, the HBM-packaged semiconductor device 400b can also be mounted on the third redistribution substrate 100-3 via the third connection terminal 450. The core chip 420a on the substrate chip 410a can be sealed with an internal sealant 440. However, the upper surface of the uppermost core chip 420a may not be covered by the internal sealant 440. However, in other example embodiments, the upper surface of the uppermost core chip 420a may be covered with the internal sealant 440.

[0069] Figures 3A to 3C These are cross-sectional views of semiconductor packages 1000a, 1000b, and 1000c according to some example embodiments. (Referenced above) Figures 1 to 2C The given description is either brief or omitted.

[0070] refer to Figure 3A The semiconductor package 1000a in this example embodiment and Figure 1The difference in the semiconductor package 1000 is that it provides a third through post 600-3. In detail, the semiconductor package 1000a of this example embodiment may include first to third redistribution substrates 100-1 to 100-3, a first semiconductor chip 200, a second semiconductor chip 300, a semiconductor device 400, a heat sink 500, first to third through posts 600-1 to 600-3, a first sealant 700-1 and a second sealant 700-2, and an external connection terminal 800.

[0071] The first to third redistribution substrates 100-1 to 100-3, the first semiconductor chip 200, the second semiconductor chip 300, the semiconductor device 400, the heat sink 500, the first through post 600-1 and the second through post 600-2, the first sealant 700-1 and the second sealant 700-2, and the external connection terminal 800 are referenced above. Figure 1 The semiconductor package 1000 described is the same as those.

[0072] The third through-post 600-3 can be disposed on the first redistribution substrate 100-1 to the right side of the first semiconductor chip 200 in the x-direction. For example, the third through-post 600-3 can be arranged in a row in the y-direction on the right side of the first semiconductor chip 200 in the x-direction on the first redistribution substrate 100-1. However, in some example embodiments, the third through-post 600-3 can be arranged in multiple rows in the y-direction. Furthermore, in some example embodiments, the third through-post 600-3 can be disposed on both sides of the first semiconductor chip 200 in the y-direction on the first redistribution substrate 100-1.

[0073] The third through-post 600-3 can be connected to the semiconductor device 400 via the second redistribution substrate 100-2, the second through-post 600-2, and the third redistribution substrate 100-3. In this way, the third through-post 600-3 is disposed on the first redistribution substrate 100-1 in the lower part of the semiconductor device 400, allowing power to be efficiently transmitted to the semiconductor device 400 via the third through-post 600-3. For example, by using the third through-post 600-3, the second redistribution substrate 100-2, the second through-post 600-2, and the third redistribution substrate 100-3, the power transmission path to the semiconductor device 400 can be configured to be the shortest possible. For example, compared to using the first through post 600-1, the second redistribution substrate 100-2, the second through post 600-2, and the third redistribution substrate 100-3, the third through post 600-3, the second redistribution substrate 100-2, the second through post 600-2, and the third redistribution substrate 100-3 can configure the power transmission path to the semiconductor device 400 to be shorter.

[0074] refer to Figure 3BThe semiconductor package 1000b in this example embodiment may differ from the structure and interconnection structure of the first semiconductor chip 200a. Figure 1 The semiconductor package 1000. In detail, the semiconductor package 1000b of this example embodiment may include first to third redistribution substrates 100-1 to 100-3, a first semiconductor chip 200a, a second semiconductor chip 300, a semiconductor device 400, a heat sink 500, a first through post 600-1 and a second through post 600-2, a first sealant 700-1 and a second sealant 700-2, and an external connection terminal 800.

[0075] The first to third redistribution substrates 100-1 to 100-3, the second semiconductor chip 300, the semiconductor device 400, the heat sink 500, the first through post 600-1 and the second through post 600-2, the first sealant 700-1 and the second sealant 700-2, and the external connection terminal 800 are as described above. Figure 1 The semiconductor package 1000 described is the same as those.

[0076] In the semiconductor package 1000b of this exemplary embodiment, the first semiconductor chip 200a may differ structurally from the first redistribution substrate 100-1 and the connection structure between the second redistribution substrate 100-2. Figure 1 The first semiconductor chip 200a is a semiconductor package 1000 and can be substantially the same in function. Therefore, the first semiconductor chip 200a can be a logic chip and can include multiple logic devices. For example, the first semiconductor chip 200a can be an NPU chip or a modem chip.

[0077] The first semiconductor chip 200a may include a substrate 201, an active layer 210, a first connection terminal 220, a fourth connection terminal 240, and a through electrode 250. The substrate 201, active layer 210, and first connection terminal 220 are as described above. Figure 1The first semiconductor chip 200 of the semiconductor package 1000 described herein is the same. However, in the semiconductor package 1000b of this example embodiment, the active layer 210 of the first semiconductor chip 200a may be disposed below the substrate 201. Therefore, the lower surface of the first semiconductor chip 200a may be the front side (which is the active surface), and the upper surface of the first semiconductor chip 200a may be the rear side (which is the passive surface). In other words, the lower surface of the active layer 210 may correspond to the front side of the first semiconductor chip 200a, and the upper surface of the substrate 201 may correspond to the rear side of the first semiconductor chip 200a. Chip pads may be formed on the front side (which is the active surface), and first connection terminals 220 may be disposed on the chip pads. Finally, the first connection terminals 220 may be disposed on the lower surface of the first semiconductor chip 200a, so the first semiconductor chip 200a can be mounted on the first redistribution substrate 100-1 via the first connection terminals 220.

[0078] Meanwhile, the arrangement position of the first semiconductor chip 200a on the first redistribution substrate 100-1 can be consistent with... Figure 1 The arrangement positions of the first semiconductor chip 200 in the semiconductor package 1000 are basically the same. For example, the first semiconductor chip 200a can be configured to be offset to the right in the x-direction on the first redistribution substrate 100-1, such as... Figure 3B As shown.

[0079] The through-electrode 250 can extend in the vertical direction (i.e., the z-direction) to penetrate the substrate 201. The lower surface of the through-electrode 250 can be connected to the interconnect lines of the multiple interconnect layers of the active layer 210, and the upper surface of the through-electrode 250 can be connected to the fourth connection terminal 240. For example, an upper pad can be disposed on the upper surface of the through-electrode 250, and the fourth connection terminal 240 can be connected to the through-electrode 250 through the upper pad. Therefore, the first semiconductor chip 200a can be connected to the second redistribution substrate 100-2 through the through-electrode 250 and the fourth connection terminal 240. Furthermore, the first semiconductor chip 200a can be connected to the second semiconductor chip 300 through the through-electrode 250 and the second redistribution substrate 100-2. In addition, the first semiconductor chip 200a can be connected to the semiconductor device 400 through the through-electrode 250, the second redistribution substrate 100-2, the second through-post 600-2, and the third redistribution substrate 100-3. Meanwhile, in some embodiments, the fourth connection terminal 240 may be omitted, and the through electrode 250 may be directly connected to the second redistribution substrate 100-2 via the upper pad on the through electrode 250.

[0080] Because the through electrode 250 has a structure that penetrates the silicon constituting the substrate 201, the through electrode 250 can be referred to as a through-silicon via (TSV). For reference, the through electrode 250 can be classified into a pre-pass structure formed before the IC layer of the active layer 210 is formed, an intermediate pass structure formed after the IC layer is formed but before the formation of the multiple interconnect layers of the active layer 210, and a post-pass structure formed after the formation of the multiple interconnect layers. Figure 3B In this example, the through electrode 250 may correspond to, for example, an intermediate pass structure. However, the inventive concept is not limited thereto, and in the semiconductor package 1000b of this exemplary embodiment, the through electrode 250 may have a first pass structure or a second pass structure.

[0081] refer to Figure 3C The semiconductor package 1000c of this example embodiment may have Figure 3A Semiconductor package 1000a and Figure 3B A composite structure of a 1000b semiconductor package. In detail, with... Figure 1 Compared to the semiconductor package 1000 of this example embodiment, the semiconductor package 1000c may further include a third through-post 600-3, and may differ in the structure of the first semiconductor chip 200a and the connection structure between the first redistribution substrate 100-1 and the second redistribution substrate 100-2. The third through-post 600-3 differs from the one referenced above. Figure 3A The third through-post 600-3 of the semiconductor package 1000a described above is the same, and the structure of the first semiconductor chip 200a and its connection structure with the first redistribution substrate 100-1 and the second redistribution substrate 100-2 are the same as those described above. Figure 3B The same as those described in the semiconductor package 1000b.

[0082] Figure 4A and Figure 4B These are cross-sectional views of semiconductor packages 1000d and 1000e according to some example embodiments. (As already referenced above...) Figures 1 to 3C The given description is either brief or omitted.

[0083] refer to Figure 4A The semiconductor package 1000d in this example embodiment and Figure 1The difference in the semiconductor package 1000 is that the second redistribution substrate 100-2 is omitted, thus changing the connection structure between the first semiconductor chip 200 and the second semiconductor chip 300. Specifically, the semiconductor package 1000d of this example embodiment may include a first redistribution substrate 100-1 and a third redistribution substrate 100-3a, a first semiconductor chip 200, a second semiconductor chip 300, a semiconductor device 400, a heat sink 500, a first through-post 600-1 and a second through-post 600-2a, a first sealant 700-1 and a second sealant 700-2, and an external connection terminal 800. The first redistribution substrate 100-1 and the third redistribution substrate 100-3a, the first semiconductor chip 200, the second semiconductor chip 300, the semiconductor device 400, the heat sink 500, the first through-post 600-1 and the second through-post 600-2a, the first sealant 700-1 and the second sealant 700-2, and the external connection terminal 800 are the same as those referenced above. Figure 1 The semiconductor package 1000 described is the same as those.

[0084] However, since the second redistribution substrate 100-2 is omitted, the connection structure between the first semiconductor chip 200 and the second semiconductor chip 300, as well as the first through-post 600-1 and the second through-post 600-2a, can be modified. Specifically, the second through-post 600-2a can be connected to the first connection terminal 220 of the first semiconductor chip 200. Furthermore, in the overlap region OLA where the first semiconductor chip 200 and the second semiconductor chip 300 overlap, the first connection terminal 220 of the first semiconductor chip 200 can be directly connected to the second connection terminal 320 of the second semiconductor chip 300. Similarly, the first through-post 600-1 can be directly connected to the second connection terminal 320 of the second semiconductor chip 300. Simultaneously, the connection between the first semiconductor chip 200 and the second semiconductor chip 300 in the overlap region OLA can be achieved through pad-to-pad bonding, HB bonding, or bonding using ACF.

[0085] Meanwhile, since the second through post 600-2a is directly connected to the first semiconductor chip 200, the length of the second through post 600-2a can be increased from... Figure 1 The second through-post 600-2 of the semiconductor package 1000 increases the thickness of the second redistribution substrate 100-2. Furthermore, when the first sealant 700-1 and the second sealant 700-2 comprise the same material, the first sealant 700-1 and the second sealant 700-2 can be integrated to configure the entire sealant 700T. Therefore, throughout the sealant 700T, the first sealant 700-1 may not be distinguishable from the second sealant 700-2.

[0086] In the case of the semiconductor package 1000d in this example embodiment, since the second redistribution substrate 1000-2 is omitted, the overall thickness of the semiconductor package can be reduced by decreasing the thickness of the second redistribution substrate 1000-2. Furthermore, because the process for forming the second redistribution substrate 1000-2 is omitted, the number of operations in the semiconductor package manufacturing process can be reduced, and materials can be saved. Therefore, the manufacturing cost of the semiconductor package can be significantly reduced.

[0087] refer to Figure 4B The semiconductor package 1000e in this example embodiment may differ from the structure and interconnection structure of the first semiconductor chip 200a. Figure 4A The semiconductor package 1000d. In detail, the semiconductor package 1000e of this example embodiment may include a first redistribution substrate 100-1 and a third redistribution substrate 100-3a, a first semiconductor chip 200a, a second semiconductor chip 300, a semiconductor device 400, a heat sink 500, a first through post 600-1 and a second through post 600-2a, a first sealant 700-1 and a second sealant 700-2, and an external connection terminal 800.

[0088] The first redistribution substrate 100-1 and the third redistribution substrate 100-3a, the second semiconductor chip 300, the semiconductor device 400, the heat sink 500, the first through post 600-1 and the second through post 600-2a, the first sealant 700-1 and the second sealant 700-2, and the external connection terminal 800 are referenced above. Figure 4A The semiconductor package 1000d described is the same.

[0089] Meanwhile, the first semiconductor chip 200a and the above reference Figure 3B The first semiconductor chip described in the semiconductor package 1000b is the same. However, since the second redistribution substrate 100-2 is omitted, the connection structure of the first semiconductor chip 200a and the second semiconductor chip 300, as well as the first through post 600-1 and the second through post 600-2a, can be changed. Specifically, the second through post 600-2a can be connected to the fourth connection terminal 240 of the first semiconductor chip 200a. Furthermore, in the overlap region OLA where the first semiconductor chip 200a and the second semiconductor chip 300 overlap, the fourth connection terminal 240 of the first semiconductor chip 200a can be directly connected to the second connection terminal 320 of the second semiconductor chip 300. Additionally, the first through post 600-1 can be directly connected to the second connection terminal 320 of the second semiconductor chip 300. Meanwhile, the connection between the first semiconductor chip 200a and the second semiconductor chip 300 in the overlap region OLA can be made by pad-to-pad bonding, HB bonding, or bonding using ACF.

[0090] Meanwhile, since the second through post 600-2a is directly connected to the first semiconductor chip 200a, the length of the second through post 600-2a can be increased from... Figure 1 The second through-post 600-2 of the semiconductor package 1000 increases the thickness of the second redistribution substrate 100-2. Furthermore, when the first sealant 700-1 and the second sealant 700-2 comprise the same material, the first sealant 700-1 and the second sealant 700-2 can be integrated to form the entire sealant 700T. Therefore, in the entire sealant 700T, the first sealant 700-1 may not be distinguishable from the second sealant 700-2.

[0091] Figure 5A and Figure 5B These are cross-sectional views of semiconductor packages 1000f and 1000g according to some example embodiments. (The above has been referenced.) Figures 1 to 4B The given description is either brief or omitted.

[0092] refer to Figure 5A The semiconductor package 1000f in this example embodiment is similar to Figure 1 The semiconductor package 1000 may include a passive device 900 disposed on the lower surface of the first redistribution substrate 100-1. In some embodiments, the passive device 900 may be disposed on the upper surface of the first redistribution substrate 100-1 or inside the first redistribution substrate 100-1. Furthermore, the passive device 900 may be disposed on the lower or upper surface of the second redistribution substrate 100-2 or the third redistribution substrate 100-3, or inside the second redistribution substrate 100-2 or the third redistribution substrate 100-3. For example, in... Figure 1 and Figures 3A to 4B In the case of semiconductor packages 1000 and 1000a to 1000e, passive devices may be disposed within at least one of the first to third redistribution substrates 100-1 to 100-3. Passive device 900 may include two-terminal devices such as resistors, inductors, or capacitors. In semiconductor package 1000f of this example embodiment, passive device 900 may include, for example, a multilayer ceramic capacitor (MLCC) 910 and a Si capacitor 920.

[0093] refer to Figure 5B The semiconductor package 1000g in this example embodiment is similar to Figure 4AThe semiconductor package 1000d may include a passive device 900 disposed on the lower surface of the first redistribution substrate 100-1. In some embodiments, the passive device 900 may be disposed on the upper surface of the first redistribution substrate 100-1 or inside the first redistribution substrate 100-1. Furthermore, the passive device 900 may be disposed on the lower or upper surface of the second redistribution substrate 100-2 or the third redistribution substrate 100-3, or inside the second or third redistribution substrate 100-2 or the third redistribution substrate 100-3. In the semiconductor package 1000g of this embodiment, the passive device 900 may include, for example, an MLCC 910 and a Si capacitor 920.

[0094] Figures 6A to 6N This is a schematic cross-sectional view illustrating a process for manufacturing a semiconductor package according to some example embodiments. (See also: [link to reference]) Figure 1 A description is provided, and the above has already been referenced. Figures 1 to 5B The given description is either brief or omitted.

[0095] refer to Figure 6A In the method of manufacturing a semiconductor package according to this exemplary embodiment, firstly, a lower redistribution substrate 100S-1 is formed. The lower redistribution substrate 100S-1 may include a body insulating layer 101, redistribution lines 103, and vertical vias 105. The lower redistribution substrate 100S-1 may be formed on a first carrier substrate 2000. The first carrier substrate 2000 may be a large-size substrate, such as a wafer. Furthermore, the lower redistribution substrate 100S-1 formed on the first carrier substrate 2000 may be a large-size redistribution substrate comprising a plurality of first redistribution substrates 100-1. Although not shown, an adhesive layer may be located between the lower redistribution substrate 100S-1 and the first carrier substrate 2000. The adhesive layer can adhere and fix the lower redistribution substrate 100S-1 to the first carrier substrate 2000.

[0096] For reference, as described below, various components can be formed on a large-size redistribution substrate and individualized through sawing or dicing processes to manufacture semiconductor packages. This type of semiconductor package is called wafer-level packaging (WLP). In the following text, for ease of description, ... Figure 6A The following figures show only the component corresponding to a first redistribution substrate 100-1.

[0097] refer to Figure 6B Subsequently, a first through-post 600-1 is formed on the lower redistribution substrate 100S-1. Considering the portion where the first semiconductor chip 200 is located laterally, the first through-post 600-1 can be formed on the left-hand portion of the lower redistribution substrate 100S-1 in the x-direction. (See below for reference...) Figures 7A to 7EThe method for forming the first through-column 600-1 is described in detail.

[0098] In addition, in manufacturing Figure 3A In the case of semiconductor package 1000a, the third through post 600-3 can be formed together with the first through post 600-1. The third through post 600-3 can be disposed on the right side of the portion where the first semiconductor chip 200 will be located in the x-direction.

[0099] refer to Figure 6C After the first through-post 600-1 is formed, the first semiconductor chip 200 is mounted in the portion where the first through-post 600-1 is not located on the lower redistribution substrate 100S-1, that is, on the right side of the lower redistribution substrate 100S-1 in the x-direction. Specifically, the first semiconductor chip 200 can be mounted on the lower redistribution substrate 100S-1 via an adhesive layer 230. Simultaneously, a first connection terminal 220 can be disposed on the upper surface of the first semiconductor chip 200. The first semiconductor chip 200 can be connected to the portion of the lower redistribution substrate 100S-1 referenced above. Figure 1 The semiconductor package 1000 described above is the same as the first semiconductor chip described above.

[0100] In addition, in manufacturing Figure 3B In the case of the semiconductor package 1000b, a first semiconductor chip 200a including a through electrode 250 can be mounted on the lower redistribution substrate 100S-1. Furthermore, the first semiconductor chip 200a can be mounted on the lower redistribution substrate 100S-1 via a first connection terminal 220, and a fourth connection terminal 240 connected to the through electrode 250 can be disposed on the upper surface of the first semiconductor chip 200a.

[0101] refer to Figure 6D After the first semiconductor chip 200 is installed, the first semiconductor chip 200 and the first through post 600-1 are sealed with a lower sealant 700S-1a. The lower sealant 700S-1a can cover the side and top surfaces of the first semiconductor chip 200 and the first through post 600-1. Furthermore, the lower sealant 700S-1a can fill the space between the first connection terminals 220. The material of the lower sealant 700S-1a is the same as described above. Figure 1 The first sealant 700-1 of the semiconductor package 1000 described is made of the same material.

[0102] Subsequently, refer to Figure 6EThe upper part of the lower sealant 700S-1a is removed by a die grinding (MG) process. After the MG process, the upper surfaces of the first connection terminal 220 and the first through post 600-1 of the first semiconductor chip 200 can be exposed from the lower sealant 700S-1. Furthermore, since the upper surfaces of the first connection terminal 220 and the first through post 600-1 are exposed by the MG process, the upper surfaces of the first connection terminal 220, the first through post 600-1, and the lower sealant 700S-1 can be substantially coplanar with each other.

[0103] refer to Figure 6F An intermediate redistribution substrate 100S-2 is formed over the first semiconductor chip 200, the first through-post 600-1, and the lower sealant 700S-1. The intermediate redistribution substrate 100S-2 may include a body insulating layer, redistribution lines, and vertical pathways. The redistribution lines of the intermediate redistribution substrate 100S-2 can be connected to the first through-post 600-1 and also to the first connection terminal 220 of the first semiconductor chip 200. Furthermore, the intermediate redistribution substrate 100S-2 is a large-size redistribution substrate and may include multiple second redistribution substrates 100-2.

[0104] refer to Figure 6G After forming the intermediate redistribution substrate 100S-2, a second through-post 600-2 is formed on the intermediate redistribution substrate 100S-2. Considering the portion where the second semiconductor chip 300 is located later, the second through-post 600-2 can be formed in the right-hand portion of the intermediate redistribution substrate 100S-2 in the x-direction. The method for forming the second through-post 600-2 can be substantially the same as the method for forming the first through-post 600-1.

[0105] refer to Figure 6H After forming the second through-post 600-2, a second semiconductor chip 300 is mounted on the intermediate redistribution substrate 100S-2. Specifically, the second semiconductor chip 300 can be mounted on the intermediate redistribution substrate 100S-2 via a second connection terminal 320, and can be disposed in the portion corresponding to the first through-post 600-1. For example, the second semiconductor chip 300 can be disposed on the left side of the second through-post 600-2 in the x-direction.

[0106] The second connection terminal 320 may include a metal pillar and solder. In some embodiments, the second connection terminal 320 may consist only of solder. When mounting the second semiconductor chip 300 using the second connection terminal 320, various bonding processes can be used, such as reflow, thermocompression bonding (TCB), laser-assisted bonding (LAB), etc. The second semiconductor chip 300 can be associated with the above references. Figure 1 The semiconductor package 1000 described above is the same as the second semiconductor chip described above.

[0107] refer to Figure 6I After the second semiconductor chip 300 is installed, the second semiconductor chip 300 and the second through-post 600-2 are sealed with an upper sealant 700S-2. The upper sealant 700S-2 can cover the side surface of the second through-post 600-2, as well as the side and bottom surfaces of the second semiconductor chip 300. Furthermore, the upper sealant 700S-2 can fill the space between the second connection terminals 320. The material of the upper sealant 700S-2 can be substantially the same as the material of the lower sealant 700S-1. Furthermore, the formation process of the upper sealant 700S-2 can be substantially the same as the formation process of the lower sealant 700S-1. For example, firstly, an initial upper sealant is formed to cover the side and top surfaces of the second semiconductor chip 300 and the second through-post 600-2. Subsequently, the upper portion of the initial upper sealant is removed by an MG process to expose the top surface of the second semiconductor chip 300 and the second through-post 600-2. Therefore, the upper surfaces of the second semiconductor chip 300 and the second through post 600-2 can be exposed from the upper sealant 700S-2. Furthermore, the upper surfaces of the second semiconductor chip 300, the second through post 600-2, and the upper sealant 700S-2 can be coplanar with each other.

[0108] refer to Figure 6J After forming the upper sealant 700S-2, an upper redistribution substrate 100S-3 is formed over the second semiconductor chip 300, the second through-post 600-2, and the upper sealant 700S-2. The upper redistribution substrate 100S-3 may include a body insulating layer, redistribution lines, and vertical pathways. The redistribution lines of the upper redistribution substrate 100S-3 may be connected to the second through-post 600-2. Furthermore, the upper redistribution substrate 100S-3 is a large-size redistribution substrate and may include multiple third redistribution substrates 100-3.

[0109] refer to Figure 6K After forming the upper redistribution substrate 100S-3, the lower redistribution substrate 100S-1 and its structure are separated from the first carrier substrate 2000, inverted, and attached to the second carrier substrate 3000. In other words, as... Figure 6K As shown, the upper redistribution substrate 100S-3 is attached to the second carrier substrate 3000, and the second semiconductor chip 300, the intermediate redistribution substrate 100S-2, the first semiconductor chip 200, and the lower redistribution substrate 100S-1 can be sequentially arranged on the upper redistribution substrate 100S-3. Although not shown, an adhesive layer can be located between the upper redistribution substrate 100S-3 and the second carrier substrate 3000.

[0110] Subsequently, refer to Figure 6L External connection terminal 800 is attached to the upper surface of the lower redistribution substrate 100S-1. Figure 6L The upper surface of the lower redistribution substrate 100S-1 can correspond to Figure 1 The lower surface of the first redistribution substrate 100-1 in the semiconductor package 1000. Simultaneously, the external connection terminal 800 is connected to the above-mentioned reference... Figure 1 The external connection terminals of the semiconductor package 1000 described are the same. Furthermore, in manufacturing... Figure 5A In the case of semiconductor package 1000f, passive device 900 can be attached to the upper surface of lower redistribution substrate 100S-1.

[0111] refer to Figure 6M After attaching the external connection terminal 800, the entire structure can be separated from the second carrier substrate 3000, and a sawing process S can be performed on the entire structure. For example, the sawing process S can be performed in a ring-shaped mounting device. Through the sawing process S, multiple structures included in the entire structure can be individualized.

[0112] refer to Figure 6N The heat sink 500 can then be disposed on the third redistribution substrate 100-3. Specifically, the heat sink 500 can be disposed on the third redistribution substrate 100-3 via an adhesive layer 530, and can be disposed in the portion corresponding to the second semiconductor chip 300. For example, the heat sink 500 can be disposed on the left side of the third redistribution substrate 100-3 in the x-direction.

[0113] Subsequently, a semiconductor device 400 can be mounted on the third redistribution substrate 100-3. Specifically, the semiconductor device 400 can be disposed on the third redistribution substrate 100-3 via a third connection terminal 450, and can be disposed in the portion corresponding to the second through post 600-2. For example, the semiconductor device 400 can be disposed on the right side of the heat sink 500 in the x-direction. Meanwhile, according to some exemplary embodiments, the order in which the heat sink 500 and the semiconductor device 400 are mounted can be changed. By mounting the heat sink 500 and the semiconductor device 400 on the third redistribution substrate 100-3, the following can be completed: Figure 1 Semiconductor package 1000.

[0114] Figures 7A to 7E To show in more detail Figure 6B A cross-sectional view of the operation.

[0115] refer to Figure 7AIn the method of manufacturing a semiconductor package according to this exemplary embodiment, the first through-pillar 600-1 can be formed on the lower redistribution substrate 100S-1 by the following process. First, a lower pad 610-1 is formed on the lower redistribution substrate 100S-1. The lower pad 610-1 may include various metal materials, such as Cu, Ti, Ta, TiN, TaN, etc. In the method of manufacturing a semiconductor package according to this exemplary embodiment, for example, the lower pad 610-1 may include Cu.

[0116] refer to Figure 7B Subsequently, photoresist (PR) 1500 is coated on the lower redistribution substrate 100S-1. PR 1500 can be applied, for example, by using a spin coater. PR 1500 can be formed to have a thickness corresponding to the length of the first through post 600-1.

[0117] refer to Figure 7C After applying PR 1500, an exposure process is performed. The exposure process can be performed using a mask incorporating a specific pattern. For example, light can be allowed to pass through a transparent portion of a transmission mask to illuminate a portion of the PR 1500. The chemical properties of the illuminated portion of the PR 1500 can be altered. For example, after the exposure process, PR 1500a can be divided into an unexposed portion 1510 and an exposed portion 1520. (As per...) Figure 7C As can be seen, the exposed portion 1520 can be located in the left portion of the lower redistribution substrate 100S-1 in the x direction.

[0118] refer to Figure 7D Following the exposure process, a development process is performed on PR 1500a. During the development process, for example, the exposed portion 1520 can be removed. For example, PR 1500a can be a positive PR. However, according to some example embodiments, a negative PR can be used. When a negative PR is used, the unexposed portion can be removed during the development process.

[0119] As the exposed portion 1520 is removed by the development process, a PR pattern 1500b can be formed. The PR pattern 1500b may include multiple through-holes H. The lower pad 610-1 may be exposed on the bottom surface of the through-holes H. Meanwhile, after the development process, byproducts such as PR slag may remain inside the through-holes H. Therefore, these byproducts are removed by a cleaning process.

[0120] refer to Figure 7EAfter the cleaning process, a first through post 600-1 is formed inside the through hole H by electroplating. The first through post 600-1 may include, for example, Cu. Although not shown, the first through post 600-1 may also be formed on the outside of the through hole H in the portion of the upper surface of the PR pattern 1500b adjacent to the through hole H.

[0121] After forming the first through-post 600-1, the PR pattern 1500b is removed. The PR pattern 1500b can be removed via an ashing / stripping process. By removing the PR pattern 1500b, a... Figure 6B The first penetrating column 600-1.

[0122] Figures 8A to 8D This is a schematic cross-sectional view illustrating a process for manufacturing a semiconductor package according to some example embodiments. (See also: [link to reference]) Figure 4A A description is provided, and the above has already been referenced. Figures 6A to 7E The given description is either brief or omitted.

[0123] refer to Figure 8A The method for manufacturing a semiconductor package in this example embodiment is executed sequentially. Figures 6A to 6E The process involves forming a second through-post 600-2a on the first semiconductor chip 200. The second through-post 600-2a can be formed as a first connection terminal 220 connected to the first semiconductor chip 200. The second through-post 600-2a can be formed using substantially the same method as that used to form the first through-post 600-1. However, the first connection terminal 220 can replace the upper pad as seed metal, and the second through-post 600-2a can be formed only on some of the first connection terminals 220.

[0124] refer to Figure 8B After forming the second through post 600-2a, the second semiconductor chip 300 is mounted on the first through post 600-1 and the first semiconductor chip 200. Specifically, the second semiconductor chip 300 can be mounted via second connection terminals 320 in the portion where the first through post 600-1 is located and in the portion where some of the first connection terminals 220 of the first semiconductor chip 200 are located. For example, the second connection terminals 320 can be connected to all of the first through posts 600-1 and to some of the first connection terminals 220 of the first semiconductor chip 200. Therefore, the second semiconductor chip 300 can at least partially overlap with the first semiconductor chip 200 in the z-direction.

[0125] refer to Figure 8CAfter the second semiconductor chip 300 is installed, the second semiconductor chip 300 and the second through post 600-2a are sealed with an upper sealant 700S-2. The upper sealant 700S-2 can cover the side surface of the second through post 600-2a, as well as the side and bottom surfaces of the second semiconductor chip 300. Furthermore, the upper sealant 700S-2 can fill the space between the second connection terminals 320. The material of the upper sealant 700S-2 can be substantially the same as the material of the lower sealant 700S-1. Furthermore, the formation process of the upper sealant 700S-2 can be substantially the same as the formation process of the lower sealant 700S-1. For example, firstly, an initial upper sealant is formed to cover the side and top surfaces of the second semiconductor chip 300 and the second through post 600-2a. Subsequently, the upper portion of the initial upper sealant is removed by an MG process to expose the top surface of the second semiconductor chip 300 and the second through post 600-2a. Therefore, the upper surfaces of the second semiconductor chip 300 and the second through post 600-2a can be exposed from the upper sealant 700S-2. Meanwhile, the upper sealant 700S-2 and the lower sealant 700S-1 comprise the same material, and the intermediate redistribution substrate 100S-2 is not present between the upper sealant 700S-2 and the lower sealant 700S-1, allowing the upper sealant 700S-2 and the lower sealant 700S-1 to be integrated to form the entire sealant.

[0126] refer to Figure 8D After forming the upper sealant 700S-2, an upper redistribution substrate 100S-3 is formed over the second semiconductor chip 300, the second through-post 600-2a, and the upper sealant 700S-2. The upper redistribution substrate 100S-3 may include a body insulating layer, redistribution lines, and vertical pathways. The redistribution lines of the upper redistribution substrate 100S-3 may be connected to the second through-post 600-2a. Subsequently, it can be performed by... Figures 6K to 6N The process to complete Figure 4A 1000d semiconductor packaging.

[0127] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0128] This application is based on and claims priority to Korean Patent Application No. 10-2024-0065361, filed on May 20, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor package, comprising: The first redistribution substrate has a first side and a second side spaced apart in a first horizontal direction; A first semiconductor chip is located on the first side of the first redistribution substrate; The first through post is on the second side of the first redistribution substrate; A second redistribution substrate is placed on the first semiconductor chip and the first through post, and the second redistribution substrate has a first side and a second side spaced apart in the first horizontal direction. The second semiconductor chip is on the second side of the second redistribution substrate; The second through post is located on the first side of the second redistribution substrate; A third redistribution substrate is placed on the second semiconductor chip and the second through post. The third redistribution substrate has a first side and a second side spaced apart in the first horizontal direction. The first side of the first redistribution substrate, the first side of the second redistribution substrate, and the first side of the third redistribution substrate are aligned in a vertical direction perpendicular to the upper surface of the first redistribution substrate. A heat sink is located on the second side of the third redistribution substrate; and A semiconductor device on the first side of the third redistribution substrate.

2. The semiconductor package of claim 1, wherein the first semiconductor chip at least partially overlaps with the second semiconductor chip in the vertical direction.

3. The semiconductor package of claim 1, wherein the heat sink overlaps with the second semiconductor chip in the vertical direction.

4. The semiconductor package according to claim 1, further comprising: Multiple first penetrating columns; as well as Multiple second penetrating columns, among which The number of first through posts in the plurality of first through posts is greater than the number of second through posts in the plurality of second through posts.

5. The semiconductor package according to claim 1, wherein The upper surface of the first semiconductor chip is an active surface and is connected to the lower surface of the second redistributed substrate. The lower surface of the second semiconductor chip is an active surface and is connected to the upper surface of the second redistribution substrate. The active layer of the first semiconductor chip is connected to the active layer of the second semiconductor chip through the second redistribution substrate.

6. The semiconductor package according to claim 1, wherein The first semiconductor chip includes a through electrode. The lower surface of the first semiconductor chip is an active surface, and the upper surface of the first semiconductor chip is connected to the lower surface of the second redistribution substrate. The lower surface of the second semiconductor chip is an active surface and is connected to the upper surface of the second redistribution substrate. The active layer of the first semiconductor chip is connected to the active layer of the second semiconductor chip through the through electrode and the second redistribution substrate.

7. The semiconductor package according to claim 1, further comprising: The third through post is on the first side of the first semiconductor chip in the first horizontal direction on the first redistribution substrate.

8. The semiconductor package according to claim 1, further comprising: A first sealant is located between the first redistribution substrate and the second redistribution substrate and covers the side surface of the first through post as well as the side and top surfaces of the first semiconductor chip. as well as The second sealant is located between the second redistribution substrate and the third redistribution substrate and covers the side surface of the second through post as well as the side and bottom surfaces of the second semiconductor chip.

9. A semiconductor package, comprising: The first redistribution substrate has a first side and a second side spaced apart in a first horizontal direction; A first semiconductor chip is located on the first side of the first redistribution substrate; The first through post is on the second side of the first redistribution substrate; The second through-post is on the first semiconductor chip; The second semiconductor chip is located on the first through-post; The second redistribution substrate, on the second semiconductor chip and the second through post, has a first side and a second side spaced apart in the first horizontal direction, and the first side of the second redistribution substrate and the first side of the first redistribution substrate are aligned in a vertical direction perpendicular to the upper surface of the first redistribution substrate. A heat sink is located on the second side of the second redistribution substrate; A semiconductor device on the first side of the second redistribution substrate; A sealant is located between the first redistribution substrate and the second redistribution substrate and covers the side surfaces of the first and second through-posts, the side and upper surfaces of the first semiconductor chip, and the side and lower surfaces of the second semiconductor chip; and External connection terminals are located on the lower surface of the first redistribution substrate.

10. The semiconductor package of claim 9, wherein The first semiconductor chip at least partially overlaps with the second semiconductor chip in the vertical direction, and The heat sink overlaps with the second semiconductor chip in the vertical direction.

11. The semiconductor package of claim 9, wherein Both the first semiconductor chip and the second semiconductor chip include an overlapping region, in which portions of the first semiconductor chip and portions of the second semiconductor chip overlap each other in the vertical direction. The upper surface of the first semiconductor chip is an active surface, and the lower surface of the second semiconductor chip is an active surface. The first semiconductor chip is coupled to the second semiconductor chip such that the active surfaces of the first semiconductor chip and the active surfaces of the second semiconductor chip face each other in the overlapping region.

12. The semiconductor package of claim 9, wherein Both the first semiconductor chip and the second semiconductor chip include an overlapping region, in which portions of the first semiconductor chip and portions of the second semiconductor chip overlap each other in the vertical direction. The first semiconductor chip includes through electrodes. The lower surface of the first semiconductor chip is an active surface, and the lower surface of the second semiconductor chip is also an active surface. The first semiconductor chip is coupled to the second semiconductor chip such that the passive surface of the first semiconductor chip faces the active surface of the second semiconductor chip in the overlapping region, and The active layer of the first semiconductor chip is connected to the active layer of the second semiconductor chip through the through electrode.

13. A semiconductor package, comprising: The first redistribution substrate has a first side and a second side spaced apart in a first horizontal direction; A first semiconductor chip is located on the first side of the first redistribution substrate; The first through post is on the second side of the first redistribution substrate; The second through-post is on the first semiconductor chip; The second semiconductor chip is located on the first through-post; The second redistribution substrate, on the second semiconductor chip and the second through post, has a first side and a second side spaced apart in the first horizontal direction, and the first side of the second redistribution substrate and the first side of the first redistribution substrate are aligned in a vertical direction perpendicular to the upper surface of the first redistribution substrate. A heat sink is located on the second side of the second redistribution substrate; A semiconductor device on the first side of the second redistribution substrate; as well as A sealant is located between the first redistribution substrate and the second redistribution substrate.

14. The semiconductor package of claim 13, wherein Both the first semiconductor chip and the second semiconductor chip include an overlapping region, in which portions of the first semiconductor chip and portions of the second semiconductor chip overlap each other in the vertical direction. The upper surface of the first semiconductor chip is an active surface, and the lower surface of the second semiconductor chip is an active surface. The first semiconductor chip is coupled to the second semiconductor chip such that the active surfaces of the first semiconductor chip and the active surfaces of the second semiconductor chip face each other in the overlapping region.

15. The semiconductor package of claim 14, further comprising: An intermediate redistribution substrate is provided on the first semiconductor chip and the first through-post. The intermediate redistribution substrate has a first side and a second side spaced apart in the first horizontal direction. The first side of the intermediate redistribution substrate is perpendicularly aligned with the first side of the second redistribution substrate and the first side of the first redistribution substrate. The second semiconductor chip is located on the second side of the intermediate redistribution substrate. The second through post is on the first side of the intermediate redistribution substrate. The sealant is divided into a lower sealant located below the intermediate redistribution substrate and an upper sealant located above the intermediate redistribution substrate, and In the overlapping region, the active surfaces of the first semiconductor chip and the second semiconductor chip face each other, and the intermediate redistribution substrate is located between the active surfaces of the first semiconductor chip and the second semiconductor chip.

16. The semiconductor package of claim 13, wherein... Both the first semiconductor chip and the second semiconductor chip include an overlapping region, in which portions of the first semiconductor chip and portions of the second semiconductor chip overlap each other in the vertical direction. The first semiconductor chip includes through electrodes. The lower surface of the first semiconductor chip is an active surface, and the lower surface of the second semiconductor chip is an active surface. The first semiconductor chip is coupled to the second semiconductor chip such that the passive surface of the first semiconductor chip faces the active surface of the second semiconductor chip in the overlapping region, and The active layer of the first semiconductor chip is connected to the active layer of the second semiconductor chip through the through electrode.

17. A method for manufacturing a semiconductor package, the method comprising: A first redistribution substrate having a first side and a second side spaced apart in a first horizontal direction is formed; A first through-post is formed on the second side of the first redistribution substrate; A first semiconductor chip is disposed on the first side of the first redistribution substrate; A second redistribution substrate is formed on the first through post and the first semiconductor chip, the second redistribution substrate having a first side and a second side spaced apart in the first horizontal direction; A second through post is formed on the first side of the second redistribution substrate; A second semiconductor chip is disposed on the second side of the second redistribution substrate; A third redistribution substrate is formed on the second semiconductor chip and the second through post. The third redistribution substrate has a first side and a second side spaced apart in the first horizontal direction. The first side of the first redistribution substrate, the first side of the second redistribution substrate, and the first side of the third redistribution substrate are aligned in a vertical direction perpendicular to the upper surface of the first redistribution substrate. as well as A heat sink is disposed on the second side of the third redistribution substrate, and a semiconductor device is disposed on the first side of the third redistribution substrate.

18. The method of claim 17, wherein The first semiconductor chip at least partially overlaps with the second semiconductor chip in the vertical direction, and The heat sink overlaps with the second semiconductor chip in the vertical direction.

19. The method of claim 17, further comprising: Before forming the second redistribution substrate A first sealant is formed covering the side surface of the first through post and the side and top surfaces of the first semiconductor chip; as well as Before forming the third redistribution substrate A second sealant is formed covering the side surface of the second through post and the side and bottom surfaces of the second semiconductor chip.

20. A method for manufacturing a semiconductor package, the method comprising: A first redistribution substrate having a first side and a second side spaced apart in a first horizontal direction is formed; A first through-post is formed on the second side of the first redistribution substrate; A first semiconductor chip is disposed on the first side of the first redistribution substrate; A lower sealant is formed covering the side surface of the first through post and the side and top surfaces of the first semiconductor chip; A second through-post is formed on the first semiconductor chip; A second semiconductor chip is disposed on the first through-post and the lower sealant; An upper sealant is formed covering the side surface of the second through post and the side and lower surfaces of the second semiconductor chip; A second redistribution substrate is formed on the second semiconductor chip and the upper sealant. The second redistribution substrate has a first side and a second side spaced apart in the first horizontal direction. The first side of the second redistribution substrate is aligned with the first side of the first redistribution substrate in the vertical direction. as well as A heat sink is disposed on the second side of the second redistribution substrate, and a semiconductor device is disposed on the first side of the second redistribution substrate.

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