Photon chip, optical module, electronic equipment and photon chip testing method

Abstract

The embodiment of the invention provides a photon chip, an optical module, electronic equipment and a photon chip testing method, and belongs to the technical field of chips. Wherein the photon chip comprises a chip body, a plurality of ball mounting bonding pads and a plurality of test bonding pads are arranged on an electric connection surface of the chip body, each ball mounting bonding pad is electrically connected with at least one test bonding pad through a metal wire in the chip body, and the ball mounting bonding pads are electrically connected with an internal circuit of the chip body; and the test bonding pad is used for providing a contact point of a probe when wafer level test is carried out on the photon chip. According to the scheme, the testing efficiency of the photon chip can be improved, and packaging use of the photon chip after testing is not affected.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and more particularly to a photonic chip, an optical module, an electronic device, and a photonic chip testing method. Background Technology

[0002] Photonic chips, also known as photonic integrated circuits (PICs), utilize the characteristics of light (such as interference, diffraction, and refraction) and the optical properties of materials (such as refractive index, photoelectric effect, and acousto-optic effect) to manipulate and process optical signals. Based on photonic chips, optical modules (optical transceivers) can be constructed. These modules, due to their high bandwidth, low power consumption, and low loss characteristics, are widely used in data centers for data transmission. Before downstream processing and manufacturing, photonic chips need to be tested to identify and remove any problematic chips.

[0003] Currently, after dicing a wafer to obtain multiple independent photonic chips, each photonic chip is tested separately.

[0004] However, testing each photonic chip individually after wafer dicing and electrically connecting the probes to the photonic chips takes a considerable amount of time, resulting in low testing efficiency. Furthermore, when photonic chips are packaged using flip-chip technology, probes hitting solder balls can easily cause the surface metal of the solder balls to be peeled off, exposing the substrate and affecting the packaged use of the photonic chip. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a photonic chip, an optical module, an electronic device, and a photonic chip testing method to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the present disclosure, a photonic chip is provided, including a chip body. The electrical connection surface of the chip body is provided with a plurality of ball pads and a plurality of test pads. Each ball pad is electrically connected to at least one test pad through a metal trace in the chip body, and the ball pad is electrically connected to the internal circuitry of the chip body. The test pads are used to provide contact points for probes when performing wafer-level testing on the photonic chip.

[0007] According to a second aspect of the present disclosure, an optical module is provided, including a printed circuit board and a photonic chip; the photonic chip includes a chip body, the electrical connection surface of the chip body is provided with a plurality of ball pads and a plurality of test pads, each ball pad is electrically connected to at least one test pad through a metal trace in the chip body, and the ball pad is electrically connected to the internal circuitry of the chip body, the test pads are used to provide contact points for probes when performing wafer-level testing on the photonic chip; the photonic chip is electrically connected to the printed circuit board.

[0008] According to a third aspect of the present disclosure, an electronic device is provided, including an optical module as described in the second aspect above.

[0009] According to a fourth aspect of the present disclosure, a photonic chip testing method is provided for testing the photonic chip described in the first aspect above. The method includes: acquiring a wafer comprising a plurality of the photonic chips; contacting a probe connected to a testing device with test pads included in the photonic chips to electrically connect the probes to the test pads; and performing wafer-level testing on the photonic chips using the testing device.

[0010] According to the solution provided in this disclosure, the photonic chip includes a chip body. Multiple ball-mount pads and multiple test pads are disposed on the electrical connection surface of the chip body. Each ball-mount pad is electrically connected to at least one test pad via a metal trace in the chip body. During wafer-level testing of the photonic chip, the test pads provide contact points for probes. The probes do not damage the ball-mount pads during wafer-level testing, thus ensuring the effective ball placement on the surface of the ball-mount pads when the photonic chip is packaged using flip-chip technology. Therefore, by providing test pads electrically connected to the ball-mount pads, wafer-level testing of the photonic chip can be performed while ensuring the quality of the ball placement, improving the testing efficiency of the photonic chip. In addition to providing probe contact points, the test pads can also be electrically connected to metal wires used for wire bonding, making the photonic chip suitable for both flip-chip and wire-bonded packaging. This eliminates the need for separate design of photonic chips for different packaging forms, thereby reducing the design cost of the photonic chip. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0012] Figure 1This is a top view of a photonic chip according to an embodiment of this disclosure;

[0013] Figure 2 This is a top view of a photonic chip according to another embodiment of this disclosure;

[0014] Figure 3 This is a top view of a photonic chip according to yet another embodiment of this disclosure;

[0015] Figure 4 This is a top view of a photonic chip according to another embodiment of the present disclosure;

[0016] Figure 5 This is a top view of a photonic chip including solder balls according to an embodiment of this disclosure;

[0017] Figure 6 This is a schematic diagram of an optical module according to an embodiment of the present disclosure;

[0018] Figure 7 This is a schematic diagram of an optical module according to another embodiment of the present disclosure;

[0019] Figure 8 This is a flowchart of a photonic chip testing method according to an embodiment of the present disclosure. Detailed Implementation

[0020] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0021] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0022] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0023] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0024] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information other than that necessary for basic functions will not affect the user's use of basic functions.

[0025] First, some nouns or terms appearing in the description of the embodiments of this disclosure shall be interpreted as follows:

[0026] Photonic chips, also known as photonic integrated circuits (PICs), are miniaturized chips that use photons as information carriers and integrate optical devices to achieve functions such as optical signal generation, modulation, transmission, and detection. The essence of photonic chips is to utilize the physical properties of photons (such as high-speed propagation, parallel transmission, and low mutual interference) to encode and process information. Photonic chips include silicon-based photonic chips (such as silicon photonic chips), III-V group photonic chips, thin-film lithium niobate (TFLN) photonic chips, and planar lightwave circuit (PLC) photonic chips, among others.

[0027] Silicon Photonics Chip: A silicon photonics chip is a new type of chip that combines silicon-based semiconductor technology and optoelectronic technology. It uses silicon material as a substrate and integrates optical devices on its surface, combining traditional electronic devices with optical devices to achieve high-speed, high-bandwidth data transmission and processing using photonics technology.

[0028] III-V group photonic chips: III-V group photonic chips are based on III-V group compound semiconductor materials and integrate multiple photonic devices on the same chip to realize functions such as optical signal production, transmission, modulation and detection. They have important application value in optical communication, optical computing and other fields.

[0029] Thin-film lithium niobate chip: A thin-film lithium niobate chip is a photonic integrated circuit based on thin-film lithium niobate material. It utilizes the excellent optical, electro-optic, and nonlinear optical properties of lithium niobate material to integrate multiple optical functional devices on a single chip, realizing functions such as optical signal generation, modulation, transmission, and detection. It has broad application prospects in fields such as optical communication, quantum information, and optical sensing.

[0030] Electronic chips: Electronic chips are the core foundation of modern information technology. They integrate a large number of electronic components (such as transistors, resistors, capacitors, etc.) on semiconductor materials to realize the calculation, storage, processing and transmission of electrical signals.

[0031] Heat sink: A heat sink is a key component for efficient heat dissipation. By increasing the heat dissipation area and optimizing the heat conduction path, it can quickly dissipate the heat generated by electronic and / or photonic devices during operation, thus preventing device failure due to high temperature.

[0032] Printed Circuit Board: A printed circuit board (PCB) is a support and electrical connection carrier for electronic devices and / or photonic devices. It connects electronic components such as resistors, capacitors, and chips into a complete circuit system through pre-set conductive lines to realize the transmission and distribution of electrical signals.

[0033] Solder Ball: Solder balls are key connecting elements commonly used in electronic packaging and assembly technology. They are mainly used to achieve electrical connections and mechanical fixation between chips (or other electronic components) and substrates or printed circuit boards. They are widely used in advanced packaging technologies such as Ball Grid Array (BGA), Chip Scale Package (CSP), and Flip Chip (FC).

[0034] Through Silicon Via (TSV): TSVs enable vertical electrical interconnects between chips by creating vertical vias in a silicon wafer. TSV technology can reduce interconnect length and signal delay, and decrease capacitance and inductance, thereby achieving low-power, high-speed communication and higher interconnect density between chips.

[0035] The photonic chip, optical module, electronic device, and photonic chip testing method provided in the embodiments of this disclosure are described in detail below with reference to the accompanying drawings.

[0036] Photonic chip

[0037] Figure 1 A top view of a photonic chip 10 according to an embodiment of this disclosure is shown. Figure 1 As shown, the photonic chip 10 includes a chip body 11, and the electrical connection surface of the chip body 11 is provided with a plurality of ball pads 12 and a plurality of test pads 13. Each ball pad 12 is electrically connected to at least one test pad 13 through a metal trace 111 in the chip body 11. The ball pads 12 are electrically connected to the internal circuitry of the chip body 11. The test pads 13 can provide contact points for probes when performing wafer-level testing on the photonic chip 10. That is, when performing wafer-level testing on the photonic chip 10, the tip of the probe can contact the test pad 13 to achieve electrical connection between the probe and the photonic chip 10.

[0038] The internal circuitry of the chip body 11 may include electronic components, optical components, and metal wires for electrical connections between components. Electronic components may include transistors, capacitors, resistors, etc.

[0039] Since the pads are the structures used to achieve electrical connections in the photonic chip 10 package, the surface of the photonic chip 10 with the ball pads 12 and test pads 13 is defined as the electrical connection surface. When the photonic chip 10 is packaged using wire bonding, the lower surface of the photonic chip 10 faces the PCB, and the upper surface of the photonic chip 10 is the electrical connection surface. When the photonic chip 10 is packaged using flip chip technology, the lower surface of the photonic chip 10 faces the PCB, and the lower surface of the photonic chip 10 is the electrical connection surface.

[0040] When the photonic chip 10 is packaged using a flip-chip method, solder balls can be placed on the surface of the ball pad 12. Since the probe contacts the test pad 13 during wafer-level testing of the photonic chip 10, but does not contact the ball pad 12, the ball pad 12 will not be damaged by the probe during wafer-level testing. This ensures the quality of the solder balls placed on the surface of the ball pad 12 after wafer-level testing and reduces the risk of solder balls falling off the ball pad 12.

[0041] When the photonic chip 10 is packaged using wire bonding, the surface of the ball-mounted pad 12 does not need to be fitted with solder balls. The test pad 13 can be electrically connected to the PCB via a metal wire, and the ball-mounted pad 12 is indirectly electrically connected to the PCB through the test pad 13 it connects to. Since the wire bonding method has lower requirements for the surface quality of the pads, after the probe contacts the test pad 13 to perform wafer-level testing on the photonic chip 10, the test pad 13 can still reliably connect to the metal wire, ensuring the quality and reliability of the wire bonding.

[0042] Wafer-level testing (WLT) is a stage in the semiconductor manufacturing process where all chips on a wafer are tested for electrical performance and functionality before the wafer is diced into individual chips (die). The goal of wafer-level testing is to identify defective chips at the wafer stage, reducing cost waste in subsequent packaging and final product testing, while also providing data feedback for process optimization.

[0043] It should be noted that when performing wafer-level testing on the photonic chip 10, not all pins of the photonic chip 10 are usually tested, but only some of the pins are tested. For example, only the pins used to transmit low-speed signals are tested. The pins corresponding to the ball pads 12 are the pins that need to be tested during the wafer-level testing process.

[0044] In this embodiment, the photonic chip 10 includes a chip body 11. Multiple ball-mounting pads 12 and multiple test pads 13 are disposed on the electrical connection surface of the chip body 11. Each ball-mounting pad 12 is electrically connected to at least one test pad 13 via a metal trace 111 in the chip body 11. During wafer-level testing of the photonic chip 10, the test pads 13 provide contact points for probes. The probes do not damage the ball-mounting pads 12 during wafer-level testing, thus ensuring the effective ball-mounting on the surface of the ball-mounting pads 12 when the photonic chip 10 is packaged using a flip-chip process. Therefore, by providing test pads 13 electrically connected to the ball-mounting pads 12, wafer-level testing of the photonic chip 10 can be performed while ensuring the quality of the ball-mounting on the ball-mounting pads 12, thereby improving the testing efficiency of the photonic chip 10. The test pad 13 provides probe contact points and can also be electrically connected to the metal wire used for wire bonding, so that the photonic chip 10 is suitable for both flip chip packaging and wire bonding packaging, thus eliminating the need to design the photonic chip 10 separately for different packaging forms, thereby reducing the design cost of the photonic chip 10.

[0045] In one possible implementation, such as Figure 2The top view of the photonic chip 10 shown shows that, in addition to the ball pads 12 and test pads 13 on the electrical connection surface of the chip body 11, multiple virtual pads 14 are also provided on the electrical connection surface. The virtual pads 14 are located in the area of ​​the electrical connection surface where the ball pads 12 are not provided, and the virtual pads 14 are not electrically connected to the internal circuitry of the chip body 11.

[0046] When the photonic chip 10 is packaged using a flip-chip method, solder balls can be placed on the surfaces of the ball pads 12 and the dummy pads 14. Since the dummy pads 14 are not electrically connected to the internal circuitry of the chip body 11, and are not used for signal transmission or power supply to the chip body 11, the solder balls placed on the surface of the dummy pads 14 are called dummy balls. When connecting the photonic chip 10 to the PCB, the solder balls on the surface of the ball pads 12 are electrically connected to the charged pads of the PCB, and the solder balls on the surface of the dummy pads 14 are connected to the uncharged pads of the PCB.

[0047] When the photonic chip 10 is packaged using wire bonding, the test pad 13 is electrically connected to the charged pads on the PCB via a metal wire, while the ball pad 12 and dummy pad 14 do not need to be connected to the PCB. The surfaces of the ball pad 12 and dummy pad 14 are provided with an insulating layer to prevent short circuits in the photonic chip 10 caused by electrical connections between the ball pad 12 and dummy pad 14 and the metal wire.

[0048] In this embodiment, the electrical connection surface of the chip body 11 is provided with ball pads 12 and virtual pads 14. When the photonic chip 10 is packaged using a flip-chip method, solder balls are provided on the surfaces of the ball pads 12 and virtual pads 14. When the photonic chip 10 is connected to the PCB, the ball pads 12 are electrically connected to the charged pads of the PCB through the solder balls, ensuring that the photonic chip 10 can communicate normally with the PCB. The virtual pads 14 are connected to the uncharged pads of the PCB through the solder balls. By setting the virtual pads 14, when the photonic chip 10 is connected to the PCB using a chip mounting method, the virtual solder balls set on the surface of the virtual pads 14 can prevent the chip body 11 from bending, improving the reliability of drop tests. By setting the virtual pads 14, the density uniformity of the chip body 11 surface can be improved, avoiding large process deviations in processes such as photolithography and chemical mechanical polishing. Virtual pads 14 enable uniform material distribution on electrical connection surfaces, resulting in more stable reflection and diffraction during photolithography, more uniform grinding during chemical mechanical polishing, and avoidance of over- or under-grinding, thus improving process consistency and yield.

[0049] In one possible implementation, such as Figure 3The top view of the photonic chip 10 shown shows that, in addition to the ball pads 12, test pads 13, and virtual pads 14 on the electrical connection surface of the chip body 11, multiple hybrid pads 15 are also provided on the electrical connection surface. The hybrid pads 15 are electrically connected to the internal circuitry of the chip body 11.

[0050] When performing wafer-level testing on the photonic chip 10, only some pins of the photonic chip 10 are usually tested, such as only the pins used to transmit low-speed signals, and not the pins used to transmit high-speed signals. The pins corresponding to the hybrid pad 15 are pins that do not need to be tested during the wafer-level testing process. Therefore, when performing wafer-level testing on the photonic chip 10, it is not necessary to contact the probes with the hybrid pad 15.

[0051] When the photonic chip 10 is packaged using a flip-chip method, solder balls can be installed on the surfaces of the ball pads 12, dummy pads 14, and hybrid pads 15. Specifically, solder balls are placed on the surfaces of the ball pads 12, dummy pads 14, and hybrid pads 15. When connecting the photonic chip 10 to the PCB, the solder balls on the surfaces of the ball pads 12 and hybrid pads 15 are electrically connected to the charged pads on the PCB, while the solder balls on the surface of the dummy pad 14 are connected to the uncharged pads on the PCB.

[0052] When the photonic chip 10 is packaged using wire bonding, the test pad 13 and the hybrid pad 15 are electrically connected to the charged pads on the PCB via metal wires, while the ball pad 12 and the dummy pad 14 do not need to be connected to the PCB. To prevent the photonic chip 10 from short-circuiting due to the electrical connection between the ball pad 12 and the dummy pad 14 and the metal wires, an insulating layer can be provided on the surface of the ball pad 12 and the dummy pad 14.

[0053] In this embodiment, since the pins corresponding to the hybrid pad 15 do not require testing during wafer-level testing, the wafer-level testing process will not damage the hybrid pad 15, so ball bonding can be directly applied to the surface of the hybrid pad 15. When the photonic chip 10 is packaged using a flip-chip method, ball bonding on the surface of the hybrid pad 15 allows the hybrid pad 15 to be electrically connected to the PCB pads via the solder balls. When the photonic chip 10 is packaged using a wire bonding method, the hybrid pad 15 can be directly electrically connected to the PCB pads via metal wires. Therefore, for pins that do not require testing during wafer-level testing, a hybrid pad 15 is provided for these pins, making the hybrid pad 15 compatible with both flip-chip and wire bonding packaging methods for the photonic chip 10, reducing the design cost of the photonic chip 10 and improving its applicability.

[0054] In one possible implementation, such as Figure 4The top view of the photonic chip 10 shown indicates that a hybrid pad 15 is disposed on the electrical connection surface near the first side 112 of the chip body 11. An optical port 16 is disposed on the second side 113 of the chip body 11, with the first side 112 and the second side 113 facing each other. At least one test pad 13 is disposed on the electrical connection surface near the third side 114 of the chip body 11, and at least one test pad 13 is disposed on the electrical connection surface near the fourth side 115 of the chip body 11, with the third side 114 and the fourth side 115 facing each other. A ball-mount pad 12 is disposed inside the connected test pad 13, and a virtual pad 14 is disposed inside the ball-mount pad 12.

[0055] The chip body 11 has a cuboid structure, and the first side 112, the second side 113, the third side 114 and the fourth side 115 of the chip body 11 are all perpendicular to the electrical connection surface.

[0056] When the photonic chip 10 is used to convert electrical signals into optical signals, the optical port 16 includes an input port and an output port. An external optical coupler can input an optical signal without information into the photonic chip 10 through the input port. After the photonic chip 10 converts the electrical signal into an optical signal carrying information, it can output the optical signal carrying information through the output port, for example, by inputting the optical signal carrying information into an optical fiber array through the output port. Alternatively, when the photonic chip 10 is used to convert optical signals into electrical signals, the optical port 16 includes an input port. An external optical coupler can input an optical signal carrying information into the photonic chip 10 through the input port. After the photonic chip 10 converts the optical signal carrying information into an electrical signal, it outputs the electrical signal.

[0057] In this embodiment, since the hybrid pad 15 is used to transmit high-speed signals, placing the hybrid pad 15 in a region far from the optical port 16 can avoid interference between the high-speed signal and the optical signal, ensuring the reliability of photoelectric signal conversion by the photonic chip 10. The ball-mounted pad 12 and the virtual pad 14 are located in the middle region of the electrical connection surface. Because the warpage of the middle region of the chip body 11 is relatively small, when the photonic chip 10 is packaged using a flip-chip packaging method, the ball-mounted pad 12 and the virtual pad 14 are firmly connected to the PCB through the solder balls, reducing the risk of desoldering due to warpage of the chip body 11. The test pad 13 is located outside the ball-mounted pad 12, facilitating contact between the probe and the test pad 13 during wafer-level testing of the photonic chip 10.

[0058] In one possible implementation, such as Figure 5 The top view of the photonic chip 10 shown shows that when the photonic chip 10 is configured to be electrically connected to the PCB via a flip chip method, solder balls 17 are provided on the surfaces of the ball pads 12, virtual pads 14 and hybrid pads 15.

[0059] When the photonic chip 10 is packaged using a flip-chip method, the ball pads 12, dummy pads 14, and hybrid pads 15 are all formed into solder balls 17 through a ball-mounting process. After the photonic chip 10 is connected to the PCB, the ball pads 12 and hybrid pads 15 are electrically connected to the charged pads of the PCB through the solder balls 17, and the dummy pads 14 are connected to the uncharged pads of the PCB through the solder balls 17.

[0060] In this embodiment of the disclosure, when the photonic chip 10 is connected to the PCB in a flip-chip manner, the surfaces of the ball pad 12, the virtual pad 14 and the hybrid pad 15 are all provided with solder balls 17. Therefore, when the photonic chip 10 is packaged, the photonic chip 10 can be soldered to the PCB through a reflow soldering process, so that the photonic chip 10 is suitable for flip-chip packaging.

[0061] In one possible implementation, such as Figure 3 As shown, when the photonic chip 10 is configured to be electrically connected to the PCB via wire bonding, the surfaces of the ball pad 12, the virtual pad 14, and the hybrid pad 15 are all equipped with solder balls.

[0062] When the photonic chip 10 is packaged using wire bonding, the test pad 13 and the hybrid pad 15 are electrically connected to the PCB pads via metal wires. The ball pad 12 and the virtual pad 14 do not need to be connected to the PCB, so there is no need to place solder balls on the surface of the ball pad 12, the virtual pad 14 and the hybrid pad 15.

[0063] In this embodiment of the disclosure, when the photonic chip 10 is connected to the PCB by wire bonding, the surfaces of the ball pad 12, the virtual pad 14, and the hybrid pad 15 do not need to be set with solder balls. When the photonic chip 10 is packaged, the test pad 13 and the hybrid pad 15 are electrically connected to the pads of the PCB by metal wires, thereby realizing the electrical connection between the photonic chip 10 and the PCB, making the photonic chip 10 suitable for wire bonding process packaging.

[0064] In one possible implementation, the length and width of the test pad 13 are both greater than 70 μm (micrometers), and the thickness of the test pad 13 is greater than 1 μm.

[0065] The length and width directions of the test pad 13 are parallel to the electrical connection surface of the chip body 11, and the length direction of the test pad 13 is perpendicular to the width direction. The thickness direction of the test pad 13 is perpendicular to the electrical connection surface of the chip body 11.

[0066] In this embodiment, the length and width of the test pad 13 are both greater than 70 μm, ensuring that the test pad 13 provides a large area for probe contact during wafer-level testing of the photonic chip 10. This reduces the difficulty of electrically connecting the probe to the test pad 13, thereby improving the efficiency of wafer-level testing of the photonic chip 10. The thickness of the test pad 13 is greater than 1 μm to prevent the probe from scratching the test pad 13 during wafer-level testing of the photonic chip 10, ensuring that wafer-level testing of the photonic chip 10 will not cause damage to the photonic chip 10.

[0067] optical module

[0068] Figure 6 and Figure 7 A schematic diagram of an optical module 20 according to an embodiment of the present disclosure is shown. (As shown) Figure 6 and Figure 7 As shown, the optical module 20 includes a printed circuit board 21 and a photonic chip 10. The photonic chip 10 can be any of the photonic chips described in the above embodiments. The photonic chip 10 is electrically connected to the printed circuit board 21. The photonic chip 10 can be electrically connected to the printed circuit board 21 using a flip-chip method or a wire bonding method.

[0069] It should be noted that, in addition to the printed circuit board 21 and the photonic chip 10, the optical module 20 may also include other components. For example, when the optical module 20 is used to convert electrical signals into optical signals, it may also include a light source, a coupling lens, an isolator, a fiber optic array, and a heat sink. When the optical module 20 is used to convert optical signals into electrical signals, it may also include a fiber optic array and a coupling lens.

[0070] In one possible implementation, the photonic chip 10 further includes multiple virtual pads and multiple hybrid pads disposed on the electrical connection surface. The virtual pads are disposed in areas of the electrical connection surface where no ball-mounted pads are provided. The virtual pads are not electrically connected to the internal circuitry of the chip body, while the hybrid pads are electrically connected to the internal circuitry of the chip body. The hybrid pads do not need to be tested during wafer-level testing of the photonic chip 10. The structure of the photonic chip can be found in [reference needed]. Figure 4 .

[0071] like Figure 6 As shown, when the photonic chip 10 is electrically connected to the printed circuit board 21 using a flip-chip method, both the ball pads and the hybrid pads are electrically connected to the printed circuit board 21 via solder balls 17, and the virtual pads are also connected to the printed circuit board 21 via solder balls 17. Since the virtual pads are not electrically connected to the internal circuitry of the chip itself, and the virtual pads are connected to the non-energized pads of the printed circuit board 21 via solder balls 17, the connection between the virtual pads and the printed circuit board 21 is only mechanical, not electrical.

[0072] like Figure 7 As shown, when the photonic chip 10 is electrically connected to the printed circuit board 21 via wire bonding, the test pads and hybrid pads are electrically connected to the printed circuit board 21 via metal wires. The ball pads and virtual pads are not directly connected to the pads of the printed circuit board 21.

[0073] It should be noted that the optical module in this embodiment is a specific application of the photonic chip in the foregoing embodiment. The structure and beneficial effects of the photonic chip in the optical module can be found in the description of the foregoing photonic chip embodiment, and will not be repeated here.

[0074] electronic devices

[0075] This disclosure also provides an electronic device that includes the optical module 20 in any of the above embodiments.

[0076] Electronic devices can be servers or switches within a data center. A data center is a globally collaborative network of specific devices used to transmit, accelerate, display, compute, and store data information on the internet network infrastructure. In the future, data centers will also become a competitive asset for enterprises. Servers are the processing and storage entities within a data center; the processing and storage of massive amounts of data in a data center are performed by servers.

[0077] Switches in a data center include access switches, aggregation switches, and core switches. Access switches are used to connect servers to aggregation switches. One access switch can connect multiple servers. Access switches are typically located at the top of the rack, so they are also called top-of-rack switches, and they physically connect the servers. Each aggregation switch can connect multiple access switches and provide other services such as firewalls, intrusion detection, and network analytics. Core switches provide high-speed forwarding of packets entering and leaving the data center and provide connectivity to aggregation switches.

[0078] The optical module 20 can be connected to other components in electronic devices. The optical module 20 can be connected to network cards, switches, etc. through the gold fingers included in the printed circuit board 21. The optical module 20 used for transmitting and the optical module 20 used for receiving are connected through optical fiber to realize data transmission between the server and the switch, as well as between different switches.

[0079] It should be noted that the electronic device in this disclosure is a specific application of the photonic chip and optical module in the foregoing embodiments. The structure and beneficial effects of the optical module in the electronic device can be found in the descriptions of the foregoing optical module embodiments and photonic chip embodiments, and will not be repeated here.

[0080] Photonic chip testing methods

[0081] Figure 8 A flowchart illustrating a photonic chip testing method according to an embodiment of this disclosure is shown, used to test the photonic chip 10 in any of the above embodiments. Figure 8 As shown, the photonic chip testing method includes the following steps:

[0082] Step 801: Obtain a wafer containing multiple photonic chips.

[0083] As an intermediate product in the manufacturing process of photonic chips, a wafer integrates multiple uncut photonic chips. The obtained wafer has undergone previous manufacturing processes (such as photolithography, chemical mechanical polishing, doping, etc.), and the photonic chips contained in the wafer already have the corresponding functions.

[0084] Step 802: Connect the probes connected to the test equipment to the test pads included in the photonic chip to make the probes electrically connected to the test pads.

[0085] The testing equipment is connected to multiple probes. When performing wafer-level testing on the photonic chip through the testing equipment, the probes are brought into contact with the test pads included in the photonic chip. At the same time, the probes and test pads are electrically connected to establish an electrical connection channel between the testing equipment and the photonic chip, so that the test signal can be transmitted between the two, providing a signal path for subsequent wafer-level testing.

[0086] The testing equipment can electrically connect to multiple photonic chips included in a wafer via multiple probes to simultaneously test multiple photonic chips, thereby improving the efficiency of photonic chip testing. The probes electrically connected to the test pads can be multiple independent probes or probe cards containing multiple probes.

[0087] Step 803: Perform wafer-level testing on the photonic chip using testing equipment.

[0088] The testing equipment can generate test signals (such as voltage, current, digital signals, etc.) and input the test signals into the photonic chip through probes. At the same time, the probes can collect the output signals of the photonic chip and analyze the results.

[0089] In this embodiment, since the photonic chip includes test pads electrically connected to the ball-mount pads, during wafer-level testing of the photonic chip, the probes contact the test pads to establish a signal path between the testing equipment and the photonic chip. During wafer-level testing, the probes do not contact the ball-mount pads, thus ensuring the quality of the ball-mounting pads while performing wafer-level testing, improving the testing efficiency of the photonic chip. The test pads, while providing probe contact points, can also be electrically connected to the metal wires used for wire bonding, making the photonic chip suitable for both flip-chip and wire-bonded packaging. This eliminates the need for separate photonic chip designs for different packaging forms, thereby reducing the design cost of the photonic chip.

[0090] In one possible implementation, if the photonic chip is packaged using a flip-chip method, after testing the multiple photonic chips included in the wafer, balls can be placed on the surfaces of the ball pads, virtual pads, and hybrid pads included in the photonic chip, thereby forming solder balls on the surfaces of the ball pads, virtual pads, and hybrid pads.

[0091] In this embodiment of the disclosure, since the solder balls formed by the ball-planting process protrude from the electrical connection surface of the chip body, that is, the solder balls are higher than the test pads, the solder balls that protrude from the test pads will hinder the movement of the probes. In order to facilitate the contact between the probes and the test pads during wafer-level testing, after the testing of the photonic chips included in the wafer is completed, balls are then planted on the surface of the ball-planting pads, virtual pads and hybrid pads, thereby reducing the difficulty of wafer-level testing and improving the efficiency of wafer-level testing.

[0092] In one possible implementation, after wafer-level testing of the photonic chips included in the wafer is completed, the wafer can be diced to obtain multiple independent photonic chips. Then, one or more photonic chips to be tested can be extracted from the multiple independent photonic chips. Then, probes are brought into contact with the hybrid pads included in the photonic chip to be tested or the solder balls disposed on the surface of the hybrid pads to make the probes electrically connected to the hybrid pads. Then, the photonic chip to be tested is subjected to die-level testing through testing equipment.

[0093] Since wafer-level testing does not test the pins corresponding to mixed pads, after wafer dicing is completed, photonic chips to be tested are randomly selected from multiple independent photonic chips obtained from dicing in a sampling manner. Then, the photonic chips to be tested are subjected to die-level testing by testing equipment to test the pins of the photonic chips that were not tested during the wafer-level testing process.

[0094] If ball bonding is performed on the surface of the ball-mounted pads, dummy pads, and hybrid pads after wafer-level testing, the probes will be electrically connected to the solder balls on the hybrid pad surface during die-level testing. The probes will be indirectly electrically connected to the hybrid pads through the solder balls. Since photonic chips that have undergone die-level testing typically do not flow into subsequent packaging processes—meaning they are not sold or used as final products—even if the probes damage the solder balls on the hybrid pad surface during die-level testing, there will be no negative impact.

[0095] If the photonic chip is packaged using wire bonding, since no balls are placed on the surface of the hybrid pads, the probes can be directly electrically connected to the hybrid pads during die-level testing.

[0096] In this embodiment of the disclosure, after performing wafer-level testing on the photonic chips included in the wafer and dicing the wafer to obtain multiple independent photonic chips, a photonic chip to be tested is then selected from these multiple independent photonic chips and subjected to die-level testing. Performing die-level testing on the photonic chips in a sampling manner allows for the testing of pins that were not tested in the wafer-level testing, ensuring the comprehensiveness of the photonic chip testing.

[0097] It should be noted that the photonic chip testing method of this disclosure is based on the photonic chip in the foregoing embodiments. The structure, testing process and beneficial effects of the photonic chip can be found in the description of the foregoing photonic chip embodiments, and will not be repeated here.

[0098] It should be understood that the various embodiments in this description are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0099] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0100] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0101] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A photonic chip, comprising a chip body, wherein the electrical connection surface of the chip body is provided with a plurality of ball pads and a plurality of test pads, each ball pad being electrically connected to at least one test pad through a metal trace in the chip body, and the ball pad being electrically connected to the internal circuitry of the chip body; The test pads are used to provide contact points for probes when performing wafer-level testing on the photonic chip.

2. The photonic chip according to claim 1, wherein, The electrical connection surface of the chip body is provided with multiple virtual pads. The virtual pads are located in the area of ​​the electrical connection surface where the ball pads are not provided, and the virtual pads are not electrically connected to the internal circuit.

3. The photonic chip according to claim 2, wherein, The electrical connection surface of the chip body is provided with multiple hybrid pads, which are electrically connected to the internal circuit. When performing wafer-level testing on the photonic chip, the hybrid pads do not need to be tested. The hybrid pad is used for ball bonding or for electrical connection with a metal wire, which is used for wire bonding.

4. The photonic chip according to claim 3, wherein, The hybrid pad is disposed on the electrical connection surface in the region of the first side of the chip body, and the second side of the chip body is provided with an optical port. The first side and the second side of the chip body are opposite to each other. At least one of the test pads is disposed on the electrical connection surface near the third side of the chip body, and at least one of the test pads is disposed on the electrical connection surface near the fourth side of the chip body, wherein the third side and the fourth side of the chip body are opposite to each other. The ball-mounted pad is located inside the connected test pad, and the virtual pad is located inside the ball-mounted pad.

5. The photonic chip according to claim 3, wherein, The photonic chip is configured to be electrically connected to the printed circuit board via a flip-chip method, and solder balls are provided on the surfaces of the ball pads, the virtual pads, and the hybrid pads.

6. The photonic chip according to claim 3, wherein, The photonic chip is configured to be electrically connected to a printed circuit board via wire bonding, and no solder balls are placed on the surfaces of the ball pads, the virtual pads, and the hybrid pads.

7. The photonic chip according to any one of claims 1-6, wherein, The length and width of the test pad are both greater than 70 micrometers, and the thickness of the test pad is greater than 1 micrometer.

8. An optical module, comprising: Printed circuit boards and photonic chips; The photonic chip includes a chip body, and the electrical connection surface of the chip body is provided with a plurality of ball pads and a plurality of test pads. Each ball pad is electrically connected to at least one test pad through a metal trace in the chip body, and the ball pad is electrically connected to the internal circuit of the chip body. The test pad is used to provide contact points for probes when performing wafer-level testing on the photonic chip. The photonic chip is electrically connected to the printed circuit board.

9. The optical module according to claim 8, wherein, The photonic chip also includes a plurality of virtual pads and a plurality of hybrid pads disposed on the electrical connection surface. The virtual pads are disposed in the area of ​​the electrical connection surface where the ball-mounted pads are not disposed. The virtual pads are not electrically connected to the internal circuitry. The hybrid pads are electrically connected to the internal circuitry. The hybrid pads do not need to be tested when the photonic chip is subjected to wafer-level testing. Both the ball-mounted pads and the hybrid pads are electrically connected to the printed circuit board via solder balls, and the virtual pads are connected to the printed circuit board via solder balls; alternatively, the test pads and the hybrid pads are electrically connected to the printed circuit board via metal wires.

10. An electronic device comprising the optical module as described in claim 8 or 9.

11. A photonic chip testing method for testing a photonic chip according to any one of claims 1-7, the method comprising: Obtain a wafer comprising multiple of the aforementioned photonic chips; The probe connected to the test equipment is brought into contact with the test pads included in the photonic chip, so that the probe is electrically connected to the test pads; The photonic chip is subjected to wafer-level testing using the aforementioned testing equipment.

12. The method according to claim 11, wherein, After testing the multiple photonic chips included in the wafer, balls are placed on the surface of the ball pads, virtual pads, and hybrid pads included in the photonic chips.

13. The method according to claim 11 or 12, further comprising: After testing the multiple photonic chips included in the wafer, the wafer is diced to obtain multiple independent photonic chips; At least one photonic chip to be tested is selected from a plurality of independent photonic chips; The probe is brought into contact with the hybrid pads of the photonic chip under test or the solder balls disposed on the surface of the hybrid pads, so that the probe is electrically connected to the hybrid pads; The photonic chip under test is subjected to die-level testing using the aforementioned testing equipment.

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