EMI shielding for flip chip package with exposed die backside

Abstract

The invention relates to EMI shielding for flip chip packages with exposed die backside. A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and the substrate, wherein a surface of the semiconductor die is exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with a surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heat sink bonded to a semiconductor die by a solder layer. A second shielding layer may be formed over a side surface of the semiconductor die.

Description

[0001] This application is a continuation-in-part of the patent application with the application number 201910734211.0, the filing date of 2019.08.09, and the invention name of “EMI shielding for flip-chip packages with exposed die backside”. TECHNICAL FIELD

[0002] The present invention relates generally to semiconductor devices, and more specifically, to semiconductor packages with electromagnetic interference (EMI) shielding formed over an exposed die backside. BACKGROUND

[0003] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight to electricity, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computing, entertainment, and consumer products.

[0004] Semiconductor devices are often susceptible to electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, or other inter-device interference such as capacitive, inductive, or conductive coupling, also known as crosstalk, which can interfere with the operation of the semiconductor device. High-speed switching of digital circuits also generates interference.

[0005] Conductive layers are often formed over semiconductor packages to shield electronic parts within the package from EMI and other interference. Shielding layers absorb EMI before the signals can hit the semiconductor die and discrete components within the package, which can otherwise cause malfunction of the device. Shielding layers are also formed over packages with components that are expected to generate EMI to protect nearby devices from malfunction.

[0006] Many factors can make proper EMI shielding difficult. Many prior art shielding methods do not allow for sufficient heat dissipation, and are unable to produce semiconductor packages with low enough profiles to meet the needs of today’s consumers. Therefore, there is a need for improvements in EMI shielding and manufacturing methods. SUMMARY

[0007] A semiconductor device according to the present invention includes a substrate, a semiconductor die disposed over the substrate, an encapsulant deposited over the semiconductor die and substrate, wherein a surface of the semiconductor die is exposed from the encapsulant, and a first shield layer formed over the semiconductor die, wherein the first shield layer includes multiple layers. Preferably, the first shield layer includes a stainless steel layer in contact with the surface of the semiconductor die, and a copper layer formed over the stainless steel layer.

[0008] The first shield layer further includes a protective layer formed over the copper layer. The semiconductor device further includes a solder layer formed over the first shield layer, and / or further includes a heat spreader bonded to the semiconductor die via the solder layer, and / or further includes a second shield layer formed over a side surface of the semiconductor die.

[0009] Another semiconductor device according to the present invention includes a semiconductor die, an encapsulant deposited over the semiconductor die, and a first shield layer formed over the semiconductor die, wherein the first shield layer includes multiple layers. Preferably, the first shield layer includes a first stainless steel layer. The first shield layer can include a copper layer formed over the first stainless steel layer, and a second stainless steel layer formed over the copper layer. The semiconductor device further includes a second shield layer formed over a side surface of the semiconductor die, and a conductive trace coupled between a contact pad of the semiconductor die and the second shield layer.

[0010] A method of manufacturing a semiconductor device according to the present invention includes providing a semiconductor die, depositing an encapsulant over the semiconductor die, wherein a surface of the semiconductor die is exposed from the encapsulant, and forming a shield layer over the surface of the semiconductor die, wherein the shield layer includes multiple layers. Preferably, the method further includes disposing a mask layer over the shield layer, depositing a solder paste in an opening of the mask layer, removing the mask layer, and reflowing the solder paste after removing the mask layer. The method further includes disposing a heat spreader over the solder paste.

[0011] The method further includes providing a semiconductor wafer including the semiconductor die, forming a trench in the semiconductor wafer adjacent to the semiconductor die, depositing a conductive material into the trench, and singulating the semiconductor die from the semiconductor wafer via the trench after depositing the conductive material. The method further includes forming a conductive trace over the semiconductor die and connected to the conductive material. Attached Figure Description

[0012] Figures la-lc The illustration shows a semiconductor wafer with multiple semiconductor dies separated by saw streets; Figures 2a-2d The illustration shows the formation of a flip-chip package with an exposed back side of a semiconductor die; Figures 3a-3c The diagram illustrates the shielding layer formed on top of the flip chip package; Figures 4a-4e The illustration shows the formation of an EMI shielding layer on the side surface of a semiconductor die; Figure 5a and 5b An embodiment of a flip-chip package with a semiconductor die having side-surface EMI shielding is illustrated. Figure 6a and 6b The diagram illustrates options for forming a shielding layer with multiple layers; Figures 7a-7f The illustration shows the addition of a heat spreader on top of the EMI shielding layer; and Figure 8 The illustration shows printed circuit boards (PCBs) with different types of packages that are mounted to the surface of a PCB. Detailed Implementation

[0013] The invention is described in one or more embodiments in the following description with reference to the accompanying drawings, wherein similar reference numerals denote the same or similar elements. While the invention has been described in accordance with the best mode for carrying out its objectives, it will be appreciated by those skilled in the art that it is intended to cover substitutions, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. As used herein, the term "semiconductor die" refers to both the singular and plural forms, and therefore may refer to both a single semiconductor device and multiple semiconductor devices.

[0014] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create the voltage and current relationships necessary to perform the circuit's function.

[0015] Back end manufacturing refers to the cutting or singulation of finished wafers into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor dies, the wafer is scribed and broken along non-functional areas of the wafer, referred to as streets or scribe lines. The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor dies are then connected to the contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wire bonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device can be used with other system components.

[0016] Figure la A semiconductor wafer 100 having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support, is shown. A plurality of semiconductor dies or components 104 are formed on the wafer 100 separated by non-active, inter-die wafer areas or streets 106. The streets 106 provide cutting areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0017] Figure lb A cross-sectional view of a portion of the semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuitry can include one or more transistors, diodes and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as a digital signal processor (DSP), application specific integrated circuit (ASIC), memory, or other signal processing circuitry. The semiconductor die 104 can also contain IPDs, such as inductors, capacitors and resistors formed in or on interconnect layers over the surface of the semiconductor die for RF signal processing.

[0018] A conductive layer 112 is formed over the active surface 110 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition process. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive material. The conductive layer 112 functions as a contact pad for electrically connecting to circuitry of the active surface 110, and can include conductive traces for horizontal wiring.

[0019] A conductive bump material is deposited over the conductive layer 112 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, and combinations thereof with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In some embodiments, the bump material is reflowed to form balls or bumps 114 by heating the material above its melting point. In one embodiment, the bumps 114 are formed over under bump metallization (UBM) having a wetting layer, barrier layer, and adhesion layer. The bumps 114 can also be compression bonded or thermocompression bonded to the conductive layer 112. The bumps 114 represent one type of interconnect structure that can be formed over the conductive layer 112. Interconnect structures can also use bond wires, conductive paste, stud bumps, micro bumps, or other electrical interconnects.

[0020] In Figure lc the semiconductor wafer 100 is singulated into individual semiconductor dies 104 via the saw lanes 106 using a saw blade or laser cutting tool 118. The individual semiconductor dies 104 can be inspected and electrically tested for identification of known good dies (KGD) after singulation.

[0021] Figures 2a-2d A process of forming a flip chip package having an exposed semiconductor die backside is illustrated. Figure 2a A cross-sectional view of a substrate 120 including a conductive layer 122 and an insulating layer 124 is shown. The conductive layer 122 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. The conductive layer 122 includes conductive traces for horizontal electrical interconnect across the substrate 120, contact pads for interconnection with other devices, and conductive vias for vertical electrical interconnect between a surface 126 and a surface 128 of the substrate.

[0022] Depending on the design and functionality of the semiconductor die 104, portions of the conductive layers 122 can be electrically common or electrically isolated. The insulating layer 124 comprises one or more layers of silicon dioxide (Si02), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta205), aluminum oxide (AI2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The insulating layer 124 provides isolation between the conductive layers 122. The substrate 120 also includes a core material 130, such as glass fabric, to reinforce the substrate and reduce warpage.

[0023] In Figure 2b , the semiconductor die 104 from Figure lc is positioned over the substrate 120 using a pick-and-place operation, with the active surface 110 and bumps 114 oriented toward the surface 126. Discrete components 136 are also positioned over the surface 126 of the substrate 120. In one embodiment, the discrete components 136 are discrete active devices, such as diodes, transistors, or voltage regulators, or discrete passive devices, such as resistors, capacitors, inductors, or RF filters. Any combination of active and passive devices can be provided on the substrate 120 along with the semiconductor die 104 to achieve the desired electrical functionality.

[0024] Figure 2c The semiconductor die 104 is shown bonded to a first portion of the conductive layers 122 through the reflow of the bumps 114. The discrete components 136 are bonded to another portion of the conductive layers 122 of the substrate 120 using solder bumps or conductive paste 138.

[0025] In Figure 2c , a sealant or molding compound 140 is deposited over the substrate 120, semiconductor die 104, and discrete electrical devices 136 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or another suitable applicator. The sealant 140 can be a polymeric composite material, such as an epoxy, an epoxy acrylate, or a polymer with or without fillers. The sealant 140 is electrically non-conductive, provides structural support, and environmentally protects the semiconductor devices from external elements and contaminants.

[0026] The encapsulant 140 is deposited with the back surface 108 of the semiconductor die 104 exposed from the encapsulant. The back surface of the encapsulant 140 is coplanar with the back surface 108 of the semiconductor die 104. In some embodiments, the encapsulant 140 is deposited using film assisted molding or by another suitable molding process where a mold plate is in contact with the back surface 108 to keep the top of the semiconductor die 104 free of the encapsulant 140. In other embodiments, the encapsulant 140 is deposited to cover the semiconductor die 104 and then back ground to expose the back surface 108.

[0027] In Figure 2d , a conductive bump material is deposited over the conductive layer 122 on the surface 128 of the substrate 120 using an evaporation, electroplating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder, or lead free solder. The bump material is bonded to the conductive layer 122 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed to form the balls or bumps 142 by heating the material above its melting point. In some embodiments, the bumps 142 are formed over UBMs with wetting, barrier, and adhesion layers. The bumps 142 can also be compression bonded or thermocompression bonded to the conductive layer 122. The bumps 142 represent one type of interconnect structure that can be formed over the conductive layer 122. The interconnect structure can also use bond wires, conductive paste, stud bumps, micro bumps, or other electrical interconnects. In another embodiment, the conductive layer 122 remains exposed as a land grid array without additional interconnect structures. The bumps 142 are electrically connected to the semiconductor die 104 and the discrete component 136 through the conductive layer 122, the bumps 114, and the solder paste 138.

[0028] Figures 3a-3c An EMI shield layer is formed over the flip chip package from Figure 2d . Figure 3a A package 160 is shown with an EMI shield layer 162 formed over the top and side surfaces of the package. Typically, the semiconductor package 160 is formed as part of a sheet of many identical packages. The sheet of devices can be disposed on a carrier with the bumps 142 contacting the carrier and then the sheet is singulated via the substrate 120 and the encapsulant 140 using a water cutting tool, a laser cutting tool, or a saw blade to physically separate the plurality of packages 160.

[0029] A conductive material is deposited over the encapsulation 160 to form a conformal shielding layer 162. The shielding layer 162 is formed by any suitable metal deposition technique, such as chemical vapor deposition, physical vapor deposition, other sputtering methods, spray coating, or electroplating. The shielding layer 162 completely covers the semiconductor dies 104, encapsulant 140, and exposed top and side surfaces of the substrate 120. Prior to forming the shielding layer 162, singulation of the panel of encapsulations 160 exposes the side surfaces of each encapsulation so that the shielding layer is formed under the side surfaces to contact the substrate 120. The shielding layer 162 physically and electrically contacts the conductive layer 122, which can be used to connect the shielding layer to a ground voltage or other reference voltage node via bumps 142. The shielding layer 160 directly contacts the back surface 108 of the semiconductor dies 104, which improves heat dissipation.

[0030] Figure 3b A semiconductor package 170 is illustrated with a shielding layer 172. The shielding layer 172 is similar to the shielding layer 162, except that the shielding layer 172 is formed over the top surface of the package 170 instead of over the side surfaces. The shielding layer 172 can be formed using similar methods as the shielding layer 162, but where singulation occurs after instead of before the shielding layer is formed. The packages 170 remain physically connected to each other in the panel during formation of the shielding layer 172, which blocks the shielding layer from covering the side surfaces of the final device. The shielding layer 172 still covers the top of the packages 170 to reduce EMI and directly contacts the semiconductor dies 104 to dissipate heat.

[0031] Figure 3c A semiconductor package 180 is illustrated with a shielding layer 182. The shielding layer 182 is similar to the shielding layers 162 and 172, but is formed only on or over the back surface 108 of the semiconductor dies 104 instead of on the encapsulant 140. In some embodiments, a photolithographic mask layer is deposited over the panel of packages and is patterned to expose the semiconductor dies 104. When the mask is subsequently removed, the metal layer is removed over the encapsulant 140 along with the mask, but it remains over the semiconductor dies 104 as the shielding layer 182. In other embodiments, a strip of tape is used to cover the encapsulant 140 between the semiconductor dies 104. Multiple vertically aligned strips of tape can be used to cover the encapsulant 140 on all four sides of the semiconductor dies 104, leaving the semiconductor dies exposed for deposition of the shielding layer 182.

[0032] Figures 4a-4e A method of processing a semiconductor wafer 100 into semiconductor dies 104 that are alternatives to Figures la-lc and result in semiconductor dies with shielding layers over the side surfaces. Figure 4aA semiconductor wafer 100 is shown with devices formed in the active surface 110 but prior to formation of the conductive layer 112. In Figure 4b In

[0033] The trench 200 is formed by deep reactive ion etching (DRIE), chemical etching, a saw blade, or another suitable process. The trench 200 extends only partially through the wafer 100 so that the semiconductor dies 104 remain physically connected by the semiconductor material 102 within the saw street 106. In other embodiments, the trench 200 extends completely through the wafer 100 to separate the semiconductor dies 104, and the relative position of the semiconductor dies is maintained by adhesive material on the carrier.

[0034] In Figure 4c The trench 200 is filled with a conductive material to form a shield layer 202 around each semiconductor die 104. Any suitable metal deposition technique can be used. The conductive layer 112 is formed before or after the shield layer 202 using any of the materials and methods discussed above. In other embodiments, the conductive layer 112 is formed in the same metal deposition step as the shield layer 202. The conductive layer 112 optionally includes conductive traces or other structures that extend from the contact pads to physical and electrical contact with the shield layer 202, which can be used to connect the shield layer to a ground node for improved shielding. Bumps 114 are formed on the contact pads of the conductive layer 112 as described above.

[0035] In Figure 4d The wafer 100 is flipped onto another carrier so that the back surface 108 is presented. The back surface 108 is back lapped to reduce the thickness of the wafer 100 and expose the shield layer 202. The semiconductor material 102 over the shield layer 202 is removed by back lapping or another suitable process. In Figure 4e In Figure lc The semiconductor dies 104 are singulated as in

[0036] Figure 5a And 5b A shielded package with a shield layer 202 formed using the semiconductor dies 104 in Figure 4d is illustrated. In Figure 5a In Figure 2bThe semiconductor die 104 and discrete components 136 are disposed on the substrate 120 as in Figure 2c The encapsulant 140 is deposited as in Figure 5a The shield layer 162 is formed over the top and side surfaces of the package as in

[0037] In Figure 5b The shield layer 182 is formed over the semiconductor die 104 instead of over the encapsulant 140. The shield layer 182 can be electrically connected to a ground node via the shield layer 202, the conductive layer 112, the bump 114, the conductive layer 122, and the bump 142. The shield layers 202 and 182 combine over the top and all side surfaces of the semiconductor die 104 to form a shield. Figure 5a and 5b Two particular embodiments are shown, but any of the shield layers 162, 172, or 182 can be used in combination with the shield layer 202, with or without the conductive layer 112 in contact with the shield layer 202.

[0038] Figure 6a and 6b The shield layer 162 is shown as optionally formed as a plurality of discrete layers. First, a stainless steel layer 210 is formed directly over the semiconductor die 104 and the encapsulant 140, if desired. The stainless steel layer 210 functions as an adhesion layer. Other suitable adhesion layer materials are used in other embodiments instead of stainless steel. A copper layer 212 is formed over the stainless steel layer 210. The copper layer 212 is strongly adhered to the die 104 by virtue of the stainless steel layer 210.

[0039] The copper layer 212 can remain as the top layer of the shield layer 162 as shown in Figure 6a Alternatively, a protective layer 214 can be formed over the copper layer 212 as shown in Figure 6b The protective layer 214 can be another stainless steel layer, a nickel layer, an organic solderability preservative (OSP) layer, or another suitable protective layer. Stainless steel is a good solution for reducing cost, while nickel is a good choice because nickel can be sputtered over the surface of the copper layer 212 using well-developed methods and provides good oxidation resistance. OSP treatment is an easy and low-cost copper surface protection solution. The protective layer 214 protects the copper layer 212 from external physical impact as well as oxidation and other chemical reactions.

[0040] Alternatively, the protective layer 214 can be a pre-solder layer based on tin or lead. The pre-solder can be applied using an easy solder paste printing method. In one embodiment, a tin-silver-copper (SnAgCu or SAC) solder paste or another tin-based material is used. The pre-solder is applied in an embodiment where a heat sink or other component will subsequently be soldered onto the top of the shield layer, as shown in Figures 7a-7f The layers 210-214 are deposited using any suitable deposition technique. Figure 6a The multi-layer structure shown in 6b may be used in any of the shield layers 162, 172, 182, and 202.

[0041] Figures 7a-7f A heat sink or heat spreader is added on top of the semiconductor package is illustrated. Figure 7a The package 160 from Figure 3a is shown. A mask layer 220 is formed on top of the faceplate of the package 160. The mask layer 220 includes a plurality of openings 222 that expose the shield layer 162. In Figure 7b solder or solder paste 224 is deposited or printed into the openings 222 of the mask layer 220. In some embodiments, the shield layer 162 has a multi-layer structure from Figure 6b where the top layer 214 is formed of a tin or lead-based pre-solder to facilitate reflow and adhesion of the solder 224.

[0042] Figure 7c and 7d The package 160 is shown where the mask layer 220 is removed after the solder 224 is deposited. Figure 7c is a cross-section, and Figure 7d is a plan view. In Figure 7e the solder 224 is melted into a uniform layer that covers the top of the package 160 on the shield layer 162. The solder 224 is deposited as a plurality of discrete portions and then melted into a single uniform layer to provide greater control over the total volume of solder applied and thus the final solder layer thickness. The thickness of the solder print can be challenging to deposit precisely for thin solder layers. The use of the mask layer 220 reduces the total footprint of the printed solder 224 when melted in Figure 7e increases the accuracy of the final thickness. Figure 7e The final thickness of the solder 224 in Figure 7b will be related proportionally to the thickness of the solder 224 in Figure 7a and also to the total footprint of the openings 222 in

[0043] In Figure 7fIn some embodiments, a heat spreader 230 is disposed on the solder layer 224. The solder layer 224 is reflowed to mechanically, thermally, and electrically connect the heat spreader 230 to the shield layer 162. Thermal energy is efficiently transferred from the semiconductor die 104 to the heat spreader 230 via the shield layer 162 and the solder layer 224. The heat spreader 230 includes fins to increase the total surface area, and thus the rate of transfer of thermal energy into the surrounding environment. The heat spreader 230 can be used with any of the above embodiments. For embodiments with a smaller shield layer 182, the heat spreader 230 can be made smaller to have a similar footprint as the shield layer.

[0044] Figure 8 An electronic device 240 is illustrated that includes a PCB 242 with a plurality of semiconductor packages mounted on a surface of the PCB, including a package 180 with a shield layer 182. Depending on the application, the electronic device 240 can have one type of semiconductor package or multiple types of semiconductor packages.

[0045] The electronic device 240 can be a stand-alone system that uses the semiconductor package to perform one or more electrical functions. Alternatively, the electronic device 240 can be a subassembly of a larger system. For example, the electronic device 240 can be part of a tablet computer, a cellular telephone, a digital camera, a communication system, or other electronic device. The electronic device 240 can also be a graphics card, a network interface card, or another signal processing card that is plugged into a computer. The semiconductor package can include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete active or passive device, or other semiconductor die or electrical component.

[0046] In some embodiments, Figure 8 The PCB 242 provides a common substrate for electrical interconnection and structural support of semiconductor packages mounted on the PCB. Conductive signal traces 244 are formed on a surface of the PCB 242 or within layers thereof using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. The signal traces 244 provide for electrical communication between the semiconductor package, mounted components, and other external systems or components. The traces 244 also provide power and ground connections to the semiconductor package as needed. By reflowing the bumps 142 onto the traces 244, the package 180 is physically and electrically connected to the PCB 242. In some embodiments, the traces 244 include contact pads for mounting the package 180.

[0047] In some embodiments, the semiconductor device has two levels of packaging. The first level of packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to the PCB 242. In other embodiments, the semiconductor device can have only the first level of packaging, where the die is mechanically and electrically mounted directly to the PCB 242.

[0048] For illustrative purposes, several types of first level packaging are shown on the PCB 242, including a wire bonded package 246 and a flip chip 248. In addition, several types of second level packaging are shown, including a ball grid array (BGA) 250, a bump chip carrier (BCC) 252, a land grid array (LGA) 256, a multi-chip module (MCM) 258, a quad flat no-lead package (QFN) 260, a quad flat package 262, and an embedded wafer level ball grid array (eWLB) 264 are mounted on the PCB 242 along with the package 180. Conductive traces 244 electrically couple the various packages and components disposed on the PCB 242 to the package 180, giving use of the components within the package to other components on the PCB.

[0049] Depending on the system requirements, any combination of semiconductor packages configured in any combination of first and second level packaging styles, as well as other electronic components, can be connected to the PCB 242. In some embodiments, the electronic device 240 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because the semiconductor packages include complex functionality, less expensive components and simplified manufacturing processes can be used to manufacture the electronic devices. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in lower costs to the consumer.

[0050] While one or more embodiments of the application have been illustrated and described, it will be appreciated that modifications and adaptations can be made to those embodiments without departing from the scope of the application as set forth in the following claims.

Claims

1. A method of manufacturing a semiconductor device, comprising: providing a semiconductor wafer comprising a plurality of semiconductor dies separated by a plurality of scribes; forming a trench within each of the scribes only partially in a first surface of the semiconductor wafer such that a second surface of the semiconductor wafer remains entirely planar across an entire footprint of the semiconductor wafer; depositing a conductive material into the trench to form a first shield layer surrounding each of the plurality of semiconductor dies; forming a first conductive layer on the first surface of the semiconductor wafer, wherein a portion of the first conductive layer extends to the first shield layer; disposing a plurality of first solder bumps on the first conductive layer; back grinding the second surface of the semiconductor wafer to expose the first shield layer at the second surface of the semiconductor wafer, wherein the first shield layer extends entirely through the semiconductor wafer after back grinding; singulating the semiconductor wafer through the first shield layer to separate the plurality of semiconductor dies, wherein each of the plurality of semiconductor dies remains entirely surrounded by the first shield layer; providing a substrate, the substrate comprising: an insulating layer, a glass fabric embedded in the insulating layer, a second conductive layer formed over a first surface of the insulating layer, wherein the second conductive layer extends to an edge of the substrate, a third conductive layer formed over a second surface of the insulating layer, wherein the third conductive layer extends to the edge of the substrate, and a conductive via extending through the insulating layer and glass fabric from the second conductive layer to the third conductive layer; mounting a first semiconductor die of the plurality of semiconductor dies onto the second conductive layer, wherein the first semiconductor die is attached to the second conductive layer by reflowing the first solder bumps; mounting a discrete component onto the second conductive layer adjacent to the first semiconductor die; depositing an encapsulant over the substrate, first semiconductor die, and discrete component, a back surface of the first semiconductor die being exposed from the encapsulant; forming a second shield layer over the encapsulant, wherein the second shield layer entirely covers the encapsulant and a top surface of the first semiconductor die and all side surfaces of the encapsulant and substrate, wherein the second shield layer is formed directly on and in direct physical contact with the first shield layer surrounding the first semiconductor die, and wherein the second shield layer is formed in direct physical contact with the second and third conductive layers at the edge of the substrate; and forming second solder bumps on the third conductive layer.

2. The method of claim 1, further comprising: disposing a mask layer over the second shield layer; depositing solder paste in openings of the second mask layer; removing the mask layer; and reflowing the solder paste after removing the mask layer.

3. The method of claim 1, wherein forming the second shield layer comprises: forming a stainless steel layer directly on the encapsulant and first semiconductor die; and forming a copper layer directly on the stainless steel layer. ​ ​ 4. The method of claim 3, wherein forming the second barrier layer further comprises forming a layer of nickel directly on the layer of copper.

5. The method of claim 3, wherein forming the second barrier layer further comprises forming an organic solderability preservative (OSP) directly on the layer of copper.

6. A method of manufacturing a semiconductor device, comprising: providing a semiconductor wafer comprising a plurality of semiconductor dies separated by a plurality of scribe lanes; forming a trench within each of the scribe lanes only partially in a first surface of the semiconductor wafer such that a second surface of the semiconductor wafer remains entirely planar across an entire footprint of the semiconductor wafer; depositing a conductive material into the trench to form a first barrier layer around each of the plurality of semiconductor dies; forming a first conductive layer on the first surface of the semiconductor wafer; disposing a plurality of first solder bumps on the first conductive layer; backgrinding the second surface of the semiconductor wafer to expose the first barrier layer at the second surface of the semiconductor wafer, wherein the first barrier layer extends entirely through the semiconductor wafer after backgrinding; singulating the semiconductor wafer through the first barrier layer to separate the plurality of semiconductor dies, wherein each of the plurality of semiconductor dies remains entirely surrounded by the first barrier layer; providing a substrate, the substrate comprising: an insulating layer, a glass fabric embedded in the insulating layer, a second conductive layer formed over a first surface of the insulating layer, wherein the second conductive layer extends to an edge of the substrate, a third conductive layer formed over a second surface of the insulating layer, wherein the third conductive layer extends to the edge of the substrate, and a conductive via extending through the insulating layer and glass fabric from the second conductive layer to the third conductive layer; mounting a first semiconductor die of the plurality of semiconductor dies onto the second conductive layer, wherein the first semiconductor die is attached to the second conductive layer by reflowing the first solder bumps; mounting a discrete component onto the second conductive layer adjacent to the first semiconductor die; depositing an encapsulant over the substrate, first semiconductor die, and discrete component, a back surface of the first semiconductor die being exposed from the encapsulant; forming a second barrier layer over the encapsulant, wherein the second barrier layer entirely covers the encapsulant and a top surface of the first semiconductor die and all side surfaces of the encapsulant and substrate, wherein the second barrier layer is formed directly on and in direct physical contact with the first barrier layer surrounding the first semiconductor die, and wherein the second barrier layer is formed in direct physical contact with the second and third conductive layers at the edge of the substrate; and forming second solder bumps on the third conductive layer.

7. The method of claim 6, further comprising: disposing a mask layer over the second barrier layer; depositing solder paste in openings of the second mask layer; removing the mask layer; and reflowing the solder paste after removing the mask layer. ​ 8. The method of claim 6, wherein forming the second shield layer comprises: forming a layer of stainless steel directly on the encapsulant and first semiconductor die; and forming a layer of copper directly on the layer of stainless steel.

9. The method of claim 8, wherein forming the second shield layer further comprises forming a layer of nickel directly on the layer of copper.

10. The method of claim 8, wherein forming the second shield layer further comprises forming an organic solderability preservative (OSP) directly on the layer of copper.

11. A method of manufacturing a semiconductor device, comprising: providing a semiconductor wafer comprising a plurality of semiconductor dies separated by a plurality of scribes; forming a trench within each of the scribes only partially in a first surface of the semiconductor wafer such that a second surface of the semiconductor wafer remains completely planar across an entire footprint of the semiconductor wafer; depositing a conductive material into the trench to form a first shield layer around each of the plurality of semiconductor dies; forming a first conductive layer on the first surface of the semiconductor wafer, wherein a portion of the first conductive layer extends to the first shield layer; disposing a plurality of first solder bumps on the first conductive layer; back grinding the second surface of the semiconductor wafer to expose the first shield layer at the second surface of the semiconductor wafer, wherein the first shield layer extends completely through the semiconductor wafer after back grinding; singulating the semiconductor wafer through the first shield layer to separate the plurality of semiconductor dies, wherein each of the plurality of semiconductor dies remains completely surrounded by the first shield layer; providing a substrate, the substrate comprising: an insulating layer, a glass fabric embedded in the insulating layer, a second conductive layer formed over a first surface of the insulating layer, a third conductive layer formed over a second surface of the insulating layer, and a conductive via extending through the insulating layer and glass fabric from the second conductive layer to the third conductive layer; mounting a first semiconductor die of the plurality of semiconductor dies onto the second conductive layer, wherein the first semiconductor die is attached to the second conductive layer by reflowing the first solder bumps; mounting a discrete component onto the second conductive layer adjacent to the first semiconductor die; depositing an encapsulant over the substrate, first semiconductor die, and discrete component, a back surface of the first semiconductor die exposed from the encapsulant; forming a second shield layer over the encapsulant, wherein the second shield layer completely covers a top surface of the first semiconductor die, and wherein the second shield layer is formed directly on and in direct physical contact with the first shield layer around the first semiconductor die; and forming a second solder bump on the third conductive layer.

12. The method of claim 11, further comprising: disposing a mask layer over the second shield layer; depositing solder paste in openings of the second mask layer; removing the mask layer; and reflowing the solder paste after removing the mask layer. ​ 13. The method of claim 11, wherein forming the second shield layer comprises: forming a stainless steel layer directly on the encapsulant and first semiconductor die; and forming a copper layer directly on the stainless steel layer.

14. The method of claim 13, wherein forming the second shield layer further comprises forming a nickel layer directly on the copper layer.

15. The method of claim 13, wherein forming the second shield layer further comprises forming an organic solderability preservative (OSP) directly on the copper layer.

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