Semiconductor device
By placing capacitors above switching elements in semiconductor devices and taking advantage of the capacitor's width, parasitic inductance and magnetic field cancellation are reduced, solving the problems of ringing peaks and increased component space, and achieving miniaturization and efficient design of the device.
Patent Information
- Application Number
- CN202411141792.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-05-21
- Filing Date
- 2024-08-20
- Publication Date
- 2025-11-21
Smart Images
Figure CN120998918A_ABST
Abstract
Description
[0001] Reference to relevant applications
[0002] This application enjoys priority based on Japanese Patent Application No. 2024-082651 (filed on May 21, 2024). This application includes all contents of the basic application by reference to that basic application. Technical Field
[0003] The implementation methods involve semiconductor devices. Background Technology
[0004] A semiconductor device is known, comprising a semiconductor chip and a resin that seals the semiconductor chip. The semiconductor device requires high-speed response and miniaturization. Summary of the Invention
[0005] The problem to be solved by the present invention is to provide a semiconductor device that can suppress component space while reducing ringing peaks.
[0006] The semiconductor device of this embodiment includes a first switching element, a second switching element, and a capacitor. The second switching element is electrically connected to the first switching element. The capacitor has a first terminal, a second terminal, and a capacitor portion, one end of which is electrically connected to the first terminal and the other end of which is electrically connected to the second terminal. The first terminal is electrically connected to the first switching element. The second terminal is electrically connected to the second switching element. The capacitor portion is located above the first and second switching elements along a first direction. The width of the capacitor portion in the second direction, i.e., the direction in which one end of the capacitor portion is connected to the other end, is greater than the width of the combination of the first and second switching elements in the second direction. The first and second switching elements are arranged in the second direction. Attached Figure Description
[0007] Figure 1 This is a perspective view showing an example of the structure of the semiconductor device according to the first embodiment.
[0008] Figure 2 This is a perspective view showing an example of the structure of the semiconductor device of the first embodiment as viewed from below.
[0009] Figure 3 This is an example of the cross-sectional structure of the semiconductor device according to the first embodiment, and it is along... Figure 1 A cross-sectional view of line III-III.
[0010] Figure 4 This is an example of the cross-sectional structure of the semiconductor device according to the first embodiment, and it is along... Figure 3 A cross-sectional view of line IV-IV.
[0011] Figure 5This is a circuit diagram illustrating an example of the electronic circuitry of the semiconductor device according to the first embodiment.
[0012] Figure 6 This is a conceptual diagram illustrating an example of a case where a high-frequency signal is input to the semiconductor device of the first embodiment. Detailed Implementation
[0013] The embodiments will now be described with reference to the accompanying drawings.
[0014] The accompanying drawings are illustrative; the relationship between thickness and planar dimensions, and the ratio of thicknesses of different layers, may differ from reality. Furthermore, the drawings may also include dimensional relationships and ratios between different elements.
[0015] The implementation method will be described below using an XYZ orthogonal coordinate system. Sometimes the positive direction of the vertical axis of the graph is called the top, and the negative direction is called the bottom. Sometimes the positive direction of the horizontal axis of the graph is called the right side, and the negative direction is called the left side. That is, in the top view representing the XY plane (XY plane view (hereinafter the same)), the top refers to the +Y direction, the bottom refers to the -Y direction, the right side refers to the +X direction, and the left side refers to the -X direction.
[0016] To facilitate observation of the accompanying drawings, shading lines have been appropriately added to the top view. The shading lines in the top view are not necessarily related to the raw materials or properties of the components to which the shading lines are added. In the sectional views, to facilitate observation, components such as insulating layers, substrates, wiring, and terminals have been appropriately omitted.
[0017] In this specification and claims, the term "connected to" another second element includes the first element being directly connected to the second element, or being connected to the second element always or selectively via an element that is conductive.
[0018] 1. First Implementation Method
[0019] The semiconductor device of the first embodiment will be described.
[0020] The semiconductor device of the first embodiment includes a semiconductor chip, a resin sealing the semiconductor chip, and external connection terminals. Examples of applications of the semiconductor device of the first embodiment include automotive switching devices. The semiconductor device may include, for example, a GaN module.
[0021] Figure 1 This is a perspective view showing an example of the structure of the semiconductor device according to the first embodiment.
[0022] Semiconductor device 1 includes a packaging substrate 10, a housing 11, a first lead frame 12, a second lead frame 13, a third lead frame 14, a capacitor 15, a first control driver 16, a second control driver 17, and external connection terminals 41-49. Figure 1 In order to ensure visibility, the shell 11 is represented by a single-dotted line box.
[0023] The packaging substrate 10 is a support for the semiconductor device 1. The packaging substrate 10 has a flat plate shape, for example, a quadrilateral shape. The packaging substrate 10 forms the lower part of the container of the semiconductor device 1. The packaging substrate 10 contains, for example, ceramic.
[0024] The housing 11 is an insulator with a cylindrical shape. The housing 11 is located on the upper surface of the packaging substrate 10. The housing 11 constitutes the side and top of the container of the semiconductor device 1. The housing 11 is fixed to the packaging substrate 10. The housing 11 is also referred to as insulating resin, sealing resin, or molding resin.
[0025] In the following description, the extended surface of the packaging substrate 10 is referred to as the XY plane. The length direction of the packaging substrate 10 is referred to as the Y direction, and the direction orthogonal to the Y direction is referred to as the X direction. The direction from the packaging substrate 10 toward the housing 11 is referred to as the Z direction. The Z direction is also the upward direction.
[0026] A first lead frame 12 is disposed on the package substrate 10. The first lead frame 12 has a flat plate shape, for example, a quadrilateral shape. The first lead frame 12 contains, for example, copper (Cu).
[0027] The second lead frame 13 is disposed on the package substrate 10. The second lead frame 13 has a flat plate shape, for example, a quadrilateral shape. The second lead frame 13 contains, for example, copper.
[0028] The third lead frame 14 is disposed on the package substrate 10. The third lead frame 14 has a flat plate shape, for example, a quadrilateral shape. The third lead frame 14 contains, for example, copper.
[0029] The first control driver 16 is disposed on the package substrate 10. The first control driver 16 has a flat plate shape. For example, the first control driver 16 has a structure in which multiple protrusions are added to a quadrilateral shape. Figure 1 The following description is based on an example where there are three protrusions. The protrusions are arranged in the Y direction, for example, on one side near the housing 11. By design, the first control actuator 16 may also not have protrusions. The first control actuator 16 may, for example, contain copper.
[0030] The second control driver 17 is disposed on the package substrate 10. The second control driver 17 has a flat plate shape. For example, the second control driver 17 has a structure in which multiple protrusions are added to a quadrilateral shape. Figure 1The following description is based on an example where there are three protrusions. The protrusions are arranged in the Y direction, for example, on one side near the housing 11. Depending on the design, the second control driver 17 may also not have protrusions. The second control driver 17 may, for example, contain copper. Here, the control driver is also referred to as a controller.
[0031] The first lead frame 12, the second lead frame 13, and the third lead frame 14 are arranged sequentially, for example, along the -Y direction. A first control driver 16 is disposed near the first lead frame 12 and the second lead frame 13. A second control driver 17 is disposed near the third lead frame 14. See below for details.
[0032] Capacitor 15 functions as a decoupling capacitor (bypass capacitor) in semiconductor device 1. Capacitor 15 is, for example, an MLCC (Multi-Layer Ceramic Capacitor). Capacitor 15 is positioned above the first lead frame 12, the second lead frame 13, and the third lead frame 14. One end of capacitor 15 is electrically connected to the first lead frame 12. The other end of capacitor 15 is electrically connected to the third lead frame 14. As long as capacitor 15 functions as a decoupling capacitor, it can also be, for example, a silicon capacitor or a film capacitor. Details of capacitor 15 will be described later.
[0033] External connection terminals 41 to 49 are terminals that electrically connect external devices of semiconductor device 1 to the interior of semiconductor device 1. Figure 1 The following description is based on an example where the semiconductor device 1 has external connection terminals on its lower surface.
[0034] Reference Figure 2 The external connection terminals 41 to 49 are described. Figure 2 This is a perspective view showing an example of the structure of the semiconductor device 1 of the first embodiment as viewed from below (-Z direction).
[0035] An external connection terminal 41 is disposed on the lower surface of the first lead frame 12, and the lower surface of the external connection terminal 41 is exposed on the lower surface of the packaging substrate 10. The external connection terminal 41 is electrically connected to the first lead frame 12. The external connection terminal 41 has a flat plate shape, for example, a quadrilateral shape.
[0036] An external connection terminal 42 is disposed on the lower surface of the second lead frame 13, and the lower surface of the external connection terminal 42 is exposed on the lower surface of the package substrate 10. The external connection terminal 42 is electrically connected to the second lead frame 13. The external connection terminal 42 has a flat plate shape, for example, a quadrilateral shape.
[0037] An external connection terminal 43 is disposed on the lower surface of the third lead frame 14, and the lower surface of the external connection terminal 43 is exposed on the lower surface of the package substrate 10. The external connection terminal 43 is electrically connected to the third lead frame 14. The external connection terminal 43 has a flat plate shape, for example, a quadrilateral shape.
[0038] External connection terminals 41 to 43 are arranged sequentially, for example, along the -Y direction.
[0039] External connection terminals 44-46 are disposed on the lower surface of the first control driver 16, and the lower surfaces of each of the external connection terminals 44-46 are exposed on the lower surface of the package substrate 10. The external connection terminals 44-46 are electrically connected to the first control driver 16. Each of the external connection terminals 44-46 has a flat plate shape, for example, a quadrilateral shape. The external connection terminals 44-46 are disposed, for example, on the lower surface of each of the three protrusions of the first control driver 16. The external connection terminals 44-46 are arranged sequentially, for example, along the -Y direction.
[0040] External connection terminals 47-49 are disposed on the lower surface of the second control driver 17, and the lower surfaces of each of the external connection terminals 47-49 are exposed on the lower surface of the package substrate 10. Each of the external connection terminals 47-49 is electrically connected to the second control driver 17. Each of the external connection terminals 47-49 has a flat plate shape, for example, a quadrilateral shape. The external connection terminals 47-49 are disposed, for example, on the lower surface of each of the three protrusions of the second control driver 17. The external connection terminals 47-49 are arranged sequentially, for example, along the -Y direction.
[0041] The location of the external connection terminals of the semiconductor device 1 is not limited to the lower surface of the semiconductor device 1; for example, the external connection terminals may also be located on the side of the semiconductor device 1. Furthermore, the number of external connection terminals in each of the first lead frame 12, the second lead frame 13, the third lead frame 14, the first control driver 16, and the second control driver 17 is designed to be arbitrary and is not limited to a specific number. Figure 1 as well as Figure 2 The record.
[0042] Figure 3 This is an example of a cross-sectional structure of a semiconductor device according to the first embodiment, showing along... Figure 1 A cross-sectional view of line III-III.
[0043] like Figure 3 As shown, the semiconductor device 1 also includes a first GaN transistor 21, a second GaN transistor 22, a first P-type MOSFET 23, a second P-type MOSFET 24, and a plurality of bonding lines 25 to 28.
[0044] The first GaN transistor 21 and the second GaN transistor 22 include, for example, normally-on GaN-HEMT (High Electron Mobility Transistor).
[0045] The first P-type MOSFET 23 and the second P-type MOSFET 24 are p-type MOS (Metal-Oxide-Semiconductor) transistors.
[0046] As described above, a first lead frame 12 is provided on the external connection terminal 41. A second lead frame 13 is provided on the external connection terminal 42. A third lead frame 14 is provided on the external connection terminal 43.
[0047] The first GaN transistor 21 is disposed on the first lead frame 12.
[0048] A first P-type MOSFET 23 is disposed on the second lead frame 13. The first P-type MOSFET 23 controls the first GaN transistor 21 so that the first GaN transistor 21 exhibits normally off behavior.
[0049] The second GaN transistor 22 and the second P-type MOSFET 24 are disposed on the third lead frame 14. The second P-type MOSFET 24 controls the second GaN transistor 22 to cause the second GaN transistor 22 to exhibit normally off behavior.
[0050] Regarding multiple junction lines 25-28, refer to... Figure 4 To be described later.
[0051] The capacitor 15, for example, has a first terminal 151, a second terminal 152, and a capacitor section 153. The first terminal 151 is disposed on and electrically connected to the first lead frame 12. The second terminal 152 is disposed on and electrically connected to the second lead frame 13.
[0052] One end of the capacitor section 153 is electrically connected to the first terminal 151, and the other end is electrically connected to the second terminal 152. The capacitor section 153 is disposed above the first GaN transistor 21, the second GaN transistor 22, the first P-type MOSFET 23, and the second P-type MOSFET 24. The capacitor section 153 extends along the Y direction and is sandwiched between the first terminal 151 and the second terminal 152. Hereinafter, the group of the first GaN transistor 21, the second GaN transistor 22, the first P-type MOSFET 23, and the second P-type MOSFET 24 is sometimes referred to as the GaN transistor group TR.
[0053] The width of the capacitor section 153 in the Y direction is larger than the width of the GaN transistor group TR in the Y direction. That is, when viewed in the XY plane (top view), the capacitor section 153 covers the GaN transistor group TR in the Y direction. In other words, with respect to the Y direction, the end of the capacitor section 153 on the first terminal 151 side is located on the +Y side closer to the end of the first terminal 151 side of the first GaN transistor 21, and is located on the side closer to the +Y side of the housing 11. Similarly, the end of the capacitor section 153 on the second terminal 152 side is located on the -Y side closer to the end of the second terminal 152 side of the second P-type MOSFET 24, and is located on the side closer to the -Y side of the housing 11.
[0054] The width of the GaN transistor group TR in the Y direction can also be described as the distance in the Y direction between the end of the element located on the +Y direction side of the first GaN transistor 21, the second GaN transistor 22, the first P-type MOSFET 23, and the second P-type MOSFET 24 arranged in the Y direction, and the end of the element located on the -Y direction side of the element located on the opposite side of the +Y direction.
[0055] In addition, the width of the GaN transistor group TR in the Y direction can also be described as the width of the first GaN transistor 21, the width of the second GaN transistor 22, the width of the first P-type MOSFET 23, the width of the second P-type MOSFET 24 in the Y direction, and the total length of the distance between each adjacent element in the first GaN transistor 21, the second GaN transistor 22, the first P-type MOSFET 23 and the second P-type MOSFET 24 arranged in the Y direction.
[0056] In addition, the width of the GaN transistor group TR in the Y direction can also be described as the total length of the width of the first GaN transistor 21, the width of the second GaN transistor 22, the width of the first P-type MOSFET 23, the width of the second P-type MOSFET 24, the distance between the first GaN transistor 21 and the first P-type MOSFET 23, the distance between the first P-type MOSFET 23 and the second GaN transistor 22, and the distance between the second GaN transistor 22 and the second P-type MOSFET 24 in the Y direction.
[0057] For example, the width of the capacitor section 153 in the X direction can be the same as or larger than the width of the GaN transistor group TR in the X direction. That is, when viewed in the XY plane (viewed from above), the capacitor section 153 can also cover the GaN transistor group TR.
[0058] The width of the GaN transistor group TR in the X direction can also be described as the distance in the X direction between the end of the element located on the +X direction side of the first GaN transistor 21, the second GaN transistor 22, the first P-type MOSFET 23, and the second P-type MOSFET 24 located on the -X direction side of the element located on the opposite side of the +X direction.
[0059] An example of the capacitor section 153 having a width in the X direction that is smaller than the width in the X direction of the GaN transistor group TR will be described later.
[0060] The configuration of the transistors included in the semiconductor device 1 is not limited to the configuration described above. For example, the first GaN transistor 21 may also be a normally off GaN transistor. In this case, the semiconductor device 1 does not have a first P-type MOSFET 23. Similarly, the second GaN transistor 22 may also be a normally off GaN transistor. In this case, the semiconductor device 1 does not have a second P-type MOSFET 24. In this configuration, the width of the capacitor portion 153 in the Y direction is also larger than the width of the group of the first GaN transistor 21 and the second GaN transistor 22 in the Y direction.
[0061] Alternatively, the group of the first GaN transistor 21 and the first P-type MOSFET 23 can be replaced with a transistor other than a GaN transistor, for example, it can be replaced with a switching element. Similarly, the group of the second GaN transistor 22 and the second P-type MOSFET 24 can also be replaced with a transistor other than a GaN transistor, for example, it can be replaced with a switching element. The first P-type MOSFET 23 and the second P-type MOSFET 24 can also be replaced with transistors other than P-type MOSFETs.
[0062] Figure 4 This is an example of a cross-sectional structure of a semiconductor device according to the first embodiment, showing along... Figure 3 A cross-sectional view of line IV-IV. (See attached image.) Figure 4 As shown, semiconductor device 1 also includes bonding lines 31 to 38.
[0063] When observing the XY plane (viewed from above), for example, the first terminal 151, the first GaN transistor 21, the first P-type MOSFET 23, the second GaN transistor 22, the second P-type MOSFET 24, and the second terminal 152 are arranged sequentially along the -Y direction.
[0064] The first control driver 16 controls the first GaN transistor 21 and the first P-type MOSFET 23. The first control driver 16 is positioned near the first GaN transistor 21 and the first P-type MOSFET 23 to reduce parasitic inductance dependent on the length of the current path. Therefore, the first control driver 16 is positioned near the first lead frame 12 and the second lead frame 13 within a range where the current flowing through the capacitor 15 will not adversely affect the first control driver 16. That is, for example, the distance between the first control driver 16 and the capacitor 15 in the XY plane direction is the minimum distance at which the current flowing through the capacitor 15 will not adversely affect the first control driver 16.
[0065] The second control driver 17 controls the second GaN transistor 22 and the second P-type MOSFET 24. The second control driver 17 is positioned near the second GaN transistor 22 and the second P-type MOSFET 24 to reduce parasitic inductance dependent on the length of the current path. Therefore, the second control driver 17 is positioned near the third lead frame 14 within a range where the current flowing through the capacitor 15 will not adversely affect the second control driver 17. That is, for example, the distance between the second control driver 17 and the capacitor 15 in the XY plane direction is the minimum distance at which the current flowing through the capacitor 15 will not adversely affect the second control driver 17.
[0066] One end of the first GaN transistor 21 is electrically connected to the first lead frame 12 via a plurality of bonding wires 25. The plurality of bonding wires 25 are connected in parallel between one end of the first GaN transistor 21 and the first lead frame 12. The other end of the first GaN transistor 21 is electrically connected to one end of the first P-type MOSFET 23 via a plurality of bonding wires 26. The plurality of bonding wires 26 are connected in parallel between the other end of the first GaN transistor 21 and one end of the first P-type MOSFET 23.
[0067] The other end of the first GaN transistor 21 is connected to the first control driver 16 via a bonding wire 31. Multiple bonding wires 31 may be used, in which case they are connected in parallel between the other end of the first GaN transistor 21 and the first control driver 16. The gate terminal of the first GaN transistor 21 is connected to the first control driver 16 via a bonding wire 32. Multiple bonding wires 32 may also be used, in which case they are connected in parallel between the gate terminal of the first GaN transistor 21 and the first control driver 16.
[0068] The other end of the first P-type MOSFET 23 is electrically connected to the second lead frame 13, for example, via the back of the first P-type MOSFET 23.
[0069] The other end of the first P-type MOSFET 23 is connected to the first control driver 16 via a bonding line 33. Multiple bonding lines 33 may be used, in which case they are connected in parallel between the other end of the first P-type MOSFET 23 and the first control driver 16. The gate of the first P-type MOSFET 23 is connected to the first control driver 16 via a bonding line 34. Multiple bonding lines 34 may also be used, in which case they are connected in parallel between the gate of the first P-type MOSFET 23 and the first control driver 16.
[0070] One end of the second GaN transistor 22 is electrically connected to the second lead frame 13 via a plurality of bonding wires 27. The plurality of bonding wires 27 are connected in parallel between one end of the second GaN transistor 22 and the second lead frame 13. The other end of the second GaN transistor 22 is electrically connected to one end of the second P-type MOSFET 24 via a plurality of bonding wires 28. The plurality of bonding wires 28 are connected in parallel between the other end of the second GaN transistor 22 and one end of the second P-type MOSFET 24.
[0071] The other end of the second GaN transistor 22 is connected to the second control driver 17 via a bonding wire 35. Multiple bonding wires 35 may be used, in which case they are connected in parallel between the other end of the second GaN transistor 22 and the second control driver 17. The gate terminal of the second GaN transistor 22 is connected to the second control driver 17 via a bonding wire 36. Multiple bonding wires 36 may also be used, in which case they are connected in parallel between the gate terminal of the second GaN transistor 22 and the second control driver 17.
[0072] The other end of the second P-type MOSFET 24 is electrically connected to the third lead frame 14 via, for example, the back side of the second P-type MOSFET 24.
[0073] The other end of the second P-type MOSFET 24 is connected to the second control driver 17, for example, via a bonding line 37. Multiple bonding lines 37 may also exist, in which case they are connected in parallel between the other end of the second P-type MOSFET 24 and the second control driver 17. The gate terminal of the second P-type MOSFET 24 is connected to the second control driver 17, for example, via a bonding line 38. Multiple bonding lines 38 may also exist, in which case they are connected in parallel between the gate terminal of the second P-type MOSFET 24 and the second control driver 17.
[0074] Capacitor 15 may be connected to the second control driver 17 via, for example, a connection wire, or it may be connected to the second control driver 17 without a connection wire.
[0075] External connection terminal 41 is an input terminal. The first lead frame 12 receives, for example, an input signal VDC+ from the outside via external connection terminal 41.
[0076] External connection terminal 42 is an output terminal. The second lead frame 13 outputs an output signal VSW to the outside via external connection terminal 42, for example.
[0077] External connection terminal 43 is an input terminal. The third lead frame 14 receives, for example, an input signal VDC- from an external source via external connection terminal 43. The input signal VDC- is smaller than the input signal VDC+, for example, containing a voltage of 0V.
[0078] The first control driver 16 is connected, for example, to an external voltage VDD1 node via an external connection terminal 44. The voltage VDD1 node is, for example, subjected to a voltage of a certain magnitude of VDD1.
[0079] The first control driver 16 receives a control signal Vx from an external source, for example, via an external connection terminal 45. The control signal Vx is, for example, a signal that controls the first control driver 16.
[0080] The first control driver 16 is connected, for example, to an external voltage VSS1 node via an external connection terminal 46. The voltage VSS1 node is, for example, subject to a voltage of a certain magnitude, VSS1. Voltage VSS1 is smaller than voltage VDD1, for example, 0V.
[0081] The second control driver 17 is connected, for example, to an external voltage VDD2 node via an external connection terminal 47. The voltage VDD2 node is, for example, subjected to a voltage of a certain magnitude of VDD2.
[0082] The second control driver 17 receives a control signal Vy from an external source, for example, via an external connection terminal 48. The control signal Vy is, for example, a signal that controls the second control driver 17.
[0083] The second control driver 17 is connected, for example, to an external voltage VSS2 node via an external connection terminal 49. The voltage VSS2 node is, for example, subject to a voltage of a certain magnitude, VSS2. Voltage VSS2 is smaller than voltage VDD2, for example, 0V.
[0084] Figure 4 The shapes (sometimes referred to as planar shapes) of the first lead frame 12, the second lead frame 13, the third lead frame 14, the first control driver 16, and the second control driver 17 along the XY plane shown are examples, and are subject to change as long as they are feasible. Figure 5 The electronic circuit shown can have any planar shape.
[0085] Figure 4 The connection of the connecting lines 31 to 38 shown is an example; any connection that can be achieved... Figure 5 The electronic circuit shown can have other connection structures.
[0086] The number of external connection terminals and the signals received by each of the first control driver 16 and the second control driver 17 are examples. Other configurations are also possible as long as they can control the first GaN transistor 21, the second GaN transistor 22, the first P-type MOSFET 23, and the second P-type MOSFET 24.
[0087] Figure 5 This is a circuit diagram illustrating an example of the electronic circuitry of the semiconductor device according to the first embodiment.
[0088] The drain terminal of the first GaN transistor 21 is connected to node N1. Node N1 corresponds to external connection terminal 41, for example, receiving the input signal VDC+.
[0089] The source terminal of the first GaN transistor 21 is connected to the drain terminal of the first P-type MOSFET 23.
[0090] The gate terminal of the first GaN transistor 21 is connected, for example, to a node corresponding to the external connection terminal 45 of the first control driver 16, for example, to receive the control signal Vx.
[0091] The source terminal of the first P-type MOSFET 23 is connected to node N2. Node N2 is equivalent to external connection terminal 42, for example, to output the output signal VSW.
[0092] The gate of the first P-type MOSFET 23 is connected, for example, to a node corresponding to the voltage VDD1 of the external connection terminal 44.
[0093] The drain terminal of the second GaN transistor 22 is connected to node N2.
[0094] The source terminal of the second GaN transistor 22 is connected to the drain terminal of the second P-type MOSFET 24.
[0095] The gate of the second GaN transistor 22 is connected, for example, to a node corresponding to the external connection terminal 48 of the second control driver 17, for example, to receive the control signal Vy.
[0096] The source terminal of the second P-type MOSFET 24 is connected to node N3. Node N3 corresponds to external connection terminal 43, for example, to receive the input signal VDC-.
[0097] The gate of the second P-type MOSFET 24 is connected, for example, to a node corresponding to the voltage VDD2 of the external connection terminal 47.
[0098] One end of capacitor 15 is connected to node N1, and the other end is connected to node N3.
[0099] The first GaN transistor 21 and the first P-type MOSFET 23 are, for example, cascaded together. The second GaN transistor 22 and the second P-type MOSFET 24 are, for example, cascaded together.
[0100] Thus, the conduction and cutoff operations of semiconductor device 1 are controlled by control signals Vx and Vy. Specifically, the conduction and cutoff operations of semiconductor device 1 are controlled by the first GaN transistor 21 and the second GaN transistor 22. The first P-type MOSFET 23 becomes conduction-enabled when the first GaN transistor 21 is turned on, and continues to conduct thereafter. Similarly, the second P-type MOSFET 24 becomes conduction-enabled when the second GaN transistor 22 is turned on, and continues to conduct thereafter.
[0101] Figure 5 This example illustrates a case where the first GaN transistor 21 and the second GaN transistor 22 are normally-on GaN-HEMTs, and the semiconductor device 1 includes a first P-type MOSFET 23 and a second P-type MOSFET 24. The electronic circuit implemented by the semiconductor device 1 is not limited to... Figure 5 Examples include the group of the first GaN transistor 21 and the first P-type MOSFET 23, which can also be a GaN transistor. Similarly, the group of the second GaN transistor 22 and the second P-type MOSFET 24 can also be a GaN transistor.
[0102] According to the semiconductor device 1 of the first embodiment, as described below, a semiconductor device capable of suppressing component space can be provided.
[0103] As previously described, the semiconductor device 1 of the first embodiment has a capacitor 15 above (in the +Z direction) the GaN transistor array TR. When the decoupling capacitor of the semiconductor device is arranged along the XY plane direction (e.g., the +X direction) of the GaN transistor array TR, the semiconductor device sometimes needs to be enlarged, for example, along the +X direction, including the package substrate 10, the housing 11, the first lead frame 12, the second lead frame 13, and the third lead frame 14. That is, sometimes the amount by which the area of the decoupling capacitor increases when viewing the XY plane (top view) increases the component space, and the overall area of the semiconductor device becomes larger.
[0104] In contrast, semiconductor device 1 can reduce component space and decrease the area of the device when viewed from above by having a capacitor 15 above the GaN transistor group TR that functions as a decoupling capacitor.
[0105] Furthermore, by having a capacitor 15 above the GaN transistor group TR, the semiconductor device 1 can reduce ringing peaks during switching by utilizing the magnetic field cancellation effect.
[0106] Figure 6This is a conceptual diagram illustrating an example of a case where a high-frequency signal is input to the semiconductor device of the first embodiment. Figure 6 Showing with Figure 3 Cross-sections of the same region.
[0107] The current path DI is an example of the path through which a high-frequency current IAC flows within the semiconductor device 1 when a high-frequency signal is input. The current path DI is, for example, a loop path including paths through the GaN transistor group TR and the capacitor 15, respectively. The high-frequency current IAC circulates, for example, within the current path DI. Specifically, the high-frequency current IAC, for example, sequentially passes through the first GaN transistor 21, the first P-type MOSFET 23, the second GaN transistor 22, the second P-type MOSFET 24, the second terminal 152, the capacitor section 153, and the first terminal 151, and circulates. That is, the high-frequency current IAC that has passed through the first terminal 151 flows back into the first GaN transistor 21.
[0108] This high-frequency current IAC flows, for example, in the +Y direction when passing through capacitor section 153 and in the -Y direction when passing through GaN transistor array TR. The magnetic field generated by the high-frequency current IAC flowing in the +Y direction cancels out the magnetic field generated by the high-frequency current IAC flowing in the -Y direction. By canceling out the magnetic field generated when the high-frequency current IAC flows, semiconductor device 1 can reduce ringing peaks generated during switching. The direction of circulation of the high-frequency current IAC can vary depending on the voltage applied to the external connection terminal.
[0109] Furthermore, by placing the decoupling capacitor near the GaN transistor array TR, parasitic inductance can be reduced, and ringing peaks can be further reduced. The semiconductor device 1, by having a capacitor 15 above the GaN transistor array TR, can reduce ringing peaks by placing the decoupling capacitor near the GaN transistor array TR in its configuration. The capacitor 15 can be positioned near the GaN transistor array TR by adjusting the height of the first terminal 151 and the second terminal 152 in the Z direction. For example, the distance between the capacitor 153 and the GaN transistor array TR in the Z direction is the minimum distance at which the capacitor 153 does not interfere with the GaN transistor array TR.
[0110] In semiconductor device 1, capacitor 15 is disposed above GaN transistor array TR, thus the first terminal 151, second terminal 152, and capacitor portion 153 are integrally formed as capacitor 15. Therefore, capacitor 15 can be easily and electrically stably connected to the lead frame. Furthermore, semiconductor device 1 has a structure with first terminal 151 and second terminal 152 and capacitor portion 153 not contacting the lead frame, thus exhibiting high vibration resistance and suppressing capacitor noise. Capacitor 15 can be inexpensively incorporated into semiconductor device 1.
[0111] Thus, by having a capacitor 15 above the GaN transistor array TR, semiconductor device 1 can reduce ringing peaks while suppressing component space and reducing device area. This design enhances design freedom and applicability of semiconductor device 1.
[0112] In the first embodiment described above, an example was described in which the width of the capacitor section 153 in the X direction was the same as or larger than the width of the GaN transistor group TR in the X direction, but this is not a limitation. For example, as long as it does not impede the reduction of the ringing peak of the semiconductor device 1, the width of the capacitor section 153 in the X direction may be smaller than the width of the GaN transistor group TR in the X direction. That is, for example, when viewing the XY plane (viewed from above), the capacitor section 153 may not cover the GaN transistor group TR in the X direction.
[0113] While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the scope of the invention as described in the claims and its equivalents.
[0114] Explanation of reference numerals in the attached figures
[0115] 1…Semiconductor devices,
[0116] 10…Packaging substrate,
[0117] 11…shell,
[0118] 12~14…leader frames,
[0119] 15… capacitors,
[0120] 16, 17… control the driver,
[0121] 21, 22… transistors,
[0122] 23, 24… MOSFETs
[0123] 25~28, 31~38… junction lines,
[0124] 41~49… External connection terminals.
Claims
1. A semiconductor device, characterized in that, have: First switching element; A second switching element is electrically connected to the first switching element; and A capacitor has a first terminal, a second terminal, and a capacitor portion, one end of which is electrically connected to the first terminal and the other end of which is electrically connected to the second terminal. The first terminal is electrically connected to the first switching element. The second terminal is electrically connected to the second switching element. The capacitor section is located above the first switching element and the second switching element along the first direction. The width of the capacitor section in the direction connecting one end to the other end of the capacitor section, i.e., the second direction, is larger than the width of the group of the first switching element and the second switching element in the second direction. The first switching element and the second switching element are arranged in the second direction.
2. The semiconductor device according to claim 1, characterized in that, The width of the group of the first and second switching elements in the second direction is the total length of the width of the first switching element, the width of the second switching element, and the distance between the first and second switching elements.
3. The semiconductor device according to claim 1, characterized in that, The width of the group of the first and second switching elements in the second direction is the distance in the second direction between the end of the first and second switching elements located on one side of the second direction and the end of the third switching element located on the third side opposite to the second direction.
4. The semiconductor device according to claim 1, characterized in that, It also has: The first lead frame has the first switching element and the first terminal on its upper surface; The second lead frame has the second switching element and the second terminal on its upper surface; The first external connection terminal is electrically connected to the first lead frame; The second external connection terminal is electrically connected to the second lead frame; as well as Third external connection terminal, One end of the first switching element is electrically connected to the first external connection terminal, and the other end is electrically connected to one end of the second switching element and the third external connection terminal. The other end of the second switching element is electrically connected to the second external connection terminal. The first terminal is electrically connected to one end of the first switching element. The second terminal is electrically connected to the other end of the second switching element.
5. The semiconductor device according to claim 1, characterized in that, It also has: The first lead frame has the first switching element and the first terminal on its upper surface; The second lead frame has the second switching element and the second terminal on its upper surface; Third lead frame; The first external connection terminal is electrically connected to the first lead frame; The second external connection terminal is electrically connected to the second lead frame; The third external connection terminal is electrically connected to the third lead frame; The first MOSFET is disposed on the third lead frame; as well as The second MOSFET is disposed on the second lead frame. One end of the first switching element is electrically connected to the first external connection terminal, and the other end is electrically connected to one end of the first MOSFET. The other end of the first MOSFET is electrically connected to the control terminal of the first switching element, one end of the second switching element, and the third external connection terminal. The other end of the second switching element is electrically connected to one end of the second MOSFET. The other end of the second MOSFET is electrically connected to the control terminal of the second switching element and the second external connection terminal. The first terminal is electrically connected to one end of the first switching element. The second terminal is electrically connected to the other end of the second MOSFET. The width of the capacitor section in the second direction is greater than the width of the group of the first switching element, the first MOSFET, the second switching element, and the second MOSFET in the second direction. The first switching element, the first MOSFET, the second switching element, and the second MOSFET are arranged in the second direction. The first switching element and the second switching element are GaN transistors.
6. The semiconductor device according to claim 5, characterized in that, The width of the group of the first switching element, the first MOSFET, the second switching element, and the second MOSFET in the second direction is the distance in the second direction between the end of the element located on the side closest to the second direction and the end of the element located on the side closest to the third direction opposite to the second direction.
7. The semiconductor device according to claim 5, characterized in that, The width of the group of the first switching element, the first MOSFET, the second switching element, and the second MOSFET in the second direction is the sum of the widths of the first switching element, the first MOSFET, the second switching element, and the second MOSFET in the second direction, and the distances between adjacent elements of the first switching element, the first MOSFET, the second switching element, and the second MOSFET arranged in the second direction.
8. The semiconductor device according to claim 5, characterized in that, The width of the group of the first switching element, the first MOSFET, the second switching element, and the second MOSFET in the second direction is the total length of the width of the first switching element, the width of the first MOSFET, the width of the second switching element, the width of the second MOSFET, the distance between the first switching element and the first MOSFET, the distance between the first MOSFET and the second switching element, and the distance between the second switching element and the second MOSFET in the second direction.
9. The semiconductor device according to claim 1, characterized in that, The first switching element and the second switching element are GaN transistors.
10. The semiconductor device according to claim 1, characterized in that, The capacitor is a multilayer ceramic capacitor (MLCC).
11. The semiconductor device according to claim 1, characterized in that, The width of the capacitor section in the fourth direction intersecting the first and second directions is the same as or greater than the width of the group of the first and second switching elements in the fourth direction.
12. The semiconductor device according to claim 11, characterized in that, The width of the group of the first switching element and the second switching element in the fourth direction is the distance in the fourth direction between the end of the first switching element and the second switching element located on one side of the fourth direction and the end of the element located on the side of the fifth direction opposite to the fourth direction.
13. The semiconductor device according to claim 1, characterized in that, It also has: A first control device controls the first switching element; and The second controller controls the second switching element.
14. The semiconductor device according to claim 4, characterized in that, It also has: A first control device controls the first switching element; A second control device controls the second switching element; and The resin covers the first switching element, the second switching element, the capacitor, the first lead frame, the second lead frame, the first control device, and the second control device.
15. The semiconductor device according to claim 11, characterized in that, When viewed from above, the capacitor section covers the first switching element and the second switching element.
Citation Information
Patent Citations
Display device, color calibration method of display device, color calibration program of display device and recording medium
JP2024082651A