Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a first semiconductor contact layer, a second semiconductor contact layer and a first electrode layer. The first surface of the first semiconductor contact layer comprises a plurality of connected step surfaces, the step surfaces comprise connected main surfaces and connecting surfaces, and the main surface of one step surface is connected with the connecting surface of an adjacent step surface. The second semiconductor contact layer comprises a plurality of sub-contact structures, the sub-contact structures are in contact with the main surfaces, and the sub-contact structures are in a nanosheet structure or a nanoisland structure. The entire surface of one sub-contact structure on the side facing the main surface is in contact with a partial area of the main surface of one step surface. The first electrode layer is located on the side of the second semiconductor contact layer away from the first semiconductor contact layer and covers the first semiconductor contact layer on the side of the sub-contact structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] The third generation semiconductor material gallium nitride (GaN) based semiconductor laser has the characteristics of good monochromaticity, high luminous efficiency, high optical power density, good directivity, low cost, small size, etc., and has broad application prospects in the fields of laser projection display, laser illumination, industrial laser processing, etc. The semiconductor laser works in a state of large current injection, and has high requirements for the contact resistance of the semiconductor laser. Reducing the contact resistance can reduce the operating voltage of the laser and improve the photoelectric conversion efficiency and reliability of the laser. SUMMARY

[0003] The present application provides a semiconductor structure, comprising a first semiconductor contact layer, a second semiconductor contact layer and a first electrode layer; wherein the first surface of the first semiconductor contact layer comprises a plurality of connected step surfaces, the step surface comprises a connected main surface and a connected surface; the main surface of one step surface is connected with the connected surface of the adjacent step surface; wherein the second semiconductor contact layer comprises a plurality of sub-contact structures, the sub-contact structure is in contact with the main surface, and the sub-contact structure is in a nanosheet structure or a nanoisland structure; the entire surface of one sub-contact structure on the side facing the main surface is in contact with part of the area of the main surface of one step surface; wherein the first electrode layer is located on the side of the second semiconductor contact layer away from the first semiconductor contact layer and covers the first semiconductor contact layer on the side of the sub-contact structure.

[0004] Optionally, the step surface extends along a first direction, and adjacent step surfaces are arranged along a second direction, the second direction intersects the first direction; the size of the step surface along the first direction is greater than the size of the step surface along the second direction.

[0005] Optionally, the height of at least part of the number of step surfaces along a third direction is less than or equal to 5nm, and the width along a second direction is less than or equal to 500nm; wherein the third direction is the stacking direction of the first semiconductor contact layer to the second semiconductor contact layer, and the third direction is perpendicular to the first direction and the second direction respectively.

[0006] Optionally, in the cross section perpendicular to the third direction, in the cross-sectional area within any 10*10um 2 range, more than or equal to half the number of step surfaces have a height along the third direction less than or equal to 5nm and a width along the second direction less than or equal to 200nm.

[0007] Optionally, the first semiconductor contact layer is doped with first conductive ions, the first conductive ions are uniformly doped in the first semiconductor contact layer.

[0008] Optionally, the first semiconductor contact layer is doped with first conductive ions, the first conductive ions are non-uniformly doped in the first semiconductor contact layer; wherein the doping concentration of at least part of the first semiconductor contact layer is greater than or equal to 1E19 atoms / cm 3 and less than or equal to 9E21 atoms / cm 3 .

[0009] Optionally, the lattice constant of the second semiconductor contact layer is greater than the lattice constant of the first semiconductor contact layer.

[0010] Optionally, the sub-contact structure is a multi-layer structure, the sub-contact structure comprises a plurality of first sub-layers to Nth sub-layers stacked in sequence along a direction perpendicular to the main surface, the distance from the first sub-layer to the first semiconductor contact layer is less than the distance from the Nth sub-layer to the first semiconductor contact layer; the size of any nth sub-layer along a direction perpendicular to the main surface is less than the size of the nth sub-layer along a direction parallel to the main surface; wherein the size of the first sub-layer along a direction parallel to the main surface to the size of the Nth sub-layer along a direction parallel to the main surface decreases; N is an integer greater than or equal to 2, and n is an integer greater than or equal to 1 and less than or equal to N.

[0011] Optionally, further comprising: a stacked substrate layer, a first confinement layer, a first waveguide layer, an active layer, a second waveguide layer, and a second confinement layer; wherein the first semiconductor contact layer is located on a side of the second confinement layer away from the second waveguide layer; and the second semiconductor contact layer is located on a side of the first semiconductor contact layer away from the second confinement layer.

[0012] The application further provides a preparation method of a semiconductor structure, comprising: forming a first semiconductor contact layer; a first surface of the first semiconductor contact layer comprises a plurality of connected step surfaces, the step surfaces comprising connected main surfaces and connecting surfaces; a main surface of one of the step surfaces is connected to a connecting surface of an adjacent step surface; forming a second semiconductor contact layer, the second semiconductor contact layer comprising a plurality of sub-contact structures, the sub-contact structures being in contact with the main surface, the sub-contact structures being in a nanosheet structure or a nanoisland structure; the entire surface of one of the sub-contact structures on a side facing the main surface is in contact with a partial area of a main surface of one of the step surfaces; and forming a first electrode layer, the first electrode layer being located on a side of the second semiconductor contact layer away from the first semiconductor contact layer and covering the first semiconductor contact layer on the side of the sub-contact structure.

[0013] Optionally, the method further comprises: sequentially forming a first confinement layer, a first waveguide layer, an active layer, a second waveguide layer and a second confinement layer on one side of a substrate layer, the substrate layer having a bevel angle greater than 0° and less than or equal to 1°; wherein forming the first semiconductor contact layer comprises: forming the first semiconductor contact layer on the side of the second confinement layer away from the substrate layer by epitaxial growth in a step-flow mode; wherein the first surface of the first semiconductor contact layer away from the substrate layer comprises a plurality of connected step faces; or forming the first semiconductor contact layer comprises: forming a first initial semiconductor contact layer; polishing the first initial surface of the first initial semiconductor contact layer to form the first semiconductor contact layer comprising step faces and to form the first surface from the first initial surface.

[0014] Optionally, the growth temperature for forming the second semiconductor contact layer is lower than the growth temperature for forming the first semiconductor contact layer.

[0015] Optionally, forming the second semiconductor contact layer comprises: depositing the second semiconductor contact layer on the surface of the first semiconductor contact layer; during the deposition of the second semiconductor contact layer, a two-dimensional wetting layer is formed when the deposited material thickness is less than a critical thickness, and the deposition continues until the deposited material thickness exceeds the critical thickness, until a nanosheet structure or a nanoisland structure is formed.

[0016] Optionally, after forming the nanosheet structure or the nanoisland structure, the temperature is lowered in an atmosphere of a protective gas.

[0017] Optionally, the sub-contact structure is a multilayer structure, and forming the sub-contact structure comprises: forming a plurality of first to Nth sub-layers stacked in sequence in a direction perpendicular to the main surface, the distance from the first sub-layer to the first semiconductor contact layer being less than the distance from the Nth sub-layer to the first semiconductor contact layer; the size of any nth sub-layer in a direction perpendicular to the main surface being less than the size of the nth sub-layer in a direction parallel to the main surface; wherein the size of the first sub-layer in a direction parallel to the main surface to the size of the Nth sub-layer in a direction parallel to the main surface decreases; N is an integer greater than or equal to 2, and n is an integer greater than or equal to 1 and less than or equal to N.

[0018] The technical scheme has the following technical effects:

[0019] The semiconductor structure provided by the technical scheme includes a plurality of sub-contact structures, the sub-contact structures are in contact with the main surface, and the sub-contact structures are in a nanosheet structure or a nanoisland structure; the entire surface of one of the sub-contact structures on the side facing the main surface is in contact with a partial region of the main surface of one of the step surfaces. The first electrode layer is in contact with a plurality of surfaces of the second semiconductor contact layer of the three-dimensional structure, the contact area between the first electrode layer and the second semiconductor contact layer is increased, and the contact resistance is reduced. The sub-contact structures are distributed along the step surfaces, the shape, size and distribution of the sub-contact structures are more easily controlled, and the contact uniformity between the second semiconductor contact layer and the first electrode layer is improved; the second semiconductor contact layer is formed based on the main surface of the step surface, and a complex process step does not need to be used. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical scheme in the specific embodiments or prior art of the present application, the drawings needed to be used in the specific embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0021] Figure 1 The schematic diagram of the semiconductor structure provided by an embodiment of the present application;

[0022] Figure 2 The structure of the first semiconductor contact layer and the second semiconductor contact layer in the present application; Figure 1 The structure of the first semiconductor contact layer and the second semiconductor contact layer in the present application;

[0023] Figure 3 The structure of the first semiconductor contact layer and the second semiconductor contact layer in the present application; Figure 2 The structure of the second semiconductor contact layer in the present application;

[0024] Figure 4 The schematic diagram of the semiconductor structure provided by another embodiment of the present application;

[0025] Figure 5 The surface atomic force microscope diagram of the second semiconductor contact layer. DETAILED DESCRIPTION

[0026] A preparation method of a semiconductor structure, the contact area is increased by changing the surface morphology of the contact layer, so as to reduce the contact resistance. A certain roughness is formed on the surface of the contact layer to increase the contact area between the contact layer and the front electrode. The roughness of the surface of the contact layer is usually formed by wet etching or dry etching, and after the front electrode is deposited, a good ohmic contact is formed between the nanometer structure and the front electrode by a heat annealing process, so as to reduce the contact resistance.

[0027] However, the above technical solutions have some problems, often need complex process step control, high cost. In addition, the method of increasing the roughness of the surface of the contact layer by etching may affect the internal structure of the contact layer, produce other defects, affect other properties of the semiconductor structure, such as the light output efficiency, current injection efficiency of the semiconductor light emitting structure when the semiconductor structure is a semiconductor light emitting structure.

[0028] How to effectively reduce the contact resistance between the contact layer and the front electrode without using complex process steps, while avoiding affecting the internal structure of the contact layer to ensure other properties of the semiconductor structure, is a technical problem that needs to be solved.

[0029] To solve the above problems, the technical scheme of the present application provides a semiconductor structure and a preparation method thereof, which effectively reduces the contact resistance between the contact layer and the front electrode without using complex process steps, while avoiding affecting the internal structure of the contact layer to ensure other properties of the semiconductor structure.

[0030] The technical solutions of the present application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0031] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0032] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0033] In addition, the technical features involved in the different embodiments of the application described below can be combined with each other as long as they do not conflict with each other.

[0034] An embodiment of the present application provides a semiconductor structure, referring to Figure 1 and Figure 2 , comprising a first semiconductor contact layer 301, a second semiconductor contact layer 302 and a first electrode layer 305.

[0035] The first surface of the first semiconductor contact layer 301 comprises a plurality of connected step surfaces 3013, and the step surface 3013 comprises a connected main surface 3011 and a connected surface 3012; the main surface 3011 of one step surface 3013 is connected with the connected surface 3012 of the adjacent step surface 3013.

[0036] The second semiconductor contact layer 302 comprises a plurality of sub-contact structures 400, the sub-contact structure 400 is in contact with the main surface 3011, and the sub-contact structure 400 is in a nanosheet structure or a nanoisland structure; the entire surface of one sub-contact structure 400 on the side facing the main surface 3011 is in contact with a partial area of the main surface 3011 of one step surface 3013.

[0037] The first electrode layer 305 is located on the side of the second semiconductor contact layer 302 away from the first semiconductor contact layer 301 and covers the first semiconductor contact layer 301 on the side of the sub-contact structure 400.

[0038] In the embodiment, the second semiconductor contact layer 302 comprises a plurality of sub-contact structures 400, the sub-contact structure 400 is in contact with the main surface 3011, and the sub-contact structure 400 is in a nanosheet structure or a nanoisland structure; the entire surface of one sub-contact structure 400 on the side facing the main surface 3011 is in contact with a partial area of the main surface 3011 of one step surface 3013. The first electrode layer 305 is in contact with a plurality of surfaces of the second semiconductor contact layer 302 in a three-dimensional structure, which increases the contact area of the first electrode layer 305 and the second semiconductor contact layer 302 and reduces the contact resistance. The sub-contact structure 400 is distributed along the step surface 3013, the shape, size and distribution of the sub-contact structure 400 are easier to control accurately, which is beneficial to improve the contact uniformity of the second semiconductor contact layer 302 and the first electrode layer 305; the second semiconductor contact layer 302 is formed based on the main surface 3011 of the step surface 3013, and a complex process step is not needed; in addition, the etching process is avoided to affect the internal structure of the second semiconductor contact layer 302 and the first semiconductor contact layer 301 to ensure other performances of the semiconductor structure.

[0039] The second semiconductor contact layer 302 does not protrude beyond the main surface 3011 toward the side surface of the first semiconductor contact layer 301.

[0040] The difference between the main surface 3011 and the connecting surface 3012 includes that, with respect to the side surface of the first semiconductor contact layer 301 facing away from the second semiconductor contact layer 302, the area of the main surface 3011 in any one of the step surfaces 3013 is greater than the area of the connecting surface 3012.

[0041] In one embodiment, the lattice constant of the second semiconductor contact layer 302 is greater than the lattice constant of the first semiconductor contact layer 301. Thus, when the second semiconductor contact layer 302 is grown, the first semiconductor contact layer 301 exerts compressive stress on the second semiconductor contact layer 302, and a nanosheet structure or a nanoisland structure is spontaneously formed.

[0042] In one embodiment, the lattice mismatch between the second semiconductor contact layer 302 and the first semiconductor contact layer 301 is 1% to 10%. The lattice mismatch is: (the difference between the lattice constant of the second semiconductor contact layer 302 and the lattice constant of the first semiconductor contact layer 301) / the lattice constant of the first semiconductor contact layer 301.

[0043] The sub-contact structure 400 is in a nanosheet structure or a nanoisland structure, that is, the size of the sub-contact structure 400 in the first direction, the second direction X and the third direction Z is nanoscale, for example, the size of the sub-contact structure 400 in the first direction, the second direction X and the third direction Z is less than 500 nanometers, for example: the size of the sub-contact structure 400 in the first direction is 10 nanometers, 200 nanometers or 500 nanometers; the size of the sub-contact structure 400 in the second direction X is 10 nanometers, 200 nanometers or 500 nanometers; the size of the sub-contact structure 400 in the third direction Z is 10 nanometers, 200 nanometers or 500 nanometers.

[0044] In some embodiments, the step surface 3013 extends along the first direction, and adjacent step surfaces are arranged along the second direction X, the second direction X intersects the first direction; the size of the step surface 3013 along the first direction is greater than the size of the step surface 3013 along the second direction X. That is, the step surface 3013 is in a strip shape, and there is no plurality of step surfaces 3013 arranged in the first direction.

[0045] The first direction intersects the second direction X, for example, the first direction is perpendicular to the second direction X.

[0046] In some embodiments, the height of at least part of the number of step surfaces 3013 along the third direction Z is less than or equal to 5 nm, and the width of the step surface 3013 along the second direction X is less than or equal to 500 nm.

[0047] Wherein, the third direction Z is the stacking direction of the first semiconductor contact layer 301 to the second semiconductor contact layer 302. The third direction Z is perpendicular to both the first direction and the second direction X. The second direction X is the arrangement direction of adjacent stepped surfaces 3013.

[0048] In some embodiments, in a cross section perpendicular to the third direction Z, at any 10*10 μm 2 Within the cross-sectional area of ​​the range, more than half of the step surfaces 3013 have a height of less than or equal to 5 nm along the third direction Z and a width of less than or equal to 200 nm along the second direction X.

[0049] In other implementations, in a cross section perpendicular to the third direction Z, all of the stepped surfaces 3013 have a height of less than or equal to 5 nm along the third direction Z and a width of less than or equal to 200 nm along the second direction X.

[0050] In some embodiments, the chamfer angle θ of the first surface is greater than 0° and less than or equal to 1°. Tan (chamfer angle θ) = D / L. L is the dimension of the main surface 3011 along the second direction X, and D is the height of the main surface 3011 along the third direction Z. The height of the main surface 3011 along the third direction Z is the distance between the top and bottom ends of the main surface 3011 along the third direction Z.

[0051] In some embodiments, the first semiconductor contact layer 301 is doped with first conductive ions, and the first conductive ions are uniformly doped in the first semiconductor contact layer 301. Further, the doping concentration of the first conductive ions in the first semiconductor contact layer 301 is 1E18 atoms / cm³. 3 ~3E21atoms / cm 3 .

[0052] The first conducting ion includes Mg ions.

[0053] In other embodiments, the first semiconductor contact layer 301 is doped with first conductive ions, and the first conductive ions are non-uniformly doped in the first semiconductor contact layer 301; furthermore, the doping concentration of the first semiconductor contact layer 301 in at least a portion of the region is greater than or equal to 1E19 atoms / cm 3 And less than or equal to 9E21 atoms / cm 3 The doping concentration of the first conductive ion in the first semiconductor contact layer 301 is 1E18 atoms / cm². 3 ~9E21atoms / cm 3 .

[0054] In some embodiments, the second conductive ions are doped in the second semiconductor contact layer 302.

[0055] In some embodiments, referring to Figure 3 , the sub-contact structure 400 is a multi-layer structure, the sub-contact structure 400 comprises a plurality of first sub-layers to Nth sub-layers sequentially stacked in a direction perpendicular to the main surface 3011, a distance from the first sub-layers to the first semiconductor contact layer 301 is less than a distance from the Nth sub-layers to the first semiconductor contact layer 301; a size of any nth sub-layer in a direction perpendicular to the main surface 3011 is less than a size of the nth sub-layer in a direction parallel to the main surface 3011. Wherein, N is an integer greater than or equal to 2, n is an integer greater than or equal to 1 and less than or equal to N.

[0056] For example, a size T1 of the first sub-layer in a direction perpendicular to the main surface 3011 is less than a size D1 of the first sub-layer in a direction parallel to the main surface 3011. A size Tn of the nth sub-layer in a direction perpendicular to the main surface 3011 is less than a size Dn of the nth sub-layer in a direction parallel to the main surface 3011. n n .

[0057] Wherein, the size of the first sub-layer in a direction parallel to the main surface 3011 to the size of the Nth sub-layer in a direction parallel to the main surface 3011 decreases. The contact area between the first electrode layer and the sub-contact structure 400 is increased, and the contact resistance between the first electrode layer and the second semiconductor contact layer 302 is reduced.

[0058] In one embodiment, a size of any nth sub-layer in a direction perpendicular to the main surface 3011 is greater than or equal to 1 atomic layer thickness and less than or equal to 10 nm.

[0059] In one embodiment, a size of the sub-contact structure 400 in a third direction Z is less than or equal to 20 nm. Too high sub-contact structure 400 and the first electrode layer 305 are prone to form pores, which is not conducive to the full contact between the sub-contact structure 400 and the first electrode layer 305.

[0060] In other embodiments, the sub-contact structure 400 is a single-layer structure. In one embodiment, a size of the sub-contact structure 400 in a direction perpendicular to the main surface is greater than or equal to 1 atomic layer thickness and less than or equal to 10 nm.

[0061] ​In one embodiment, the second conductive ions are doped in the second semiconductor contact layer 302. The doping concentration of the second conductive ions in the first sub-layer to the doping concentration of the second conductive ions in the Nth sub-layer is increasing, that is, the doping concentration of the second conductive ions in the first sub-layer is less than the doping concentration of the second conductive ions in the Nth sub-layer, and the doping concentration of the second conductive ions in the Nth sub-layer is higher, so as to ensure that the contact barrier of the Nth sub-layer and the first electrode layer is lower. The doping concentration of the second conductive ions in the first sub-layer is lower, so that the sub-contact structure 400 has a higher material quality towards the side surface of the first semiconductor contact layer 301 and the material near the side surface.

[0062] In other embodiments, the second conductive ions in the first sub-layer to the second conductive ions in the Nth sub-layer are uniformly doped.

[0063] The conductive types of the second conductive ions and the first conductive ions are the same. For example, the conductive types of the second conductive ions and the first conductive ions are both N-type, or the conductive types of the second conductive ions and the first conductive ions are both P-type. When the conductive types of the second conductive ions and the first conductive ions are both P-type, the second conductive ions include Mg ions, and the first conductive ions include Mg ions.

[0064] In one embodiment, the doping concentration of the second conductive ions is greater than the doping concentration of the first conductive ions. In other embodiments, the doping concentration of the second conductive ions is equal to the doping concentration of the first conductive ions.

[0065] In one embodiment, the doping concentration of the second conductive ions is greater than the doping concentration of the first conductive ions, and the second conductive ions are doped in the second semiconductor contact layer. The doping concentration of the second conductive ions in the first sub-layer to the doping concentration of the second conductive ions in the Nth sub-layer is increasing.

[0066] In one embodiment, the shape of the second semiconductor contact layer 302 towards the side surface of the first semiconductor contact layer 301 includes a circle, an ellipse, or an irregular shape.

[0067] In one embodiment, the material of the first semiconductor contact layer 301 is Al x1 Ga 1- x1 N, 0≤x1≤1, and the material of the second semiconductor contact layer 302 is In y1 Ga 1-y1 N, 0≤y1≤1. The material of the first semiconductor contact layer 301 and the material of the second semiconductor contact layer 302 are different.

[0068] In one embodiment, the material of the first semiconductor contact layer 301 is Al x1 Ga 1-x1N (0 < x1 ≤ 0.75), and the material of the second semiconductor contact layer 302 is In y1 Ga 1-y1 N (0 ≤ y1 ≤ 1.

[0069] In one embodiment, the material of the first semiconductor contact layer 301 is GaN, and the material of the second semiconductor contact layer 302 is In y1 Ga 1-y1 N, 0.05 < y1 ≤ 1.

[0070] In one embodiment, the first electrode layer 305 is a metal electrode layer, such as Ti, Pt, Au, Ni, Co, Pb, Ag or Cu. In one embodiment, the first electrode layer 305 is a transparent oxide conductive layer, such as indium tin oxide (ITO), fluorine-doped tin oxide (FTO), AZO (aluminum-doped zinc oxide), SnO2:Sb, CdIn2O4, Cd2SnO4, ZnSnO3, Zn2SnO4, MgIn2O4, Zn2In2O5, GaInO3 or In4Sn3O 12 。

[0071] Reference Figure 4 , the semiconductor structure is a semiconductor laser. The semiconductor structure further includes: a stacked first confinement layer 110, a first waveguide layer 120, an active layer 200, a second waveguide layer 310 and a second confinement layer 320; wherein, the first semiconductor contact layer 301 is located on a side of the second confinement layer 320 away from the second waveguide layer 310; the second semiconductor contact layer 302 is located on a side of the first semiconductor contact layer 301 away from the second confinement layer 320.

[0072] Since the present invention can effectively reduce the contact resistance, thereby improving the overall performance of the semiconductor structure, such as current injection efficiency, light emission efficiency, etc., the semiconductor structure has better use effects.

[0073] The semiconductor laser includes a GaN-based semiconductor laser.

[0074] [[ID=**30**]]The conductivity type of the first confinement layer 110 is opposite to that of the second confinement layer 320.

[0075] In one embodiment, the conductivity type of the first confinement layer 110 is n-type, and the conductivity type of the second confinement layer 320 is p-type.

[0076] The conductivity type of the first waveguide layer 120 is opposite to that of the second waveguide layer 310.

[0077] In one embodiment, the conductivity type of the first waveguide layer 120 is n-type, and the conductivity type of the second waveguide layer 310 is p-type.

[0078] In one embodiment, the second waveguide layer 310 is non-intentionally doped.

[0079] The first confinement layer 110 and the first waveguide layer 120 have the same conductivity type, and the second confinement layer 320 and the second waveguide layer 310 have the same conductivity type.

[0080] The second confinement layer 320, the first semiconductor contact layer 301 and the second semiconductor contact layer 302 have the same conductivity type.

[0081] In one embodiment, the refractive index of the first semiconductor contact layer 301 is less than or equal to the refractive index of the second confinement layer 320.

[0082] In one embodiment, the material of the second confinement layer 320 includes p-type Al x2 Ga 1-x2 N. 0 < x2 < 1.

[0083] In one embodiment, x1 is less than x2.

[0084] In the embodiment, the semiconductor structure further includes: a substrate layer 100, the substrate layer 100 is located on the side of the first confinement layer 110 away from the first waveguide layer 120; a second electrode layer (not shown), the second electrode layer is located on the side of the substrate layer 100 away from the first confinement layer 110.

[0085] The substrate layer 100 is located on the side of the first semiconductor contact layer 301 away from the second semiconductor contact layer 302; the surface of the substrate layer 100 facing the first semiconductor contact layer 301 has a beveling angle θ greater than 0° and less than or equal to 1°.

[0086] In one embodiment, the semiconductor structure has a front cavity surface and a rear cavity surface arranged oppositely; the semiconductor structure further includes: an anti-reflection film located on the front cavity surface, and a reflective film located on the rear cavity surface.

[0087] Referring to Figure 5 , the thickness of the second semiconductor contact layer 302 needs to exceed the critical thickness of the material of the second semiconductor contact layer 302 to form a nanosheet structure or a nano-island structure. Whether the required second semiconductor contact layer 302 is formed can be observed by an atomic force microscope.

[0088] Another embodiment of the present application provides a preparation method of a semiconductor structure, comprising:

[0089] forming a first semiconductor contact layer 301; a first surface of the first semiconductor contact layer 301 comprises a plurality of connected step faces 3013, the step faces 3013 comprising connected main surfaces 3011 and connecting surfaces 3012; a main surface 3011 of one of the step faces 3013 is connected to a connecting surface 3012 of an adjacent one of the step faces 3013;

[0090] forming a second semiconductor contact layer 302 comprising a plurality of sub-contact structures 400, the sub-contact structures 400 being in contact with the main surfaces 3011, the sub-contact structures 400 being in a nanosheet structure or a nanoisland structure; an entire surface of one of the sub-contact structures 400 on a side facing the main surfaces 3011 is in contact with a partial area of a main surface 3011 of one of the step faces 3013;

[0091] forming a first electrode layer 305 on a side of the second semiconductor contact layer 302 facing away from the first semiconductor contact layer 301 and covering the first semiconductor contact layer 301 on sides of the sub-contact structures 400.

[0092] In the embodiment, the first electrode layer 305 is in contact with a plurality of surfaces of the second semiconductor contact layer 302 in a three-dimensional structure, the contact area of the first electrode layer 305 and the second semiconductor contact layer 302 is increased, and the contact resistance is reduced. The sub-contact structures 400 are distributed along the step faces, the shape, size and distribution of the sub-contact structures are easier to control accurately, and thus the uniformity of the contact between the second semiconductor contact layer 302 and the first electrode layer 305 is ensured.

[0093] In the embodiment, by controlling the growth conditions on the surface of the first semiconductor contact layer 301 having step faces, a stress-induced Stranski-Krastanow mode (S-K mode) is formed, the sub-contact structures in a nanosheet structure or a nanoisland structure are formed on the main surfaces, the contact area of the second semiconductor contact layer 302 and the first electrode layer 305 is increased, and the contact resistance is reduced. This method does not require complex process steps, greatly simplifies the production process, and reduces the production cost.

[0094] The sub-contact structures in a nanosheet structure or a nanoisland structure of the present application are directly formed in the process of epitaxial growth, and the sub-contact structures are formed without additional dry etching or wet etching, which avoids etching damage to the internal structure of the first semiconductor contact layer 301 and the second semiconductor contact layer 302, and avoids the influence of surface states formed in the etching process on the ohmic contact.

[0095] In one embodiment, forming the first semiconductor contact layer 301 comprises: forming the first semiconductor contact layer 301 on one side of the substrate layer 100 by epitaxial growth in a step-flow mode; the surface of the substrate layer 100 has a bevel angle, the bevel angle is greater than 0° and less than or equal to 1°; wherein the first surface of the first semiconductor contact layer 301 facing away from the substrate layer 100 comprises a plurality of connected step faces.

[0096] In one embodiment, the semiconductor structure is a semiconductor laser. The method for preparing the semiconductor structure further comprises: forming a stacked first confinement layer 110, a first waveguide layer 120, an active layer 200, a second waveguide layer 310, and a second confinement layer 320, for example, forming the stacked first confinement layer 110, the first waveguide layer 120, the active layer 200, the second waveguide layer 310, and the second confinement layer 320 on one side of the substrate layer 100 in sequence, the surface of the substrate layer 100 has a bevel angle, the bevel angle is greater than 0° and less than or equal to 1°; wherein forming the first semiconductor contact layer 301 comprises: forming the first semiconductor contact layer 301 on one side of the second confinement layer 320 facing away from the substrate layer 100, for example, forming the first semiconductor contact layer 301 on one side of the second confinement layer 320 facing away from the substrate layer 100 by epitaxial growth in a step-flow mode, wherein the first surface of the first semiconductor contact layer 301 facing away from the substrate layer 100 comprises a plurality of connected step faces; wherein forming the second semiconductor contact layer 302 comprises: forming the second semiconductor contact layer 302 on one side of the first semiconductor contact layer 301 facing away from the second confinement layer 320.

[0097] In one embodiment, forming the first semiconductor contact layer comprises: forming a first initial semiconductor contact layer; polishing the first initial surface of the first initial semiconductor contact layer to form the first semiconductor contact layer comprising step faces, and to form the first surface from the first initial surface.

[0098] In one embodiment, the growth temperature for forming the second semiconductor contact layer 302 is lower than the growth temperature for forming the first semiconductor contact layer 301.

[0099] In one embodiment, forming the second semiconductor contact layer 302 comprises: depositing and growing the second semiconductor contact layer 302 on the surface of the first semiconductor contact layer 301; the process of depositing and growing the second semiconductor contact layer 302 comprises a first stage and a second stage after the first stage; in the first stage, a two-dimensional wetting layer is formed when the thickness of the deposited material is less than a critical thickness; in the second stage, the deposition and growth continues until a nanosheet structure or a nanoisland structure is formed when the thickness of the deposited material exceeds the critical thickness. In the first stage, the growth mode is two-dimensional, and in the second stage, the growth mode changes to three-dimensional when the thickness of the deposited material exceeds the critical thickness.

[0100] The lattice mismatch degree of the second semiconductor contact layer 302 and the first semiconductor contact layer 301 is 1% to 10%. The lattice mismatch degree is: (the difference between the lattice constant of the second semiconductor contact layer 302 and the lattice constant of the first semiconductor contact layer 301) / the lattice constant of the first semiconductor contact layer 301.

[0101] The epitaxial process for forming the second semiconductor contact layer 302 includes an MOCVD epitaxial process or an MBE epitaxial growth.

[0102] In this embodiment, the step surface of the first semiconductor contact layer 301 is used to regulate the size and distribution of the sub-contact structure of the second semiconductor contact layer 302.

[0103] In this embodiment, the epitaxial growth conditions are controlled so that the second semiconductor contact layer 302 forms a nanosheet structure or a nanoisland structure. The epitaxial growth conditions are, for example, temperature, chamber pressure, and gas flow. In one embodiment, the second semiconductor contact layer 302 is formed by using an MOCVD epitaxial growth process, and the process conditions include: a growth temperature of 650°C to 740°C, a chamber pressure of 400 mbar to 1000 mbar, and the use of a first gas source containing a group III element and a second gas source containing a group V element (for example, NH3), wherein the flow ratio of the second gas source to the first gas source is 20000 to 30000.

[0104] In one embodiment, after the nanosheet structure or the nanoisland structure is generated, the temperature is lowered in an atmosphere of a protective gas. The protective gas includes, for example, any one or a combination of NH3 and N2. For example, after the nanosheet structure or the nanoisland structure is generated, the temperature is lowered under the protection of NH3 until the chamber temperature reaches 550°C. When the chamber temperature is less than 550°C, the decomposition of the second semiconductor contact layer is weakened, at which time NH3 can be kept flowing or stopped and N2 can be used instead.

[0105] In one embodiment, the sub-contact structure is a multilayer structure, and forming the sub-contact structure includes: forming a plurality of first sub-layers to Nth sub-layers stacked in sequence in a direction perpendicular to the main surface, the distance from the first sub-layer to the first semiconductor contact layer being less than the distance from the Nth sub-layer to the first semiconductor contact layer; the size of any nth sub-layer in a direction perpendicular to the main surface being less than the size of the nth sub-layer in a direction parallel to the main surface; wherein the size of the first sub-layer in a direction parallel to the main surface to the size of the Nth sub-layer in a direction parallel to the main surface decreases; N is an integer greater than or equal to 2, and n is an integer greater than or equal to 1 and less than or equal to N.

[0106] In one embodiment, the sub-contact structure is a single-layer structure.

[0107] The description of the first and second semiconductor contact layers refers to the description of the previous embodiments and is not described in detail.

[0108] Obviously, the above-mentioned embodiments are merely examples for the purpose of clear illustration, and are not intended to limit the embodiments. Based on the above description, other different forms of changes or variations can also be made by those of ordinary skill in the art. It is not necessary and impossible to enumerate all the embodiments here. The obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A semiconductor structure, characterized by, The semiconductor contact layer includes a plurality of sub-contact structures, the sub-contact structures are in contact with the main surfaces, and the sub-contact structures are in a nanosheet structure or a nanoisland structure. The first surface of the first semiconductor contact layer includes a plurality of connected step faces, the step faces include connected main surfaces and connected faces; a main surface of one of the step faces is connected to a connected face of an adjacent step face, and the main surface is arranged obliquely relative to the arrangement direction of the adjacent step face; the first surface has an oblique cutting angle θ=D / L, L is the size of the main surface along the second direction, and D is the height of the main surface along the third direction; the step faces extend along the first direction, and the adjacent step faces are arranged along the second direction; the size of the step face along the first direction is greater than the size of the step face along the second direction, and the step face is in a strip shape; the second direction, the first direction, and the third direction are perpendicular to each other. The second semiconductor contact layer includes a plurality of sub-contact structures, the sub-contact structures are in contact with the main surfaces, and the sub-contact structures are in a nanosheet structure or a nanoisland structure. The first electrode layer is located on the side of the second semiconductor contact layer away from the first semiconductor contact layer and covers the first semiconductor contact layer on the side of the sub-contact structure. At least part of the number of step faces has a height along the third direction less than or equal to 5 nm and a width along the second direction less than or equal to 500 nm.

2. The semiconductor structure of claim 1, wherein, The third direction is the stacking direction of the first semiconductor contact layer to the second semiconductor contact layer, and the third direction is perpendicular to the first direction and the second direction. The first semiconductor contact layer is doped with first conductive ions, and the first conductive ions are uniformly doped in the first semiconductor contact layer.

3. The semiconductor structure of claim 2, wherein, In a cross section perpendicular to the third direction, in a cross-sectional area within any 10*10um 2 range, more than or equal to half the number of the step surfaces have a height in the third direction of less than or equal to 5nm and a width in the second direction of less than or equal to 200nm.

4. The semiconductor structure of claim 1, wherein, Any nth sub-layer has a size along a direction perpendicular to the main surface less than a size along a direction parallel to the main surface.

5. The semiconductor structure of claim 1, wherein, The first semiconductor contact layer is doped with first conductive ions, the first conductive ions being inhomogeneously doped in the first semiconductor contact layer; wherein the doping concentration of at least a partial region of the first semiconductor contact layer is greater than or equal to 1E19 atoms / cm 3 and less than or equal to 9E21 atoms / cm 3 .

6. The semiconductor structure of claim 1, wherein, The semiconductor contact layer includes a plurality of sub-contact structures, the sub-contact structures are in contact with the main surfaces, and the sub-contact structures are in a nanosheet structure or a nanoisland structure.

7. A method of fabricating a semiconductor structure, characterized by, The semiconductor contact layer includes a plurality of sub-contact structures, the sub-contact structures are in contact with the main surfaces, and the sub-contact structures are in a nanosheet structure or a nanoisland structure. ​ forming a first semiconductor contact layer on a side of the second confinement layer facing away from the second waveguide layer; a first surface of the first semiconductor contact layer comprises a plurality of connected step faces, the step faces comprising connected main surfaces and connecting surfaces; a main surface of one of the step faces is connected to a connecting surface of an adjacent one of the step faces, the main surface being arranged obliquely with respect to a direction of arrangement of the adjacent one of the step faces; the first surface has a bevel angle θ = D / L, L being a dimension of the main surface in a second direction, D being a height of the main surface in a third direction; the step faces extend in a first direction, the adjacent ones of the step faces being arranged in the second direction; a dimension of the step faces in the first direction is greater than a dimension of the step faces in the second direction, the step faces being elongated; the second direction, the first direction and the third direction are perpendicular to each other; forming a second semiconductor contact layer on a side of the first semiconductor contact layer facing away from the second confinement layer, a lattice constant of the second semiconductor contact layer being greater than a lattice constant of the first semiconductor contact layer; the second semiconductor contact layer comprises a plurality of sub-contact structures, the sub-contact structures being located on the main surfaces, the sub-contact structures being in a nanoplate structure or a nanoisland structure; an entire surface of one of the sub-contact structures on a side facing the main surface is in contact with a partial area of a main surface of one of the step faces; wherein forming the sub-contact structures comprises forming a plurality of first to Nth sub-layers stacked in a direction perpendicular to the main surface, a distance of the first sub-layer to the first semiconductor contact layer being less than a distance of the Nth sub-layer to the first semiconductor contact layer; a dimension of the first sub-layer in a direction parallel to the main surface decreases to a dimension of the Nth sub-layer in a direction parallel to the main surface; wherein N is an integer greater than or equal to 2, n is an integer greater than or equal to 1 and less than or equal to N; forming a first electrode layer on a side of the second semiconductor contact layer facing away from the first semiconductor contact layer and covering the first semiconductor contact layer on sides of the sub-contact structures.

8. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: The method for preparing a semiconductor structure further comprises: sequentially forming a first confinement layer, a first waveguide layer, an active layer, a second waveguide layer and a second confinement layer on a side of a substrate layer, a surface of the substrate layer having a bevel angle, the bevel angle being greater than 0° and less than or equal to 1°; wherein forming the first semiconductor contact layer comprises: forming the first semiconductor contact layer on a side surface of the second confinement layer facing away from the substrate layer by epitaxial growth in a step flow mode; wherein a first surface of the first semiconductor contact layer facing away from the substrate layer comprises a plurality of connected step faces; Alternatively, forming the first semiconductor contact layer comprises: forming a first initial semiconductor contact layer; polishing a first initial surface of the first initial semiconductor contact layer by grinding, so as to form the first semiconductor contact layer comprising the step faces from the first initial semiconductor contact layer, and to form the first surface from the first initial surface.

9. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: The growth temperature for forming the second semiconductor contact layer is lower than the growth temperature for forming the first semiconductor contact layer.

10. The method of claim 9, wherein the semiconductor structure is prepared by a method comprising: Forming the second semiconductor contact layer includes: depositing a second semiconductor contact layer on the surface of the first semiconductor contact layer; during the deposition of the second semiconductor contact layer, a two-dimensional wetting layer is formed when the thickness of the deposited material is less than a critical thickness, and the deposition continues until the thickness of the deposited material exceeds the critical thickness, until a nanosheet structure or a nanoisland structure is formed.

11. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: The size of any nth sublayer in a direction perpendicular to the major surface is less than the size of the nth sublayer in a direction parallel to the major surface.

Images