SIMOBUCK control circuit based on zero cross detection

Abstract

The invention provides an SIMOBUCK control circuit based on zero cross detection, which comprises a state detection circuit, a logic control circuit and an SIMOBUCK circuit, and is characterized in that the state detection circuit monitors the SIMOBUCK circuit in real time to obtain detection data; the logic control circuit realizes charge and discharge time sequence cooperative control on each output branch of the SIMOBUCK circuit; the SIMOBUCK circuit performs electric energy conversion according to the control instruction output by the logic control circuit to obtain an output voltage VO1 and an output voltage VO2; according to the control circuit, through the synergistic effect of zero-cross detection and sequential control, precise control over the SIMOBUCK circuit can be achieved, completeness and independence of the charging and discharging processes of all branches are ensured, the problem that charge distribution is uneven under the load difference scene through existing TMC control is effectively solved, and stable operation of the circuit under complex work can be effectively guaranteed.

Description

Technical Field

[0001] This invention belongs to the field of SIMBUCK control circuit technology, and mainly relates to a SIMBUCK control circuit based on zero-crossing detection. Background Technology

[0002] The SIMOBUCK circuit, a single-inductor, multi-output buck DC-DC converter, is an innovative topology developed from the traditional BUCK circuit. The BUCK circuit, a classic buck DC-DC converter, converts a higher input voltage to a lower, stable output voltage by controlling the on / off state of switching elements (such as MOSFETs). The SIMOBUCK circuit, however, utilizes a single inductor to achieve multiple different voltage outputs, providing different supply voltages to multiple loads. Compared to traditional multiple independent BUCK circuits, the SIMOBUCK circuit offers advantages such as higher integration, smaller size, lower cost, and better electromagnetic compatibility.

[0003] In terms of timing control strategies, SIMBUCK circuits are mainly divided into two modes: Ordered-Power Distributive Control (OPDC) and Time-Multiplexing Control (TMC). The OPDC mode works by charging each output branch sequentially according to a preset order within a single switching cycle, with all outputs sharing the same feedback control network. The advantage of this mode is that it can fully utilize the entire charging cycle and has no strict limitations on load power differences; however, because each branch shares the inductor current path, when the load on one branch changes, the resulting inductor current fluctuations will couple to other branches through the common path, causing overshoot or negative pulse phenomena in the output voltage, i.e., generating a cross-modulation effect.

[0004] In contrast, the TMC mode employs a time-division multiplexing mechanism, selecting only one branch for charging in each switching cycle. Each output terminal achieves closed-loop control through an independent feedback loop, thus exhibiting higher stability and lower cross-interference. However, the TMC mode has inherent drawbacks when dealing with scenarios with significant differences in load power: for high-power load branches, the charging time allocated in a single cycle may be insufficient to provide enough charge, leading to a drop in output voltage; while for low-power load branches, excessive charging time may result in excess charge, causing voltage overshoot. This charge distribution imbalance severely restricts the application of TMC sequential SIMBUCK circuits in scenarios with large load differences. Summary of the Invention

[0005] The purpose of this invention is to provide a SIMBUCK control circuit based on zero-crossing detection to solve the problem of charge distribution imbalance in multi-output scenarios where there are significant differences in load power, which exists in the prior art.

[0006] The technical solution of this invention is: A SIMBUCK control circuit based on zero-crossing detection includes a state detection circuit, a logic control circuit, and a SIMBUCK circuit. State detection circuit: The SIMBUCK circuit is monitored in real time to obtain detection data including the inductor current IL of the SIMBUCK circuit and the output voltages VO1 and VO2 of the SIMBUCK circuit. The state detection signals are then transmitted to the logic control circuit. The state detection signals include a first voltage state detection signal, a second voltage state detection signal, a current state detection signal, and a counting state detection signal. Logic control circuit: Receives the status detection signal output by the status detection circuit, implements coordinated charging and discharging timing control of each output branch of the SIMBUCK circuit, and generates control instructions to drive the operation of the SIMBUCK circuit after internal logic operation. SIMOBUCK circuit: Based on the control commands output by the logic control circuit, it converts electrical energy to obtain output voltages VO1 and VO2.

[0007] Furthermore, in the logic control circuit, the charging and discharging timing coordination control of each output branch of the SIMBUCK circuit is implemented so that the charging operation of another branch is started only after the discharging process of one branch is completed.

[0008] Furthermore, the logic control circuit includes logic circuit LC1 and logic circuit LC2. The input terminals of logic circuit LC1 are connected to clock CLK and state detection signal, respectively. The output terminals DP0 and DN0 of logic circuit LC1 are connected to the first control terminal and the second control terminal of the SIMBUCK circuit, respectively. The counting state detection signal and the output terminals DP0 and DN0 of logic circuit LC1 are connected to the input terminals of logic circuit LC2, respectively. The output terminals DS1 and DS2 of logic circuit LC2 are connected to the third control terminal and the fourth control terminal of the SIMBUCK circuit, respectively.

[0009] Furthermore, the state detection circuit includes comparators COM1 and COM2, a zero-crossing detection circuit ZCD, a counter, and a D flip-flop DFF. The output voltage VO1 and the reference voltage VREF1 are respectively input to comparator COM1, and the output terminal D1 of comparator COM1 outputs a first voltage state detection signal to logic circuit LC1. The output voltage VO2 and the reference voltage VREF2 are respectively input to comparator COM2, and the output terminal D2 of comparator COM2 outputs a second voltage state detection signal to logic circuit LC1. The inductor current IL is input to the zero-crossing detection circuit, and the output terminal D0 of the zero-crossing detection circuit ZCD outputs a current state detection signal to the input terminal Inc of counter and logic circuit LC1. The input terminal Rst of counter is connected to a level signal, and the output terminal Cnt of counter is connected to the input terminal D of D flip-flop DFF. The input terminal CP of D flip-flop DFF is connected to clock CLK. The state signal State output by D flip-flop DFF, i.e., the counting state detection signal, is connected to logic circuit LC1 and logic circuit LC2 respectively.

[0010] Furthermore, the zero-crossing detection circuit ZCD is used to monitor the inductor current IL in real time: when the inductor current IL has not been fully discharged, the output terminal D0 of the zero-crossing detection circuit ZCD is at a low level; when the inductor current has been fully discharged, the output terminal D0 of the zero-crossing detection circuit ZCD jumps to a high level.

[0011] Furthermore, the SIMBUCK circuit includes power transistor MP0, rectifier transistor MN0, power transistor MP1, power transistor MP2, capacitors C1 and C2, loads R1 and R2. The gate of power transistor MP0 is the first control terminal connected to the output terminal DP0 of logic circuit LC1. The source of power transistor MP0 is connected to the power supply VDD. The drain of power transistor MP0 is connected to the end of inductor L and the drain of rectifier transistor MN0. The gate of rectifier transistor MN0, i.e., the second control terminal, is connected to the output terminal DN0 of logic circuit LC1. The source is connected to GND. The other end of the inductor L is connected to the source of power transistor MP1 and the source of power transistor MP2, respectively. The gate of power transistor MP1, i.e. the third control terminal, is connected to the output terminal DS1 of logic circuit LC2. The drain of power transistor MP1 is connected to capacitor C1 and load R1, respectively. Capacitor C1 and load R1 are connected in parallel and connected to GND. The gate of power transistor MP2, i.e. the fourth control terminal, is connected to the output terminal DS2 of logic circuit LC2. The drain of power transistor MP2 is connected to capacitor C2 and load R2, respectively. Capacitor C2 and load R2 are connected in parallel and connected to GND.

[0012] Furthermore, in the logic control circuit, when the rising edge of the clock CLK arrives, logic circuit LC1 performs the following logical operation based on the state signal State output by the D flip-flop DFF and each detection signal: When the state signal State output by the D flip-flop DFF is high and the output D0 of the zero-crossing detection circuit ZCD is high, the logic circuit LC1 further detects the output state of the comparator COM1: 1) When the output voltage VO1 is less than the reference voltage VREF1, it is determined that branch 1 needs to be charged. The output terminals DP0 and DN0 of the logic circuit LC1 both output low level, and the inductor L of the SIMBUCK circuit is charged to complete the charging operation of branch 1. 2) When the output voltage VO1 is greater than the reference voltage VREF1, the logic circuit LC1 determines that the charging of branch one is complete. At this time, the output terminals DP0 and DN0 of the logic circuit LC1 are both at high level, causing the inductor L of the SIMBUCK circuit to discharge. When the current of the inductor L discharges to zero, the output terminal D0 of the zero-crossing detection circuit ZCD jumps to high level, triggering the logic circuit LC1 to adjust the output terminal DP0 to high level and the output terminal DN0 to low level. The logic circuit LC2 responds to the change of the state signal State and sets the output terminals DS1 and DS2 of the logic circuit LC2 to high level. At this point, the complete charging and discharging cycle of branch one is completed, and it enters the standby state to wait for the next trigger.

[0013] Furthermore, in the logic control circuit, when the rising edge of the next clock CLK arrives, if the discharge process of inductor L has not yet ended (i.e., the output terminal D0 of the zero-crossing detection circuit ZCD remains low) and the state signal State of the output of the D flip-flop DFF is still high, then the logic circuit LC1 maintains the output terminals DP0 and DN0 at high levels. At the same time, the logic circuit LC2 maintains the output terminal DS1 at low level and the output terminal DS2 at high level, thereby maintaining the discharge of inductor L in the SIMBUCK circuit until the inductor current is completely released. Then, the output terminal D0 of the zero-crossing detection circuit jumps to high level, triggering the logic circuit LC1 to adjust the output to output terminal DP0 at high level and output terminal DN0 at low level. The logic circuit LC2 simultaneously sets both output terminals DS1 and DS2 to high level, completing the energy release process of branch one.

[0014] Furthermore, in the logic control circuit, when the rising edge of the next clock CLK arrives, if the inductor L has completed discharging (i.e., the zero-crossing detection circuit outputs D0 at a high level and the state signal State of the D flip-flop DFF output is at a low level), the control logic switches to branch two: The logic circuit LC1 first detects the output terminal D2 of comparator COM2. When the output voltage VO2 is less than the reference voltage VREF2, that is, when the output terminal D2 of comparator COM2 is at a high level, it is determined that branch two needs to be charged. At this time, the output terminals DP0 and DN0 of the logic circuit LC1 are both at a low level. At the same time, the output terminal DS1 of the logic circuit LC2 is at a high level and the output terminal DS2 is at a low level, so that the power supply charges the inductor L of the SIMBUCK circuit. During the charging process, the state of the output terminal D2 of comparator COM2 is continuously monitored. When the output voltage VO2 is greater than the reference voltage VREF2, that is, when the output terminal D2 of comparator COM2 turns low, it indicates that the charging of branch two is complete. The logic circuit LC1 adjusts the output terminals DP0 and DN0 to high level; the logic circuit LC2 maintains the output terminal DS1 at high level and the output terminal DS2 at low level, so that the inductor L of the SIMBUCK circuit discharges. When the current in inductor L discharges to zero, the output D0 of the zero-crossing detection circuit ZCD jumps to a high level again, triggering logic circuit LC1 to set output DP0 to a high level and output DN0 to a low level; logic circuit LC2 simultaneously sets outputs DS1 and DS2 to a high level, and the circuit enters standby mode. When the rising edge of the next clock CLK arrives, the charging and discharging control process of branch one or branch two is repeated according to the current state signal State and the state detection signal, so as to realize the time-division independent management of multiple outputs.

[0015] The beneficial effects of this invention are: I. This SIMBUCK control circuit based on zero-crossing detection can achieve precise control of the SIMBUCK circuit through the synergistic effect of zero-crossing detection and timing control, ensuring the integrity and independence of the charging and discharging process of each branch. It effectively solves the problem of uneven charge distribution in existing TMC control under load difference scenarios, and can effectively ensure the stable operation of the circuit under complex working conditions.

[0016] II. In this invention, the state detection circuit detects the current state of inductor L in real time and transmits the detection signal to the logic control circuit. This ensures that each output branch of the SIMBUCK circuit completes energy transfer within the charge / discharge cycle before switching to the next branch for charging, enabling precise monitoring and timing control of the inductor current. This design effectively solves the charge distribution imbalance in existing TMC timing SIMBUCK circuits in multi-output scenarios: that is, the branch with a larger load power experiences output voltage fluctuations due to insufficient charge in a single cycle, while the branch with a smaller load power suffers energy waste and voltage overshoot due to overcharging.

[0017] Third, this zero-crossing detection-based SIMBUCK control circuit significantly reduces the cross-interference problem of the TMC timing SIMBUCK circuit by optimizing the charging and discharging timing between branches. It breaks through the technical bottleneck that the circuit cannot be applied to scenarios with significant differences in load power, and provides an innovative solution for the efficient and stable operation of multi-output power supply systems. Attached Figure Description

[0018] Figure 1 This is a schematic diagram illustrating the SIMBUCK control circuit based on zero-crossing detection according to an embodiment of the present invention; Figure 2 This is an illustrative diagram illustrating a specific example of a SIMBUCK control circuit based on zero-crossing detection. Figure 3 This is a simulation waveform diagram of the inductor current and the output of the logic control circuit in a traditional TMC sequential SIMBUCK circuit. Figure 4 This is the output voltage waveform diagram of a traditional TMC sequential SIMBUCK circuit; Figure 5 This is a simulation waveform diagram of the state detection circuit of the SIMBUCK control circuit based on zero-crossing detection in the embodiment. Figure 6 This is the output voltage waveform of the SIMBUCK control circuit based on zero-crossing detection in the embodiment. Detailed Implementation

[0019] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0020] The embodiment provides a SIMBUCK control circuit based on zero-crossing detection, such as Figure 1 It includes state detection circuits, logic control circuits, and SIMBUCK circuits. State detection circuit: The SIMBUCK circuit is monitored in real time to obtain detection data including the inductor current IL of the SIMBUCK circuit and the output voltages VO1 and VO2 of the SIMBUCK circuit. The state detection signals are then transmitted to the logic control circuit. The state detection signals include a first voltage state detection signal, a second voltage state detection signal, a current state detection signal, and a counting state detection signal. Logic control circuit: Receives the status detection signal output by the status detection circuit, implements coordinated charging and discharging timing control of each output branch of the SIMBUCK circuit, and generates control instructions to drive the operation of the SIMBUCK circuit after internal logic operation. SIMOBUCK circuit: Based on the control commands output by the logic control circuit, it converts electrical energy to obtain output voltages VO1 and VO2.

[0021] This zero-crossing detection-based SIMBUCK control circuit, through the synergistic effect of zero-crossing detection and timing control, can achieve precise control of the SIMBUCK circuit, ensuring the integrity and independence of the charging and discharging process of each branch. It effectively solves the problem of uneven charge distribution in existing TMC control under load difference scenarios, and can effectively ensure the stable operation of the circuit under complex working conditions.

[0022] The state detection circuit includes comparators COM1 and COM2, a zero-crossing detection circuit ZCD, a counter, and a D flip-flop DFF. The output voltage VO1 and the reference voltage VREF1 are input to comparator COM1, and the output terminal D1 of comparator COM1 outputs a first voltage state detection signal to logic circuit LC1. The output voltage VO2 and the reference voltage VREF2 are input to comparator COM2, and the output terminal D2 of comparator COM2 outputs a second voltage state detection signal to logic circuit LC1. The inductor current IL is input to the zero-crossing detection circuit, and the output terminal D0 of the zero-crossing detection circuit ZCD outputs a current state detection signal to the input terminal Inc of counter and logic circuit LC1. The input terminal Rst of counter is connected to a level signal, and the output terminal Cnt of counter is connected to the input terminal D of D flip-flop DFF. The input terminal CP of D flip-flop DFF is connected to clock CLK. The state signal State output by D flip-flop DFF, i.e., the counting state detection signal, is connected to logic circuit LC1 and logic circuit LC2.

[0023] In the state detection circuit, the zero-crossing detection circuit ZCD is used to monitor the inductor current IL in real time and compare it with the zero current reference. The comparison result is connected to the counter Counter and the logic circuit LC1 respectively: when the inductor current IL has not been fully discharged, the output terminal D0 of the zero-crossing detection circuit ZCD is at a low level; when the inductor current is fully discharged, the output terminal D0 of the zero-crossing detection circuit ZCD jumps to a high level. The counter Counter performs edge-triggered processing on the output terminal D0 of the zero-crossing detection circuit ZCD: when the signal at the output terminal D0 jumps from a low level to a high level, the output signal Count of the counter Counter performs a state toggle operation, that is, switches from the current logic state to the opposite state (e.g., from low level to high level, or from high level to low level). The input terminal D of the D flip-flop DFF is connected to the output signal Count of the counter Counter. When the rising edge of the clock CLK arrives, the current value of the Count signal is latched and output through the output terminal Q of the D flip-flop DFF. This process enables timing synchronization and data storage of the Counter output, ensuring that the State signal of the D flip-flop (DFF) is updated only when the clock CLK is active, thus providing a stable state indication for subsequent logic control circuits.

[0024] By integrating a zero-crossing detection circuit (ZCD), a counter (Counter), and a D flip-flop (DFF) into the state detection circuit, the current state of the inductor L in the SIMBUCK circuit is sampled and processed in real time, and the state detection signal is transmitted to the logic control circuit. This enables coordinated control of the charging and discharging timing of each output branch of the SIMBUCK circuit, ensuring that the charging operation of another branch is started only after the discharge process of one branch is completed.

[0025] The logic control circuit includes logic circuit LC1 and logic circuit LC2. The input terminals of logic circuit LC1 are connected to the clock CLK and the state detection signal, respectively. The output terminals DP0 and DN0 of logic circuit LC1 are connected to the first control terminal and the second control terminal of the SIMBUCK circuit, respectively. The counting state detection signal and the output terminals DP0 and DN0 of logic circuit LC1 are connected to the input terminals of logic circuit LC2, respectively. The output terminals DS1 and DS2 of logic circuit LC2 are connected to the third control terminal and the fourth control terminal of the SIMBUCK circuit, respectively.

[0026] like Figure 2The SIMBUCK circuit includes power transistor MP0, rectifier transistor MN0, power transistors MP1 and MP2, capacitors C1 and C2, loads R1 and R2. The gate of power transistor MP0 is the first control terminal, connected to the output terminal DP0 of logic circuit LC1. The source of power transistor MP0 is connected to the power supply VDD. The drain of power transistor MP0 is connected to the end of inductor L and the drain of rectifier transistor MN0. The gate of rectifier transistor MN0, i.e., the second control terminal, is connected to the output terminal DN0 of logic circuit LC1. The source of rectifier transistor MN0... Connect to GND. The other end of the inductor L is connected to the source of power transistor MP1 and the source of power transistor MP2, respectively. The gate of power transistor MP1, i.e. the third control terminal, is connected to the output terminal DS1 of logic circuit LC2. The drain of power transistor MP1 is connected to capacitor C1 and load R1, respectively. Capacitor C1 and load R1 are connected in parallel and connected to GND. The gate of power transistor MP2, i.e. the fourth control terminal, is connected to the output terminal DS2 of logic circuit LC2. The drain of power transistor MP2 is connected to capacitor C2 and load R2, respectively. Capacitor C2 and load R2 are connected in parallel and connected to GND.

[0027] In the logic control circuit, when the rising edge of the clock CLK arrives, logic circuit LC1 performs the following logical operations based on the state signal State output by the D flip-flop DFF and various detection signals, such as... Figure 2 : When the state signal State output by the D flip-flop DFF is high and the output D0 of the zero-crossing detection circuit ZCD is high, the logic circuit LC1 further detects the output state of the comparator COM1: 1) When the output voltage VO1 is less than the reference voltage VREF1 (i.e., the output terminal D1 of comparator COM1 is high), it is determined that branch one needs to be charged. The output terminals DP0 and DN0 of logic circuit LC1 both output low levels, thereby driving power transistor MP0 to conduct and rectifier transistor MN0 to turn off. At the same time, logic circuit LC2 responds to the output state of logic circuit LC1. The output terminal DS1 of logic circuit LC2 outputs a low level and the output terminal DS2 outputs a high level, thereby turning on power transistor MP1 and turning off power transistor MP2. This realizes the process of power supply charging inductor L through MP0 and transferring energy to capacitor C1 and load R1 through the conducting power transistor MP1, thus completing the charging operation of branch one.

[0028] 2) When the output voltage VO1 is greater than the reference voltage VREF1 (i.e., the output terminal D1 of comparator COM1 is low), logic circuit LC1 determines that branch one is fully charged. At this time, the output terminals DP0 and DN0 of logic circuit LC1 are both high, turning off power transistor MP0 and turning on rectifier transistor MN0. Simultaneously, logic circuit LC2 maintains its output terminal DS1 at a low level and its output terminal DS2 at a high level, keeping power transistor MP1 on and power transistor MP2 off, thus allowing inductor L to pass through power transistor MP1, capacitor C1, load R1, and... The circuit formed by rectifier diode MN0 discharges; when the current of inductor L discharges to zero, the output terminal D0 of the zero-crossing detection circuit ZCD jumps to a high level, triggering logic circuit LC1 to adjust the output terminal DP0 to a high level and the output terminal DN0 to a low level, thereby simultaneously turning off power transistor MP0 and rectifier diode MN0; in response to the change of state signal State, logic circuit LC2 sets the output terminals DS1 and DS2 of logic circuit LC2 to a high level, turning off power transistors MP1 and MP2. Thus, the complete charging and discharging cycle of branch one is completed, and it enters standby state to wait for the next trigger.

[0029] In the logic control circuit, when the rising edge of the next clock CLK arrives, if the discharge process of inductor L has not yet ended (i.e., the output D0 of the zero-crossing detection circuit ZCD remains low), and the state signal State of the D flip-flop DFF is still high, then logic circuit LC1 maintains both outputs DP0 and DN0 at high levels, ensuring that power transistor MP0 remains off and rectifier transistor MN0 remains on. Simultaneously, logic circuit LC2 maintains outputs DS1 at low levels and DS2 at high levels, turning on power transistor MP1 and turning off power transistor MP2, thereby maintaining... Inductor L continues to discharge through the loop formed by power transistor MP1, capacitor C1, load R1, and rectifier MN0 until the inductor current is completely discharged. At this point, the output D0 of the zero-crossing detection circuit jumps to a high level, triggering logic circuit LC1 to adjust its output to a high level at output DP0 and a low level at output DN0, thereby simultaneously turning off power transistor MP0 and rectifier MN0. Logic circuit LC2 simultaneously sets both outputs DS1 and DS2 to a high level, turning off power transistors MP1 and MP2, putting the entire circuit into a shutdown state, completing the energy release process of branch one. This control mechanism ensures that the inductor current will not switch to the next stage before it is fully discharged, thus avoiding cross-interference problems caused by residual energy.

[0030] In the logic control circuit, when the rising edge of the next clock CLK arrives, if the inductor L has completed discharging (i.e., the zero-crossing detection circuit output D0 is high and the state signal State of the D flip-flop DFF is low), the control logic switches to branch two. The logic circuit LC1 first detects the output terminal D2 of comparator COM2. When the output voltage VO2 is less than the reference voltage VREF2, i.e., the output terminal D2 of comparator COM2 is at a high level, it is determined that branch two needs to be charged. At this time, the output terminals DP0 and DN0 of the logic circuit LC1 are both at a low level, which turns on the power transistor MP0 and turns off the rectifier transistor MN0. At the same time, the output terminals DS1 and DS2 of the logic circuit LC2 are at a high level, which turns off the power transistor MP1 and turns on the power transistor MP2. The power supply charges the inductor L through the power transistor MP0 and transfers energy to the capacitor C2 and the load R2 through the power transistor MP2. During the charging process, the state of the output terminal D2 of comparator COM2 is continuously monitored. When the output voltage VO2 is greater than the reference voltage VREF2, that is, when the output terminal D2 of comparator COM2 turns low, it indicates that the charging of branch two is complete. The logic circuit LC1 adjusts the output terminals DP0 and DN0 to high level, turns off the power transistor MP0 and turns on the rectifier transistor MN0. The logic circuit LC2 maintains the output terminal DS1 at high level and the output terminal DS2 at low level, so that the power transistor MP1 remains off and the power transistor MP2 remains on. The inductor L discharges through the loop formed by the power transistor MP2, capacitor C2, load R2 and rectifier transistor MN0. When the current in inductor L discharges to zero, the output D0 of the zero-crossing detection circuit ZCD jumps high again, triggering logic circuit LC1 to set output DP0 high and output DN0 low, while simultaneously turning off power transistor MP0 and rectifier transistor MN0. Logic circuit LC2 simultaneously sets outputs DS1 and DS2 high, turning off power transistors MP1 and MP2, and the circuit enters standby mode. When the next rising edge of clock CLK arrives, the charging and discharging control process of branch one or branch two is repeated based on the current state signal State and the state detection signal, achieving time-division independent management of multiple outputs. This mechanism, through the synergistic effect of zero-crossing detection and timing control, ensures the integrity and independence of the charging and discharging process of each branch, effectively solving the problem of uneven charge distribution in existing TMC control under load differences.

[0031] In this invention, the state detection circuit monitors the current state of inductor L in real time and transmits the detection signal to the logic control circuit. This ensures that each output branch of the SIMBUCK circuit completes energy transfer within a charge / discharge cycle before switching to the next branch for charging, enabling precise monitoring and timing control of the inductor current. This design effectively solves the charge distribution imbalance in existing TMC timing SIMBUCK circuits in multi-output scenarios: branches with higher load power experience output voltage fluctuations due to insufficient charge in a single cycle, while branches with lower load power suffer from energy waste and voltage overshoot due to overcharging.

[0032] This zero-crossing detection-based SIMBUCK control circuit significantly reduces the cross-interference problem of the TMC timing SIMBUCK circuit by optimizing the charging and discharging timing between branches. It overcomes the technical bottleneck that the circuit cannot be applied to scenarios with significant differences in load power, and provides an innovative solution for the efficient and stable operation of multi-output power supply systems.

[0033] The simulation comparison between this zero-crossing detection-based SIMBUCK control circuit and the traditional TMC timing SIMBUCK circuit is as follows: Figure 3 This is a simulation waveform diagram of the inductor current and the output of the logic control circuit in a traditional TMC sequential SIMBUCK circuit. Figure 3 The timing relationship of the clock signal CLK, the gate control voltage DP0 of power transistor MP0, the control level DN0 of switching transistor MN0, and the inductor current IL is presented sequentially. Figure 3 Analysis shows that when the next clock CLK signal arrives, the inductor current IL has not yet finished discharging (it is still in the positive range), and the system directly switches to charging operation for another branch, that is, the DP0 and DN0 levels switch to charging state. This forced timing switching mechanism without zero-crossing detection leads to two types of problems: for branches with high load power, the output voltage fluctuates significantly due to insufficient inductor charge in a single cycle; while branches with low load power suffer from overcharging, resulting in energy waste and voltage overshoot.

[0034] Figure 4 This is the output voltage waveform diagram of a traditional TMC sequential SIMBUCK circuit. Figure 4 Further verification revealed that the output voltages of both branches fluctuated significantly and could not be stably maintained at the target value, exposing the charge distribution imbalance problem caused by the lack of a zero-crossing detection mechanism in traditional TMC timing SIMBUCK circuits under load power difference scenarios.

[0035] Figure 5 This is a simulation waveform diagram of the state detection circuit of the SIMBUCK control circuit based on zero-crossing detection in the embodiment. Figure 5 The graph sequentially displays the curves of the clock signal CLK, the inductor current IL, and the output signal Count of the counter. Figure 5 Analysis shows that when the clock CLK signal arrives, the output signal Count of the counter is detected. When Count is high, the circuit charges and discharges the inductor and branch one; when Count is low, the circuit charges and discharges the inductor and branch two. This waveform visually demonstrates the logic of the circuit to implement time-sharing charging and discharging control of the two branches based on the Count signal, verifying the effectiveness and stability of this invention in multi-output power supply management.

[0036] Figure 6 This is the output voltage waveform of the SIMBUCK control circuit based on zero-crossing detection in the embodiment.

[0037] Figure 6 In the simulation, from top to bottom, the output voltages of branch one (VO1=1.4V) and branch two (VO2=0.9V) are exactly the same as the preset reference voltages VREF1=1.4V and VREF2=0.9V. This simulation is based on a 555kHz operating frequency, a 3.3V power supply, and uses load resistors R1=10Ω and R2=15Ω, filter capacitors C1=6μF and C2=2.2μF, and an energy storage inductor L=2μH. Figure 6 The waveform shows that the two output voltages are stable at the target value, which verifies that the SIMBUCK circuit implemented by the present invention through zero-crossing detection and timing control can accurately maintain the output voltage of each branch under load power difference scenarios (resistance difference of 50% between R1 and R2), solves the charge distribution imbalance problem of the existing TMC timing, and proves the effectiveness and reliability of the circuit design.

[0038] The simulation results above verify that the zero-crossing detection-based SIMBUCK control circuit of this embodiment can effectively solve the inherent defects of existing SIMBUCK circuits under TMC timing in multi-output scenarios: namely, the output voltage fluctuates due to insufficient charging charge in a single cycle in branches with high load power, while the energy is wasted and voltage overshoot occurs due to overcharging in branches with low load power. This zero-crossing detection-based SIMBUCK control circuit of this embodiment, through optimized control logic and detection mechanism, can effectively ensure stable operation of the circuit under complex working conditions, significantly reduce cross-interference between output branches, and improve the reliability and practicality of the power supply system.

[0039] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

Claims

1. A SIMBUCK control circuit based on zero-crossing detection, characterized in that: Includes state detection circuitry, logic control circuitry, and SIMBUCK circuitry. State detection circuit: The SIMBUCK circuit is monitored in real time to obtain detection data including the inductor current IL of the SIMBUCK circuit and the output voltages VO1 and VO2 of the SIMBUCK circuit. The state detection signals are then transmitted to the logic control circuit. The state detection signals include a first voltage state detection signal, a second voltage state detection signal, a current state detection signal, and a counting state detection signal. Logic control circuit: Receives the status detection signal output by the status detection circuit, implements coordinated charging and discharging timing control of each output branch of the SIMBUCK circuit, and generates control instructions to drive the operation of the SIMBUCK circuit after internal logic operation. SIMOBUCK circuit: Based on the control commands output by the logic control circuit, it converts electrical energy to obtain output voltages VO1 and VO2.

2. The SIMBUCK control circuit based on zero-crossing detection as described in claim 1, characterized in that: In the logic control circuit, the charging and discharging timing coordination control of each output branch of the SIMBUCK circuit is implemented by starting the charging operation of another branch only after the discharging process of one branch is completed.

3. The SIMBUCK control circuit based on zero-crossing detection as described in claim 1, characterized in that: The logic control circuit includes logic circuit LC1 and logic circuit LC2. The input terminals of logic circuit LC1 are connected to the clock CLK and the state detection signal, respectively. The output terminals DP0 and DN0 of logic circuit LC1 are connected to the first control terminal and the second control terminal of the SIMBUCK circuit, respectively. The counting state detection signal and the output terminals DP0 and DN0 of logic circuit LC1 are connected to the input terminals of logic circuit LC2, respectively. The output terminals DS1 and DS2 of logic circuit LC2 are connected to the third control terminal and the fourth control terminal of the SIMBUCK circuit, respectively.

4. The SIMBUCK control circuit based on zero-crossing detection as described in claim 3, characterized in that: The state detection circuit includes comparators COM1 and COM2, a zero-crossing detection circuit ZCD, a counter, and a D flip-flop DFF. The output voltage VO1 and the reference voltage VREF1 are respectively input to comparator COM1, and the output terminal D1 of comparator COM1 outputs a first voltage state detection signal to logic circuit LC1. The output voltage VO2 and the reference voltage VREF2 are respectively input to comparator COM2, and the output terminal D2 of comparator COM2 outputs a second voltage state detection signal to logic circuit LC1. The inductor current IL is input to the zero-crossing detection circuit. The output terminal D0 of the zero-crossing detection circuit ZCD outputs current state detection signals to the input terminal Inc of the counter and the logic circuit LC1, respectively. The input terminal Rst of the counter is connected to a level signal, and the output terminal Cnt of the counter is connected to the input terminal D of the D flip-flop DFF. The input terminal CP of the D flip-flop DFF is connected to the clock CLK. The state signal State output by the D flip-flop DFF, i.e., the counting state detection signal, is connected to the logic circuit LC1 and the logic circuit LC2, respectively.

5. The SIMBUCK control circuit based on zero-crossing detection as described in claim 4, characterized in that: The zero-crossing detection circuit ZCD is used to monitor the inductor current IL in real time: when the inductor current IL has not been fully discharged, the output terminal D0 of the zero-crossing detection circuit ZCD is at a low level; when the inductor current is fully discharged, the output terminal D0 of the zero-crossing detection circuit ZCD jumps to a high level.

6. The SIMBUCK control circuit based on zero-crossing detection as described in claim 4, characterized in that: The SIMOBUCK circuit includes power transistor MP0, rectifier transistor MN0, power transistors MP1 and MP2, capacitors C1 and C2, loads R1 and R2. The gate of power transistor MP0, which is the first control terminal, is connected to the output terminal DP0 of logic circuit LC1. The source of power transistor MP0 is connected to the power supply VDD. The drain of power transistor MP0 is connected to the end of inductor L and the drain of rectifier transistor MN0. The gate of rectifier transistor MN0, which is the second control terminal, is connected to the output terminal DN0 of logic circuit LC1. The source of rectifier transistor MN0 is connected to... GND, the other end of the inductor L is connected to the source of power transistor MP1 and the source of power transistor MP2 respectively; the gate of power transistor MP1, i.e. the third control terminal, is connected to the output terminal DS1 of logic circuit LC2, and the drain of power transistor MP1 is connected to capacitor C1 and load R1 respectively. Capacitor C1 and load R1 are connected in parallel and connected to GND; the gate of power transistor MP2, i.e. the fourth control terminal, is connected to the output terminal DS2 of logic circuit LC2, and the drain of power transistor MP2 is connected to capacitor C2 and load R2 respectively. Capacitor C2 and load R2 are connected in parallel and connected to GND.

7. The SIMBUCK control circuit based on zero-crossing detection as described in any one of claims 4-6, characterized in that: In the logic control circuit, when the rising edge of the clock CLK arrives, logic circuit LC1 performs the following logical operation based on the state signal State output by the D flip-flop DFF and various detection signals: When the state signal State output by the D flip-flop DFF is high and the output D0 of the zero-crossing detection circuit ZCD is high, the logic circuit LC1 further detects the output state of the comparator COM1: 1) When the output voltage VO1 is less than the reference voltage VREF1, it is determined that branch 1 needs to be charged. The output terminals DP0 and DN0 of the logic circuit LC1 both output low level, and the inductor L of the SIMBUCK circuit is charged to complete the charging operation of branch 1. 2) When the output voltage VO1 is greater than the reference voltage VREF1, the logic circuit LC1 determines that the charging of branch one is complete. At this time, the output terminals DP0 and DN0 of the logic circuit LC1 are both at high level, causing the inductor L of the SIMBUCK circuit to discharge. When the current of the inductor L discharges to zero, the output terminal D0 of the zero-crossing detection circuit ZCD jumps to high level, triggering the logic circuit LC1 to adjust the output terminal DP0 to high level and the output terminal DN0 to low level. The logic circuit LC2 responds to the change of the state signal State and sets the output terminals DS1 and DS2 of the logic circuit LC2 to high level. At this point, the complete charging and discharging cycle of branch one is completed, and it enters the standby state to wait for the next trigger.

8. The SIMBUCK control circuit based on zero-crossing detection as described in claim 7, characterized in that: In the logic control circuit, when the rising edge of the next clock CLK arrives, if the discharge process of inductor L has not yet ended (i.e., the output terminal D0 of the zero-crossing detection circuit ZCD remains low) and the state signal State of the output of the D flip-flop DFF is still high, then the logic circuit LC1 maintains the output terminals DP0 and DN0 at high levels. At the same time, the logic circuit LC2 maintains the output terminal DS1 at low level and the output terminal DS2 at high level, thereby maintaining the discharge of inductor L in the SIMBUCK circuit until the inductor current is completely released. Then, the output terminal D0 of the zero-crossing detection circuit jumps to high level, triggering the logic circuit LC1 to adjust the output to output terminal DP0 at high level and output terminal DN0 at low level. The logic circuit LC2 simultaneously sets both output terminals DS1 and DS2 to high level, completing the energy release process of branch one.

9. The SIMBUCK control circuit based on zero-crossing detection as described in claim 7, characterized in that: In the logic control circuit, when the rising edge of the next clock CLK arrives, if the inductor L has completed discharging (i.e., the zero-crossing detection circuit output D0 is high and the state signal State of the D flip-flop DFF is low), the control logic switches to branch two. The logic circuit LC1 first detects the output terminal D2 of comparator COM2. When the output voltage VO2 is less than the reference voltage VREF2, that is, when the output terminal D2 of comparator COM2 is at a high level, it is determined that branch two needs to be charged. At this time, the output terminals DP0 and DN0 of the logic circuit LC1 are both at a low level. At the same time, the output terminal DS1 of the logic circuit LC2 is at a high level and the output terminal DS2 is at a low level, so that the power supply charges the inductor L of the SIMBUCK circuit. During the charging process, the state of the output terminal D2 of comparator COM2 is continuously monitored. When the output voltage VO2 is greater than the reference voltage VREF2, that is, when the output terminal D2 of comparator COM2 turns low, it indicates that the charging of branch two is complete. The logic circuit LC1 adjusts the output terminals DP0 and DN0 to high level; the logic circuit LC2 maintains the output terminal DS1 at high level and the output terminal DS2 at low level, so that the inductor L of the SIMBUCK circuit discharges. When the current in inductor L discharges to zero, the output D0 of the zero-crossing detection circuit ZCD jumps to a high level again, triggering logic circuit LC1 to set output DP0 to a high level and output DN0 to a low level; logic circuit LC2 simultaneously sets outputs DS1 and DS2 to a high level, and the circuit enters standby mode. When the rising edge of the next clock CLK arrives, the charging and discharging control process of branch one or branch two is repeated according to the current state signal State and the state detection signal, so as to realize the time-division independent management of multiple outputs.

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