Inverter and control method thereof

Abstract

The invention discloses an inverter and a control method thereof. The inverter comprises a direct current bus positive electrode, a direct current bus negative electrode, a positive bus capacitor, a negative bus capacitor, an HERI C circuit, a clamping circuit and a controller. The HERI C circuit comprises a first bridge arm and a second bridge arm which are connected in parallel between the direct current bus positive electrode and the direct current bus negative electrode. The clamping circuit is connected with the midpoint of the bus, the midpoint of the first bridge arm and the midpoint of the second bridge arm. And if the absolute value of the difference value between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold value, the controller controls at least one of the rising edge moment and the falling edge moment of the PWM waves received by the two synchronous switch tubes to be different so as to reduce the absolute value of the difference value. The two synchronous tubes are an upper bridge arm switch tube of the first bridge arm and a lower bridge arm switch tube of the second bridge arm, or the upper bridge arm switch tube of the second bridge arm and the lower bridge arm switch tube of the first bridge arm. Therefore, when the two synchronous switch tubes are not synchronous, the loss between the two synchronous switch tubes is balanced.

Description

Technical Field

[0001] This application relates to the field of power supply technology, and in particular to an inverter and its control method. Background Technology

[0002] With the trend towards higher frequencies, the turn-on and turn-off times of the switching transistors in photovoltaic inverters are reduced. This exacerbates the problem of asynchronous switching transistors caused by issues such as device consistency, printed circuit board (PCB) layout, and power supply accuracy, thereby intensifying the uneven losses of the switching transistors.

[0003] Specifically, photovoltaic inverters adopt Figure 1 The illustrated Highly Efficient and Reliable Inverter Concept (HERIC) topology uses synchronous switches Q1 and Q4, and synchronous switches Q2 and Q3. Here, synchronous switches refer to those with overlapping Pulse Width Modulation (PWM) waveforms. When the turn-on or turn-off times of the two synchronous switches are asynchronous, either the positive bus capacitor C1 or the negative bus capacitor C2 will participate in commutation, causing the bus midpoint voltage (i.e., the N-point voltage) to deviate from half of the bus voltage (i.e., the voltage between BUS+ and BUS-), resulting in unbalanced losses between the two synchronous switches. For example, during the positive half-cycle of the AC grid voltage Vg, when switch Q1 turns on before switch Q4, there will be... Figure 2 The current shown by the dashed line flows through the negative bus capacitor C2, making the voltage of the negative bus capacitor C2 greater than the voltage of the positive bus capacitor C1.

[0004] In summary, when two synchronous switches are out of sync, it is particularly important to balance the losses between them. Summary of the Invention

[0005] This application provides an inverter and its control method, which can balance the losses between two synchronous switches when the two synchronous switches are out of sync.

[0006] In a first aspect, this application provides an inverter comprising a DC bus positive terminal, a DC bus negative terminal, a positive bus capacitor, a negative bus capacitor, a HERIC circuit, a clamping circuit, and a controller. The positive and negative bus capacitors are connected in series between the DC bus positive and negative terminals. The HERIC circuit includes a first bridge arm and a second bridge arm, which are connected in parallel between the DC bus positive and negative terminals. Each bridge arm includes an upper bridge arm switch and a lower bridge arm switch connected in series. The clamping circuit is connected to the bus midpoint, the midpoint of the first bridge arm, and the midpoint of the second bridge arm. The midpoints of the first and second bridge arms are used to connect to the AC power grid, and the bus midpoint is the connection point between the positive and negative bus capacitors. The controller is configured to, when the AC grid voltage is in the positive half-cycle, if the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold, indicating that at least one of the turn-on and turn-off times of the upper bridge arm switch of the first bridge arm and the lower bridge arm switch of the second bridge arm are out of sync, then control the PWM wave received by the upper bridge arm switch of the first bridge arm to have at least one different rising edge and falling edge time from the PWM wave received by the lower bridge arm switch of the second bridge arm, in order to reduce the absolute value of the difference. The controller is also configured to, when the AC grid voltage is in the negative half-cycle, if the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold, indicating that at least one of the turn-on and turn-off times of the upper bridge arm switch of the second bridge arm and the lower bridge arm switch of the first bridge arm are out of sync, then control the PWM wave received by the upper bridge arm switch of the second bridge arm to have at least one different rising edge and falling edge time from the PWM wave received by the lower bridge arm switch of the first bridge arm, in order to reduce the absolute value of the difference.

[0007] Understandably, when the turn-on and / or turn-off times of the two synchronous switches (the upper bridge arm switch of the first bridge arm and the lower bridge arm switch of the second bridge arm, or the upper bridge arm switch of the second bridge arm and the lower bridge arm switch of the first bridge arm) are not synchronized, the inverter compensates for the asynchronous defects caused by issues such as device consistency, PCB layout, and power supply accuracy by controlling the different rising and / or falling edge times of the PWM waves received by the two synchronous switches. This makes the turn-on and / or turn-off times of the two synchronous switches more consistent, thereby reducing the absolute value of the voltage difference between the positive bus capacitor and the negative bus capacitor, and thus balancing the losses between the two synchronous switches.

[0008] In a first possible implementation, both the switches in the first and second bridge arms are turned on at a high level, meaning that both switches in the first and second bridge arms are triggered to turn on on by a rising edge and to turn off by a falling edge. The controller is configured to, when the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold, indicating that the upper bridge arm switch of the first bridge arm turns off or turns on before the lower bridge arm switch of the second bridge arm, then control the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. That is, the upper bridge arm switch of the first bridge arm is turned on and / or turned off before the lower bridge arm switch of the second bridge arm, so that the turn-on time and / or turn-off time of the upper bridge arm switch of the first bridge arm and the lower bridge arm switch of the second bridge arm are more consistent after the control, thereby reducing the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor, so as to balance the losses between the upper bridge arm switch of the first bridge arm and the lower bridge arm switch of the second bridge arm. The controller is configured to, when the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold, indicating that the upper bridge arm switch of the second bridge arm is turned off or turned on before the lower bridge arm switch of the first bridge arm, control the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or, control the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm. That is, the upper bridge arm switch of the second bridge arm is turned on and / or turned off before the lower bridge arm switch of the first bridge arm, so that the turn-on time and / or turn-off time of the upper bridge arm switch of the second bridge arm and the lower bridge arm switch of the first bridge arm are more consistent, thereby reducing the absolute value of the voltage difference between the positive bus capacitor and the negative bus capacitor, so as to balance the losses between the upper bridge arm switch of the second bridge arm and the lower bridge arm switch of the first bridge arm.

[0009] In a second possible implementation, both the switches in the first and second bridge arms are turned on at a high level. The controller, when the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than a voltage threshold, indicating that the lower bridge arm switch of the second bridge arm is turned off or turned on before the upper bridge arm switch of the first bridge arm, controls the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. That is, the lower bridge arm switch of the second bridge arm is turned on and / or turned off before the upper bridge arm switch of the first bridge arm, so that the turn-on time and / or turn-off time of the upper bridge arm switch of the first bridge arm and the lower bridge arm switch of the second bridge arm are more consistent after the control, thereby reducing the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor, so as to balance the losses between the upper bridge arm switch of the first bridge arm and the lower bridge arm switch of the second bridge arm. The controller is configured to, when the voltage of the AC power grid is in the negative half-cycle, if the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than the voltage threshold, indicating that the lower bridge arm switch of the first bridge arm is turned off or turned on before the upper bridge arm switch of the second bridge arm, control the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or, control the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm. That is, the lower bridge arm switch of the first bridge arm is turned on and / or turned off before the upper bridge arm switch of the second bridge arm, so that the turn-on time and / or turn-off time of the upper bridge arm switch of the second bridge arm and the lower bridge arm switch of the first bridge arm are more consistent, thereby reducing the absolute value of the voltage difference between the positive bus capacitor and the negative bus capacitor, so as to balance the losses between the upper bridge arm switch of the second bridge arm and the lower bridge arm switch of the first bridge arm.

[0010] In a third possible implementation, both the switches in the first and second bridge arms are turned on at a low level, meaning that both switches in the first and second bridge arms are triggered to turn on by a falling edge and to turn off by a rising edge. The controller, when the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold, indicating that the upper bridge arm switch of the first bridge arm turns off or turns on before the lower bridge arm switch of the second bridge arm, controls the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. That is, the upper bridge arm switch of the first bridge arm is turned on and / or turned off before the lower bridge arm switch of the second bridge arm, so that the turn-on time and / or turn-off time of the upper bridge arm switch of the first bridge arm and the lower bridge arm switch of the second bridge arm are more consistent after the control, thereby reducing the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor, so as to balance the losses between the upper bridge arm switch of the first bridge arm and the lower bridge arm switch of the second bridge arm. The controller is configured to, when the voltage of the AC power grid is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than the voltage threshold, indicating that the upper bridge arm switch of the second bridge arm is turned off before or after the lower bridge arm switch of the first bridge arm, control the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or, control the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm. That is, the upper bridge arm switch of the second bridge arm is turned on and / or turned off before the lower bridge arm switch of the first bridge arm, so that the turn-on time and / or turn-off time of the upper bridge arm switch of the second bridge arm and the lower bridge arm switch of the first bridge arm are more consistent, thereby reducing the absolute value of the voltage difference between the positive bus capacitor and the negative bus capacitor, so as to balance the losses between the upper bridge arm switch of the second bridge arm and the lower bridge arm switch of the first bridge arm.

[0011] In a fourth possible implementation, both the switches in the first and second bridge arms are turned on at a low level. The controller, when the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than a voltage threshold, indicating that the lower bridge arm switch of the second bridge arm is turned off or turned on before the upper bridge arm switch of the first bridge arm, controls the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. That is, the lower bridge arm switch of the second bridge arm is turned on and / or turned off before the upper bridge arm switch of the first bridge arm, so that the turn-on time and / or turn-off time of the upper bridge arm switch of the first bridge arm and the lower bridge arm switch of the second bridge arm are more consistent after the control, thereby reducing the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor, so as to balance the losses between the upper bridge arm switch of the first bridge arm and the lower bridge arm switch of the second bridge arm. The controller is configured to, when the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than a voltage threshold, indicating that the lower bridge arm switch of the first bridge arm is turned off or turned on before the upper bridge arm switch of the second bridge arm, control the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or, control the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm. That is, the lower bridge arm switch of the first bridge arm is turned on and / or turned off before the upper bridge arm switch of the second bridge arm, so that the turn-on time and / or turn-off time of the upper bridge arm switch of the second bridge arm and the lower bridge arm switch of the first bridge arm are more consistent, thereby reducing the absolute value of the voltage difference between the positive bus capacitor and the negative bus capacitor, so as to balance the losses between the upper bridge arm switch of the second bridge arm and the lower bridge arm switch of the first bridge arm.

[0012] In a fifth possible implementation, the controller is configured to maintain the modulation wave of the upper bridge arm switch of the first bridge arm being the same as the modulation wave of the lower bridge arm switch of the second bridge arm, and, during the process of increasing the carrier amplitude of the upper bridge arm switch of the first bridge arm, control the carrier amplitude of the upper bridge arm switch of the first bridge arm to be greater than the carrier amplitude of the lower bridge arm switch of the second bridge arm, so that the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. The controller is also configured to maintain the modulation wave of the upper bridge arm switch of the second bridge arm being the same as the modulation wave of the lower bridge arm switch of the first bridge arm, and, during the process of increasing the carrier amplitude of the upper bridge arm switch of the second bridge arm, control the carrier amplitude of the upper bridge arm switch of the second bridge arm to be greater than the carrier amplitude of the lower bridge arm switch of the first bridge arm, so that the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0013] In a sixth possible implementation, the controller is configured to maintain the modulation wave of the upper bridge arm switch of the first bridge arm being the same as the modulation wave of the lower bridge arm switch of the second bridge arm, and, during the process of the carrier amplitude of the upper bridge arm switch of the first bridge arm decreasing, control the carrier amplitude of the upper bridge arm switch of the first bridge arm to be greater than the carrier amplitude of the lower bridge arm switch of the second bridge arm, so that the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. The controller is also configured to maintain the modulation wave of the upper bridge arm switch of the second bridge arm being the same as the modulation wave of the lower bridge arm switch of the first bridge arm, and, during the process of the carrier amplitude of the upper bridge arm switch of the second bridge arm decreasing, control the carrier amplitude of the upper bridge arm switch of the second bridge arm to be greater than the carrier amplitude of the lower bridge arm switch of the first bridge arm, so that the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0014] In a seventh possible implementation, the controller is configured to maintain the carrier wave of the upper bridge arm switch of the first bridge arm being the same as the carrier wave of the lower bridge arm switch of the second bridge arm, and, during the process of increasing the carrier amplitude of the upper bridge arm switch of the first bridge arm, control the modulation amplitude of the upper bridge arm switch of the first bridge arm to be less than the modulation amplitude of the lower bridge arm switch of the second bridge arm, so that the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. The controller is also configured to maintain the carrier wave of the upper bridge arm switch of the second bridge arm being the same as the carrier wave of the lower bridge arm switch of the first bridge arm, and, during the process of increasing the carrier amplitude of the upper bridge arm switch of the second bridge arm, control the modulation amplitude of the upper bridge arm switch of the second bridge arm to be less than the modulation amplitude of the lower bridge arm switch of the first bridge arm, so that the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0015] In an eighth possible implementation, the controller is configured to maintain the carrier wave of the upper bridge arm switch of the first bridge arm being the same as the carrier wave of the lower bridge arm switch of the second bridge arm, and, during the process of decreasing the carrier amplitude of the upper bridge arm switch of the first bridge arm, control the modulation amplitude of the upper bridge arm switch of the first bridge arm to be less than the modulation amplitude of the lower bridge arm switch of the second bridge arm, so that the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. The controller is also configured to maintain the carrier wave of the upper bridge arm switch of the second bridge arm being the same as the carrier wave of the lower bridge arm switch of the first bridge arm, and, during the process of decreasing the carrier amplitude of the upper bridge arm switch of the second bridge arm, control the modulation amplitude of the upper bridge arm switch of the second bridge arm to be less than the modulation amplitude of the lower bridge arm switch of the first bridge arm, so that the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0016] In a ninth possible implementation, the controller is configured to maintain the modulation wave of the upper bridge arm switch of the first bridge arm being the same as the modulation wave of the lower bridge arm switch of the second bridge arm, and, during the process of increasing the carrier amplitude of the lower bridge arm switch of the second bridge arm, control the carrier amplitude of the upper bridge arm switch of the first bridge arm to be less than the carrier amplitude of the lower bridge arm switch of the second bridge arm, so that the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. The controller is also configured to maintain the modulation wave of the upper bridge arm switch of the second bridge arm being the same as the modulation wave of the lower bridge arm switch of the first bridge arm, and, during the process of increasing the carrier amplitude of the lower bridge arm switch of the first bridge arm, control the carrier amplitude of the upper bridge arm switch of the second bridge arm to be less than the carrier amplitude of the lower bridge arm switch of the first bridge arm, so that the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0017] In a tenth possible implementation, the controller is configured to maintain the modulation wave of the upper bridge arm switch of the first bridge arm being the same as the modulation wave of the lower bridge arm switch of the second bridge arm, and, during the process of the carrier amplitude of the lower bridge arm switch of the second bridge arm decreasing, control the carrier amplitude of the upper bridge arm switch of the first bridge arm to be less than the carrier amplitude of the lower bridge arm switch of the second bridge arm, so that the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. The controller is also configured to maintain the modulation wave of the upper bridge arm switch of the second bridge arm being the same as the modulation wave of the lower bridge arm switch of the first bridge arm, and, during the process of the carrier amplitude of the lower bridge arm switch of the first bridge arm decreasing, control the carrier amplitude of the upper bridge arm switch of the second bridge arm to be less than the carrier amplitude of the lower bridge arm switch of the first bridge arm, so that the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0018] In an eleventh possible implementation, the controller is configured to maintain the carrier wave of the upper bridge arm switch of the first bridge arm being the same as the carrier wave of the lower bridge arm switch of the second bridge arm, and, during the process of increasing the carrier amplitude of the upper bridge arm switch of the first bridge arm, control the modulation amplitude of the upper bridge arm switch of the first bridge arm to be greater than the modulation amplitude of the lower bridge arm switch of the second bridge arm, so that the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. The controller is also configured to maintain the carrier wave of the upper bridge arm switch of the second bridge arm being the same as the carrier wave of the lower bridge arm switch of the first bridge arm, and, during the process of increasing the carrier amplitude of the upper bridge arm switch of the second bridge arm, control the modulation amplitude of the upper bridge arm switch of the second bridge arm to be greater than the modulation amplitude of the lower bridge arm switch of the first bridge arm, so that the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0019] In a twelfth possible implementation, the controller is configured to maintain the carrier wave of the upper bridge arm switch of the first bridge arm being the same as the carrier wave of the lower bridge arm switch of the second bridge arm, and, during the process of decreasing the carrier wave amplitude of the upper bridge arm switch of the first bridge arm, control the modulation amplitude of the upper bridge arm switch of the first bridge arm to be greater than the modulation amplitude of the lower bridge arm switch of the second bridge arm, so that the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. The controller is also configured to maintain the carrier wave of the upper bridge arm switch of the second bridge arm being the same as the carrier wave of the lower bridge arm switch of the first bridge arm, and, during the process of decreasing the carrier wave amplitude of the upper bridge arm switch of the second bridge arm, control the modulation amplitude of the upper bridge arm switch of the second bridge arm to be greater than the modulation amplitude of the lower bridge arm switch of the first bridge arm, so that the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0020] In the thirteenth possible implementation, the clamping circuit includes a third bridge arm and a fourth bridge arm, wherein the third bridge arm is connected between the midpoint of the bus and the midpoint of the first bridge arm, and the fourth bridge arm is connected between the midpoint of the bus and the midpoint of the second bridge arm. Both the third bridge arm and the fourth bridge arm include an upper bridge arm switch and a lower bridge arm switch connected in reverse series.

[0021] Secondly, this application provides a control method for an inverter, applied to an inverter. The inverter includes a DC bus positive terminal, a DC bus negative terminal, a positive bus capacitor, a negative bus capacitor, a HERIC circuit, and a clamping circuit. The positive and negative bus capacitors are connected in series between the DC bus positive and negative terminals. The HERIC circuit includes a first bridge arm and a second bridge arm, connected in parallel between the DC bus positive and negative terminals. Each bridge arm includes an upper bridge arm switch and a lower bridge arm switch connected in series. The clamping circuit is connected to the bus midpoint, the midpoint of the first bridge arm, and the midpoint of the second bridge arm. The midpoints of the first and second bridge arms are used to connect to the AC power grid, and the bus midpoint is the connection point between the positive and negative bus capacitors. The method includes: when the AC grid voltage is in the positive half-cycle, if the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold, the inverter controls the PWM wave received by the upper bridge arm switch of the first bridge arm to have at least one different rising edge time and falling edge time from the PWM wave received by the lower bridge arm switch of the second bridge arm, so as to reduce the absolute value of the difference. Conversely, when the AC grid voltage is in the negative half-cycle, if the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold, the inverter controls the PWM wave received by the upper bridge arm switch of the second bridge arm to have at least one different rising edge time and falling edge time from the PWM wave received by the lower bridge arm switch of the first bridge arm, so as to reduce the absolute value of the difference.

[0022] In a first possible implementation, both the switches in the first and second bridge arms are turned on at a high level. When the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold, the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than the voltage threshold, the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0023] In a second possible implementation, both the switches in the first and second bridge arms are turned on at a high level. When the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than a voltage threshold, the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than the voltage threshold, the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0024] In a third possible implementation, both the switches in the first and second bridge arms are turned on at a low level. When the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold, the inverter controls the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than the voltage threshold, the inverter controls the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0025] In a fourth possible implementation, both the switches in the first and second bridge arms are turned on at a low level. When the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than a voltage threshold, the inverter controls the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than the voltage threshold, the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0026] In a fifth possible implementation, the inverter maintains the modulation wave of the upper arm switch of the first bridge arm as the same as the modulation wave of the lower arm switch of the second bridge arm. As the carrier amplitude of the upper arm switch of the first bridge arm increases, the inverter controls the carrier amplitude of the upper arm switch of the first bridge arm to be greater than the carrier amplitude of the lower arm switch of the second bridge arm, so that the rising edge of the PWM wave received by the upper arm switch of the first bridge arm is earlier than the rising edge of the PWM wave received by the lower arm switch of the second bridge arm. The inverter also maintains the modulation wave of the upper arm switch of the second bridge arm as the same as the modulation wave of the lower arm switch of the first bridge arm. As the carrier amplitude of the upper arm switch of the second bridge arm increases, the inverter controls the carrier amplitude of the upper arm switch of the second bridge arm to be greater than the carrier amplitude of the lower arm switch of the first bridge arm, so that the rising edge of the PWM wave received by the upper arm switch of the second bridge arm is earlier than the rising edge of the PWM wave received by the lower arm switch of the first bridge arm.

[0027] In a sixth possible implementation, the inverter maintains the modulation wave of the upper bridge arm switch of the first bridge arm as the same as the modulation wave of the lower bridge arm switch of the second bridge arm. During the process of decreasing the carrier amplitude of the upper bridge arm switch of the first bridge arm, the inverter controls the carrier amplitude of the upper bridge arm switch of the first bridge arm to be greater than the carrier amplitude of the lower bridge arm switch of the second bridge arm, so that the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. The inverter maintains the modulation wave of the upper bridge arm switch of the second bridge arm as the same as the modulation wave of the lower bridge arm switch of the first bridge arm. During the process of decreasing the carrier amplitude of the upper bridge arm switch of the second bridge arm, the inverter controls the carrier amplitude of the upper bridge arm switch of the second bridge arm to be greater than the carrier amplitude of the lower bridge arm switch of the first bridge arm, so that the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0028] In a seventh possible implementation, the inverter maintains the carrier wave of the upper arm switch of the first bridge arm and the carrier wave of the lower arm switch of the second bridge arm the same. As the carrier wave amplitude of the upper arm switch of the first bridge arm increases, the inverter controls the modulation amplitude of the upper arm switch of the first bridge arm to be less than the modulation amplitude of the lower arm switch of the second bridge arm, so that the rising edge of the PWM wave received by the upper arm switch of the first bridge arm is earlier than the rising edge of the PWM wave received by the lower arm switch of the second bridge arm. The inverter also maintains the carrier wave of the upper arm switch of the second bridge arm and the carrier wave of the lower arm switch of the first bridge arm the same. As the carrier wave amplitude of the upper arm switch of the second bridge arm increases, the inverter controls the modulation amplitude of the upper arm switch of the second bridge arm to be less than the modulation amplitude of the lower arm switch of the first bridge arm, so that the rising edge of the PWM wave received by the upper arm switch of the second bridge arm is earlier than the rising edge of the PWM wave received by the lower arm switch of the first bridge arm.

[0029] In the eighth possible implementation, the inverter maintains the carrier wave of the upper arm switch of the first bridge arm and the carrier wave of the lower arm switch of the second bridge arm the same. During the process of decreasing the carrier wave amplitude of the upper arm switch of the first bridge arm, the inverter controls the modulation amplitude of the upper arm switch of the first bridge arm to be less than the modulation amplitude of the lower arm switch of the second bridge arm, so that the falling edge of the PWM wave received by the upper arm switch of the first bridge arm is later than the falling edge of the PWM wave received by the lower arm switch of the second bridge arm. The inverter also maintains the carrier wave of the upper arm switch of the second bridge arm and the carrier wave of the lower arm switch of the first bridge arm the same. During the process of decreasing the carrier wave amplitude of the upper arm switch of the second bridge arm, the inverter controls the modulation amplitude of the upper arm switch of the second bridge arm to be less than the modulation amplitude of the lower arm switch of the first bridge arm, so that the falling edge of the PWM wave received by the upper arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower arm switch of the first bridge arm.

[0030] In a ninth possible implementation, the inverter maintains the modulation wave of the upper bridge arm switch of the first bridge arm as the same as the modulation wave of the lower bridge arm switch of the second bridge arm. During the process of increasing the carrier amplitude of the lower bridge arm switch of the second bridge arm, the inverter controls the carrier amplitude of the upper bridge arm switch of the first bridge arm to be less than the carrier amplitude of the lower bridge arm switch of the second bridge arm, so that the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. The inverter maintains the modulation wave of the upper bridge arm switch of the second bridge arm as the same as the modulation wave of the lower bridge arm switch of the first bridge arm. During the process of increasing the carrier amplitude of the lower bridge arm switch of the first bridge arm, the inverter controls the carrier amplitude of the upper bridge arm switch of the second bridge arm to be less than the carrier amplitude of the lower bridge arm switch of the first bridge arm, so that the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0031] In a tenth possible implementation, the inverter maintains the modulation wave of the upper bridge arm switch of the first bridge arm as the same as the modulation wave of the lower bridge arm switch of the second bridge arm. During the process of decreasing the carrier amplitude of the lower bridge arm switch of the second bridge arm, the inverter controls the carrier amplitude of the upper bridge arm switch of the first bridge arm to be less than the carrier amplitude of the lower bridge arm switch of the second bridge arm, so that the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. The inverter maintains the modulation wave of the upper bridge arm switch of the second bridge arm as the same as the modulation wave of the lower bridge arm switch of the first bridge arm. During the process of decreasing the carrier amplitude of the lower bridge arm switch of the first bridge arm, the inverter controls the carrier amplitude of the upper bridge arm switch of the second bridge arm to be less than the carrier amplitude of the lower bridge arm switch of the first bridge arm, so that the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0032] In an eleventh possible implementation, the inverter maintains the carrier wave of the upper arm switch of the first bridge arm and the carrier wave of the lower arm switch of the second bridge arm the same. As the carrier wave amplitude of the upper arm switch of the first bridge arm increases, the inverter controls the modulation amplitude of the upper arm switch of the first bridge arm to be greater than the modulation amplitude of the lower arm switch of the second bridge arm, so that the rising edge of the PWM wave received by the upper arm switch of the first bridge arm is later than the rising edge of the PWM wave received by the lower arm switch of the second bridge arm. The inverter also maintains the carrier wave of the upper arm switch of the second bridge arm and the carrier wave of the lower arm switch of the first bridge arm the same. As the carrier wave amplitude of the upper arm switch of the second bridge arm increases, the inverter controls the modulation amplitude of the upper arm switch of the second bridge arm to be greater than the modulation amplitude of the lower arm switch of the first bridge arm, so that the rising edge of the PWM wave received by the upper arm switch of the second bridge arm is later than the rising edge of the PWM wave received by the lower arm switch of the first bridge arm.

[0033] In the twelfth possible implementation, the inverter maintains the carrier wave of the upper arm switch of the first bridge arm and the carrier wave of the lower arm switch of the second bridge arm the same. During the process of decreasing the carrier wave amplitude of the upper arm switch of the first bridge arm, the inverter controls the modulation amplitude of the upper arm switch of the first bridge arm to be greater than the modulation amplitude of the lower arm switch of the second bridge arm, so that the falling edge of the PWM wave received by the upper arm switch of the first bridge arm is earlier than the falling edge of the PWM wave received by the lower arm switch of the second bridge arm. The inverter also maintains the carrier wave of the upper arm switch of the second bridge arm and the carrier wave of the lower arm switch of the first bridge arm the same. During the process of decreasing the carrier wave amplitude of the upper arm switch of the second bridge arm, the inverter controls the modulation amplitude of the upper arm switch of the second bridge arm to be greater than the modulation amplitude of the lower arm switch of the first bridge arm, so that the falling edge of the PWM wave received by the upper arm switch of the second bridge arm is earlier than the falling edge of the PWM wave received by the lower arm switch of the first bridge arm.

[0034] In the thirteenth possible implementation, the clamping circuit includes a third bridge arm and a fourth bridge arm, wherein the third bridge arm is connected between the midpoint of the bus and the midpoint of the first bridge arm, and the fourth bridge arm is connected between the midpoint of the bus and the midpoint of the second bridge arm. Both the third bridge arm and the fourth bridge arm include an upper bridge arm switch and a lower bridge arm switch connected in reverse series.

[0035] It should be understood that the implementations and beneficial effects of the above-mentioned aspects of this application can be referenced from each other. Attached Figure Description

[0036] Figure 1 This is a structural schematic diagram of a photovoltaic inverter provided by existing technology;

[0037] Figure 2 This is a schematic diagram of the current flow in a photovoltaic inverter provided by existing technology when the two synchronous switching tubes are not synchronized;

[0038] Figure 3 This is a schematic diagram illustrating the application scenario of the inverter provided in this application;

[0039] Figure 4 This is a structural schematic diagram of the inverter provided in this application;

[0040] Figure 5 This is another structural schematic diagram of the inverter provided in this application;

[0041] Figure 6 This is a control timing diagram of the inverter provided in this application;

[0042] Figure 7 This is another control timing diagram of the inverter provided in this application;

[0043] Figure 8This is another control timing diagram of the inverter provided in this application;

[0044] Figure 9 This is another control timing diagram of the inverter provided in this application;

[0045] Figure 10 This is another control timing diagram of the inverter provided in this application;

[0046] Figure 11 This is another control timing diagram of the inverter provided in this application;

[0047] Figure 12 This is a flowchart illustrating the control method for the inverter provided in this application. Detailed Implementation

[0048] The inverter provided in this application is applicable to various fields such as photovoltaic-storage hybrid power generation, new energy smart microgrids, and power transmission and distribution, and is suitable for different application scenarios, such as photovoltaic power supply scenarios and photovoltaic-storage hybrid power supply scenarios. The following explanation uses the photovoltaic power supply scenario as an example.

[0049] See Figure 3 , Figure 3 This is a schematic diagram illustrating an application scenario of the inverter provided in this application. In a photovoltaic power supply scenario, the inverter provided in this application is... Figure 3The photovoltaic inverter 1 shown has its input connected to a photovoltaic string and its output connected to the AC grid and household loads. The photovoltaic inverter 1 includes a DC bus positive terminal (BUS+), a DC bus negative terminal (BUS-), a positive bus capacitor (C1), a negative bus capacitor (C2), a clamping circuit (11), a HERIC circuit (12), a controller (13), and a DC / DC converter circuit (14). The input of the DC / DC converter circuit (14) is connected to the input of the photovoltaic inverter 1, and its outputs are connected to both the DC bus positive terminal (BUS+) and the DC bus negative terminal (BUS-). The positive bus capacitor (C1) and the negative bus capacitor (C2) are connected in series between the DC bus positive terminal (BUS+) and the DC bus negative terminal (BUS-). The HERIC circuit 12 includes a first bridge arm, a second bridge arm, and a fifth bridge arm. The first and second bridge arms are connected in parallel between the positive terminal BUS+ and the negative terminal BUS- of the DC bus. The fifth bridge arm is connected between the midpoint of the first and second bridge arms. The first bridge arm includes an upper bridge arm switch Q1 and a lower bridge arm switch Q2 connected in series. The second bridge arm includes an upper bridge arm switch Q3 and a lower bridge arm switch Q4 connected in series. The fifth bridge arm includes an upper bridge arm switch Q5 and a lower bridge arm switch Q6 connected in reverse series. The clamping circuit 11 is connected to the bus midpoint N, the midpoint of the first bridge arm, and the midpoint of the second bridge arm. The midpoints of the first and second bridge arms are also connected to the output terminal of the photovoltaic inverter 1. Here, the bus midpoint N is the connection point of the positive bus capacitor C1 and the negative bus capacitor C2. The midpoint of either the first or second bridge arm is the connection point of the upper and lower bridge arm switches in that bridge arm.

[0050] After the photovoltaic inverter 1 starts operating, the controller 13 controls the DC / DC conversion circuit 14 to convert the DC power output from the photovoltaic string to DC power and output it to the positive terminal BUS+ and the negative terminal BUS- of the DC bus. The controller 13 also controls the clamping circuit 11 and the HERIC circuit 12 to invert the DC power between the positive terminal BUS+ and the negative terminal BUS- of the DC bus to obtain AC power and output it, so as to supply power to the AC grid and household loads.

[0051] In actual control, the PWM waves generated by the controller 13 for the two synchronous switches (such as the upper bridge arm switch Q1 and the lower bridge arm switch Q4, or the lower bridge arm switch Q2 and the upper bridge arm switch Q3) are overlapping. The two overlapping PWM waves are output to the two synchronous switches through different optocouplers. There is a difference in transmission delay between the different optocouplers, which causes the turn-on or turn-off times of the two synchronous switches to be asynchronous, thereby aggravating the imbalance of losses between the two synchronous switches. Based on this, when the voltage of the AC power grid is in the positive half-cycle, if the absolute value of the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, it indicates that the turn-on or turn-off times of the upper bridge arm switch Q1 and the lower bridge arm switch Q4 are not synchronized. Therefore, the controller 13 controls the rise time of the PWM wave received by the upper bridge arm switch Q1 to be different from at least one of the rise time and fall time of the PWM wave received by the lower bridge arm switch Q4, so as to reduce the absolute value of the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2. When the AC grid voltage is in the negative half-cycle, if the absolute value of the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, it indicates that the turn-on or turn-off times of the upper bridge arm switch Q3 and the lower bridge arm switch Q2 are not synchronized. Therefore, the controller 13 controls the rise time of the PWM wave received by the upper bridge arm switch Q3 to be different from at least one of the rise time and fall time of the PWM wave received by the lower bridge arm switch Q2, so as to reduce the absolute value of the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2.

[0052] It is understandable that the photovoltaic inverter 1 compensates for the transmission delay difference of the optocoupler by controlling the rise time and / or fall time of the PWM wave received by the two synchronous switching transistors to be different, so that the turn-on time and / or turn-off time of the two synchronous switching transistors after control tend to be consistent, thereby reducing the absolute value of the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2, so as to balance the loss between the two synchronous switching transistors.

[0053] The above are merely examples of application scenarios for the inverter provided in this application, and are not exhaustive. This application does not limit the application scenarios.

[0054] The following is combined Figures 4 to 11 The working principle of the inverter provided in this application is illustrated by an example.

[0055] See Figure 4 , Figure 4 This is a structural schematic diagram of the inverter provided in this application. Figure 4As shown, inverter 1 includes a DC bus positive terminal BUS+, a DC bus negative terminal BUS-, a positive bus capacitor C1, a negative bus capacitor C2, a clamping circuit 11, a HERIC circuit 12, and a controller 13. The DC terminals i11 and i12 of inverter 1 are used to connect to a DC power supply, and the AC terminals o11 and o12 of inverter 1 are used to connect to the AC power grid. The DC bus positive terminal BUS+ is connected to the DC terminal i11 of inverter 1, and the DC bus negative terminal BUS- is connected to the DC terminal i12 of inverter 1. For the specific connection methods between the circuits in inverter 1, please refer to [link to relevant documentation]. Figure 3 The description of the corresponding part in the photovoltaic inverter 1 shown is not repeated here. Optionally, inverter 1 also includes a DC / DC conversion circuit. For the specific location of this DC / DC conversion circuit in inverter 1, please refer to [link to relevant documentation]. Figure 3 The description of the DC / DC converter circuit 14 shown will not be repeated here.

[0056] The inverter 1 provided in this application is a clamped HERIC inverter. Please refer to [link / reference] for details. Figure 5 .like Figure 5 As shown, the clamping circuit 11 includes a third bridge arm and a fourth bridge arm. The third bridge arm is connected between the midpoint N of the bus and the midpoint of the first bridge arm. In this application, the first bridge arm is the bridge arm containing the upper bridge arm switch Q1 and the upper bridge arm switch Q2, or the bridge arm containing the upper bridge arm switch Q3 and the lower bridge arm switch Q4. Correspondingly, the second bridge arm is the bridge arm containing the upper bridge arm switch Q3 and the lower bridge arm switch Q4, or the bridge arm containing the upper bridge arm switch Q1 and the lower bridge arm switch Q2; this application does not limit this. Taking the bridge arm containing the upper bridge arm switch Q1 and the lower bridge arm switch Q2 as an example, and the bridge arm containing the upper bridge arm switch Q3 and the lower bridge arm switch Q4 as an example, then the third bridge arm includes the upper bridge arm switch Q7 and the lower bridge arm switch Q8 connected in reverse series, and the fourth bridge arm includes the upper bridge arm switch Q9 and the lower bridge arm switch Q10 connected in reverse series. For example, when the switching transistors of the bridge arms in inverter 1 are Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), the reverse series connection of the upper bridge arm switch Q7 and the lower bridge arm switch Q8 means that the drain of Q7 is connected to the drain of Q8. When the switching transistors of the bridge arms in inverter 1 are Insulated-Gate Bipolar Transistors (IGBTs), the reverse series connection of the upper bridge arm switch Q7 and the lower bridge arm switch Q8 means that the collector of Q7 is connected to the collector of Q8. Furthermore, Q5 and Q6 can be interchanged, and similarly, Q7 and Q8, as well as Q9 and Q10, can also be interchanged.

[0057] Optionally, inverter 1 also includes inductors L11 and L12. The midpoint of the first bridge arm is connected to the AC terminal o11 of inverter 1 through inductor L11, and the midpoint of the second bridge arm is connected to the AC terminal o12 of inverter 1 through inductor L12. Furthermore, for simplicity, the upper and lower bridge arm switching transistors will be referred to as "switching transistors" below.

[0058] After inverter 1 starts working, when the AC grid voltage is in the positive half-cycle, controller 13 controls switch Q1 and switch Q6 to conduct complementaryly, controls switch Q4 and switch Q1 to work synchronously (i.e., the PWM wave received by switch Q4 coincides with the PWM wave received by switch Q1), and controls switch Q7, switch Q10 and switch Q6 to work synchronously; when the AC grid voltage is in the negative half-cycle, controller 13 controls switch Q2 and switch Q5 to conduct complementaryly, controls switch Q3 and switch Q2 to work synchronously, and controls switch Q8, switch Q9 and switch Q5 to work synchronously, thereby realizing the power supply to the AC grid.

[0059] Simultaneously, controller 13 acquires the voltages of the positive bus capacitor C1 and the negative bus capacitor C2. When the AC grid voltage is in the positive half-cycle, if the absolute value of the difference between the voltages of the positive bus capacitor C1 and the negative bus capacitor C2 is greater than a voltage threshold, controller 13 controls the PWM wave received by switch Q1 to have at least one different rising edge and falling edge time from the PWM wave received by switch Q4, thereby reducing the absolute value of the voltage difference between the positive bus capacitor C1 and the negative bus capacitor C2. When the AC grid voltage is in the negative half-cycle, if the absolute value of the difference between the voltages of the positive bus capacitor C1 and the negative bus capacitor C2 is greater than a voltage threshold, controller 13 controls the PWM wave received by switch Q3 to have at least one different rising edge and falling edge time from the PWM wave received by switch Q2, thereby reducing the absolute value of the voltage difference between the positive bus capacitor C1 and the negative bus capacitor C2. The voltage threshold is greater than 0. In practical applications, the voltage threshold can be set to a relatively large value, such as 50V, so that the bus capacitor voltage equalization control mode will not be frequently activated, thereby improving the stability of inverter 1.

[0060] In one implementation scenario, all switches Q1 to Q4 are turned on at a high level and turned off at a low level; that is, the rising edge triggers the switch to turn on and the falling edge triggers the switch to turn off.

[0061] In an optional embodiment, when the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than a voltage threshold, it indicates that switch Q1 is turned off before switch Q4 or turned on after switch Q4. Therefore, the rising edge of the PWM wave received by switch Q1 is earlier than the rising edge of the PWM wave received by switch Q4, and / or the falling edge of the PWM wave received by switch Q1 is later than the falling edge of the PWM wave received by switch Q4. That is, switch Q1 is turned off after switch Q4 and / or turned on before switch Q4, thereby making the turn-on and / or turn-off times of the controlled switch Q1 and switch Q4 more consistent, thus reducing the absolute value of the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2, and balancing the losses between switch Q1 and switch Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, it indicates that switch Q3 is turned off before or after switch Q2. Therefore, the rising edge of the PWM wave received by switch Q3 is earlier than the rising edge of the PWM wave received by switch Q2, and / or the falling edge of the PWM wave received by switch Q3 is later than the falling edge of the PWM wave received by switch Q2. That is, switch Q3 is turned off after and / or turned on before switch Q2, thus making the turn-on and / or turn-off times of the controlled switch Q3 and switch Q2 more consistent. This reduces the absolute value of the voltage difference between the positive bus capacitor C1 and the negative bus capacitor C2, thereby balancing the losses between switch Q3 and switch Q2.

[0062] The controller 13 can adjust the carrier amplitude of the two switching transistors to make the rising and / or falling edge times of the PWM waves received by the two switching transistors different, as follows:

[0063] In an optional embodiment, when the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than a voltage threshold, the controller 13 keeps the modulation wave of switch Q1 the same as the modulation wave of switch Q4. During the process of increasing the carrier amplitude of switch Q1, the controller controls the carrier amplitude of switch Q1 to be greater than the carrier amplitude of switch Q4. During the process of decreasing the carrier amplitude of switch Q4, the controller keeps the carrier amplitude of switch Q1 equal to the carrier amplitude of switch Q4. This makes the rising edge of the PWM wave received by switch Q1 earlier than the rising edge of the PWM wave received by switch Q4, and the falling edge of the PWM wave received by switch Q1 is the same as the falling edge of the PWM wave received by switch Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, the controller 13 keeps the modulation wave of switch Q3 the same as that of switch Q2. During the process of increasing the carrier amplitude of switch Q3, the controller controls the carrier amplitude of switch Q3 to be greater than that of switch Q2. During the process of decreasing the carrier amplitude of switch Q2, the controller keeps the carrier amplitude of switch Q3 equal to that of switch Q2. This makes the rising edge of the PWM wave received by switch Q3 earlier than the rising edge of the PWM wave received by switch Q2, and the falling edge of the PWM wave received by switch Q3 is the same as that of switch Q2.

[0064] For example, such as Figure 6 As shown, the thick gray triangular carrier wave represents the carrier wave of switch Q1, and the thin black triangular carrier wave represents the carrier wave of switch Q4. The modulation wave L1 of switch Q1 is the same as the modulation wave L4 of switch Q4. During the period from t0 to t3, when the carrier amplitude of switch Q1 increases, the carrier amplitude of switch Q1 is greater than that of switch Q4. Therefore, the rising edge time t1 of the PWM wave received by switch Q1 is earlier than the rising edge time t2 of the PWM wave received by switch Q4. During the period from t4 to t6, when the carrier amplitude of switch Q4 decreases, the carrier amplitude of switch Q1 is equal to that of switch Q4. Therefore, the falling edge time of the PWM wave received by switch Q1 is the same as that of switch Q4, both being t5.

[0065] In another optional embodiment, when the voltage of the AC power grid is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, the controller 13 keeps the modulation wave of switch Q1 the same as the modulation wave of switch Q4. During the process of increasing the carrier amplitude of switch Q4, the controller 13 keeps the carrier amplitude of switch Q1 the same as the carrier amplitude of switch Q4. During the process of decreasing the carrier amplitude of switch Q1, the controller 13 controls the carrier amplitude of switch Q1 to be greater than the carrier amplitude of switch Q4. This makes the rising edge time of the PWM wave received by switch Q1 the same as the rising edge time of the PWM wave received by switch Q4, and the falling edge time of the PWM wave received by switch Q1 is later than the falling edge time of the PWM wave received by switch Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, the controller 13 keeps the modulation wave of switch Q3 the same as the modulation wave of switch Q2. During the process of increasing the carrier amplitude of switch Q2, the controller keeps the carrier amplitude of switch Q3 the same as the carrier amplitude of switch Q2. During the process of decreasing the carrier amplitude of switch Q3, the controller controls the carrier amplitude of switch Q3 to be greater than the carrier amplitude of switch Q2. This makes the rising edge time of the PWM wave received by switch Q3 the same as the rising edge time of the PWM wave received by switch Q2, and the falling edge time of the PWM wave received by switch Q3 is later than the falling edge time of the PWM wave received by switch Q2.

[0066] For example, such as Figure 7 As shown, the thick gray triangular carrier wave represents the carrier wave of switch Q1, and the thin black triangular carrier wave represents the carrier wave of switch Q4. The modulation wave L1 of switch Q1 is the same as the modulation wave L4 of switch Q4. During the time interval t0 to t2, i.e., as the carrier amplitude of switch Q4 increases, the carrier amplitude of switch Q1 is the same as that of switch Q4. Therefore, the rising edge time of the PWM wave of switch Q1 is the same as that of the PWM wave of switch Q4, both being time t1. During the time interval t3 to t6, i.e., as the carrier amplitude of switch Q1 decreases, the carrier amplitude of switch Q1 is greater than that of switch Q4. Therefore, the falling edge time t5 of the PWM wave of switch Q1 is later than the falling edge time t4 of the PWM wave of switch Q4.

[0067] In another optional embodiment, when the voltage of the AC power grid is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, the controller 13 keeps the modulation wave of the switch Q1 the same as the modulation wave of the switch Q4, and controls the carrier amplitude of the switch Q1 to be greater than the carrier amplitude of the switch Q4, so that the rising edge of the PWM wave received by the switch Q1 is earlier than the rising edge of the PWM wave received by the switch Q4, and the falling edge of the PWM wave received by the switch Q1 is later than the falling edge of the PWM wave received by the switch Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, the controller 13 keeps the modulation wave of the switch Q3 the same as the modulation wave of the switch Q2, and controls the carrier amplitude of the switch Q3 to be greater than the carrier amplitude of the switch Q2. This makes the rising edge of the PWM wave received by the switch Q3 earlier than the rising edge of the PWM wave received by the switch Q2, and the falling edge of the PWM wave received by the switch Q3 later than the falling edge of the PWM wave received by the switch Q2.

[0068] For example, such as Figure 8 As shown, the thick gray triangular carrier wave represents the carrier wave of switch Q1, and the thin black triangular carrier wave represents the carrier wave of switch Q4. The modulation wave L1 of switch Q1 is the same as the modulation wave L4 of switch Q4. During the time period from t0 to t6, the carrier amplitude of switch Q1 is greater than that of switch Q4. Therefore, it can be determined that the rising edge time t1 of the PWM wave of switch Q1 is earlier than the rising edge time t2 of the PWM wave of switch Q4, and the falling edge time t5 of the PWM wave of switch Q1 is later than the falling edge time t4 of the PWM wave of switch Q4.

[0069] The controller 13 can also adjust the modulation amplitude of the two switching transistors to make the rising and / or falling edge times of the PWM waves received by the two switching transistors different, as follows:

[0070] In an optional embodiment, when the AC power grid is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than a voltage threshold, the controller 13 keeps the carrier wave of switch Q1 the same as the carrier wave of switch Q4. During the process of increasing the carrier wave amplitude of switch Q1, the controller controls the modulation wave amplitude of switch Q1 to be less than the modulation wave amplitude of switch Q4. During the process of decreasing the carrier wave amplitude of switch Q1, the controller keeps the modulation wave amplitude of switch Q1 the same as the modulation wave amplitude of switch Q4. This makes the rising edge of the PWM wave received by switch Q1 earlier than the rising edge of the PWM wave received by switch Q4, and the falling edge of the PWM wave received by switch Q1 is the same as the falling edge of the PWM wave received by switch Q4. When the AC power grid is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, the controller 13 keeps the carrier wave of switch Q3 the same as the carrier wave of switch Q2. As the carrier wave amplitude of switch Q3 increases, the controller controls the modulation wave amplitude of switch Q3 to be less than the modulation wave amplitude of switch Q2. As the carrier wave amplitude of switch Q3 decreases, the controller keeps the modulation wave amplitude of switch Q3 the same as the modulation wave amplitude of switch Q2. This makes the rising edge of the PWM wave received by switch Q3 earlier than the rising edge of the PWM wave received by switch Q2, and the falling edge of the PWM wave received by switch Q3 is the same as the falling edge of the PWM wave received by switch Q2.

[0071] For example, such as Figure 9 As shown, switches Q1 and Q4 use the same triangular carrier wave, with LA and LB being two different modulation waves. The PWM wave triggering logic for switch Q1 is that modulation wave LB triggers the rising edge, and modulation wave LA triggers the falling edge; the PWM wave triggering logic for switch Q4 is that modulation wave LA triggers both the rising and falling edges. In other words, the modulation wave for switch Q4 is LA; the modulation wave for switch Q1 is LB as the carrier amplitude of switch Q1 increases, and LA as the carrier amplitude of switch Q1 decreases. Clearly, the rising edge time t1 of the PWM wave for switch Q1 is earlier than the rising edge time t2 of the PWM wave for switch Q4, and the falling edge time of the PWM wave for switch Q1 is the same as the falling edge time of the PWM wave for switch Q4, both being time t4.

[0072] In another optional embodiment, when the voltage of the AC power grid is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, the controller 13 keeps the carrier wave of switch Q1 the same as the carrier wave of switch Q4. During the process of increasing the carrier wave amplitude of switch Q1, the controller keeps the modulation wave amplitude of switch Q1 the same as the modulation wave amplitude of switch Q4. During the process of decreasing the carrier wave amplitude of switch Q1, the controller controls the modulation wave amplitude of switch Q1 to be less than the modulation wave amplitude of switch Q4. This makes the rising edge time of the PWM wave received by switch Q1 the same as the rising edge time of the PWM wave received by switch Q4, and the falling edge time of the PWM wave received by switch Q1 is later than the falling edge time of the PWM wave received by switch Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, the controller 13 keeps the carrier wave of switch Q3 the same as the carrier wave of switch Q2. As the carrier wave amplitude of switch Q3 increases, the controller keeps the modulation wave amplitude of switch Q3 the same as the modulation wave amplitude of switch Q2. As the carrier wave amplitude of switch Q3 decreases, the controller controls the modulation wave amplitude of switch Q3 to be less than the modulation wave amplitude of switch Q2. This makes the rising edge of the PWM wave received by switch Q3 the same as the rising edge of the PWM wave received by switch Q2, and the falling edge of the PWM wave received by switch Q3 is later than the falling edge of the PWM wave received by switch Q2.

[0073] For example, such as Figure 9 As shown, switches Q1 and Q4 use the same triangular carrier wave, with LA and LB being two different modulation waves. The PWM wave triggering logic for switch Q1 is that modulation wave LB triggers the rising edge, and modulation wave LA triggers the falling edge; the PWM wave triggering logic for switch Q4 is that modulation wave LB triggers both the rising and falling edges. In other words, the modulation wave for switch Q4 is LB; the modulation wave for switch Q1 is LB as the carrier amplitude of switch Q1 increases, and LA as the carrier amplitude of switch Q1 decreases. Clearly, the rising edge time of the PWM wave for switch Q1 is the same as that for switch Q4, both at time t1, and the falling edge time t4 of the PWM wave for switch Q1 is later than the falling edge time t3 of the PWM wave for switch Q4.

[0074] In another optional embodiment, when the voltage of the AC power grid is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, the controller 13 keeps the carrier wave of the switch Q1 the same as the carrier wave of the switch Q4, and controls the modulation amplitude of the switch Q1 to be less than the modulation amplitude of the switch Q4, so that the rising edge of the PWM wave received by the switch Q1 is earlier than the rising edge of the PWM wave received by the switch Q4, and the falling edge of the PWM wave received by the switch Q1 is later than the falling edge of the PWM wave received by the switch Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, the controller 13 keeps the carrier wave of the switch Q3 the same as the carrier wave of the switch Q2, and controls the modulation amplitude of the switch Q3 to be less than the modulation amplitude of the switch Q2. This makes the rising edge of the PWM wave received by the switch Q3 earlier than the rising edge of the PWM wave received by the switch Q2, and the falling edge of the PWM wave received by the switch Q3 later than the falling edge of the PWM wave received by the switch Q2.

[0075] For example, such as Figure 9 As shown, switches Q1 and Q4 use the same triangular carrier wave. The modulation wave of switch Q1 is LA, and the modulation wave of switch Q4 is LB. Clearly, the rising edge time t1 of the PWM wave of switch Q1 is earlier than the rising edge time t2 of the PWM wave of switch Q4, and the falling edge time t5 of the PWM wave of switch Q1 is later than the falling edge time t4 of the PWM wave of switch Q4.

[0076] It should be noted that this embodiment uses the adjustment of the upper bridge arm switch as an example to illustrate the specific implementation process of different rising and / or falling edge times of the PWM waves received by the two synchronous switches. In practical applications, the rising and / or falling edge times of the PWM waves received by the two synchronous switches can also be different by adjusting the lower bridge arm switch.

[0077] In another optional embodiment, when the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than a voltage threshold, it indicates that switch Q4 is turned off before or after switch Q1. Therefore, the rising edge of the PWM wave received by switch Q1 is later than the rising edge of the PWM wave received by switch Q4, and / or the falling edge of the PWM wave received by switch Q1 is earlier than the falling edge of the PWM wave received by switch Q4. That is, switch Q4 is turned off after and / or turned on before switch Q1, thereby making the turn-on and / or turn-off times of the controlled switches Q1 and Q4 more consistent, thus reducing the absolute value of the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2, and thus balancing the losses between switches Q1 and Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than the voltage threshold, it indicates that switch Q2 is turned off before switch Q3 or turned on after switch Q3. Therefore, the rising edge of the PWM wave received by switch Q3 is later than the rising edge of the PWM wave received by switch Q2, and / or the falling edge of the PWM wave received by switch Q3 is earlier than the falling edge of the PWM wave received by switch Q2. That is, switch Q2 is turned off after switch Q3 and / or turned on before switch Q3, thus making the turn-on and / or turn-off times of the controlled switch Q3 and switch Q2 more consistent. This reduces the absolute value of the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2, thereby balancing the losses between switch Q3 and switch Q2.

[0078] The controller 13 can adjust the carrier amplitude of the two switching transistors to make the rising and / or falling edge times of the PWM waves received by the two switching transistors different, as follows:

[0079] In an optional embodiment, when the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than a voltage threshold, the controller 13 keeps the modulation wave of switch Q1 the same as that of switch Q4. During the process of increasing the carrier amplitude of switch Q4, the controller controls the carrier amplitude of switch Q1 to be less than that of switch Q4. During the process of decreasing the carrier amplitude of switch Q1, the controller keeps the carrier amplitude of switch Q1 and the carrier amplitude of switch Q4 equal. This makes the rising edge of the PWM wave received by switch Q1 later than the rising edge of the PWM wave received by switch Q4, and the falling edge of the PWM wave received by switch Q1 is the same as that of switch Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than the voltage threshold, the controller 13 keeps the modulation wave of switch Q3 the same as that of switch Q2. During the process of increasing the carrier amplitude of switch Q2, the controller controls the carrier amplitude of switch Q3 to be less than that of switch Q2. During the process of decreasing the carrier amplitude of switch Q3, the controller keeps the carrier amplitude of switch Q3 equal to that of switch Q2. This makes the rising edge of the PWM wave received by switch Q3 later than the rising edge of the PWM wave received by switch Q2, and the falling edge of the PWM wave received by switch Q3 is the same as the falling edge of the PWM wave received by switch Q2.

[0080] For example, the modulation wave, carrier wave, and PWM wave of switching transistors Q1 and Q4 can be found in [reference needed]. Figure 6 The waveform diagram after Q1 and Q4 are swapped is shown below. Figure 6 In this embodiment, the modulation wave, carrier wave, and PWM wave of Q1 are respectively the modulation wave, carrier wave, and PWM wave of Q4. Figure 6 In this embodiment, the modulation wave, carrier wave, and PWM wave of Q4 are respectively the modulation wave, carrier wave, and PWM wave of Q1.

[0081] In another optional embodiment, when the voltage of the AC power grid is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than the voltage threshold, the controller 13 keeps the modulation wave of switch Q1 the same as the modulation wave of switch Q4. During the process of increasing the carrier amplitude of switch Q1, the controller keeps the carrier amplitude of switch Q1 the same as the carrier amplitude of switch Q4. During the process of decreasing the carrier amplitude of switch Q4, the controller controls the carrier amplitude of switch Q1 to be less than the carrier amplitude of switch Q4. This makes the rising edge time of the PWM wave received by switch Q1 the same as the rising edge time of the PWM wave received by switch Q4, and the falling edge time of the PWM wave received by switch Q1 is earlier than the falling edge time of the PWM wave received by switch Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than the voltage threshold, the controller 13 keeps the modulation wave of switch Q3 the same as the modulation wave of switch Q2. During the process of increasing the carrier amplitude of switch Q3, the controller keeps the carrier amplitude of switch Q3 the same as the carrier amplitude of switch Q2. During the process of decreasing the carrier amplitude of switch Q2, the controller controls the carrier amplitude of switch Q3 to be less than the carrier amplitude of switch Q2. This makes the rising edge time of the PWM wave received by switch Q3 the same as the rising edge time of the PWM wave received by switch Q2, and the falling edge time of the PWM wave received by switch Q3 is earlier than the falling edge time of the PWM wave received by switch Q2.

[0082] For example, the modulation wave, carrier wave, and PWM wave of switching transistors Q1 and Q4 can be found in [reference needed]. Figure 7 A schematic diagram of the waveform after Q1 and Q4 are swapped.

[0083] In another optional embodiment, when the voltage of the AC power grid is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than the voltage threshold, the controller 13 keeps the modulation wave of the switch Q1 the same as the modulation wave of the switch Q4, and controls the carrier amplitude of the switch Q1 to be less than the carrier amplitude of the switch Q4, so that the rising edge of the PWM wave received by the switch Q1 is later than the rising edge of the PWM wave received by the switch Q4, and the falling edge of the PWM wave received by the switch Q1 is earlier than the falling edge of the PWM wave received by the switch Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than the voltage threshold, the controller 13 keeps the modulation wave of the switch Q3 the same as the modulation wave of the switch Q2, and controls the carrier amplitude of the switch Q3 to be less than the carrier amplitude of the switch Q2. This makes the rising edge of the PWM wave received by the switch Q3 later than the rising edge of the PWM wave received by the switch Q2, and the falling edge of the PWM wave received by the switch Q3 earlier than the falling edge of the PWM wave received by the switch Q2.

[0084] For example, the modulation wave, carrier wave, and PWM wave of switching transistors Q1 and Q4 can be found in [reference needed]. Figure 8 A schematic diagram of the waveform after Q1 and Q4 are swapped.

[0085] The controller 13 can also adjust the modulation amplitude of the two switching transistors to make the rising and / or falling edge times of the PWM waves received by the two switching transistors different, as follows:

[0086] In an optional embodiment, when the voltage of the AC power grid is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than a voltage threshold, the controller 13 keeps the carrier wave of switch Q1 the same as the carrier wave of switch Q4. During the process of increasing the carrier wave amplitude of switch Q1, the controller controls the modulation wave amplitude of switch Q1 to be greater than the modulation wave amplitude of switch Q4. During the process of decreasing the carrier wave amplitude of switch Q1, the controller keeps the modulation wave amplitude of switch Q1 the same as the modulation wave amplitude of switch Q4. This makes the rising edge of the PWM wave received by switch Q1 later than the rising edge of the PWM wave received by switch Q4, and the falling edge of the PWM wave received by switch Q1 is the same as the falling edge of the PWM wave received by switch Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than the voltage threshold, the controller 13 keeps the carrier wave of switch Q3 the same as the carrier wave of switch Q2. As the carrier wave amplitude of switch Q3 increases, the controller controls the modulation wave amplitude of switch Q3 to be greater than the modulation wave amplitude of switch Q2. As the carrier wave amplitude of switch Q3 decreases, the controller keeps the modulation wave amplitude of switch Q3 the same as the modulation wave amplitude of switch Q2. This makes the rising edge of the PWM wave received by switch Q3 later than the rising edge of the PWM wave received by switch Q2, and the falling edge of the PWM wave received by switch Q3 is the same as the falling edge of the PWM wave received by switch Q2.

[0087] For example, the modulation wave, carrier wave, and PWM wave of switching transistors Q1 and Q4 can be found in [reference needed]. Figure 9 A schematic diagram of the waveform after Q1 and Q4 are swapped, and Figure 9 The description in the corresponding embodiment.

[0088] In another optional embodiment, when the voltage of the AC power grid is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than the voltage threshold, the controller 13 keeps the carrier wave of switch Q1 the same as the carrier wave of switch Q4. During the process of increasing the carrier wave amplitude of switch Q1, the controller 13 keeps the modulation wave amplitude of switch Q1 the same as the modulation wave amplitude of switch Q4. During the process of decreasing the carrier wave amplitude of switch Q1, the controller controls the modulation wave amplitude of switch Q1 to be greater than the modulation wave amplitude of switch Q4. This makes the rising edge time of the PWM wave received by switch Q1 the same as the rising edge time of the PWM wave received by switch Q4, and the falling edge time of the PWM wave received by switch Q1 is earlier than the falling edge time of the PWM wave received by switch Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than the voltage threshold, the controller 13 keeps the carrier wave of switch Q3 the same as the carrier wave of switch Q2. As the carrier wave amplitude of switch Q3 increases, the controller 13 keeps the modulation wave amplitude of switch Q3 the same as the modulation wave amplitude of switch Q2. As the carrier wave amplitude of switch Q3 decreases, the controller 13 controls the modulation wave amplitude of switch Q3 to be greater than the modulation wave amplitude of switch Q2. This makes the rising edge time of the PWM wave received by switch Q3 the same as the rising edge time of the PWM wave received by switch Q2, and the falling edge time of the PWM wave received by switch Q3 is earlier than the falling edge time of the PWM wave received by switch Q2.

[0089] For example, the modulation wave, carrier wave, and PWM wave of switching transistors Q1 and Q4 can be found in [reference needed]. Figure 10 A schematic diagram of the waveform after Q1 and Q4 are swapped, and Figure 10 The description in the corresponding embodiment.

[0090] In another optional embodiment, when the voltage of the AC power grid is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than the voltage threshold, the controller 13 keeps the carrier wave of the switch Q1 the same as the carrier wave of the switch Q4, and controls the modulation amplitude of the switch Q1 to be greater than the modulation amplitude of the switch Q4, so that the rising edge of the PWM wave received by the switch Q1 is later than the rising edge of the PWM wave received by the switch Q4, and the falling edge of the PWM wave received by the switch Q1 is earlier than the falling edge of the PWM wave received by the switch Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than the voltage threshold, the controller 13 keeps the carrier wave of the switch Q3 the same as the carrier wave of the switch Q2, and controls the modulation amplitude of the switch Q3 to be greater than the modulation amplitude of the switch Q2. This makes the rising edge of the PWM wave received by the switch Q3 later than the rising edge of the PWM wave received by the switch Q2, and the falling edge of the PWM wave received by the switch Q3 earlier than the falling edge of the PWM wave received by the switch Q2.

[0091] For example, the modulation wave, carrier wave, and PWM wave of switching transistors Q1 and Q4 can be found in [reference needed]. Figure 11 A schematic diagram of the waveform after Q1 and Q4 are swapped, and Figure 11 The description in the corresponding embodiment.

[0092] It should be noted that the voltage equalization control method (hereinafter referred to as voltage equalization control) in this application, which balances the voltage of the positive bus capacitor C1 and the negative bus capacitor C2 by controlling the different rising and / or falling edges of the PWM waves received by the two synchronous switching transistors, is a closed-loop control. Furthermore, considering that the collected voltages of the positive bus capacitor C1 and the negative bus capacitor C2 contain high-frequency ripple and second-harmonic ripple, noise data in the bus capacitor voltages may falsely trigger the voltage equalization control. Therefore, the controller 13 filters the collected bus capacitor voltages to obtain their average value, which is used as the criterion for triggering the voltage equalization control, ensuring a more accurate value of the bus capacitor voltage and thus avoiding false triggering of the voltage equalization control.

[0093] In another implementation scenario, all switches Q1 to Q4 are turned on at a low level and turned off at a high level; that is, the falling edge triggers the switch to turn on and the rising edge triggers the switch to turn off.

[0094] In an optional embodiment, when the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than a voltage threshold, it indicates that switch Q1 is turned off before switch Q4 or turned on after switch Q4. Therefore, the falling edge of the PWM wave received by switch Q1 is earlier than the falling edge of the PWM wave received by switch Q4, and / or the rising edge of the PWM wave received by switch Q1 is later than the rising edge of the PWM wave received by switch Q4. That is, switch Q1 is turned off after switch Q4 and / or turned on before switch Q4, thereby making the turn-on and / or turn-off times of the controlled switch Q1 and switch Q4 more consistent, thus reducing the absolute value of the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2, and balancing the losses between switch Q1 and switch Q4. When the AC grid voltage is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2 is greater than the voltage threshold, it indicates that switch Q3 is turned off before or after switch Q2. Therefore, the falling edge of the PWM wave received by switch Q3 is earlier than the falling edge of the PWM wave received by switch Q2, and / or the rising edge of the PWM wave received by switch Q3 is later than the rising edge of the PWM wave received by switch Q2. That is, switch Q3 is turned off after and / or turned on before switch Q2, thus making the turn-on and / or turn-off times of the controlled switch Q3 and switch Q2 more consistent. This reduces the absolute value of the voltage difference between the positive bus capacitor C1 and the negative bus capacitor C2, thereby balancing the losses between switch Q3 and switch Q2.

[0095] In another optional embodiment, when the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than a voltage threshold, it indicates that switch Q4 is turned off before or after switch Q1. Therefore, the falling edge of the PWM wave received by switch Q1 is later than the falling edge of the PWM wave received by switch Q4, and / or the rising edge of the PWM wave received by switch Q1 is earlier than the rising edge of the PWM wave received by switch Q4. That is, switch Q4 is turned off after and / or turned on before switch Q1, thereby making the turn-on and / or turn-off times of the controlled switches Q1 and Q4 more consistent, thus reducing the absolute value of the difference between the voltage of the positive bus capacitor C1 and the voltage of the negative bus capacitor C2, and thus balancing the losses between switches Q1 and Q4. When the AC grid voltage is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor C2 and the voltage of the positive bus capacitor C1 is greater than the voltage threshold, it indicates that switch Q2 is turned off before switch Q3 or turned on after switch Q3. Therefore, the falling edge of the PWM wave received by switch Q3 is later than the falling edge of the PWM wave received by switch Q2, and / or the rising edge of the PWM wave received by switch Q3 is earlier than the rising edge of the PWM wave received by switch Q2. That is, switch Q2 is turned off after switch Q3 and / or turned on before switch Q3, thus making the turn-on and / or turn-off times of the controlled switch Q3 and switch Q2 more consistent. This reduces the absolute value of the voltage difference between the positive bus capacitor C1 and the negative bus capacitor C2, thereby balancing the losses between switch Q3 and switch Q2.

[0096] In this implementation scenario, the controller 13 controls the carrier amplitude or modulation wave amplitude of the two switching transistors to make the rising edge time and / or falling edge time of the PWM wave received by the two switching transistors different. For the specific implementation method, please refer to the description of the corresponding part in the previous implementation scenario, which will not be repeated here.

[0097] In this application, inverter 1 compensates for the asynchrony defects of the switching transistors caused by issues such as device consistency (e.g., transmission delay differences in optocouplers), PCB layout, and power supply accuracy by controlling the different rising and / or falling edge times of the PWM waves of the two synchronous switching transistors. This makes the turn-on and / or turn-off times of the two synchronous switching transistors more consistent, thereby reducing the absolute value of the voltage difference between the positive bus capacitor C1 and the negative bus capacitor C2, thus balancing the losses between the two synchronous switching transistors. Furthermore, since the smaller the capacitance value, the faster the absolute value of the voltage difference between the positive bus capacitor C1 and the negative bus capacitor C2 changes, existing technologies often use large-capacity film capacitors as bus capacitors to avoid excessively rapid changes in the absolute value of this difference. However, the inverter 1 provided in this application can achieve voltage balance between the positive bus capacitor C1 and the negative bus capacitor C2. Therefore, inverter 1 can use small-capacity film capacitors as bus capacitors, thereby reducing the size of the bus capacitors and consequently reducing the size of inverter 1.

[0098] See Figure 12 , Figure 12 This is a flowchart illustrating the control method for the inverter provided in this application. The control method for the inverter provided in this application is applicable to... Figure 4 and Figure 5 Inverter 1 is shown. The control method for the inverter may include the following steps:

[0099] S101 controls the clamping circuit and the HERIC circuit to enable the inverter to supply power to the AC grid.

[0100] S102, when the AC grid voltage is in the positive half-cycle, if the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than the voltage threshold, control the PWM wave received by the upper bridge arm switch of the first bridge arm to be different from the rising edge time and falling edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm; when the AC grid voltage is in the negative half-cycle, if the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than the voltage threshold, control the PWM wave received by the upper bridge arm switch of the second bridge arm to be different from the rising edge time and falling edge time of the PWM wave received by the lower bridge arm switch of the first bridge arm, so as to reduce the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor.

[0101] In one implementation scenario, the switches in both the first and second bridge arms are turned on at a high level and turned off at a low level:

[0102] In one optional embodiment, when the AC grid voltage is in the positive half-cycle, if the voltage difference between the positive bus capacitor and the negative bus capacitor is greater than a voltage threshold, the inverter controls the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. When the AC grid voltage is in the negative half-cycle, if the voltage difference between the positive bus capacitor and the negative bus capacitor is greater than a voltage threshold, the inverter controls the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or, the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0103] The inverter can achieve different rising and / or falling edge times for the PWM waves received by the two switching transistors by adjusting the carrier amplitude of the two switching transistors, as detailed below:

[0104] In one optional embodiment, the inverter maintains the modulation wave of the upper bridge arm switch of the first bridge arm as the same as the modulation wave of the lower bridge arm switch of the second bridge arm. During the process of increasing the carrier amplitude of the upper bridge arm switch of the first bridge arm, the inverter controls the carrier amplitude of the upper bridge arm switch of the first bridge arm to be greater than the carrier amplitude of the lower bridge arm switch of the second bridge arm. During the process of decreasing the carrier amplitude of the lower bridge arm switch of the second bridge arm, the inverter maintains the carrier amplitude of the upper bridge arm switch of the first bridge arm as equal to the carrier amplitude of the lower bridge arm switch of the second bridge arm. This ensures that the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is the same as the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. Similarly, the inverter can make the rising edge of the PWM wave received by the upper arm switch of the second bridge arm earlier than the rising edge of the PWM wave received by the lower arm switch of the first bridge arm, and the falling edge of the PWM wave received by the upper arm switch of the second bridge arm is the same as the falling edge of the PWM wave received by the lower arm switch of the first bridge arm.

[0105] In another optional embodiment, the inverter maintains the modulation wave of the upper bridge arm switch of the first bridge arm as the same as the modulation wave of the lower bridge arm switch of the second bridge arm. During the process of increasing the carrier amplitude of the lower bridge arm switch of the second bridge arm, the inverter maintains the carrier amplitude of the upper bridge arm switch of the first bridge arm as the same as the carrier amplitude of the lower bridge arm switch of the second bridge arm. During the process of decreasing the carrier amplitude of the upper bridge arm switch of the first bridge arm, the inverter controls the carrier amplitude of the upper bridge arm switch of the first bridge arm to be greater than the carrier amplitude of the lower bridge arm switch of the second bridge arm. This makes the rising edge time of the PWM wave received by the upper bridge arm switch of the first bridge arm the same as the rising edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm. Furthermore, the falling edge time of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the falling edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm. Similarly, the inverter can make the rising edge of the PWM wave received by the upper arm switch of the second bridge arm the same as the rising edge of the PWM wave received by the lower arm switch of the first bridge arm, and the falling edge of the PWM wave received by the upper arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower arm switch of the first bridge arm.

[0106] In another optional embodiment, the inverter maintains the modulation wave of the upper bridge arm switch of the first bridge arm as the same as the modulation wave of the lower bridge arm switch of the second bridge arm, and controls the carrier amplitude of the upper bridge arm switch of the first bridge arm to be greater than the carrier amplitude of the lower bridge arm switch of the second bridge arm. This ensures that the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. Similarly, the inverter can ensure that the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0107] The inverter can also achieve different rising and / or falling times of the PWM waves received by the two switching transistors by adjusting the modulation amplitude values ​​of the two switching transistors, as detailed below:

[0108] In one optional embodiment, the inverter maintains the carrier wave of the upper bridge arm switch of the first bridge arm and the carrier wave of the lower bridge arm switch of the second bridge arm the same. During the process of increasing the carrier wave amplitude of the upper bridge arm switch of the first bridge arm, the inverter controls the modulation wave amplitude of the upper bridge arm switch of the first bridge arm to be less than the modulation wave amplitude of the lower bridge arm switch of the second bridge arm. During the process of decreasing the carrier wave amplitude of the upper bridge arm switch of the first bridge arm, the inverter maintains the modulation wave amplitude of the upper bridge arm switch of the first bridge arm and the modulation wave amplitude of the lower bridge arm switch of the second bridge arm the same. This makes the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm and the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm the same. Similarly, the inverter can make the rising edge of the PWM wave received by the upper arm switch of the second bridge arm earlier than the rising edge of the PWM wave received by the lower arm switch of the first bridge arm, and the falling edge of the PWM wave received by the upper arm switch of the second bridge arm is the same as the falling edge of the PWM wave received by the lower arm switch of the first bridge arm.

[0109] In another optional embodiment, the inverter maintains the carrier wave of the upper bridge arm switch of the first bridge arm and the carrier wave of the lower bridge arm switch of the second bridge arm the same. During the process of increasing the carrier wave amplitude of the upper bridge arm switch of the first bridge arm, the inverter maintains the modulation wave amplitude of the upper bridge arm switch of the first bridge arm and the modulation wave amplitude of the lower bridge arm switch of the second bridge arm the same. During the process of decreasing the carrier wave amplitude of the upper bridge arm switch of the first bridge arm, the inverter controls the modulation wave amplitude of the upper bridge arm switch of the first bridge arm to be less than the modulation wave amplitude of the lower bridge arm switch of the second bridge arm. This makes the rising edge time of the PWM wave received by the upper bridge arm switch of the first bridge arm the same as the rising edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm. Furthermore, the falling edge time of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the falling edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm. Similarly, the inverter can make the rising edge of the PWM wave received by the upper arm switch of the second bridge arm the same as the rising edge of the PWM wave received by the lower arm switch of the first bridge arm, and the falling edge of the PWM wave received by the upper arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower arm switch of the first bridge arm.

[0110] In another optional embodiment, the inverter maintains the carrier wave of the upper bridge arm switch of the first bridge arm and the carrier wave of the lower bridge arm switch of the second bridge arm the same, and controls the modulation amplitude of the upper bridge arm switch of the first bridge arm to be less than the modulation amplitude of the lower bridge arm switch of the second bridge arm. This ensures that the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. Similarly, the inverter can ensure that the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0111] In another optional implementation, when the AC grid voltage is in the positive half-cycle, if the voltage difference between the negative bus capacitor and the positive bus capacitor is greater than a voltage threshold, the inverter controls the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. When the AC grid voltage is in the negative half-cycle, if the voltage difference between the negative bus capacitor and the positive bus capacitor is greater than a voltage threshold, the inverter controls the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or, the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0112] The inverter can achieve different rising and / or falling edge times for the PWM waves received by the two switching transistors by adjusting the carrier amplitude of the two switching transistors, as detailed below:

[0113] In one optional embodiment, the inverter maintains the modulation wave of the upper bridge arm switch of the first bridge arm as the same as the modulation wave of the lower bridge arm switch of the second bridge arm. During the process of increasing the carrier amplitude of the lower bridge arm switch of the second bridge arm, the inverter controls the carrier amplitude of the upper bridge arm switch of the first bridge arm to be less than the carrier amplitude of the lower bridge arm switch of the second bridge arm. During the process of decreasing the carrier amplitude of the upper bridge arm switch of the first bridge arm, the inverter maintains the carrier amplitude of the upper bridge arm switch of the first bridge arm as equal to the carrier amplitude of the lower bridge arm switch of the second bridge arm. This ensures that the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and that the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is the same as the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. Similarly, the inverter can make the rising edge of the PWM wave received by the upper arm switch of the second bridge arm later than the rising edge of the PWM wave received by the lower arm switch of the first bridge arm, and the falling edge of the PWM wave received by the upper arm switch of the second bridge arm is the same as the falling edge of the PWM wave received by the lower arm switch of the first bridge arm.

[0114] In another optional embodiment, the inverter maintains the modulation wave of the upper bridge arm switch of the first bridge arm as the same as the modulation wave of the lower bridge arm switch of the second bridge arm. During the process of increasing the carrier amplitude of the upper bridge arm switch of the first bridge arm, the inverter maintains the carrier amplitude of the upper bridge arm switch of the first bridge arm as the same as the carrier amplitude of the lower bridge arm switch of the second bridge arm. During the process of decreasing the carrier amplitude of the lower bridge arm switch of the second bridge arm, the inverter controls the carrier amplitude of the upper bridge arm switch of the first bridge arm to be less than the carrier amplitude of the lower bridge arm switch of the second bridge arm. This makes the rising edge time of the PWM wave received by the upper bridge arm switch of the first bridge arm the same as the rising edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm. Furthermore, the falling edge time of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the falling edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm. Similarly, the inverter can make the rising edge of the PWM wave received by the upper arm switch of the second bridge arm the same as the rising edge of the PWM wave received by the lower arm switch of the first bridge arm, and the falling edge of the PWM wave received by the upper arm switch of the second bridge arm is earlier than the falling edge of the PWM wave received by the lower arm switch of the first bridge arm.

[0115] In another optional embodiment, the inverter maintains the modulation wave of the upper bridge arm switch of the first bridge arm as the same as the modulation wave of the lower bridge arm switch of the second bridge arm, and controls the carrier amplitude of the upper bridge arm switch of the first bridge arm to be less than the carrier amplitude of the lower bridge arm switch of the second bridge arm. This results in the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm being later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm being earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. Similarly, the inverter can make the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm being earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0116] The inverter can also achieve different rising and / or falling times of the PWM waves received by the two switching transistors by adjusting the modulation amplitude values ​​of the two switching transistors, as detailed below:

[0117] In one optional embodiment, the inverter maintains the carrier wave of the upper bridge arm switch of the first bridge arm and the carrier wave of the lower bridge arm switch of the second bridge arm the same. During the process of increasing the carrier wave amplitude of the upper bridge arm switch of the first bridge arm, the inverter controls the modulation wave amplitude of the upper bridge arm switch of the first bridge arm to be greater than the modulation wave amplitude of the lower bridge arm switch of the second bridge arm. During the process of decreasing the carrier wave amplitude of the upper bridge arm switch of the first bridge arm, the inverter maintains the modulation wave amplitude of the upper bridge arm switch of the first bridge arm and the modulation wave amplitude of the lower bridge arm switch of the second bridge arm the same. This makes the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm and the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm the same. Similarly, the inverter can make the rising edge of the PWM wave received by the upper arm switch of the second bridge arm later than the rising edge of the PWM wave received by the lower arm switch of the first bridge arm, and the falling edge of the PWM wave received by the upper arm switch of the second bridge arm is the same as the falling edge of the PWM wave received by the lower arm switch of the first bridge arm.

[0118] In another optional embodiment, the inverter maintains the carrier wave of the upper bridge arm switch of the first bridge arm and the carrier wave of the lower bridge arm switch of the second bridge arm the same. During the process of increasing the carrier wave amplitude of the upper bridge arm switch of the first bridge arm, the inverter maintains the modulation wave amplitude of the upper bridge arm switch of the first bridge arm and the modulation wave amplitude of the lower bridge arm switch of the second bridge arm the same. During the process of decreasing the carrier wave amplitude of the upper bridge arm switch of the first bridge arm, the inverter controls the modulation wave amplitude of the upper bridge arm switch of the first bridge arm to be greater than the modulation wave amplitude of the lower bridge arm switch of the second bridge arm. This makes the rising edge time of the PWM wave received by the upper bridge arm switch of the first bridge arm the same as the rising edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm. Furthermore, the falling edge time of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the falling edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm. Similarly, the inverter can make the rising edge of the PWM wave received by the upper arm switch of the second bridge arm the same as the rising edge of the PWM wave received by the lower arm switch of the first bridge arm, and the falling edge of the PWM wave received by the upper arm switch of the second bridge arm is earlier than the falling edge of the PWM wave received by the lower arm switch of the first bridge arm.

[0119] In another optional embodiment, the inverter maintains the carrier wave of the upper bridge arm switch of the first bridge arm and the carrier wave of the lower bridge arm switch of the second bridge arm the same, and controls the modulation amplitude of the upper bridge arm switch of the first bridge arm to be greater than the modulation amplitude of the lower bridge arm switch of the second bridge arm. This results in the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm being later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm being earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. Similarly, the inverter can make the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm being earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0120] In one implementation scenario, the switches in both the first and second bridge arms are turned on at a low level and turned off at a high level:

[0121] In one optional embodiment, when the AC grid voltage is in the positive half-cycle, if the voltage difference between the positive bus capacitor and the negative bus capacitor is greater than a voltage threshold, the inverter controls the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. When the AC grid voltage is in the negative half-cycle, if the voltage difference between the positive bus capacitor and the negative bus capacitor is greater than a voltage threshold, the inverter controls the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or, the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0122] In another optional implementation, when the AC grid voltage is in the positive half-cycle, if the voltage difference between the negative bus capacitor and the positive bus capacitor is greater than a voltage threshold, the inverter controls the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. When the AC grid voltage is in the negative half-cycle, if the voltage difference between the negative bus capacitor and the positive bus capacitor is greater than a voltage threshold, the inverter controls the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or, the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm to be earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

[0123] In specific implementation, further details regarding the operations performed by the power conversion device in the inverter control method provided in this application can be found in [reference needed]. Figure 4 and Figure 5 The implementation method of inverter 1 shown will not be described in detail here.

[0124] In this application, the inverter compensates for the asynchrony defects of the switching transistors caused by issues such as device consistency, PCB layout, and power supply accuracy by controlling the different rising and / or falling edge times of the PWM waves of the two synchronous switching transistors. This makes the turn-on and / or turn-off times of the two synchronous switching transistors more consistent, thereby reducing the absolute value of the voltage difference between the positive and negative bus capacitors and balancing the losses between the two synchronous switching transistors. Furthermore, since the smaller the capacitance value, the faster the absolute value of the voltage difference between the positive and negative bus capacitors changes, existing technologies often use large-capacity film capacitors as bus capacitors to avoid excessively rapid changes in the absolute value of this difference. However, the inverter provided in this application can achieve voltage balance between the positive and negative bus capacitors. Therefore, the inverter can use small-capacity film capacitors as bus capacitors, thereby reducing the size of the bus capacitors and consequently the size of the inverter.

[0125] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An inverter, characterized in that, The inverter includes a positive DC bus, a negative DC bus, a positive bus capacitor, a negative bus capacitor, a HERIC circuit, a clamping circuit, and a controller, wherein: The positive bus capacitor and the negative bus capacitor are connected in series between the positive terminal of the DC bus and the negative terminal of the DC bus. The HERIC circuit includes a first bridge arm and a second bridge arm, which are connected in parallel between the positive terminal of the DC bus and the negative terminal of the DC bus. Both the first bridge arm and the second bridge arm include an upper bridge arm switch and a lower bridge arm switch connected in series. The clamping circuit is connected to the midpoint of the busbar, the midpoint of the first bridge arm, and the midpoint of the second bridge arm, respectively. The midpoint of the first bridge arm and the midpoint of the second bridge arm are used to connect to the AC power grid. The midpoint of the busbar is the connection point of the positive busbar capacitor and the negative busbar capacitor. The controller is configured to, when the voltage of the AC power grid is in the positive half-cycle, if the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold, control the PWM wave received by the upper bridge arm switch of the first bridge arm to be different from the rising edge time and falling edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm; and when the voltage of the AC power grid is in the negative half-cycle, if the absolute value of the difference is greater than the voltage threshold, control the PWM wave received by the upper bridge arm switch of the second bridge arm to be different from the rising edge time and falling edge time of the PWM wave received by the lower bridge arm switch of the first bridge arm, so as to reduce the absolute value of the difference.

2. The inverter according to claim 1, characterized in that, The switching transistors in both the first and second bridge arms are turned on at a high level; The controller is configured to, when the voltage of the AC power grid is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than the voltage threshold, control the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, control the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. When the voltage of the AC power grid is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than the voltage threshold, the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is controlled to be earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

3. The inverter according to claim 1, characterized in that, The switching transistors in both the first and second bridge arms are turned on at a high level; The controller is configured to, when the voltage of the AC power grid is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than the voltage threshold, control the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, control the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. When the voltage of the AC power grid is in the negative half-cycle, if the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than the voltage threshold, the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

4. The inverter according to claim 1, characterized in that, The switching transistors in both the first and second bridge arms are turned on at a low level; The controller is configured to, when the voltage of the AC power grid is in the positive half-cycle, if the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than the voltage threshold, control the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, control the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. When the voltage of the AC power grid is in the negative half-cycle, if the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than the voltage threshold, the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is controlled to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

5. The inverter according to claim 1, characterized in that, The switching transistors in both the first and second bridge arms are turned on at a low level; The controller is configured to, when the voltage of the AC power grid is in the positive half-cycle, if the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than the voltage threshold, control the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or, control the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. When the voltage of the AC power grid is in the negative half-cycle, if the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than the voltage threshold, the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

6. The inverter according to claim 2 or 5, characterized in that, The condition that the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm includes: The modulation wave of the upper bridge arm switch of the first bridge arm is kept the same as that of the lower bridge arm switch of the second bridge arm, and during the process of increasing the carrier amplitude of the upper bridge arm switch of the first bridge arm, the carrier amplitude of the upper bridge arm switch of the first bridge arm is controlled to be greater than the carrier amplitude of the lower bridge arm switch of the second bridge arm.

7. The inverter according to claim 2, 5 or 6, characterized in that, The statement that the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm includes: The modulation wave of the upper bridge arm switch of the first bridge arm is kept the same as that of the lower bridge arm switch of the second bridge arm, and during the process of the carrier amplitude of the upper bridge arm switch of the first bridge arm decreasing, the carrier amplitude of the upper bridge arm switch of the first bridge arm is controlled to be greater than the carrier amplitude of the lower bridge arm switch of the second bridge arm.

8. The inverter according to claim 2 or 5, characterized in that, The condition that the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm includes: The carrier wave of the upper bridge arm switch of the first bridge arm is kept the same as that of the lower bridge arm switch of the second bridge arm, and as the carrier wave amplitude of the upper bridge arm switch of the first bridge arm increases, the modulation amplitude of the upper bridge arm switch of the first bridge arm is controlled to be less than the modulation amplitude of the lower bridge arm switch of the second bridge arm.

9. The inverter according to claim 2, 5 or 8, characterized in that, The statement that the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm includes: The carrier wave of the upper bridge arm switch of the first bridge arm is kept the same as that of the lower bridge arm switch of the second bridge arm, and during the process of the carrier wave amplitude of the upper bridge arm switch of the first bridge arm decreasing, the modulation wave amplitude of the upper bridge arm switch of the first bridge arm is controlled to be less than the modulation wave amplitude of the lower bridge arm switch of the second bridge arm.

10. The inverter according to claim 3 or 4, characterized in that, The statement that the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm includes: The modulation wave of the upper bridge arm switch of the first bridge arm is kept the same as that of the lower bridge arm switch of the second bridge arm, and as the carrier amplitude of the lower bridge arm switch of the second bridge arm increases, the carrier amplitude of the upper bridge arm switch of the first bridge arm is controlled to be less than that of the lower bridge arm switch of the second bridge arm.

11. The inverter according to claim 3, 4 or 10, characterized in that, The step of controlling the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm includes: The modulation wave of the upper bridge arm switch of the first bridge arm is kept the same as that of the lower bridge arm switch of the second bridge arm, and during the process of the carrier amplitude of the lower bridge arm switch of the second bridge arm decreasing, the carrier amplitude of the upper bridge arm switch of the first bridge arm is controlled to be less than the carrier amplitude of the lower bridge arm switch of the second bridge arm.

12. The inverter according to claim 3 or 4, characterized in that, The statement that the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm includes: The carrier wave of the upper bridge arm switch of the first bridge arm is kept the same as the carrier wave of the lower bridge arm switch of the second bridge arm, and as the carrier wave amplitude of the upper bridge arm switch of the first bridge arm increases, the modulation wave amplitude of the upper bridge arm switch of the first bridge arm is controlled to be greater than the modulation wave amplitude of the lower bridge arm switch of the second bridge arm.

13. The inverter according to claim 3, 4 or 12, characterized in that, The step of controlling the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm to be earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm includes: The carrier wave of the upper bridge arm switch of the first bridge arm is kept the same as that of the lower bridge arm switch of the second bridge arm, and during the process of the carrier wave amplitude of the upper bridge arm switch of the first bridge arm decreasing, the modulation wave amplitude of the upper bridge arm switch of the first bridge arm is controlled to be greater than that of the lower bridge arm switch of the second bridge arm.

14. The inverter according to any one of claims 1-13, characterized in that, The clamping circuit includes a third bridge arm and a fourth bridge arm, wherein the third bridge arm is connected between the midpoint of the busbar and the midpoint of the first bridge arm, and the fourth bridge arm is connected between the midpoint of the busbar and the midpoint of the second bridge arm. Both the third bridge arm and the fourth bridge arm include an upper bridge arm switch and a lower bridge arm switch connected in reverse series.

15. A control method for an inverter, applied to the inverter, the inverter comprising a positive DC bus, a negative DC bus, a positive bus capacitor, a negative bus capacitor, a HERIC circuit, and a clamping circuit, wherein, The positive bus capacitor and the negative bus capacitor are connected in series between the positive and negative terminals of the DC bus; the HERIC circuit includes a first bridge arm and a second bridge arm, which are connected in parallel between the positive and negative terminals of the DC bus. Each of the first and second bridge arms includes an upper bridge arm switch and a lower bridge arm switch connected in series. The clamping circuit is connected to the midpoint of the bus, the midpoint of the first bridge arm, and the midpoint of the second bridge arm, respectively. The midpoints of the first and second bridge arms are used to connect to the AC power grid. The midpoint of the bus is the connection point between the positive and negative bus capacitors. The method includes: When the AC grid voltage is in the positive half-cycle, if the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold, the rising edge and falling edge times of the PWM wave received by the upper bridge arm switch of the first bridge arm are controlled to be different from those of the rising edge and falling edge times of the PWM wave received by the lower bridge arm switch of the second bridge arm; when the AC grid voltage is in the negative half-cycle, if the absolute value of the difference is greater than the voltage threshold, the rising edge and falling edge times of the PWM wave received by the upper bridge arm switch of the second bridge arm are controlled to be different from those of the rising edge and falling edge times of the PWM wave received by the lower bridge arm switch of the first bridge arm, so as to reduce the absolute value of the difference.

16. The method according to claim 15, characterized in that, The switching transistors in both the first and second bridge arms are turned on at a high level; The step of controlling the PWM wave received by the upper bridge arm switch of the first bridge arm to have at least one difference between the rising edge time and the falling edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm if the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold includes: If the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than the voltage threshold, the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. If the absolute value of the difference is greater than the voltage threshold, controlling the PWM wave received by the upper bridge arm switch of the second bridge arm to have at least one difference between the rising edge time and the falling edge time of the PWM wave received by the lower bridge arm switch of the first bridge arm includes: If the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than the voltage threshold, the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

17. The method according to claim 15, characterized in that, The switching transistors in both the first and second bridge arms are turned on at a high level; The step of controlling the PWM wave received by the upper bridge arm switch of the first bridge arm to have at least one difference between the rising edge time and the falling edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm if the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold includes: If the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than the voltage threshold, the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. If the absolute value of the difference is greater than the voltage threshold, controlling the PWM wave received by the upper bridge arm switch of the second bridge arm to have at least one difference between the rising edge time and the falling edge time of the PWM wave received by the lower bridge arm switch of the first bridge arm includes: If the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than the voltage threshold, the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

18. The method according to claim 15, characterized in that, The switching transistors in both the first and second bridge arms are turned on at a low level; The step of controlling the PWM wave received by the upper bridge arm switch of the first bridge arm to have at least one difference between the rising edge time and the falling edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm if the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold includes: If the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than the voltage threshold, the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. If the absolute value of the difference is greater than the voltage threshold, controlling the PWM wave received by the upper bridge arm switch of the second bridge arm to have at least one difference between the rising edge time and the falling edge time of the PWM wave received by the lower bridge arm switch of the first bridge arm includes: If the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than the voltage threshold, the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

19. The method according to claim 15, characterized in that, The switching transistors in both the first and second bridge arms are turned on at a low level; The step of controlling the PWM wave received by the upper bridge arm switch of the first bridge arm to have at least one difference between the rising edge time and the falling edge time of the PWM wave received by the lower bridge arm switch of the second bridge arm if the absolute value of the difference between the voltage of the positive bus capacitor and the voltage of the negative bus capacitor is greater than a voltage threshold includes: If the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than the voltage threshold, the falling edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the second bridge arm, and / or the rising edge of the PWM wave received by the upper bridge arm switch of the first bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the second bridge arm. If the absolute value of the difference is greater than the voltage threshold, controlling the PWM wave received by the upper bridge arm switch of the second bridge arm to have at least one difference between the rising edge time and the falling edge time of the PWM wave received by the lower bridge arm switch of the first bridge arm includes: If the difference between the voltage of the negative bus capacitor and the voltage of the positive bus capacitor is greater than the voltage threshold, the falling edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is later than the falling edge of the PWM wave received by the lower bridge arm switch of the first bridge arm, and / or the rising edge of the PWM wave received by the upper bridge arm switch of the second bridge arm is earlier than the rising edge of the PWM wave received by the lower bridge arm switch of the first bridge arm.

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