Holding register

Abstract

The invention provides a holding register. The holding register comprises a control signal processing module, a first latch module and an output module, the control signal processing module is powered by a turn-off power supply and a normally open power supply and is used for generating a clock signal and a holding signal; the first latch module supplies power through a turn-off power supply and a normally open power supply, is coupled with the control signal processing module and the output module, and is used for latching the received input signal and outputting the input signal through the output module under the control of the clock signal and the holding signal when the turn-off power supply supplies power; when the turn-off power supply is powered off and only the normally open power supply supplies power, under the control of the holding signal, the final state of the input signal when the turn-off power supply is powered off is latched, and when the turn-off power supply recovers power supply, the final state of the input signal is output through the output module; the output module is powered by a turn-off power supply. The retaining register is compact in structure and small in occupied chip area.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically to a holding register. Background Technology

[0002] A retention register is a key component in low-power chip design. It saves the current data state when power is off and quickly outputs the saved data when power is restored, significantly reducing circuit power consumption. In low-power chip design, multiple different power supplies are typically defined; some are always-on (NOT) power supplies, and others are power supplies that can be turned off as needed (STO). The biggest difference between a retention register and a regular register is that it is powered by two different power supplies. During normal operation, both power supplies operate simultaneously, and the circuit performs the same function as a regular register. When the STO is off, only the circuit powered by the NOT power supply operates, thus saving the current signal (data).

[0003] The existing holding register generally consists of two parts: one part is powered by a power supply that can be turned off, and the other part is powered by a normally open power supply. This makes the holding register structure relatively large and occupies a lot of chip area. Summary of the Invention

[0004] The purpose of this application is to provide a holding register that is compact in structure and occupies less chip area.

[0005] To achieve the above objectives, this application provides the following technical solution: This application provides a holding register, which includes: a control signal processing module, a first latch module, and an output module; The control signal processing module is powered by a power-off switch and a normally-on power supply and is used to generate clock signals and hold signals. The clock signals include opposite positive clock signals and negative clock signals, and the hold signals include opposite positive hold signals and negative hold signals. The first latch module is powered by both a power-off switch and a normally-on power supply, and is coupled to both the control signal processing module and the output module. When the power-off switch is powered, under the control of the clock signal and the hold signal, it latches the received input signal and outputs the input signal through the output module. When the power-off switch is powered off and only the normally-on power supply is available, under the control of the hold signal, it latches the input signal in its final state when the power-off switch is powered off, and outputs the final state of the input signal through the output module when the power-off switch is restored. The output module is powered by a power-off switch.

[0006] In one embodiment, the first latch module includes: a first tri-state inverting submodule, a first switching submodule, and a first latch submodule; The first tri-state inverting submodule is powered by the power supply that can be turned off. The input terminal of the first tri-state inverting submodule receives an input signal and is used to output the input signal under the control of the clock signal. The first terminal of the first switch submodule is coupled to the output terminal of the first tri-state inverting submodule, and the second terminal of the first switch submodule is coupled to the first latch submodule. It is used to transmit the input signal output by the first tri-state inverting submodule to the first latch submodule or output the input signal latched by the first latch submodule under the control of the holding signal. The first latching submodule is powered by the normally open power supply and is used to latch the signal transmitted from the first switching submodule under the control of the clock signal and the hold signal. The input terminal of the output module is coupled to the coupling point between the first switch submodule and the first tri-state inverting submodule.

[0007] In one embodiment, the first tri-state inverting submodule includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The first terminal of the first PMOS transistor is connected to a power supply that can be turned off. The second terminal of the first PMOS transistor is connected to the first terminal of the second PMOS transistor. The second terminal of the second PMOS transistor is coupled to the first terminal of the first NMOS transistor as the output terminal of the first tri-state inverting sub-module. The second terminal of the first NMOS transistor is connected to the first terminal of the second NMOS transistor. The second terminal of the second NMOS transistor is grounded. The gate terminals of the first PMOS transistor and the second NMOS transistor are coupled to the input terminal of the first tri-state inverting sub-module. The gate terminals of the second PMOS transistor and the first NMOS transistor respectively receive the negative clock signal and the positive clock signal.

[0008] In one embodiment, the first switching submodule includes: a third PMOS transistor and a third NMOS transistor; The first terminal of the third PMOS transistor and the first terminal of the third NMOS transistor are coupled to form the first terminal of the first switching submodule. The second terminal of the third PMOS transistor and the second terminal of the third NMOS transistor are coupled to form the second terminal of the first switching submodule. The gate terminal of the third PMOS transistor and the gate terminal of the third NMOS transistor respectively receive the hold positive signal and the hold negative signal.

[0009] In one embodiment, the first latch submodule includes: a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; The first terminal of the fourth PMOS transistor is connected to a normally open power supply, the second terminal of the fourth PMOS transistor is coupled to the first terminal of the fourth NMOS transistor, the second terminal of the fourth NMOS transistor is grounded, and the gate terminals of both the fourth PMOS transistor and the fourth NMOS transistor are coupled to the first switch submodule. The first terminal of the fifth PMOS transistor is connected to a normally open power supply. The second terminal of the fifth PMOS transistor is connected to the first terminals of the sixth and seventh PMOS transistors. The second terminals of the sixth PMOS transistor, the fifth NMOS transistor, the seventh PMOS transistor, and the sixth NMOS transistor are all connected to the first switch submodule. The second terminals of the fifth and sixth NMOS transistors are connected to the first terminal of the seventh NMOS transistor. The second terminal of the seventh NMOS transistor is grounded. The gate terminals of the fifth and seventh NMOS transistors are connected to the second terminals of the fourth PMOS transistor and the first terminals of the fourth NMOS transistor. The gate terminals of the sixth PMOS transistor and the fifth NMOS transistor receive the positive clock signal and the negative clock signal, respectively. The gate terminals of the seventh PMOS transistor and the sixth NMOS transistor receive the positive hold signal and the negative hold signal, respectively.

[0010] In one embodiment, the holding register further includes: a second latch module coupled to the first latch module and the control signal processing module; the second latch module includes: a second tri-state inverting submodule and a second latch submodule; The input terminal of the second tri-state inverting submodule is coupled to the input signal terminal, and is used to receive and output the input signal under the control of the clock signal; The input terminal of the second latch submodule is coupled to the output terminal of the second tri-state inverting submodule to latch the input signal or output the input signal to the first latch module under the control of the clock signal.

[0011] In one embodiment, the second tri-state inverting submodule includes: an eighth PMOS transistor, a ninth PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; The first terminal of the eighth PMOS transistor is connected to a power-off switch. The second terminal of the eighth PMOS transistor is connected to the first terminal of the ninth PMOS transistor. The second terminal of the ninth PMOS transistor is coupled to the first terminal of the eighth NMOS transistor as the output terminal of the second tri-state inverting sub-module. The second terminal of the eighth NMOS transistor is connected to the first terminal of the ninth NMOS transistor. The second terminal of the ninth NMOS transistor is grounded. The gate terminals of the eighth PMOS transistor and the ninth NMOS transistor are coupled to the input terminal of the second tri-state inverting sub-module. The gate terminals of the ninth PMOS transistor and the eighth NMOS transistor receive the positive clock signal and the negative clock signal, respectively.

[0012] In one embodiment, the second latch submodule includes: a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor; The first terminal of the tenth PMOS transistor is connected to the power supply that can be turned off. The second terminal of the tenth PMOS transistor is coupled to the first terminal of the tenth NMOS transistor as the output terminal of the second latch submodule. The second terminal of the tenth NMOS transistor is grounded. The gate terminal of the tenth PMOS transistor is coupled to the gate terminal of the tenth NMOS transistor as the input terminal of the second latch submodule. The first terminal of the eleventh PMOS transistor is connected to the power supply that can be turned off. The second terminal of the eleventh PMOS transistor is connected to the first terminal of the twelfth PMOS transistor. The second terminal of the twelfth PMOS transistor and the first terminal of the eleventh NMOS transistor are coupled to the input terminal of the second latch submodule. The second terminal of the eleventh NMOS transistor is connected to the first terminal of the twelfth NMOS transistor. The second terminal of the twelfth NMOS transistor is grounded. The gate terminals of the eleventh PMOS transistor and the twelfth NMOS transistor are coupled to the output terminal of the second latch submodule. The gate terminals of the twelfth PMOS transistor and the eleventh NMOS transistor receive the negative clock signal and the positive clock signal, respectively.

[0013] In one embodiment, the output module includes: a thirteenth PMOS transistor and a thirteenth NMOS transistor; The first terminal of the thirteenth PMOS transistor is connected to a power supply that can be turned off. The second terminal of the thirteenth PMOS transistor is coupled to the first terminal of the thirteenth NMOS transistor to form the output terminal of the output module. The second terminal of the thirteenth NMOS transistor is grounded. The gate terminals of the thirteenth PMOS transistor and the gate terminals of the thirteenth NMOS transistor are coupled to form the input terminal of the output module.

[0014] In one embodiment, the control signal processing module includes a clock signal processing submodule and a hold signal processing submodule; The clock signal processing submodule includes a fourteenth PMOS transistor, a fifteenth PMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor. The first terminal of the fourteenth PMOS transistor is connected to a power supply that can be turned off. The second terminal of the fourteenth PMOS transistor and the first terminal of the fourteenth NMOS transistor are coupled to form the intermediate output terminal of the clock signal processing submodule, which outputs a negative clock signal. The second terminal of the fourteenth NMOS transistor is grounded. The gate terminals of the fourteenth PMOS transistor and the fourteenth NMOS transistor are coupled to form the input terminal of the clock signal processing submodule, which receives the main input clock signal. The first terminal of the fifteenth PMOS transistor is connected to a power supply that can be turned off. The second terminal of the fifteenth PMOS transistor and the first terminal of the fifteenth NMOS transistor are coupled to form the rear output terminal of the clock signal processing submodule, which outputs a positive clock signal. The second terminal of the fifteenth NMOS transistor is grounded. The gate terminals of the fifteenth PMOS transistor and the fifteenth NMOS transistor are coupled to the intermediate output terminal of the clock signal processing submodule. The hold signal processing submodule includes a sixteenth PMOS transistor and a sixteenth NMOS transistor. The first terminal of the sixteenth PMOS transistor is connected to a normally open power supply. The second terminal of the sixteenth PMOS transistor is coupled to the first terminal of the sixteenth NMOS transistor as the output terminal of the hold signal processing submodule, outputting a hold inverse signal. The second terminal of the sixteenth NMOS transistor is grounded. The gate terminals of the sixteenth PMOS transistor and the sixteenth NMOS transistor are coupled to the input terminal of the hold signal processing submodule, receiving the input hold main signal. The hold positive signal is the same as the hold main signal.

[0015] Compared with the prior art, the technical solution of this application has the following beneficial effects: The holding register of this application integrates the data trigger output function and the data power-down retention function into the same module structure. Therefore, the holding register of this application has a compact structure and occupies less chip area. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a holding register provided in the first embodiment of this application. Detailed Implementation

[0018] The technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application. Moreover, in the following embodiments, the description of each embodiment has its own emphasis, and for parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0019] Please see Figure 1 As shown, the first embodiment of this application provides a holding register, which may include: a control signal processing module 1, a first latching module 2, and an output module 3.

[0020] The control signal processing module 1 is powered by a power supply that can be turned off, VDD, and a normally open power supply, VDDG, and is used to generate a clock signal and a hold signal. The clock signal may include opposite clock positive signals and clock negative signals, and the hold signal may include opposite hold positive signals and hold negative signals.

[0021] In this embodiment, the first latch module 2 is powered by a power-off switchable power supply VDD and a normally-on power supply VDDG, and is coupled to both the control signal processing module 1 and the output module 3. When the power-off switchable power supply VDD is powered, under the control of the clock signal and the hold signal, it latches the received input signal and outputs the input signal through the output module 3. When the power-off switchable power supply VDD is de-energized and only the normally-on power supply VDDG is powered, under the control of the hold signal, it latches the input signal in its final state when the power-off switchable power supply VDD is de-energized, and when the power-off switchable power supply VDD is restored, it outputs the final state of the input signal through the output module 3.

[0022] In this embodiment, the output module 3 is powered by a power supply that can be turned off, VDD.

[0023] In this application's holding register, the first latch module 2 is powered by both a power-off switch (VDD) and a normally-on power supply (VDDG). When the power-off switch (VDD) is operating normally, the first latch module 2 outputs a signal or latches a signal under the control of a clock signal (with the hold signal as an auxiliary factor). When the power-off switch (VDD) is normally de-energized and only the normally-on power supply (VDDG) is powered, the first latch module 2 latches the signal under the control of the hold signal. In other words, the first latch module 2 integrates data trigger output and data power-off retention functions into a single module structure. Therefore, this application's holding register has a compact structure, reducing the chip area it occupies.

[0024] The following sections will provide a more detailed explanation of each module.

[0025] In one embodiment, the first latch module 2 may include: a first tri-state inverting submodule 21, a first switching submodule 22, and a first latch submodule 23.

[0026] The first tri-state inverting submodule 21 is powered by the power supply VDD. The input terminal of the first tri-state inverting submodule 21 receives the input signal. Under the control of the clock signal, the first tri-state inverting submodule 21 outputs the received input signal through the output terminal.

[0027] In this embodiment, the first terminal of the first switch submodule 22 is coupled to the output terminal of the first tri-state inverting submodule 21, and the second terminal of the first switch submodule 22 is coupled to the first latch submodule 23. The first switch submodule 22 is used to transmit the input signal output by the first tri-state inverting submodule 21 to the first latch submodule 23, or output the input signal latched by the first latch submodule 23, under the control of the holding signal.

[0028] In this embodiment, the first latch submodule 23 is powered by the normally open power supply VDDG and is used to latch the signal transmitted from the first switch submodule 22 under the control of the clock signal and the hold signal.

[0029] In this embodiment, the input terminal of the output module 3 is coupled to the coupling point between the first switch submodule 22 and the first tri-state inverting submodule 21, that is, the input terminal of the output module 3 is coupled to the first terminal of the first switch submodule 22 and the output terminal of the first tri-state inverting submodule 21.

[0030] In the first latch module 2 of this application, the output terminal of the first tri-state inverting submodule 21 is coupled to the input terminal of the output module 3. Under the control of the clock signal, it outputs or does not output the input signal, realizing the data-triggered output function of the holding register. The first terminal of the first switching submodule 22 is coupled to the coupling point of the first tri-state inverting submodule 21 and the output module 3, and the second terminal of the first switching submodule 22 is coupled to the first latch submodule 23. With the cooperation of the first switching submodule 22, and under the control of the clock signal and the holding signal, the first latch submodule 23 latches the input signal output by the first tri-state inverting submodule 21 via the first switching submodule 22, or transmits the latched input signal to the output module 3 via the first switching submodule 22 for output, realizing the data power-down retention function of the register. Therefore, the first latch module 2 integrates the data-triggered output function and the data power-down retention function into the same module structure, so the structure is compact and can reduce the chip area occupied.

[0031] In one embodiment, the first tri-state inverting submodule 21 may include: a first PMOS transistor 101, a second PMOS transistor 102, a first NMOS transistor 201, and a second NMOS transistor 202.

[0032] In this configuration, the first terminal of the first PMOS transistor 101 is connected to the power supply VDD, the second terminal of the first PMOS transistor 101 is connected to the first terminal of the second PMOS transistor 102, the second terminal of the second PMOS transistor 102 is coupled to the first terminal of the first NMOS transistor 201 as the output terminal of the first tri-state inverting sub-module 21, the second terminal of the first NMOS transistor 201 is connected to the first terminal of the second NMOS transistor 202, the second terminal of the second NMOS transistor 202 is grounded, the gate terminal of the first PMOS transistor 101 and the gate terminal of the second NMOS transistor 202 are coupled to the input terminal of the first tri-state inverting sub-module 21, and the gate terminal of the second PMOS transistor 102 and the gate terminal of the first NMOS transistor 201 respectively receive the negative clock signal and the positive clock signal.

[0033] To clarify beforehand, for the sake of simplicity, in this application, the first terminal of each PMOS is the source and the second terminal is the drain, and the first terminal of each NMOS is the drain and the second terminal is the source (the same applies below, and will not be repeated hereafter).

[0034] In one specific embodiment, the input signal D is directly connected to the input terminal of the first tri-state inverter submodule 21, that is, the input signal D is directly input to the gate terminal of the first PMOS transistor 101 and the gate terminal of the second NMOS transistor 202, as a control signal for the first PMOS transistor 101 and the second NMOS transistor 202. When the clock negative signal CKN (opposite to the clock main signal CK, see details below) is low, the clock positive signal CKP is high, and both the second PMOS transistor 102 and the first NMOS transistor 201 are turned on, which can be regarded as a wire; at this time, if the input signal D is high, the first PMOS transistor 101 is turned off and the second NMOS transistor 202 is turned on, the first terminal of the second NMOS transistor 202 is low (grounded), and the corresponding coupling point between the second terminal of the second PMOS transistor 102 and the first terminal of the first NMOS transistor 201 is low, that is, the output terminal of the first tri-state inverter submodule 21 is low; at this time, if the input signal D is low, the first PMOS transistor 101 is low. When MOSFET 101 is turned on and NMOS transistor 202 is turned off, the second terminal of the first PMOS transistor 101 is high (connected to the power supply VDD), and correspondingly, the connection point between the second terminal of the second PMOS transistor 102 and the first terminal of the first NMOS transistor 201 is high, which is the output terminal of the first tri-state inverter submodule 21. Therefore, the first PMOS transistor 101 and the second NMOS transistor 202 can be considered as forming an inverter, inverting the input signal D and outputting it to the connection point between the second terminal of the second PMOS transistor 102 and the first terminal of the first NMOS transistor 201 (point a), which is the output terminal of the first tri-state inverter submodule 21. When the negative clock signal CKN is high and the positive clock signal CKP is low, both the second PMOS transistor 102 and the first NMOS transistor 201 are turned off, and the first PMOS transistor 101 and the second NMOS transistor 202 are disconnected, thus no signal path can be formed. The input signal D can only remain at the gate terminal of the first PMOS transistor 101 and the gate terminal of the second NMOS transistor 202.

[0035] To better explain the working principle of the technical solution of this application, the output module 3 will be described in detail first.

[0036] In one embodiment, the output module 3 may include a thirteenth PMOS transistor 113 and a thirteenth NMOS transistor 213.

[0037] The first terminal of the thirteenth PMOS transistor 113 is connected to the power supply VDD, the second terminal of the thirteenth PMOS transistor 113 is coupled to the first terminal of the thirteenth NMOS transistor 213 as the output terminal of the output module 3, the second terminal of the thirteenth NMOS transistor 213 is grounded, and the gate terminals of the thirteenth PMOS transistor 113 and the gate terminals of the thirteenth NMOS transistor 213 are coupled to the input terminals of the output module 3.

[0038] Referring to the previous description, it is easy to understand that the thirteenth PMOS transistor 113 and the thirteenth NMOS transistor 213 also constitute an inverter, inverting the signal at point a and outputting it as the output signal Q. Combining this with the previous description, we can see that when the negative clock signal CKN is low, the output signal Q continuously outputs the input signal D (because of the repeated inversion, a high input signal D results in a high output signal Q, and a low input signal D results in a low output signal Q, which are consistent); when the negative clock signal CKN is high, the output signal Q remains unchanged (because at this time, the input signal D only stays at the gate of the first PMOS transistor 101 and the gate of the second NMOS transistor 202, and the signal at point a remains unchanged).

[0039] Next, we will introduce the other sub-modules in the first latch module 2.

[0040] In one embodiment, the first switching submodule 22 may include a third PMOS transistor 103 and a third NMOS transistor 203.

[0041] The first terminal of the third PMOS transistor 103 and the first terminal of the third NMOS transistor 203 are coupled to form the first terminal of the first switching submodule 22. The second terminal of the third PMOS transistor 103 and the second terminal of the third MOS transistor are coupled to form the second terminal of the first switching submodule 22. The gate terminal of the third PMOS transistor 103 and the gate terminal of the third NMOS transistor 203 respectively receive the hold positive signal and the hold inverse signal (i.e., the gate terminal of the third PMOS transistor 103 is coupled to the hold inverse signal RET, and the gate terminal of the third NMOS transistor 203 is coupled to the hold positive signal RETN).

[0042] In this embodiment, when the inverted signal RET is kept low (which is also when the power supply VDD is not powered off and is working normally, please refer to the detailed description below), the positive signal RETN is kept high, and both the third PMOS transistor 103 and the third NMOS transistor 203 are turned on. The first switching submodule 22 can be regarded as a portal, transmitting the signal from the first end (point a) of the first switching submodule 22 to the second end (point b) of the first switching submodule 22. Of course, the signal from point b can also be transmitted to point a. When the inverted signal RET is kept high (which is also when the power supply VDD is powered off and turned off, please refer to the detailed description below), the positive signal RETN is kept low, and both the third PMOS transistor 103 and the third NMOS transistor 203 are turned off. The first switching submodule 22 is in an open state, and the signal from point a cannot be transmitted to point b, nor can the signal from point b be transmitted to point a.

[0043] In one embodiment, the first latch submodule 23 may include: a fourth PMOS transistor 104, a fifth PMOS transistor 105, a sixth PMOS transistor 106, a seventh PMOS transistor 107, a fourth NMOS transistor 204, a fifth NMOS transistor 205, a sixth NMOS transistor 206, and a seventh NMOS transistor 207.

[0044] The first terminal of the fourth PMOS transistor 104 is connected to the normally open power supply VDDG, the second terminal of the fourth PMOS transistor 104 is coupled to the first terminal of the fourth NMOS transistor 204, the second terminal of the fourth NMOS transistor 204 is grounded, and the gate terminals of the fourth PMOS transistor 104 and the fourth NMOS transistor 204 are both coupled to the first switch submodule 22.

[0045] As can be easily understood from the previous description, the fourth PMOS transistor 104 and the fourth NMOS transistor 204 also form an inverter, which inverts the signal at point b and outputs it to the coupling point between the second terminal of the fourth PMOS transistor 104 and the first terminal of the fourth NMOS transistor 204 (referred to as point c).

[0046] In this embodiment, the first terminal of the fifth PMOS transistor 105 is connected to the normally open power supply VDDG. The second terminal of the fifth PMOS transistor 105 is connected to the first terminals of the sixth PMOS transistor 106 and the seventh PMOS transistor 107. The second terminals of the sixth PMOS transistor 106, the fifth NMOS transistor 205, the seventh PMOS transistor 107, and the sixth NMOS transistor 206 are all connected to the first switch submodule 22. The second terminals of the fifth NMOS transistor 205 and the sixth NMOS transistor 206 are connected to the first terminal of the seventh NMOS transistor 207. The second terminal of the seventh NMOS transistor 207 is grounded. The gate terminal of the fifth PMOS transistor 105 and the gate terminal of the seventh NMOS transistor 207 are connected to the first switch submodule 22. The gate of PMOS transistor 107 is connected to the second terminal of the fourth PMOS transistor 104 and the first terminal of the fourth NMOS transistor 204. The gate of the sixth PMOS transistor 106 and the gate of the fifth NMOS transistor 205 receive the positive clock signal and the negative clock signal, respectively (i.e., the gate of the sixth PMOS transistor 106 is coupled to the positive clock signal CKP, and the gate of the fifth NMOS transistor 205 is coupled to the negative clock signal CKN). The gate of the seventh PMOS transistor 107 and the gate of the sixth NMOS transistor 206 receive the hold positive signal and the hold inverse signal, respectively (i.e., the gate of the seventh PMOS transistor 107 is coupled to the hold positive signal RETN, and the gate of the sixth NMOS transistor 206 is coupled to the hold inverse signal RET).

[0047] In this embodiment, when the inverse signal RET is kept low, the positive signal RETN is kept high. Both the seventh PMOS transistor 107 and the sixth NMOS transistor 206 are turned off, and the path formed by the seventh PMOS transistor 107 and the sixth NMOS transistor 206 (referred to as channel R) is open. At this time, different operations are performed depending on the different states of the sixth PMOS transistor 106 and the fifth NMOS transistor 205: if the positive clock signal CKP is low and the negative clock signal CKN is high, then the sixth PMOS transistor 106 and the fifth NMOS transistor 205... All transistors are conducting. The path formed by the sixth PMOS transistor 106 and the fifth NMOS transistor 205 (referred to as channel L) is in a conducting state and can be considered as a wire. Therefore, the fifth PMOS transistor 105 and the seventh NMOS transistor 207 also form an inverter, which inverts the signal at point c and outputs it to point b. Combining the above description, we know that because the inverter formed by the fourth PMOS transistor 104 and the fourth NMOS transistor 204 inverts the signal at point b and outputs it to point c, the signal is transmitted through the fourth PMOS transistor 104, the fourth NMOS transistor 204, and the fifth PMOS transistor 205. The circuit cycles between OS transistor 105 and the seventh NMOS transistor 207, which is signal latching (at this time, the second PMOS transistor 102 and the first NMOS transistor 201 are both in the off state, the input signal D cannot enter the circuit, the signal at point a continues to be in the previous state, and the corresponding signal at point b also remains in the previous state. The signal at point b is inverted, goes to point c, is inverted again, and then returns to the original state back to point b). If the positive clock signal CKP is high and the negative clock signal CKN is low, then the sixth PMOS transistor 106 and the fifth NMOS transistor 207... If all 5 are closed and channel L is also in an open state, then the fifth PMOS transistor 105 and the seventh NMOS transistor 207 cannot form an inverter or a path. The signal at point c can only stay at point c (at this time, the second PMOS transistor 102 and the first NMOS transistor 201 are both in the on state. The input signal D is inverted by the first PMOS transistor 101 and the second NMOS transistor 202 and output to point a. Then it is inverted by the thirteenth PMOS transistor 113 and the thirteenth NMOS transistor 213 and returns to the original state as the output signal Q). When the inverted signal RET is kept high, the positive signal RETN is kept low. The seventh PMOS transistor 107 and the sixth NMOS transistor 206 are both turned on, and channel R is in the on state. Regardless of the state of channel L, the fifth PMOS transistor 105 and the seventh NMOS transistor 207 can form an inverter to invert the signal at point c and transmit it to point b. This is also the signal latching state (at this time, the fourth PMOS transistor 104 and the fourth NMOS transistor 204 are both turned off, and the signal at point a cannot be transmitted to point b. Only the signal at point b is inverted, goes to point c, and then is inverted again to return to the original state and return to point b).

[0048] As described above, under normal operating conditions, both the power supply VDD (which can be turned off) and the normally open power supply VDDG provide power normally, and all MOSFETs operate normally. At this time, the positive signal RETN remains high, the third PMOS transistor 103 and the third NMOS transistor 203 are both turned on, the first switch submodule 22 is regarded as a wire, and the seventh PMOS transistor 107 and the sixth NMOS transistor 206 are both turned off (channel R is turned off). At this time, different operations are performed according to different states of the main clock signal CK: when the main clock signal CK is high, the second PMOS transistor 102 and the first NMOS transistor 201 are both turned on, the input signal D enters and forms the output signal Q before outputting, the sixth PMOS transistor 106 and the fifth NMOS transistor 205 are both turned off (channel L is also turned off), and the signal is not latched; when the main clock signal CK is low, the second PMOS transistor 102 and the first NMOS transistor 201 are both turned off, the input signal D cannot enter, the sixth PMOS transistor 106 and the fifth NMOS transistor 205 are both turned on (channel L is turned on), and the signal cycles between points b and c, that is, latching is performed. When the power supply VDD is turned off, only the normally open power supply VDDG provides power, and the MOS transistors powered only by VDDG operate normally. At this time, the positive signal RETN remains low, the third PMOS transistor 103 and the third NMOS transistor 203 are both turned off, the first switch submodule 22 is in an open state, there is no signal transmission between points a and b, the seventh PMOS transistor 107 and the sixth NMOS transistor 206 are both turned on (channel R is turned on), and the signal cycles between points b and c. The signal at point b is the same as the signal at point a when the power supply VDD is turned off, and the signal at point a corresponds to the last state of the input signal when the power is turned off. Therefore, the first latch submodule 23 can latch the last state of the input signal when the power is turned off. Subsequently, when the power supply VDD is restored, since the thirteenth PMOS transistor 113 and the thirteenth NMOS transistor 213 have no other signals to control their operation, the signal at point a is inverted and output as the output signal Q. The signal at point a is the same as the signal at point b because the third PMOS transistor 103 and the third NMOS transistor 203 are conducting at this time. The signal at point b is the latched state corresponding to the input signal at the last state before power failure (the input signal is inverted). Therefore, the output signal Q at this time corresponds to the input signal D before power failure. This fulfills the basic function of the holding register: during normal operation, it outputs the input signal based on the clock signal trigger; during power failure, it latches the state of the input signal at the time of power failure; and when power is restored, it immediately outputs the last state of the input signal at the time of power failure (also known as the state before power failure).

[0049] In the above embodiments, under normal operating conditions, the positive signal RETN is kept high, and when the power-off power supply VDDG is powered off, the positive signal RETN is kept low for signal latching. In another embodiment, the gate of the third PMOS transistor 103 is used to receive the hold-positive signal RETN, and the gate of the third NMOS transistor 203 is used to receive the hold-inverse signal RET. Correspondingly, the gate of the seventh PMOS transistor 107 is used to receive the hold-inverse signal RET, and the gate of the sixth NMOS transistor 206 is used to receive the hold-positive signal RETN. This achieves the following: under normal operating conditions, the positive signal RETN is kept low, and when the power-off power supply VDDG is powered off, the positive signal RETN is kept high for signal latching. Similarly, in the above embodiments, under normal operating conditions, signal input and output are performed when the main clock signal CK is high, and signal latching is performed when the main clock signal CK is low. In another embodiment, the gate of the second PMOS transistor 102 is used to receive the positive clock signal CKP, the gate of the first NMOS transistor 201 is used to receive the negative clock signal CKN, and correspondingly, the gate of the sixth PMOS transistor 106 is used to receive the negative clock signal CKN, and the gate of the fifth NMOS transistor 205 is used to receive the positive clock signal CKP. This enables signal input and output when the main clock signal CK is low, and signal latching when the main clock signal CK is high.

[0050] The holding register described in the above embodiments is a type of latch holding register (referred to as a latch), and the inventive concept of this application can also be applied to the retention flip-flop holding register (referred to as a D flip-flop).

[0051] Please continue reading. Figure 1 As shown, in one embodiment, the holding register may further include a second latch module 4 coupled to the first latch module 2 and the control signal processing module 1; the second latch module 4 may include a second tri-state inverting submodule 41 and a second latch submodule 42.

[0052] The input terminal of the second tri-state inverting submodule 41 is coupled to the input signal terminal and is used to receive and output the input signal under the control of the clock signal.

[0053] In this embodiment, the input terminal of the second latch submodule 42 is coupled to the output terminal of the second tri-state inverting submodule 41, so as to latch the input signal or output the input signal to the first latch module 2 under the control of the clock signal.

[0054] In this embodiment, the second latch module 4 works in conjunction with the first latch module 2 to jointly implement the function of the D flip-flop. Because the first latch module 2 integrates the data trigger output function and the data power-down retention function into the same module structure, the structure is compact and can reduce the chip area occupied, so the D flip-flop also occupies less chip area.

[0055] In one embodiment, the second tri-state inverting submodule 41 may include: an eighth PMOS transistor 108, a ninth PMOS transistor 109, an eighth NMOS transistor 208, and a ninth NMOS transistor 209.

[0056] In this configuration, the first terminal of the eighth PMOS transistor 108 is connected to the power supply VDD, the second terminal of the eighth PMOS transistor 108 is connected to the first terminal of the ninth PMOS transistor 109, the second terminal of the ninth PMOS transistor 109 is coupled to the first terminal of the eighth NMOS transistor 208 as the output terminal of the second tri-state inverting sub-module 41, the second terminal of the eighth NMOS transistor 208 is connected to the first terminal of the ninth NMOS transistor 209, the second terminal of the ninth NMOS transistor 209 is grounded, the gate terminals of the eighth PMOS transistor 108 and the ninth NMOS transistor 209 are coupled to the input terminal of the second tri-state inverting sub-module 41, and the gate terminals of the ninth PMOS transistor 109 and the eighth NMOS transistor 208 respectively receive the positive clock signal and the negative clock signal (i.e., the gate terminal of the ninth PMOS transistor 109 is coupled to the positive clock signal CKP, and the gate terminal of the eighth NMOS transistor 208 is coupled to the negative clock signal CKN).

[0057] In this embodiment, the second tri-state inverting submodule 41, composed of the eighth PMOS transistor 108, the ninth PMOS transistor 109, the eighth NMOS transistor 208, and the ninth NMOS transistor 209, has the same structure as the first tri-state inverting submodule 21, composed of the first PMOS transistor 101, the second PMOS transistor 102, the first NMOS transistor 201, and the second NMOS transistor 202. Therefore, their working principles are exactly the same. The only difference is that the clock signal connection is reversed, resulting in completely opposite working states. Therefore, the specific working principle process will not be described in detail here.

[0058] In one embodiment, the second latch submodule 42 may include: a tenth PMOS transistor 110, an eleventh PMOS transistor 111, a twelfth PMOS transistor 112, a tenth NMOS transistor 210, an eleventh NMOS transistor 211, and a twelfth NMOS transistor 212.

[0059] The first end of the tenth PMOS transistor 110 is connected to the power supply VDD that can be turned off. The second end of the tenth PMOS transistor 110 is coupled to the first end of the tenth NMOS transistor 210 as the output end of the second latch submodule 42 (that is, the output end of the second latch module 4). The second end of the tenth NMOS transistor 210 is grounded. The gate end of the tenth PMOS transistor 110 is coupled to the gate end of the tenth NMOS transistor 210 as the input end of the second latch submodule 42.

[0060] In this embodiment, the structure formed by the tenth PMOS transistor 110 and the tenth NMOS transistor 210 is exactly the same as the structure formed by the fourth PMOS transistor 104 and the fourth NMOS transistor 204. Therefore, the working principle is exactly the same. The only difference is that the former is powered by the turn-off power supply VDD, while the latter is powered by the normally open power supply VDDG. Therefore, the specific working principle process will not be described in detail here.

[0061] In this embodiment, the first terminal of the eleventh PMOS transistor 111 is connected to the power supply VDD, the second terminal of the eleventh PMOS transistor 111 is connected to the first terminal of the twelfth PMOS transistor 112, the second terminal of the twelfth PMOS transistor 112 and the first terminal of the eleventh NMOS transistor 211 are coupled to the input terminal of the second latch submodule 42, the second terminal of the eleventh NMOS transistor 211 is connected to the first terminal of the twelfth NMOS transistor 212, the second terminal of the twelfth NMOS transistor 212 is grounded, the gate terminal of the eleventh PMOS transistor 111 and the gate terminal of the twelfth NMOS transistor 212 are coupled to the output terminal of the second latch submodule 42, and the gate terminal of the twelfth PMOS transistor 112 and the gate terminal of the eleventh NMOS transistor 211 respectively receive the negative clock signal and the positive clock signal (i.e., the gate terminal of the twelfth PMOS transistor 112 is coupled to the negative clock signal CKN, and the gate terminal of the eleventh NMOS transistor 211 is coupled to the positive clock signal CKP).

[0062] In this embodiment, the structure formed by the eleventh PMOS transistor 111, the twelfth PMOS transistor 112, the eleventh NMOS transistor 211, and the twelfth NMOS transistor 212 is exactly the same as the structure formed by the eighth PMOS transistor 108, the ninth PMOS transistor 109, the eighth NMOS transistor 208, and the ninth NMOS transistor 209. Therefore, the working principle is exactly the same. The only difference is that the clock signal connection is reversed, so the working state is completely reversed. Therefore, the specific working principle process will not be described in detail here.

[0063] In the above embodiment, the D flip-flop, under normal operating conditions, keeps the positive signal RETN high, the third PMOS transistor 103 and the third NMOS transistor 203 are both turned on, and points a and b are directly connected. The seventh PMOS transistor 107 and the sixth NMOS transistor 206 are both turned off, and channel R is turned off. When the main clock signal CK is low, the ninth PMOS transistor 109 and the eighth NMOS transistor 208 are both turned on. The input signal D is inverted by the eighth PMOS transistor 108 and the ninth NMOS transistor 209 and output to the coupling point between the second terminal of the ninth PMOS transistor 109 and the first terminal of the eighth NMOS transistor 208, which is the output terminal of the second tri-state inverting submodule 41 (referred to as point e). The signal at point e is inverted by the tenth PMOS transistor 110 and the tenth NMOS transistor 210 and output to the coupling point between the second terminal of the tenth PMOS transistor 110 and the first terminal of the tenth NMOS transistor 210, which is the output terminal of the second latch submodule 42 (referred to as point f). The second PMOS transistor 102 and the first NMOS transistor 201 are both turned off, so the signal at point f cannot be transmitted to point a. The twelfth PMOS transistor 112 and the eleventh NMOS transistor 211 are also turned off, so the signal at point f cannot be transmitted back to point e. When the main clock signal CK switches from low to high, the ninth PMOS transistor 109 and the eighth NMOS transistor 208 are both turned off, so the input signal D can no longer be transmitted to point e. Points e and f are both the signals before the switch. At this time, the second PMOS transistor 102 and the first NMOS transistor 201 are both turned on. The signal at point f is inverted and transmitted to point a. The signal at point a is then inverted and output as the output signal Q (because it is actually the same as the input signal D after four inversions) and output. At the same time, the signal at point a is also directly transmitted to point b. The twelfth PMOS transistor 112 and the eleventh NMOS transistor 211 are also turned on, and a signal latching state is formed between points f and e. When the main clock signal CK switches from high to low again, the ninth PMOS transistor 109 and the eighth NMOS transistor 208 are both turned on. The next input signal D (or the new input signal D, or the new state of input signal D, which may be the same as or different from the previous state) is inverted and output to point e. The operating states of the other MOS transistors are the same as described above. When the power-off switchable power supply VDD is turned off, the positive signal RETN remains low, and the third PMOS transistor 103 and the third NMOS transistor 203 are both turned off. The part to the left of point a in the figure is completely inactive, and a latch state is formed between point b (the same signal as point a) and point c (as described in the Latch embodiment section). When the power-off switchable power supply VDD is restored, the signal at point a is inverted by output module 3 and output as the output signal Q (corresponding to the input signal D before the power failure).

[0064] In the above embodiments, the holding register of this application is a rising-edge triggered D flip-flop. Similarly, in another embodiment, the second PMOS transistor 102 is used to receive the positive clock signal CKP, the first NMOS transistor 201 is used to receive the negative clock signal CKN; the sixth PMOS transistor 106 is used to receive the negative clock signal CKN, the fifth NMOS transistor 205 is used to receive the positive clock signal CKP; the ninth PMOS transistor 109 is used to receive the negative clock signal CKN, the eighth NMOS transistor 208 is used to receive the positive clock signal CKP; the twelfth PMOS transistor 112 is used to receive the positive clock signal CKP, and the eleventh NMOS transistor 211 is used to receive the negative clock signal CKN. This holding register is a falling-edge triggered D flip-flop. Moreover, in the above embodiments, under normal operating conditions, the positive signal RETN is held high, and when the power supply VDD is turned off, the positive signal RETN is held low, thus performing signal latching. Similarly, in another embodiment, the gate of the third PMOS transistor 103 is used to receive the hold positive signal RETN, and the gate of the third NMOS transistor 203 is used to receive the hold negative signal RET. Correspondingly, the gate of the seventh PMOS transistor 107 is used to receive the hold negative signal RET, and the gate of the sixth NMOS transistor 206 is used to receive the hold positive signal RETN. This enables the positive signal RETN to be kept low under normal operating conditions and to be kept high when the power supply VDD is turned off, thus performing signal latching.

[0065] Continue to refer to Figure 1 The control signal processing module 1 is applicable to both latches and D flip-flops.

[0066] In one embodiment, the control signal processing module 1 may include a clock signal processing submodule 11 and a hold signal processing submodule 12.

[0067] The clock signal processing submodule 11 is used to generate the corresponding positive clock signal CKP and negative clock signal CKN based on the main clock signal CK. The hold signal processing submodule 12 is used to generate the inverse hold signal RET based on the positive hold signal RETN.

[0068] In this embodiment, the clock signal processing submodule 11 may include a fourteenth PMOS transistor 114, a fifteenth PMOS transistor 115, a fourteenth NMOS transistor 214, and a fifteenth NMOS transistor 215. The first terminal of the fourteenth PMOS transistor 114 is connected to the power supply VDD, and the second terminal of the fourteenth PMOS transistor 114 is coupled to the first terminal of the fourteenth NMOS transistor 214 as the intermediate output terminal of the clock signal processing submodule 11, outputting a negative clock signal CKN. The second terminal of the fourteenth NMOS transistor 214 is grounded, and the gate terminal of the fourteenth PMOS transistor 114 and the fourteenth NMOS transistor 215 are connected to the power supply VDD. The gate of S-channel transistor 214 is coupled to the input terminal of the clock signal processing submodule 11, receiving the main input clock signal CK. The first terminal of the fifteenth PMOS transistor 115 is connected to the power supply VDD, and the second terminal of the fifteenth PMOS transistor 115 and the first terminal of the fifteenth NMOS transistor 215 are coupled to the rear output terminal of the clock signal processing submodule 11, outputting the positive clock signal CKP. The second terminal of the fifteenth NMOS transistor 215 is grounded, and the gate terminals of the fifteenth PMOS transistor 115 and the fifteenth NMOS transistor 215 are coupled to the intermediate output terminal of the clock signal processing submodule 11.

[0069] Referring to the previous description, it is easy to understand that the fourteenth PMOS transistor 114 and the fourteenth NMOS transistor 214 also form an inverter, inverting the main clock signal CK and outputting it from the middle output terminal. The signal output here is the negative clock signal CKN. The fifteenth MOS transistor and the fifteenth NMOS transistor 215 also form an inverter, inverting the negative clock signal CKN and outputting it from the rear output terminal. The signal output here is the positive clock signal CKP. Therefore, the positive clock signal CKP is actually in phase with the main clock signal CK, and the negative clock signal CKN is out of phase with the main clock signal CK. The negative clock signal CKN and the positive clock signal CKP are also out of phase. The main clock signal CK is provided by the control unit in the larger application circuit where the holding register is located. Because the clock signal changes at a high frequency and the timing requirements are strict, the main clock signal CK from the control unit may not meet the requirements. Therefore, the holding register in this application internally processes and generates two clock signals, the negative clock signal CKN and the positive clock signal CKP, to ensure the stability of the operation.

[0070] In one embodiment, the hold signal processing submodule 12 may include a sixteenth PMOS transistor 116 and a sixteenth NMOS transistor 216. The first terminal of the sixteenth PMOS transistor 116 is connected to a normally open power supply VDDG. The second terminal of the sixteenth PMOS transistor 116 is coupled to the first terminal of the sixteenth NMOS transistor 216 as the output terminal of the hold signal processing submodule 12, outputting a hold inverse signal RET. The second terminal of the sixteenth NMOS transistor 216 is grounded. The gate terminals of the sixteenth PMOS transistor 116 and the sixteenth NMOS transistor 216 are coupled to the input terminals of the hold signal processing submodule 12, receiving the input hold master signal (i.e., the hold positive signal RETN).

[0071] Referring to the previous description, it is easy to understand that the sixteenth PMOS transistor 116 and the sixteenth NMOS transistor 216 also form an inverter. After inverting the main hold signal, the inverted hold signal RET is output from the coupling point between the second terminal of the sixteenth PMOS transistor 116 and the first terminal of the sixteenth NMOS transistor 216 (that is, the output terminal of the hold signal processing submodule 12). The main hold signal is also provided by the control unit in the larger application circuit where the hold register is located. The main hold signal is a control signal, which generally has a low frequency of change and only flips when needed. The timing requirements are not very strict, so the main hold signal provided by the control unit can be used directly as the positive hold signal RETN without processing (therefore...). Figure 1 (Using RETN directly to represent the hold master signal) only requires an inverter to generate a hold inverse signal RET.

[0072] Furthermore, in the first switching submodule 22, the connection relationships between the first and second terminals of the third PMOS transistor 103 and the first and second terminals of the third NMOS transistor 203 can be interchanged. That is, the first terminal of the third PMOS transistor 103 can be connected to the second terminal of the third NMOS transistor 203, and vice versa. Even more... Figure 1 Point a in the middle is where the second terminal of the third PMOS transistor 103 is connected to the second terminal of the third NMOS transistor 203. Figure 1 Point b is where the first terminal of the third PMOS transistor 103 is connected to the first terminal of the third NMOS transistor 203. Alternatively, Figure 1 Point a in the middle is where the second terminal of the third PMOS transistor 103 is connected to the first terminal of the third NMOS transistor 203. Figure 1 Point b is where the first terminal of the third PMOS transistor 103 is connected to the second terminal of the third NMOS transistor 203.

[0073] The above provides a full description of the various embodiments of the holding register of this application. The inventors of this application have also conducted tests and verifications. Compared with existing holding registers, the holding register of this application can reduce the chip area occupied by about 3-10%. The reason is that the holding register of this application has a compact structure and the number of MOS transistors used is reduced compared with the number of existing holding registers.

[0074] In summary, it is easy to see that, compared with the prior art, the technical solution of this application has the following beneficial effects: The holding register of this application integrates the data trigger output function and the data power-down retention function into the same module structure. Therefore, the holding register of this application has a compact structure and occupies less chip area.

[0075] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the claims. Furthermore, specific examples have been used in the specification to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application, and the content of this specification should not be construed as a limitation of this application.

Claims

1. A holding register, characterized in that, The holding register includes: a control signal processing module, a first latch module, and an output module; The control signal processing module is powered by a power-off switch and a normally-on power supply and is used to generate clock signals and hold signals. The clock signals include opposite positive clock signals and negative clock signals, and the hold signals include opposite positive hold signals and negative hold signals. The first latch module is powered by both a power-off switch and a normally-on power supply, and is coupled to both the control signal processing module and the output module. When the power-off switch is powered, under the control of the clock signal and the hold signal, it latches the received input signal and outputs the input signal through the output module. When the power-off switch is powered off and only the normally-on power supply is available, under the control of the hold signal, it latches the input signal in its final state when the power-off switch is powered off, and outputs the final state of the input signal through the output module when the power-off switch is restored. The output module is powered by a power-off switch.

2. The holding register according to claim 1, characterized in that, The first latch module includes: a first tri-state inverting submodule, a first switching submodule, and a first latch submodule; The first tri-state inverting submodule is powered by the power supply that can be turned off. The input terminal of the first tri-state inverting submodule receives an input signal and is used to output the input signal under the control of the clock signal. The first terminal of the first switch submodule is coupled to the output terminal of the first tri-state inverting submodule, and the second terminal of the first switch submodule is coupled to the first latch submodule. It is used to transmit the input signal output by the first tri-state inverting submodule to the first latch submodule or output the input signal latched by the first latch submodule under the control of the holding signal. The first latching submodule is powered by the normally open power supply and is used to latch the signal transmitted from the first switching submodule under the control of the clock signal and the hold signal. The input terminal of the output module is coupled to the coupling point between the first switch submodule and the first tri-state inverting submodule.

3. The holding register according to claim 2, characterized in that, The first tri-state inverting submodule includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The first terminal of the first PMOS transistor is connected to a power supply that can be turned off. The second terminal of the first PMOS transistor is connected to the first terminal of the second PMOS transistor. The second terminal of the second PMOS transistor is coupled to the first terminal of the first NMOS transistor as the output terminal of the first tri-state inverting sub-module. The second terminal of the first NMOS transistor is connected to the first terminal of the second NMOS transistor. The second terminal of the second NMOS transistor is grounded. The gate terminals of the first PMOS transistor and the second NMOS transistor are coupled to the input terminal of the first tri-state inverting sub-module. The gate terminals of the second PMOS transistor and the first NMOS transistor respectively receive the negative clock signal and the positive clock signal.

4. The holding register according to claim 2, characterized in that, The first switching submodule includes: a third PMOS transistor and a third NMOS transistor; The first terminal of the third PMOS transistor and the first terminal of the third NMOS transistor are coupled to form the first terminal of the first switching submodule. The second terminal of the third PMOS transistor and the second terminal of the third NMOS transistor are coupled to form the second terminal of the first switching submodule. The gate terminal of the third PMOS transistor and the gate terminal of the third NMOS transistor respectively receive the hold positive signal and the hold negative signal.

5. The holding register according to claim 2, characterized in that, The first latch submodule includes: a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; The first terminal of the fourth PMOS transistor is connected to a normally open power supply, the second terminal of the fourth PMOS transistor is coupled to the first terminal of the fourth NMOS transistor, the second terminal of the fourth NMOS transistor is grounded, and the gate terminals of both the fourth PMOS transistor and the fourth NMOS transistor are coupled to the first switch submodule. The first terminal of the fifth PMOS transistor is connected to a normally open power supply. The second terminal of the fifth PMOS transistor is connected to the first terminals of the sixth and seventh PMOS transistors. The second terminals of the sixth PMOS transistor, the fifth NMOS transistor, the seventh PMOS transistor, and the sixth NMOS transistor are all connected to the first switch submodule. The second terminals of the fifth and sixth NMOS transistors are connected to the first terminal of the seventh NMOS transistor. The second terminal of the seventh NMOS transistor is grounded. The gate terminals of the fifth and seventh NMOS transistors are connected to the second terminals of the fourth PMOS transistor and the first terminals of the fourth NMOS transistor. The gate terminals of the sixth PMOS transistor and the fifth NMOS transistor receive the positive clock signal and the negative clock signal, respectively. The gate terminals of the seventh PMOS transistor and the sixth NMOS transistor receive the positive hold signal and the negative hold signal, respectively.

6. The holding register according to claim 1, characterized in that, The holding register further includes: a second latch module coupled to the first latch module and the control signal processing module; the second latch module includes: a second tri-state inverting submodule and a second latch submodule; The input terminal of the second tri-state inverting submodule is coupled to the input signal terminal, and is used to receive and output the input signal under the control of the clock signal; The input terminal of the second latch submodule is coupled to the output terminal of the second tri-state inverting submodule to latch the input signal or output the input signal to the first latch module under the control of the clock signal.

7. The holding register according to claim 6, characterized in that, The second tri-state inverting submodule includes: an eighth PMOS transistor, a ninth PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; The first terminal of the eighth PMOS transistor is connected to a power-off switch. The second terminal of the eighth PMOS transistor is connected to the first terminal of the ninth PMOS transistor. The second terminal of the ninth PMOS transistor is coupled to the first terminal of the eighth NMOS transistor as the output terminal of the second tri-state inverting sub-module. The second terminal of the eighth NMOS transistor is connected to the first terminal of the ninth NMOS transistor. The second terminal of the ninth NMOS transistor is grounded. The gate terminals of the eighth PMOS transistor and the ninth NMOS transistor are coupled to the input terminal of the second tri-state inverting sub-module. The gate terminals of the ninth PMOS transistor and the eighth NMOS transistor receive the positive clock signal and the negative clock signal, respectively.

8. The holding register according to claim 6, characterized in that, The second latch submodule includes: a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor; The first terminal of the tenth PMOS transistor is connected to the power supply that can be turned off. The second terminal of the tenth PMOS transistor is coupled to the first terminal of the tenth NMOS transistor as the output terminal of the second latch submodule. The second terminal of the tenth NMOS transistor is grounded. The gate terminal of the tenth PMOS transistor is coupled to the gate terminal of the tenth NMOS transistor as the input terminal of the second latch submodule. The first terminal of the eleventh PMOS transistor is connected to the power supply that can be turned off. The second terminal of the eleventh PMOS transistor is connected to the first terminal of the twelfth PMOS transistor. The second terminal of the twelfth PMOS transistor and the first terminal of the eleventh NMOS transistor are coupled to the input terminal of the second latch submodule. The second terminal of the eleventh NMOS transistor is connected to the first terminal of the twelfth NMOS transistor. The second terminal of the twelfth NMOS transistor is grounded. The gate terminals of the eleventh PMOS transistor and the twelfth NMOS transistor are coupled to the output terminal of the second latch submodule. The gate terminals of the twelfth PMOS transistor and the eleventh NMOS transistor receive the negative clock signal and the positive clock signal, respectively.

9. The holding register according to claim 1, characterized in that, The output module includes: a thirteenth PMOS transistor and a thirteenth NMOS transistor; The first terminal of the thirteenth PMOS transistor is connected to a power supply that can be turned off. The second terminal of the thirteenth PMOS transistor is coupled to the first terminal of the thirteenth NMOS transistor to form the output terminal of the output module. The second terminal of the thirteenth NMOS transistor is grounded. The gate terminals of the thirteenth PMOS transistor and the gate terminals of the thirteenth NMOS transistor are coupled to form the input terminal of the output module.

10. The holding register according to claim 1, characterized in that, The control signal processing module includes a clock signal processing submodule and a hold signal processing submodule; The clock signal processing submodule includes a fourteenth PMOS transistor, a fifteenth PMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor. The first terminal of the fourteenth PMOS transistor is connected to a power supply that can be turned off. The second terminal of the fourteenth PMOS transistor and the first terminal of the fourteenth NMOS transistor are coupled to form the intermediate output terminal of the clock signal processing submodule, which outputs a negative clock signal. The second terminal of the fourteenth NMOS transistor is grounded. The gate terminals of the fourteenth PMOS transistor and the fourteenth NMOS transistor are coupled to form the input terminal of the clock signal processing submodule, which receives the main input clock signal. The first terminal of the fifteenth PMOS transistor is connected to a power supply that can be turned off. The second terminal of the fifteenth PMOS transistor and the first terminal of the fifteenth NMOS transistor are coupled to form the rear output terminal of the clock signal processing submodule, which outputs a positive clock signal. The second terminal of the fifteenth NMOS transistor is grounded. The gate terminals of the fifteenth PMOS transistor and the fifteenth NMOS transistor are coupled to the intermediate output terminal of the clock signal processing submodule. The hold signal processing submodule includes a sixteenth PMOS transistor and a sixteenth NMOS transistor. The first terminal of the sixteenth PMOS transistor is connected to a normally open power supply. The second terminal of the sixteenth PMOS transistor is coupled to the first terminal of the sixteenth NMOS transistor as the output terminal of the hold signal processing submodule, outputting a hold inverse signal. The second terminal of the sixteenth NMOS transistor is grounded. The gate terminals of the sixteenth PMOS transistor and the sixteenth NMOS transistor are coupled to the input terminal of the hold signal processing submodule, receiving the input hold main signal. The hold positive signal is the same as the hold main signal.

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