Low k and tantalum nitride barrier recovery using soak treatment

Abstract

Embodiments herein describe a method of fabricating an interconnect structure. The method includes depositing a selective tungsten layer on a tungsten-containing surface, the tungsten-containing surface disposed within a feature, where the feature includes one or more surfaces comprising a dielectric material, and the depositing of the selective tungsten layer results in formation of a residue on the dielectric material. The method also includes performing a reduction reaction by exposing the residue and dielectric material to immersion in an organosilane-containing precursor, wherein the organosilane-containing precursor reduces the residue. The method further includes forming a conformal layer over the dielectric material and the selective tungsten layer.

Description

Background Technology Technical Field

[0001] The embodiments described herein generally relate to methods for filling gaps in features formed in a substrate. Specifically, embodiments of this disclosure relate to methods for post-processing features containing a low-dielectric-constant dielectric formed on a substrate.

[0002] Related technical descriptions

[0003] Tungsten (W) is widely used in the manufacture of integrated circuit (IC) devices to form conductive features in semiconductor devices, where relatively low resistance and relatively high electromigration resistance are desired. For example, tungsten can be used as a metal filler to form source contacts, drain contacts, metal gate fillers, gate contacts, interconnects (e.g., horizontal features formed in the surface of a dielectric layer), and vias (e.g., vertical features formed through a dielectric layer to connect other interconnect features disposed above and below it). Due to its relatively low resistivity, tungsten is also commonly used to form interconnects at the M0 level of IC devices, and also to form bit lines and word lines for addressing individual memory cells in memory cell arrays of three-dimensional NAND (3D NAND) devices.

[0004] It has been known that post-processing methods used to remove tungsten and chlorine contamination from low-dielectric-constant dielectric surfaces during device manufacturing processes can damage the low-dielectric-constant dielectric layer. The presence of contamination within a feature or damage to the low-dielectric-constant material within a feature during the contamination removal process can affect the electrical characteristics of the semiconductor device including that feature and / or reduce the lifetime of the formed semiconductor device.

[0005] Therefore, a process is needed to solve these problems. Summary of the Invention

[0006] The embodiments described herein generally relate to methods for filling gaps in semiconductors. Specifically, embodiments of this disclosure relate to methods for post-processing of low-dielectric-constant dielectrics.

[0007] In one embodiment, a method for manufacturing an interconnect structure is disclosed. The method includes depositing a selective tungsten layer on a tungsten-containing surface disposed within a feature, wherein the feature includes one or more surfaces comprising a dielectric material, and the deposition of the selective tungsten layer results in the formation of a residue on the dielectric material. The method also includes performing a reduction reaction by exposing the residue and the dielectric material to a precursor containing an organosilane for immersion, wherein the precursor containing the organosilane reduces the residue. The method further includes forming a conformal layer over the dielectric material and the selective tungsten layer.

[0008] In another embodiment, a method for manufacturing an interconnect structure is disclosed. The method includes performing a pretreatment process. The method also includes depositing a selective tungsten layer on a tungsten-containing surface disposed within features, wherein the features include one or more surfaces comprising a low-dielectric-constant dielectric material, wherein the deposition results in the formation of residues on the low-dielectric-constant dielectric material. The method further includes performing a reduction reaction by immersion in 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexane (CHD), wherein the CHD reduces the residues. The method also includes forming a conformal layer over the low-dielectric-constant dielectric and the selective tungsten layer, and depositing a metal filler layer over the conformal layer.

[0009] In another embodiment, a method for manufacturing an interconnect structure is disclosed. The method includes performing a pretreatment process. The method also includes depositing a selective tungsten layer on a tungsten-containing surface using a fluorine-free tungsten (FFW) deposition process, wherein the tungsten-containing surface is disposed within features, wherein the features include one or more surfaces comprising a low-dielectric-constant dielectric material, wherein the deposition results in the formation of chlorine and tungsten residues on the low-dielectric-constant dielectric material; the method further includes performing a reduction reaction by immersion in 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexane (CHD), wherein CHD reduces the chlorine and tungsten residues; forming a conformal layer over the low-dielectric-constant dielectric material and the selective tungsten layer; and depositing a metal filler layer over the conformal layer. Attached Figure Description

[0010] To gain a more detailed understanding of the features described above in this disclosure, a more specific description of the disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate common embodiments of this disclosure and are not intended to limit its scope, as this disclosure allows for other equivalent and effective embodiments.

[0011] Figure 1 illustrates an exemplary processing method according to one or more embodiments of the present disclosure.

[0012] Figures 2A to 2E A schematic cross-sectional view of a semiconductor element during a processing method according to one or more embodiments of the present disclosure is shown.

[0013] Figure 3 A schematic representation of a processing tool used in conjunction with one or more embodiments of this disclosure is shown. Detailed Implementation

[0014] The embodiments described herein generally relate to methods for filling gaps in features formed in a substrate. Specifically, embodiments of this disclosure relate to methods for post-processing features containing a low-dielectric-constant dielectric formed on a substrate.

[0015] Selective growth of tungsten (W) on tungsten vias within interconnect structures can lead to residue accumulation on low-dielectric-constant dielectric structures within the interconnect structure. This residue can result in loss of tungsten selectivity and / or reduced tantalum nitride (TaN) blocking quality during subsequent tungsten deposition processes. Therefore, a method is needed to remove residue from the surface of features formed within a substrate before filling the features with one or more metal layers. In some embodiments, the method includes removing residue formed after selective tungsten growth is performed on features containing a low-dielectric-constant dielectric material.

[0016] The method disclosed herein includes a post-treatment involving immersion in an organosilane-containing precursor (e.g., 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexane (CHD) immersion), which significantly reduces the content of residues, including halogen-containing residues (e.g., chlorine (Cl) residues), and better prevents damage to the conformal barrier layer compared to other known processes. Known post-treatment methods (such as sputter-based pre-cleaning processes, advanced pre-cleaning processes (APC), capacitively coupled plasma (CCP) hydrogen (H2) plasma, and H2O-based pre-cleaning processes) are less effective than the organosilane immersion process described herein for residue removal and do not completely prevent degradation of the conformal barrier resistance attributable to the presence of residues on the underlying surface. More importantly, most known post-treatment methods damage low-dielectric-constant materials, a condition not observed in the CHD immersion process disclosed herein. Furthermore, CHD immersion requires less time compared to other post-treatment methods and can be integrated into the same chamber as fluorine-free tungsten deposition processes.

[0017] Figure 1 illustrates an exemplary processing method 100 according to one or more embodiments of the present disclosure. Figures 2A to 2E A schematic cross-sectional view of the interconnect structure 200 during processing method 100 according to one or more embodiments of the present disclosure is shown. It should be understood that... Figures 2A to 2E Only a partial schematic diagram of the interconnect structure 200 is shown, and the interconnect structure 200 may contain any number of transistor segments and additional material with aspects as shown in the figures. It should also be noted that although the method 100 shown in Figure 1 has been described sequentially, including one or more operations that have been omitted and / or added and / or other process sequences that have been rearranged in a different desired order, fall within the scope of the embodiments of the disclosure provided herein.

[0018] As used herein, the term "substrate" refers to a layer of material used as the base for subsequent processing operations and comprising the surface to be cleaned. Depending on the requirements, the substrate may be a silicon-based material or any suitable insulating or conductive material. The substrate may include materials such as crystalline silicon (e.g., Si). <100> or Si <111> Silicon oxide, strained silicon, germanium silicon, doped or undoped polycrystalline silicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0019] In some embodiments, method 100 includes an optional pretreatment process in operation 110. Figure 2A The interconnect structure 200 is shown after operation 110 has been performed. Figure 2A In this embodiment, a hard mask 222 is disposed above the surface of a low-dielectric-constant dielectric layer 220 formed on an etch-stop layer 214. The hard mask 222, the low-dielectric-constant dielectric layer 220, and the etch-stop layer 214 include features 201 formed therein. The low-dielectric-constant dielectric may be formed of silicate glass (SiCOH), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), alumina (Al2O3), aluminum nitride (AlN), or any other low-dielectric-constant dielectric material. The low-dielectric-constant dielectric 220 is typically disposed on the etch-stop layer 214. In some embodiments, the etch-stop layer may include alumina (Al2O3). The etch-stop layer 214 is disposed on dielectric material portions 210 disposed within underlying contacts or interconnect structures. The dielectric material portions 210 may be formed of a dielectric material such as silicon dioxide. Tungsten vias 212 are located between the dielectric material portions 210. Dielectric material portion 210 and tungsten through-hole 212 are formed above the substrate (not shown).

[0020] In some embodiments, operation 110 comprises the following three steps: a cleaning process for removing impurities, a defect curing process, and an oxide reduction process. In some embodiments, operation 110 includes etching, reduction, oxidation, hydroxylation, annealing, and / or thermal treatment of the interconnect structure 200.

[0021] In some embodiments, a radical-based pre-cleaning technique is used in operation 110. In some embodiments, the pre-cleaning technique utilizes a remote plasma source to provide a radical-containing gas for removing at least a portion of residual contaminants, solidifying defects and / or chemical alterations in the low-dielectric-constant dielectric 220, and residual contaminants found within feature 201.

[0022] In some embodiments, during operation 110, the interconnect structure 200 is maintained at a temperature ranging from 200°C to 550°C while exposed to a gas containing plasma or free radicals. In some embodiments, the interconnect structure 200 is maintained at a temperature of 345°C while exposed to a gas containing plasma or free radicals.

[0023] In some embodiments, during operation 110, the interconnect structure 200 is exposed to a helium plasma, a hydrogen plasma, or a combination thereof. In some embodiments, the plasma contains helium (He), and the helium is supplied to the interconnect structure 200 at a flow rate between 250 sccm and 500 sccm. In some embodiments, the plasma contains hydrogen (H2), and the hydrogen is supplied to the interconnect structure 200 at a flow rate between 10 and 40 sccm. In some embodiments, the interconnect structure 200 is exposed to a plasma formed by supplying 380 sccm of helium and 20 sccm of hydrogen, while maintaining the processed area formed above the substrate at a pressure of 300 mTorr.

[0024] In some implementations, operation 110 is performed for a period of 5 seconds to 1 minute. In some implementations, operation 110 is performed for a period of 25 seconds.

[0025] In operation 120, a selective tungsten layer 216 is deposited on the tungsten via 212, such as... Figure 2B As shown. In some embodiments, the selective tungsten layer 216 is deposited using an atomic layer deposition (ALD) fluorine-free tungsten (FFW) deposition process. In operation 120, the selective tungsten layer 216 is selectively deposited on the tungsten via 212 above the low dielectric constant dielectric 220.

[0026] In some embodiments, operation 120 includes two or more sub-processes. Sub-processes may include exposing the interconnect structure 200 to a fluorine-free tungsten precursor to clean the surface of the interconnect structure 200 and exposing the interconnect structure 200 to a fluorine-free tungsten reagent to deposit a tungsten film.

[0027] Some implementations use fluorine-free tungsten precursors to increase selectivity and / or deposition rate. In some implementations, the fluorine-free tungsten precursor may be the same chemical substance as the fluorine-free tungsten reagent. In some implementations, the fluorine-free tungsten precursor is a different chemical substance from the fluorine-free tungsten reagent.

[0028] In some embodiments, the fluorine-free tungsten precursor and / or fluorine-free tungsten reagent comprises tungsten halide, tungsten halide, tungsten hydride, or combinations thereof. In some embodiments, the fluorine-free tungsten precursor comprises tungsten halide or tungsten halide of greater than or equal to 95%, 98%, 99%, or 99.5% in moles. In some embodiments, the tungsten halide comprises tungsten pentachloride (WCl5), tungsten hexachloride (WCl6), tungsten pentabromide (WBr5), tungsten hexabromide (WBr6), or combinations thereof. In some embodiments, the tungsten halide precursor comprises tungsten tetrachloride (WOCl4), tungsten dichlorodioxide (WO2Cl2), or combinations thereof. In some embodiments, the fluorine-free tungsten precursor comprises tungsten pentachloride (WCl5), tungsten hexachloride (WCl6), tungsten tetrachloride (WOCl4), tungsten dichlorodioxide (WO2Cl2), tungsten pentabromide (WBr5), tungsten hexabromide (WBr6), or combinations thereof. In other embodiments, the first processing condition includes a tungsten precursor selected from the group consisting of fluorine-free tungsten halide precursors or chlorohalide-free tungsten precursors, such as tungsten pentabromide (WBr5) or tungsten hexabromide (WBr6).

[0029] In some embodiments, the fluorine-free tungsten reagent flows together with the reducing agent. In some embodiments, the reducing agent comprises hydrogen (H2), silane (SiH4), disilane (Si2H6), trisilane (Si3H8), or tetrasilane (Si4H2H6). 10 One or more of hydrazine (N2H4) or ammonia (NH3).

[0030] In some embodiments, the interconnect structure 200 is exposed to a fluorine-free tungsten precursor and / or a fluorine-free tungsten reagent at a temperature between 15°C and 450°C. In some embodiments, the interconnect structure 200 is exposed to a fluorine-free tungsten precursor and a fluorine-free tungsten reagent at a temperature of about 420°C.

[0031] In some embodiments, the fluorine-free tungsten precursor flows into the chamber at a rate between 500 sccm and 900 sccm. In some embodiments, the fluorine-free tungsten precursor flows into the chamber at a temperature between 380°C and 460°C. In some embodiments, the chamber is maintained at a pressure between 15 Torr and 100 Torr. In some embodiments, the fluorine-free tungsten precursor is WCl5, and it flows at a rate of 700 sccm at 420°C for approximately four minutes, while the chamber is maintained at a pressure of approximately 28 Torr. In some embodiments, the fluorine-free tungsten reagent is WCl5, which flows co-flows with hydrogen (H2). In some embodiments, the fluorine-free tungsten reagent flows at 420°C for approximately five minutes.

[0032] like Figure 2B As shown, a side effect of operation 120 is the accumulation of residue 224 on the low dielectric constant dielectric 220. Residue 224 may be chlorine, tungsten, WCl, etc.x and WO x Cl x Byproducts and combinations thereof. Residue 224 may lead to loss of tungsten selectivity and reduced tantalum nitride (TaN) blocking quality due to the TaN barrier positioned above it. In one embodiment, residue 224 comprises trapped Cl radicals and WCl. x .

[0033] In operation 130, residue 224 is removed by performing a immersion process containing an organosilicon precursor. In one example, the immersion process includes exposing feature 201 to a solution containing 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexane (C 13 H 26 The precursor gas of Si2)(CHD). CHD molecules perform a reduction reaction to remove residue 224 from the low dielectric constant dielectric 220, such as Figure 2C As shown. In one embodiment, CHD molecules and MCl in residue 224 x The reaction involves Cl radicals, where M is a metal contamination (e.g., W, Mo, etc.) found on low-dielectric-constant dielectric materials. The byproducts of this reduction reaction are low-dielectric-constant dielectric chloride (MCl5), trimethylsilyl chloride ((CH3)3SiCl), the metal (M) on the low-dielectric-constant dielectric material, and toluene (C6H5CH3).

[0034] In some embodiments, the organosilane precursor is combined with the carrier gas. In some embodiments, the flow rates of the organosilane precursor and the carrier gas are between 50 sccm and 300 sccm. In some embodiments, the total flow rate of the organosilane precursor and the carrier gas is 150 sccm.

[0035] In some embodiments, the immersion of the organosilane precursor is performed at a temperature between 300°C and 500°C. In some embodiments, the immersion of the organosilane precursor is performed at 400°C.

[0036] In some embodiments, the organosilane precursor is immersed at a pressure between 1 Torr and 100 Torr. In some embodiments, the pressure is 5 Torr.

[0037] In some embodiments, the immersion containing the organosilane precursor is performed for a period of time between 20 seconds and 240 seconds. In some embodiments, the immersion containing the organosilane precursor is performed for a period of time of 30 seconds.

[0038] In operation 140, such as Figure 2DAs shown, the tungsten carbide hard mask 222 is removed and a conformal layer 226 is deposited on the interconnect structure 200, such that the conformal layer 226 substantially liner the low-dielectric-constant dielectric 220 and the selective tungsten layer 216. The conformal layer 226 protects the material beneath the conformal layer 226 from damage caused by additional operations of method 100 or subsequent operations. Furthermore, the conformal layer 226 prevents damage from the final deposited metal fill 228 (…). Figure 2E The atoms in the (shown) move and migrate to the remainder of the interconnect structure 200.

[0039] The conformal layer 226 can be used as a barrier layer and is formed of tantalum nitride (TaN) or doped tantalum nitride (TaN), metal-doped TaN, titanium nitride (TiN), tungsten nitride (WN), or tungsten carbonitride (WCN). The barrier conformal layer 226 can be deposited using any suitable film deposition method, such as ALD.

[0040] like Figure 2E As shown, in operation 150, a metal fill process is performed to fill the remaining area between the low-dielectric-constant dielectrics 220 and cover it with a conformal layer 226. The metal fill process deposits a metal filler layer 228. In some embodiments, the metal filler 228 may include tungsten (W), copper (Cu), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). In some embodiments, the metal filler layer 228 is tungsten (W).

[0041] Operation 150 can be performed in a processing chamber (such as...) Figure 3 The operation is performed in the processing chambers 324, 326, 328, or 330 by chemical vapor deposition (CVD) and / or physical vapor deposition (PVD). In other embodiments, operation 150 is performed by electroplating.

[0042] Figure 3 A schematic representation of a processing tool 300 used in conjunction with one or more embodiments of this disclosure is shown. In some embodiments, the processing tool 300 may be used to perform all or part of method 100.

[0043] The processing tool 300 generally includes a factory interface 302, load-locking chambers 304 and 306, transfer chambers 308 and 310 with corresponding transfer robots 312 and 314, holding chambers 316 and 318, and processing chambers 320, 322, 324, 326, 328, and 330. As detailed herein, substrates in the processing tool 300 can be processed in and transferred between the chambers without exposing the substrates to the surrounding environment outside the processing tool 300 (e.g., the atmospheric environment, such as that present in a semiconductor foundry). For example, substrates can be processed in and transferred between chambers under low-pressure (e.g., less than or equal to about 300 Torr) or vacuum conditions without disrupting the low-pressure or vacuum environment in the various processes performed on the substrates in the processing tool 300. Thus, the processing tool 300 provides an integrated solution for some processing of substrates.

[0044] Examples of processing systems that can be appropriately modified based on the teachings provided herein include: or Integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc., located in Santa Clara, California. It will be anticipated that other processing systems (including those from other manufacturers) may be applicable and beneficial to the aspects described herein.

[0045] exist Figure 3 In the illustrated example, the factory interface 302 includes a docking station 332 and a factory interface robot 334 to facilitate the transfer of substrates. The docking station 332 is adapted to receive one or more front-opening unified pods (FOUPs) 336. In some examples, each factory interface robot 334 generally includes blades 338 disposed at one end of the respective factory interface robot 334, which are adapted to transfer substrates from the factory interface 302 to load-locking chambers 304, 306.

[0046] Load-locking chambers 304 and 306 have corresponding ports 340 and 342 coupled to factory interface 302 and corresponding ports 344 and 346 coupled to transfer chamber 308. Transfer chamber 308 further has corresponding ports 348 and 350 coupled to holding chambers 316 and 318 and corresponding ports 352 and 354 coupled to processing chambers 320 and 322. Similarly, transfer chamber 310 has corresponding ports 356 and 358 coupled to holding chambers 316 and 318 and corresponding ports 360, 362, 364, and 366 coupled to processing chambers 324, 326, 328, and 330. Ports 344, 346, 348, 350, 352, 354, 356, 358, 360, 362, 364, and 366 can be, for example, slit valve openings with slit valves, which are used for the transfer robots 312 and 314 to pass through their transfer substrates and to provide a seal between the respective chambers to prevent the transfer of gas between the respective chambers. Generally, any port is open for passage through its transfer substrate. Otherwise, the port is closed.

[0047] Load locking chambers 304 and 306, transfer chambers 308 and 310, holding chambers 316 and 318, and processing chambers 320, 322, 324, 326, 328, and 330 are fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryogenic pumps, roughing pumps), gas sources, valves, and piping fluidly coupled to the respective chambers. In operation, a factory interface robot 334 transfers a substrate from FOUP 336 through port 340 or 342 to load locking chambers 304 or 306. The gas and pressure control system then evacuates load locking chambers 304 or 306. The gas and pressure control system further maintains transfer chambers 308 and 310 and holding chambers 316 and 318 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, the evacuated load-locking chamber 304 or 306 facilitates the transfer of substrates between the atmospheric environment of, for example, the factory interface 302 and the low-pressure or vacuum environment of the transfer chamber 308.

[0048] Using the substrate in the evacuated load-locking chamber 304 or 306, the transfer robot 312 transfers the substrate through port 344 or 346 from the load-locking chamber 304 or 306 to the transfer chamber 308. The transfer robot 312 can then transfer the substrate through the corresponding ports 352, 354 to either of the processing chambers 320, 322 and / or between the processing chambers for processing, and through the corresponding ports 348, 350 to the holding chambers 316, 318 and / or between the holding chambers for holding to await further transfer. Similarly, the transfer robot 314 can access substrates in holding chambers 316 or 318 through ports 356 or 358, and can transfer substrates through corresponding ports 360, 362, 364, 366 to any of the processing chambers 324, 326, 328, 330 and / or between any of the processing chambers for processing, and through corresponding ports 356, 358 to holding chambers 316, 318 and / or between the holding chambers for holding to await further transfer. The transfer and holding of substrates within each chamber can be conducted in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0049] Processing chambers 320, 322, 324, 326, 328, and 330 can be any suitable chamber for processing a substrate. In some examples, processing chamber 320 can perform etching processes, processing chamber 322 can perform cleaning processes, and processing chambers 326, 328, and 330 can perform corresponding epitaxial growth processes. Processing chamber 320 is available from Selectra, Applied Materials, Inc., Santa Clara, California. TM Etched chamber. Processor chamber 322 is available from SiCoNi from Applied Materials, Santa Clara, California. TM Pre-clean chambers. Processing chambers 326, 328, or 330 are available from Centura, Applied Materials, Santa Clara, California. TM Epi chamber, Volta TM CVD / ALD chamber, or Encore TM PVD chamber.

[0050] System controller 368 is coupled to processing tool 300 for controlling processing tool 300 or its components. For example, system controller 368 may control the operation of processing tool 300 by directly controlling chambers 304, 306, 308, 310, 316, 318, 320, 322, 324, 326, 328, and 330 of processing tool 300, or by controlling controllers associated with chambers 304, 306, 308, 310, 316, 318, 320, 322, 324, 326, 328, and 330. During operation, system controller 368 performs data collection and feedback from the respective chambers to coordinate the performance of processing tool 300.

[0051] The system controller 368 generally includes a central processing unit (CPU) 370, memory 372, and support circuitry 374. The CPU 370 can be one of any type of general-purpose processor that can be used in industrial settings. Memory 372, or a non-transitory computer-readable medium, is accessible through the CPU 370 and can be one or more types of memory, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of digital storage (local or remote). Support circuitry 374 is coupled to the CPU 370 and may include cache, clock circuitry, input / output subsystems, power supplies, and the like. The various methods disclosed herein can be implemented generally under the control of the CPU 370 by executing computer instruction code stored in memory 372 (or in the memory of a specific processing chamber), for example, as software routines. When the computer instruction code is executed by the CPU 370, the CPU 370 controls the chamber to perform the process according to various methods.

[0052] Other processing systems may be configured differently. For example, more or fewer processing chambers may be coupled to a transport device. In the illustrated example, the transport device includes transport chambers 308, 310 and holding chambers 316, 318. In other examples, more or fewer transport chambers (e.g., one transport chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as transport devices in a processing system.

[0053] The embodiments described herein provide a method for removing chlorine (Cl) and tungsten (W) residues from a low-dielectric-constant dielectric after selective tungsten deposition. In the method described herein, an organosilane precursor is impregnated (such as 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexane (C... 13 H 26Si2)(CHD) immersion is used to perform a reduction reaction to remove residues formed within features formed in a substrate. In one instance, CHD immersion removes residues faster than other residue removal methods, does not damage any exposed layers within the formed features (e.g., layers containing low-dielectric-constant dielectrics), and can be performed as selective tungsten deposition in the same processing chamber.

[0054] Although the foregoing relates to embodiments of this disclosure, other and further embodiments of this disclosure may be designed without departing from its basic scope, which is defined by the following claims.

Claims

1. A method for manufacturing an interconnect structure, the method comprising: A selective tungsten layer is deposited on a tungsten-containing surface, the tungsten-containing surface being disposed within a feature, wherein the feature includes one or more surfaces comprising a dielectric material, and the deposition of the selective tungsten layer results in the formation of a residue on the dielectric material; A reduction reaction is performed by exposing the residue and dielectric material to an organosilane-containing precursor immersion, wherein the organosilane-containing precursor reduces the residue; and A conformal layer is formed over the dielectric material and the selective tungsten layer.

2. The method of claim 1, wherein the dielectric material comprises a low dielectric constant dielectric material, and the organosilane precursor comprises 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexane (C 13 H 26 Si2)(CHD).

3. The method of claim 2, wherein the residue comprises at least one of tungsten and chlorine.

4. The method of claim 1, wherein the conformal layer comprises tantalum nitride (TaN).

5. The method of claim 1, wherein the immersion in the organosilane precursor and the deposition of the selective tungsten layer are performed in the same processing chamber.

6. The method of claim 1, wherein the deposition of the selective tungsten layer is performed by a fluorine-free tungsten (FFW) deposition process.

7. The method of claim 6, wherein the FFW deposition process comprises: Expose the interconnect structure to a fluorine-free tungsten precursor; and The interconnect structure was exposed to a fluorine-free tungsten reagent.

8. The method of claim 1, wherein The dielectric material comprises a low dielectric constant dielectric material. The organosilanes-containing precursor comprises 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexane (C 13 H 26 Si2)(CHD), and The deposition of the selective tungsten layer is performed using a fluorine-free tungsten (FFW) deposition process.

9. A method for manufacturing an interconnect structure, the method comprising: Perform pretreatment processes; A selective tungsten layer is deposited on a tungsten-containing surface, the tungsten-containing surface being disposed within a feature, wherein the feature includes one or more surfaces comprising a low-dielectric-constant dielectric material, wherein the deposition results in the formation of a residue on the low-dielectric-constant dielectric material; The reduction reaction was performed by immersion in 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexane (CHD), wherein the CHD reduced the residue; A conformal layer is formed over the low dielectric constant dielectric and the selective tungsten layer; as well as A metal filler layer is deposited over the conformal layer.

10. The method of claim 9, wherein the pretreatment process comprises at least one of the following: Cleaning processes used to remove impurities; Defect curing process; and Oxide reduction process.

11. The method of claim 9, wherein the conformal layer comprises tantalum nitride (TaN).

12. The method of claim 9, wherein the CHD immersion and the deposition of the selective tungsten layer are performed in the same processing chamber.

13. The method of claim 9, wherein the deposition of the selective tungsten layer is performed by a fluorine-free tungsten (FFW) deposition process.

14. The method of claim 13, wherein the FFW deposition process comprises: Expose the interconnect structure to a fluorine-free tungsten precursor; and The interconnect structure was exposed to a fluorine-free tungsten reagent.

15. The method of claim 14, wherein the fluorine-free tungsten precursor comprises a first chemical substance and the fluorine-free tungsten reagent comprises a second chemical substance, wherein the first chemical substance and the second chemical substance are the same.

16. A method of manufacturing an interconnect structure, the method comprising: Perform pretreatment processes; A selective tungsten layer is deposited on a tungsten-containing surface using a fluorine-free tungsten (FFW) deposition process, wherein the tungsten-containing surface is disposed within a feature, wherein the feature includes one or more surfaces comprising a low-dielectric-constant dielectric material, wherein the deposition results in the formation of chlorine and tungsten residues on the low-dielectric-constant dielectric material; The reduction reaction was performed by immersion in 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexane (CHD), wherein the CHD reduced the chlorine and tungsten residues. A conformal layer is formed over the low dielectric constant dielectric material and the selective tungsten layer; and A metal filler layer is deposited over the conformal layer.

17. The method of claim 16, wherein the metal filler layer comprises tungsten.

18. The method of claim 16, wherein the conformal layer comprises tantalum nitride (TaN).

19. The method of claim 16, wherein the pretreatment process comprises one or more of etching, reduction, oxidation, hydroxylation, annealing, and / or chemical treatment of the interconnect structure.

20. The method of claim 16, wherein the low dielectric constant dielectric comprises one or more of organosilicon glass (SiCOH), silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), aluminum oxide (Al2O3), and aluminum nitride (AlN).

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