Dual gate structure for memory device

Abstract

A memory device includes at least one transistor having a dual gate structure including a first gate metal and a second gate metal, where the first gate metal has a work function of less than 4.55 eV and the second gate metal has a work function of greater than 4.55 eV. A method of forming the memory device is also provided.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to electronic device manufacturing. In particular, embodiments of the present disclosure relate to memory devices including at least one transistor having a dual gate structure. BACKGROUND

[0002] Memory devices are formed using a variety of materials. It is beneficial for memory devices, such as dynamic random access memory (DRAM), to have low or no leakage current. Current two-dimensional (2D) DRAM technology has reached a scaling limit. Accordingly, three-dimensional (3D) DRAM devices have been developed to increase the memory density and capacity of DRAM. Some 3D memory devices can include nanowire transistors (e.g., gate all around nanowire (GAA NW)) or nanosheet transistors (e.g., gate all around nanosheet (GAA NS)). However, it has been found that a "floating body effect" can occur in these 3D memory devices including nanosheet transistors or nanowire transistors because the body of the transistor is not in contact with the ground terminal of the 3D memory device. The floating body effect is an effect of the dependence of the transistor body potential on its biasing and carrier recombination process history, which is realized in silicon on insulator (SOI) technology. Charge accumulates on the body of the transistor and can cause adverse effects, such as triggering a parasitic transistor in the structure and causing off-state leakage, resulting in higher current consumption and, in the case of DRAM, loss of information in the memory cell. The charge also causes a history effect, in which the threshold voltage of the transistor depends on its previous state. Ultimately, the floating body effect induces leakage in the storage capacitor, which degrades the characteristics of the memory device. There have been methods to mitigate the floating body effect in memory devices, but these methods are not sufficient to completely mitigate the problem of the floating body effect. SUMMARY

[0003] According to an embodiment, a memory device is provided. The memory device can include at least one transistor having a dual gate structure including a first gate metal and a second gate metal, where the first gate metal has a low work function less than 4.55 eV and the second gate metal has a high work function greater than 4.55 eV. For example, the low work function can be equal to or less than 4.25 eV and the high work function can be equal to or greater than 4.75 eV. In another example, the low work function can be less than 4.55 eV and the high work function can be greater than 4.55 eV.

[0004] According to another embodiment, a method of fabricating a memory device is also provided. The method includes forming a first gate over a first portion of a gate oxide using a first metal, wherein the first metal has a low work function less than 4.55 eV or less than 4.25 eV; and forming a second gate over a second portion of the gate oxide using a second metal, wherein the second metal has a high work function greater than 4.55 eV or greater than 4.75 eV. BRIEF DESCRIPTION OF DRAWINGS

[0005] The disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that different references to "an" or "one" embodiment of the present disclosure in this disclosure do not necessarily refer to the same embodiment, and such references mean at least one.

[0006] Figure 1 A schematic diagram of an example portion of a memory device including a dual gate structure according to some embodiments.

[0007] Figures 2A-2F Various stages in the formation of a memory device including gates having dual work functions according to some embodiments are shown.

[0008] Figure 3 A graph showing ID-VG characteristics of transistors having gates with different gate work functions according to an embodiment.

[0009] Figure 4 A graph showing simulated transient characteristics for a memory node voltage as a function of a bit line (BL) voltage pulse for transistors having gates with different gate work functions according to an embodiment. DETAILED DESCRIPTION

[0010] Embodiments described herein relate to a memory device including at least one transistor having a dual gate structure including a first gate metal and a second gate metal, where each gate metal has a different work function. The first gate metal can have a work function less than 4.55 eV, and the second gate metal can have a work function greater than 4.55 eV. It has been found that transistors in 3D DRAM elements having a single metal gate are affected by floating body effects. Thus, when dynamic pulses are applied to such memory devices, the stored voltage decreases over time due to floating body effects. The dual gate structure of the transistors for 3D memory devices (e.g., 3D DRAM memory devices having GAA NS transistors and / or GAA NW transistors) according to embodiments of the present disclosure largely or completely eliminates floating body effects because it has been found that the dual gate eliminates dynamic retention degradation of the storage node. The dual gate structure according to embodiments employs dual word line metals (e.g., including a first metal for a first portion of the transistor and a second metal for a second portion of the transistor, the second metal having a different work function than the first metal). Experiments have shown that GAA DRAM elements and other memory devices (e.g., other 3D memory devices) having transistors employing dual gate structures with dual word line (WL) metals having different work functions completely eliminate dynamic refresh degradation that would otherwise be suffered by such elements due to the floating body effects described herein.

[0011] To implement the dual gate structure of the present disclosure, two different gate metals are incorporated. The inventors have discovered that when the work function of the gate metal is carefully selected, it can effectively prevent the floating body effect in the memory device. In embodiments, a first gate metal of the dual gate structure has a first work function, and a second gate metal of the dual gate structure has a second work function that is higher than the first work function. In embodiments, the first gate metal of the dual gate structure can have a work function that is less than 4.55 eV, and the second gate metal of the dual gate structure can have a work function that is greater than 4.55 eV, to effectively mitigate the floating body effect. In some examples, the first gate metal can have a work function of 4.45 eV, 4.35 eV, 4.25 eV, 4.1 eV, 4.0 eV, or another work function that is less than 4.55 eV. In some examples, the first gate metal can have a work function of about 3.5 eV to about 4.55 eV, about 3.7 eV to about 4.45 eV, about 3.9 eV to about 4.35 eV, or about 4.0 eV to about 4.25 eV. In some examples, the second gate metal can have a work function of 4.65 eV, 4.75 eV, 4.85 eV, 5.0 eV, 5.25 eV, or another work function that is higher than 4.55 eV. In some examples, the second gate metal can have a work function of about 4.6 eV to about 5.5 eV, about 4.75 eV to about 5.6 eV, about 4.85 eV to about 5.4 eV, or about 5.0 eV to about 5.2 eV. In some embodiments, the difference in work function between the first gate metal and the second gate metal is about 0.25 eV, about 0.3 eV, about 0.35 eV, about 0.4 eV, about 0.45 eV, or about 0.5 eV. In other embodiments, the difference in work function between the first gate metal and the second gate metal is greater than 0.25 eV. The difference in work function between the gate metals can be created through other methods, such as through ion implantation in the gate electrode, or by sandwiching a dipole layer between the gate oxide and the gate metal. In embodiments, to mitigate the floating body effect, the first gate metal with the lower work function is the gate metal closest to the storage node, and the second gate metal with the higher work function is the gate metal closest to the bit line. The first gate metal can include at least one of tantalum (Ta), tungsten (W), titanium nitride (TiN), titanium (Ti), a metal alloy such as titanium aluminum (TiAl), or N+ polysilicon. The second gate metal can include at least one of nickel (Ni), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), molybdenum (Mo), or another suitable alloy.

[0012] The memory device can further include a bit line contacting the second gate metal and a storage node contacting the first gate metal. It has been discovered that in order to effectively eliminate or mitigate floating body effects, the gate metal contacting or proximate to the bit line should have a higher work function than the gate metal contacting or proximate to the storage node. The inventors have discovered that if the gate metal contacting the storage node has a higher work function than the gate metal contacting the bit line, floating body effects can still occur.

[0013] In embodiments, the first gate metal and the second gate metal can be disposed on a spacer, where the first gate metal extends over about 50% of the spacer, and where the second gate metal extends over the remaining area of the spacer. In some embodiments, the spacer can be a gate insulator. In an embodiment, the first gate metal does not overlap the second gate metal. In some embodiments, the first gate metal can overlap the second gate metal.

[0014] In some embodiments, the memory device can include a passageway on each side of the spacer. In some embodiments, the passageway can have a thickness of about 10 nanometers to about 25 nanometers or about 5 nanometers to about 40 nanometers.

[0015] In some embodiments, the memory device can be a dynamic random access memory (DRAM).

[0016] In an embodiment, the memory device can include a support including a plurality of alternating layers of silicon (Si) and silicon germanium (SiGe) and at least one nitride layer.

[0017] In embodiments described herein, a method of manufacturing a memory device can include forming a first gate over a first portion of a gate oxide using a first metal, where the first metal has a work function less than 4.55 eV; and forming a second gate over a second portion of the gate oxide using a second metal, where the second metal has a work function greater than 4.55 eV. In some examples, the first metal can have a work function of 4.45 eV, 4.35 eV, 4.25 eV, 4.1 eV, 4.0 eV, or another work function less than 4.55 eV. In some examples, the first metal can have a work function of about 3.5 eV to about 4.55 eV, about 3.7 eV to about 4.45 eV, about 3.9 eV to about 4.35 eV, or about 4.0 eV to about 4.25 eV. In some examples, the second metal can have a work function of 4.65 eV, 4.75 eV, 4.85 eV, 5.0 eV, 5.25 eV, or another work function higher than 4.55 eV. In some examples, the second metal can have a work function of about 4.6 eV to about 5.5 eV, about 4.75 eV to about 5.6 eV, about 4.85 eV to about 5.4 eV, or about 5.0 eV to about 5.2 eV. In some embodiments, the difference in work function between the first metal and the second metal is about 0.25 eV, about 0.3 eV, about 0.35 eV, about 0.4 eV, about 0.45 eV, or about 0.5 eV. In other embodiments, the difference in work function between the first metal and the second metal is greater than 0.25 eV.

[0018] As used herein, "substrate" refers to a surface upon which processing is performed or a portion of a surface. One having ordinary skill in the art will further understand that reference to a substrate can also refer to only that portion of the substrate that is being affected by the process employed so that only a portion of the substrate is physically modified. Further, reference to depositing on a substrate can mean both a bare substrate and a substrate that has one or more films or features deposited or formed thereon. Examples of substrates include a wafer (e.g., a patterned or unpatterned wafer such as a silicon wafer), etc.

[0019] As used herein, a substrate can also refer to any substrate or substrate surface upon which film processing is performed during manufacturing, or any material surface formed on a substrate surface during manufacturing. For example, depending on the application, a substrate surface on which processing can be performed can include materials such as silicon, silicon dioxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, etc., and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers, displays, etc.

[0020] The substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate (or otherwise create or graft a target chemical moiety to impart a chemical functionality), anneal, and / or bake the substrate surface. In addition to layer treatment steps performed directly on the substrate's own surface, in the present disclosure any layer treatment step disclosed can also be performed on an underlayer formed on the substrate, as disclosed in greater detail below, and the term "substrate surface" is intended to include such underlayers as the context indicates.

[0021] Referring now to the drawings, Figure 1 A cross-sectional view of a portion of a memory device 100 including a transistor having a dual gate structure 140 according to embodiments of the present disclosure. The memory device 100 of the present disclosure can be various memory devices, including dynamic random access memory ("DRAM") elements, which include gate all around (GAA) field effect transistors (FETs), such as GAA NWFETs and / or GAA NS FETs. There are two types of GAAFETs: nanowire (NW) FETs, which have the same channel width (W NW) and thickness; and nanosheet (NS) FETs, which have a wider width (W NS) but the channel thickness is fixed at 5 nanometers.

[0022] The memory device 100 includes a substrate 105. The substrate 105 can be made of silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxides, silicon nitride, doped silicon, silicon germanium, and any other materials such as metal, metal nitrides, metal alloys, and other conductive materials.

[0023] The memory device 100 includes a transistor having a dual gate structure 140 formed on the substrate 105. In embodiments, the transistor includes a gate having a dual work function, where the gate has a first work function proximate to a source (e.g., storage node 110 or bit line 115) and a second work function proximate to a drain (e.g., storage node 110 or bit line 115). The transistor having a dual work function (e.g., implemented by configuring the gate to have a first gate metal in a first region and a second gate metal in a second region) reduces or eliminates floating body effects or floating body effect-induced retention degradation of the transistor, such as a GAAFET.

[0024] In some embodiments, the transistor having the dual gate structure 140 is formed on a full bottom dielectric isolation (BDI) layer 137. The full bottom BDI layer 137 can provide improved process control due to full bottom dielectric isolation (FBDI) in the source / drain regions of the transistor. In one embodiment, the full bottom insulating BDI layer 137 includes a high concentration SiGe layer at the bottom of the transistor (e.g., at the bottom of a Si, SiGe nanosheet stack). The dual gate structure 140 of the transistor includes a first gate metal 130 and a second gate metal 135. The first gate metal 130 is proximate to a storage node 110 of the memory device 100, while the second gate metal 135 is proximate to a bit line or capacitor 115 of the memory device 100. In embodiments, the storage node 110 can be a source and can include a source doping, while the bit line 115 can be a drain and can include a drain doping. In another embodiment, the storage node 110 can be a drain and can include a drain doping, while the bit line 115 can be a source and can include a source doping.

[0025] In embodiments, a channel 125a separates the first gate metal 130 from the storage node 110, and a channel 125b separates the second gate metal 135 from the bit line 115. Increasing the length 138 of the channels 125a-b (e.g., the length of the spacers between the storage node and the gate, and between the bit line and the gate) can reduce the floating body effect of the transistor, but at the cost of reducing current. In embodiments, the first gate metal 130 and the second gate metal 135 are formed on, under, and / or around a stack of SiGe and Si alternating layers, referred to as a nanosheet stack 120.

[0026] The transistor includes a spacer (e.g., gate insulator) 139 that separates the nanosheet stack 120 from the first gate metal 130 and the second gate metal 135, such that the first gate metal 130 and the second gate metal 135 are applied in contact with the nanosheet stack 120. The spacer 139 can be a gate insulator or dielectric, such as an oxide or nitride (e.g., Si02or SiN). In one embodiment, the first gate metal 130 has a work function less than 4.55 eV. In some examples, the first gate metal 130 can have a work function of 4.45 eV, 4.35 eV, 4.25 eV, 4.1 eV, 4.0 eV, or another work function less than 4.55 eV. In some examples, the first gate metal 130 can have a work function of about 3.5 eV to about 4.55 eV, about 3.7 eV to about 4.45 eV, about 3.9 eV to about 4.35 eV, or about 4.0 eV to about 4.25 eV. The first gate metal can include at least one of Ta, W, TiN, Ti, or N+polysilicon. In one embodiment, the second gate metal 135 has a work function greater than 4.55 eV. In some examples, the second gate metal 135 can have a work function of 4.65 eV, 4.75 eV, 4.85 eV, 5.0 eV, 5.25 eV, or another work function higher than 4.55 eV. In some examples, the second gate metal 135 can have a work function of about 4.6 eV to about 5.5 eV, about 4.75 eV to about 5.6 eV, about 4.85 eV to about 5.4 eV, or about 5.0 eV to about 5.2 eV. The second gate metal 135 can include at least one of Ni, Co, Pt, Pd, Ru, or Mo. In some embodiments, the work function difference between the first gate metal and the second gate metal is about 0.25 eV, about 0.3 eV, about 0.35 eV, about 0.4 eV, about 0.45 eV, or about 0.5 eV. In other embodiments, the work function difference between the first gate metal and the second gate metal is greater than 0.25 eV. In one embodiment, the first gate metal 130 and the second gate metal 135 are disposed on the spacer 139. The first gate metal 130 can extend over about 50% of the spacer 139 (and about 50% of the nanosheet stack 120 of Si and SiGe alternating layers). In another embodiment, the first gate metal 130 can extend over about 30% to about 65% of the spacer 139 (and about 30% to about 65% of the nanosheet stack 120 of Si and SiGe alternating layers). The second gate metal 135 can extend over the remaining area of the spacer 139 (and the nanosheet stack 120) that does not include the first gate metal 130. In some embodiments, the first gate metal 130 and the second gate metal 135 do not overlap.In other embodiments, the first gate metal 130 overlaps the second gate metal 135 by about 5% to about 15%.

[0027] As noted above, the memory device 100 includes a channel 125a, 125b (e.g., including a nanosheet stack 120, a spacer 139, a first gate metal 130, and a second gate metal 135) on each side of the dual gate structure 140. The channel 125a, 125b can have a length (e.g., a distance between a storage node / bit line and the dual gate structure 140) of about 5 nanometers to about 40 nanometers or about 10 nanometers to about 25 nanometers. The channel 125a, 125b can be doped or undoped. If doped, the channel 125a, 125b can be doped with any Group III or Group V element.

[0028] The memory device 100 can include a storage node 110. In embodiments, the storage node 110 can include doped polysilicon (e.g., with n or p doping), while in other embodiments can include TiN or W. The memory device 100 can also include a bit line 115. The bit line 115 can also be doped polysilicon (e.g., with n or p doping).

[0029] In one embodiment, the first gate metal 130 contacts or is proximate to the storage node 110 through the channel 125a, and the second gate metal 135 contacts or is proximate to the bit line 115 through the channel 125b. It should be appreciated that the gate metal contacting / proximate to the storage node 110 has a lower work function than the gate metal contacting / proximate to the bit line 115.

[0030] In some embodiments, the memory device can be a dynamic random access memory (“DRAM”), which can be a 3D DRAM having a GAA NS FET or a GAA NW FET.

[0031] To simplify the illustration, Figure 1 A 2D structure (e.g., a horizontal transistor) with a gate having a dual work function is shown. However, it should be appreciated that the principles with respect to the 2D architecture are even more beneficially applied to 3D structures (e.g., such as a 3D DRAM including a vertical transistor).

[0032] Figures 2A-2F Various stages in the formation of a memory device including a gate having a dual work function are shown, in accordance with some embodiments.

[0033] In Figure 2AIn some embodiments, a memory device 200 is received that includes a substrate 203 having a stack of a silicon (Si) layer 202 and silicon germanium (SiGe) layers 201a, 201b. The stack of Si and SiGe layers can be patterned into a lattice structure and can be referred to as a nanosheet stack 205. It should be understood that although two SiGe layers and one Si layer are shown in Figure 2A

[0034] In some embodiments, a region of the SiGe layers is removed from the stack and replaced with nitride layers 204a, 204b, respectively, to be used as spacers. In addition, the Si layer 202 can be etched. The etching can be achieved through any method known to one of skill in the art. Figure 2B

[0035] In some embodiments, spacers 206a, 206b are formed on either side of the nanosheet stack, such as the Si layer 202, as shown in Figure 2C Figure 2C The spacers can be an undoped or low doped polysilicon layer.

[0036] In some embodiments, a channel 208 is formed on both sides of the nanosheet stack, such as the Si layer 202. The channel 208 is formed such that there is space for spacers that form an oxide, nitride, or other dielectric, and space for a metal gate (e.g., a dual work function gate having a first metal and a second metal) to be added. After the channel 208 is formed, the spacers can be formed, and as shown in Figure 2D Figure 2E To apply the gate, a first photoresist can be deposited, patterned (e.g., through photolithography), and etched to expose the area where the first metal (Ml) 210 will be deposited. The first metal 210 can then be deposited. The first photoresist can be removed, and a second photoresist can be deposited, patterned, and etched to expose a second area where the second metal (M2) 209 will be deposited. After the second metal 209 is deposited, the second photoresist can be removed.

[0037] ​​​​In some embodiments, the spacer can include a sacrificial layer. In some embodiments, the sacrificial layer can be a polymer layer, a nitride layer, or a silicon layer. In some embodiments, a gate oxide layer can be formed on the spacer of the transistor. The gate oxide can be a dielectric. In one embodiment, a portion of the sacrificial layer can be removed after performing a photolithography process associated with the formation of one of the gate metals. After the sacrificial layer is removed, the first metal can then be applied to the area. The first metal fills the space in the sacrificial layer that was removed. In one embodiment, the first gate metal or the first metal can be applied to the memory device such that it contacts the entire spacer / gate insulator. In one embodiment, the first gate metal / first metal can be applied such that it contacts only a portion of the spacer / gate insulator. For example, the first gate metal / first metal can be applied to about 30% to about 65% of the spacer / gate insulator. After the first metal is applied, a protective layer can be formed. Once the protective layer is formed, the second metal is then applied to the unprotected area. As Figure 2E As can be seen in FIG. 2, the first metal 210 is formed such that it can contact the storage node 207b, and the second metal 209 is formed such that it can contact the bit line 207a.

[0038] The work function of the first metal 210 is less than 4.55 eV, while the work function of the second metal 209 is greater than 4.55 eV. In some instances, the first metal 210 may have a work function of 4.45 eV, 4.35 eV, 4.25 eV, 4.1 eV, 4.0 eV, or another work function less than 4.55 eV. In some instances, the first metal 210 may have a work function of about 3.5 eV to about 4.55 eV, about 3.7 eV to about 4.45 eV, about 3.9 eV to about 4.35 eV, or about 4.0 eV to about 4.25 eV. In some instances, the second metal 209 may have a work function of 4.65 eV, 4.75 eV, 4.85 eV, 5.0 eV, 5.25 eV, or another work function higher than 4.55 eV. In some instances, the second metal 209 may have a work function of about 4.6 eV to about 5.5 eV, about 4.75 eV to about 5.6 eV, about 4.85 eV to about 5.4 eV, or about 5.0 eV to about 5.2 eV. In some embodiments, the work function difference between the first metal 210 and the second metal 209 is about 0.25 eV, about 0.3 eV, about 0.35 eV, about 0.4 eV, about 0.45 eV, or about 0.5 eV. In other embodiments, the work function difference between the first gate metal 210 and the second gate metal 209 is greater than 0.25 eV. The first metal may include at least one of Ta, W, TiN, Ti, or N+ polysilicon, or an alloy having the work function described herein. The second metal 209 may include at least one of Ni, Co, Pt, Pd, Ru, or Mo, or an alloy having the work function described herein.

[0039] exist Figure 2E After forming a dual gate, in Figure 2F A capacitor or storage node 212 is formed at the source node 207b, and a bit line 211 is formed at the drain node / bit line compensation (BLC) 207a.

[0040] Example

[0041] The memory devices disclosed herein will be described through the following examples. It should be understood that these examples are not limiting.

[0042] Example 1: Id-Vg characteristics of single and double gate structures

[0043] Three sample elements were created in a TCAD tool to simulate Id-Vg characteristics for different gate work functions. In the first sample (SI), a single gate structure was fabricated using a single metal. The single metal had a work function of 4.65 eV. In the second sample (S2), a dual gate structure was fabricated using two metals with different work functions. In the second sample (S2), the metal contacting the storage node had a work function of 4.8 eV, while the metal contacting the bit line had a work function of 4.25 eV. In the third sample (S3), a dual gate structure was fabricated using two different metals with different work functions. In the third sample (S3), the metal contacting the storage node had a work function of 4.25 eV, while the metal contacting the bit line had a work function of 4.8 eV. As can be seen in Figure 3 Figure 3, the third sample (S3), i.e. the dual gate with high work function on the bit line side, resulted in the lowest Ioff current (current when the transistor is turned off) and higher Ion current (e.g. current when the transistor is turned on). The results of this test are shown in Table 1 below.

[0044] Table 1

[0045] Sample ]]> ​ Ion current (A) ]]> ​ Ioff current (A) ]]> ​ Threshold voltage (V) ]]> ​ First sample: single gate (SI) 6.48e-5 9.80e-14 0.41 Second sample: double gate (S2) 6.28e-5 3.53e-13 0.49 Third sample: double gate (S3) 6.38e-5 1.69e-15 0.53

[0046] The remaining parameters of the samples are shown in Table 2. Note that the parameters were kept constant in the three samples, with only the work function varying in the gate structures described above.

[0047] Table 2

[0048] Parameter Value Channel length 70 nm Oxide thickness 3.5 nm Channel thickness 20 nm Channel width 50 nm Channel doping 1e15 cm"3 Source / drain extension length 30 nm Source doping 1e20 cm"3 Drain doping 5e19 cm"3 Source / drain length 60 nm Gate metal overlap 10 nm

[0049] Example 2: Effect of gate on dynamic retention time

[0050] Another test was performed on the three samples described in Embodiment 1 to investigate the storage node voltage for various gates with different bit line voltage pulses. The results of this test can be seen in Figure 4 . As can be seen in Figure 4 , the third sample with a dual gate structure with higher work function on the bit line side did not experience floating gate induced storage node reduction, as the storage node voltage remained constant over the measurement time. In contrast, the storage node voltage for the first sample (single gate) and the second sample (dual gate with low work function on the bit line side) started to decrease around the 20e-3 time point and steadily decreased over time, indicating the presence of floating body effects.

[0051] The foregoing description sets forth numerous specific details, such as examples of specific systems, components, methods and so forth, in order to provide a thorough understanding of several embodiments of the present disclosure. However, it will be apparent to one skilled in the art that at least some embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram format in order to avoid unnecessarily obscuring the present disclosure. Thus, the specific details set forth are merely exemplary. Particular implementations can vary from these exemplary details and still be contemplated to be within the scope of the present disclosure.

[0052] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless specified otherwise, or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; or if X employs B; or if X employs both A and B, then "X employs A or B" is satisfied. Moreover, the term "a" or "an" is intended to mean "one or more" unless specified otherwise.

[0053] Although the operations of the methods herein are shown and described in a particular order, the order of the operations can be altered so that certain operations are performed in an inverse order or so that certain operations are performed, at least partially, concurrently with other operations. In another embodiment, instructions or sub-operations of distinct operations can be in an intermittent and / or alternating manner.

[0054] It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A memory device, comprising: at least one transistor having a dual gate structure including a first gate metal and a second gate metal, wherein the first gate metal has a first work function and the second gate metal has a second work function higher than the first work function.

2. The memory device of claim 1, wherein the first work function is less than 4.55 eV and the second work function is greater than 4.55 eV.

3. The memory device of claim 1, wherein the first gate metal includes at least one of tantalum (Ta), tungsten (W), titanium nitride (TiN), titanium (Ti), or N+ polysilicon, and wherein the second gate metal includes at least one of nickel (Ni), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), or molybdenum (Mo).

4. The memory device of claim 1, further comprising a bit line contacting or proximate to the second gate metal and a storage node contacting or proximate to the first gate metal.

5. The memory device of claim 1, wherein the first gate metal and the second gate metal are disposed on a spacer, wherein the first gate metal extends over about 50% of the spacer, and wherein the second gate metal extends over a remaining area of the spacer.

6. The memory device of claim 5, wherein the first gate metal and the second gate metal do not overlap.

7. The memory device of claim 5, wherein the first gate metal and the second gate metal overlap by about 10% to about 20%.

8. The memory device of claim 5, further comprising a channel on each side of the spacer, wherein the channel has a thickness of about 5 nanometers to about 40 nanometers.

9. The memory device of claim 1, wherein the memory device is a dynamic random access memory (DRAM).

10. The memory device of claim 1, further comprising: a support including a plurality of silicon (Si) and silicon germanium (SiGe) alternating layers; and at least one nitride layer.

11. A method of fabricating a memory device, comprising: forming a first gate on a first portion of a gate oxide using a first metal, wherein the first metal has a work function less than 4.55 eV; and forming a second gate on a second portion of the gate oxide using a second metal, wherein the second metal has a work function greater than 4.55 eV.

12. The method of claim 11, wherein the first metal includes at least one of tantalum (Ta), tungsten (W), titanium nitride (TiN), titanium (Ti), or N+ polysilicon.

13. The method of claim 11, wherein the second metal includes at least one of nickel (Ni), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), or molybdenum (Mo).

14. The method of claim 11, further comprising: forming a bit line contacting or proximate to the second metal, and forming a storage node contacting or proximate to the first metal.

15. The method of claim 11, further comprising: forming the first gate and the second gate over the spacers.

16. The method of claim 15, wherein the first gate extends over about 50% of the spacer, and wherein the second gate extends over the remaining area of the spacer.

17. The method of claim 15, further comprising: forming a channel on each side of the spacer.

18. The method of claim 17, wherein the channel has a thickness of about 5 nanometers to about 40 nanometers.

19. The method of claim 11, wherein the memory device is a DRAM.

20. The method of claim 11, wherein the gate oxide comprises a dielectric layer.

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