Silicon carbide semiconductor device

Abstract

In a SiC semiconductor device in which a semiconductor element having a trench gate structure is formed, a JFET layer (14) of a first conductivity type and a first deep layer (15) of a second conductivity type are formed in a cell region (1). An outer peripheral end position (Po), which is an end position on the outer peripheral side of the cell region in the JFET layer, is closer to the cell region side than an inner peripheral end position (Pi), which is an end position on the cell region side in the gate wiring (26).

Description

Cross Reference to Related Applications

[0001] This application is based on Japanese Patent Application No. 2023-072621 filed on April 26, 2023, the content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to a silicon carbide (hereinafter, also referred to as SiC) semiconductor device having a trench gate structure. BACKGROUND

[0003] In the SiC semiconductor device of the MOSFET having the trench gate structure, the gate insulating film is extended to the outer periphery of the cell region in which the MOSFET is formed, and a field oxide film is disposed thereon. Also, the gate electrode of the MOSFET possessed by the cell region is extended to the gate insulating film or the field insulating film disposed to the outer periphery of the cell region, and is connected to the gate wiring.

[0004] In the SiC semiconductor device thus configured, the thin insulating film such as the gate insulating film is easily broken due to the displacement current flowing at the time of high-speed switching. Therefore, in Patent Literature 1, the distance from the source contact portion of the cell region to the step portion which becomes the boundary portion of the gate insulating film and the field insulating film is set to be short, so that the distance of the current path is shortened. Thereby, the current path resistance is reduced, the breakage of the gate insulating film due to the displacement current is suppressed, and the switching endurance is improved.

[0005] PRIOR ART DOCUMENTS PATENT LITERATURE Patent Literature 1: Japanese Patent Application Publication No. 2015-057850 SUMMARY

[0006] However, in the configuration of Patent Literature 1, in the case where the endurance of the SiC semiconductor device is limited at a portion other than the step portion of the field oxide film, even in the configuration of Patent Literature 1, the effect of reducing the current path resistance cannot be obtained, and the switching endurance cannot be improved.

[0007] An object of the present disclosure is to provide a SiC semiconductor device capable of improving the switching endurance regardless of the limited portion of the endurance.

[0008] One aspect of the present disclosure is a SiC semiconductor device having: a cell region in which a semiconductor element of a trench gate structure is formed; and a peripheral region provided with a peripheral withstand voltage structure portion constituting a peripheral withstand voltage structure at a periphery of the cell region, and a connection portion between the peripheral withstand voltage structure portion and the cell region, the SiC semiconductor device being characterized by having: a substrate composed of SiC of a first conductivity type or a second conductivity type; and a first impurity region of the first conductivity type formed on a surface of the substrate and having a lower impurity concentration than that of the substrate. The cell region is provided with a semiconductor element having: a JFET layer composed of SiC of the first conductivity type formed in a surface layer portion of the first impurity region and having a higher impurity concentration than that of the first impurity region; a deep layer composed of SiC of the second conductivity type formed in the surface layer portion of the first impurity region and alternately arranged with the JFET layer in a surface direction of the substrate; a base layer composed of SiC of the second conductivity type formed on the JFET layer and the deep layer; a trench gate structure having a gate insulating film formed on inner wall surfaces of a plurality of gate trenches arranged in a one direction as a length direction deeper than the base layer, and a gate electrode formed on the gate insulating film in the gate trenches; a second impurity region composed of SiC of the first conductivity type formed in a surface layer portion of the base layer in contact with the trench gate structure and having a higher impurity concentration than that of the first impurity region; a first electrode electrically connected to the second impurity region and the base layer; and a second electrode arranged on a back surface side of the substrate and electrically connected to the substrate. The connection portion is provided with: the gate insulating film formed on the first impurity region by being extended from the cell region; the gate electrode arranged on the gate insulating film by being extended from the cell region; and a gate wiring connected to the gate electrode. An outer peripheral end position of the cell region in the JFET layer is closer to the cell region side than an inner peripheral end position of the cell region in the gate wiring.

[0009] Thus, in particular, below the gate wiring, an electric field applied to the gate insulating film is likely to become large, but in this portion, the JFET layer is not formed, and the outer peripheral end position of the JFET layer is closer to the cell region side than the inner peripheral end position of the gate wiring. Since this configuration is provided, the impurity concentrations of the p-type layer and the n-type layer constituting the pn junction become small, and a displacement current generated at the time of a voltage surge at the time of switching can be reduced. Therefore, electric field concentration caused by the displacement current is mitigated, and breakdown of the gate insulating film can be suppressed, and the switching endurance can be improved. Moreover, this effect can be obtained regardless of the position of the endurance limitation. Therefore, the SiC semiconductor device in which the switching endurance can be improved regardless of the position of the endurance limitation can be obtained.

[0010] In a second aspect of the present disclosure, the JFET layer is formed only in the cell region side in the cell region and the connection portion.

[0011] Thus, a configuration is made in which the JFET layer is formed on the side of the cell region in the cell region and the connecting portion, but not on the outside thereof. Therefore, the pn junction of the portion on the outer edge side in the connecting portion is constituted by the low concentration layer and the deep layer. Thus, the effect of the first viewpoint can be obtained.

[0012] In the third viewpoint of the present disclosure, the JFET layer is also formed in the connecting portion, and the first conductivity type impurity concentration of the portion of the JFET layer that is more on the outside than the end position on the cell region side in the gate wiring, that is, the inner periphery end position, is lower than the first conductivity type impurity concentration of the first impurity region.

[0013] Even if the JFET layer is formed in the connecting portion, if the first conductivity type impurity concentration is lowered at a position that is more on the outside than the inner periphery end position of the gate wiring, the impurity concentrations of the p-type layer and the n-type layer that constitute the pn junction in the outer periphery region become low. Thus, the time variation amount dV / dt becomes small, and the displacement current can be reduced, and thus the switching endurance can be improved, and a SiC semiconductor device in which the switching endurance can be improved regardless of the position of the endurance limitation can be made.

[0014] Further, the bracketed reference numerals attached to each constituent element and the like indicate an example of the correspondence relationship of the constituent element and the like to the specific constituent element and the like described in the embodiments described later. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a plan view of the SiC semiconductor device of the first embodiment.

[0016] Figure 2 is a perspective cross-sectional view when the region RA in Figure 1 is viewed from the II direction.

[0017] Figure 3 is a cross-sectional view along the III-III line in Figure 1 .

[0018] Figure 4 is a cross-sectional view along the IV-IV line in Figure 1 .

[0019] Figure 5 is a cross-sectional view that explains the displacement current generated in the outer periphery region.

[0020] Figure 6A is a cross-sectional view that shows the manufacturing process of the SiC semiconductor device of the first embodiment.

[0021] Figure 6B is a cross-sectional view that shows the manufacturing process of Figure 6A next.

[0022] Figure 6C is a cross-sectional view that shows the manufacturing process of Figure 6BA cross-sectional view of the manufacturing process.

[0023] Figure 6D It means to continue Figure 6C A cross-sectional view of the manufacturing process.

[0024] Figure 6E It means to continue Figure 6D A cross-sectional view of the manufacturing process.

[0025] Figure 7 This is a cross-sectional view of the SiC semiconductor device according to the second embodiment.

[0026] Figure 8A This is a cross-sectional view showing the manufacturing process of the SiC semiconductor device according to the second embodiment.

[0027] Figure 8B It means to continue Figure 8A A cross-sectional view of the manufacturing process.

[0028] Figure 8C It means to continue Figure 8B A cross-sectional view of the manufacturing process.

[0029] Figure 8D It means to continue Figure 8C A cross-sectional view of the manufacturing process.

[0030] Figure 8E It means to continue Figure 8D A cross-sectional view of the manufacturing process. Detailed Implementation

[0031] Hereinafter, embodiments of the present invention will be described based on the accompanying drawings. Furthermore, in the following embodiments, the same or equivalent parts will be described using the same reference numerals.

[0032] (First Implementation) The first embodiment will be described with reference to the accompanying drawings. Figure 1 As shown, the SiC semiconductor device of this embodiment is configured to have a cell region 1 that serves as an active region for performing element operation and an outer peripheral region 2 surrounding the cell region 1.

[0033] In addition, Figure 1 Below the cell region 1 in the SiC semiconductor device, various pads 3 are formed for controlling the components provided in the cell region 1, for temperature detection, etc.

[0034] like Figure 2As shown, the outer peripheral region 2 is configured to have a guard ring portion 2a, which corresponds to an outer peripheral pressure-resistant structure portion configured with an outer peripheral pressure-resistant structure, and a connecting portion 2b disposed at a position inward of the guard ring portion 2a. In other words, the outer peripheral region 2 is configured to have the guard ring portion 2a and the connecting portion 2b disposed between the cell region 1 and the guard ring portion 2a.

[0035] Hereinafter, the description will be made with reference to Figures 2-4 A SiC semiconductor device of a vertical MOSFET having an n-channel provided in a semiconductor element of a trench gate structure in the cell region 1 will be described. Hereinafter, one direction in a surface direction of the semiconductor substrate 10 described later will be referred to as an X-axis direction, a direction intersecting the one direction in the surface direction of the semiconductor substrate 10 will be referred to as a Y-axis direction, and a direction intersecting the X-axis direction and the Y-axis direction will be referred to as a Z-axis direction. Here, the X-axis direction, the Y-axis direction, and the Z-axis direction will be referred to as mutually orthogonal axes. In addition, the Z-axis direction in the present embodiment corresponds to a thickness direction of the semiconductor substrate 10 described later, and also corresponds to a stacking direction of the substrate 11 and the low-concentration layer 13 described later. The Y-axis direction is, for example, a <11-20> direction.

[0036] The SiC semiconductor device is configured using a semiconductor substrate 10 of an element in which a vertical MOSFET is formed. The semiconductor substrate 10 is configured by forming various semiconductor layers composed of SiC on an n + -type substrate 11 composed of SiC. In the present embodiment, as the substrate 11, for example, a substrate having a misalignment angle of 0 to 8° with respect to a (0001) Si surface, an n-type impurity concentration of 1.0 x 10 19 / cm 3 , and a thickness of about 300 μm is used. In the case of the vertical MOSFET, the substrate 11 constitutes a drain region.

[0037] An n-type buffer layer 12 composed of SiC is formed on a surface of the substrate 11 as needed. The buffer layer 12 is configured by epitaxial growth on the surface of the substrate 11. Further, the n-type impurity concentration of the buffer layer 12 is a concentration between the substrate 11 and a low-concentration layer 13 described later, and the thickness is about 1 μm.

[0038] On a surface of the buffer layer 12, for example, an n 15 -type layer composed of SiC having an n-type impurity concentration of 5.0 x 10 16 ~2.0 x 10 3 / cm -The low-concentration layer 13 is of a low-concentration type. The impurity concentration of the low-concentration layer 13 can be constant in the Z-axis direction, but preferably the concentration distribution has a tilt, with the concentration on the substrate 11 side being higher than the concentration away from the substrate 11 in the low-concentration layer 13. In addition, in the present embodiment, the low-concentration layer 13 corresponds to the first impurity region.

[0039] In the surface layer portion of the low-concentration layer 13 in the cell region 1, a JFET (Junction Field-Effect Transistor) layer 14 and a first deep layer 15 are formed. In the present embodiment, the JFET layer 14 and the first deep layer 15 each have linear portions arranged extending along the X-axis direction and arranged in an alternating pattern in the Y-axis direction. That is, the JFET layer 14 and the first deep layer 15 are each arranged in a stripe shape extending along the X-axis direction when viewed in the normal direction to the surface of the substrate 11 (hereinafter, also simply referred to as the normal direction), and have an arrangement in which the linear portions are arranged in an alternating pattern in the Y-axis direction. Further, the JFET layer 14 and the first deep layer 15 can also be said to be viewed from the normal direction to the surface of the substrate 11, in other words, when viewed from the normal direction to the surface of the substrate 11. In addition, the normal direction to the surface of the substrate 11 is also the direction along the stacking direction of the drift layer 17 and the base layer 18 described later, and is the direction along the Z-axis direction.

[0040] The JFET layer 14 is of an n-type with a higher impurity concentration than the low-concentration layer 13, and has a thickness of 0.3 μm to 1.5 μm. In the present embodiment, the n-type impurity concentration of the JFET layer 14 is 5.0 x 1018 / cm3 to 1.0 x 1020 / cm3. The JFET layer 14 is formed by ion implantation of an n-type impurity into the low-concentration layer 13. 16 ~1.0×10 17 / cm 3 The first deep layer 15 has a p-type impurity concentration of about 2.0 x 1018 / cm3 to 2.0 x 1020 / cm3. 17 18 / cm 3

[0041] Further, the first deep layer 15 can have the same depth as the JFET layer 14, or can be deeper or shallower than the JFET layer 14, but in the present embodiment, the first deep layer 15 is formed shallower than the JFET layer 14. That is, the first deep layer 15 is formed such that the bottom portion thereof is located within the JFET layer 14. In other words, the first deep layer 15 is formed such that the JFET layer 14 is located between the first deep layer 15 and the low-concentration layer 13. Thereby, the extension of the depletion layer into the JFET layer 14 between the first deep layer 15 is suppressed, and thus the on-resistance is reduced. In addition, such a JFET layer 14 and first deep layer 15 are formed by appropriately ion implanting an impurity into the surface layer portion of the low-concentration layer 13.

[0042] ​​On the other hand, the surface portion of the low-concentration layer 13 in the protective ring portion 2a in the outer peripheral region 2, as an outer peripheral pressure-resistant structure, is provided with multiple p-shaped protective rings 16 in a manner that surrounds the unit region 1. In this embodiment, the upper surface layout of the protective rings 16 is set to a quadrilateral shape or a circular shape, etc., with rounded corners when viewed in the normal direction.

[0043] Furthermore, the surface portion of the low-concentration layer 13 in the connecting portion 2b of the outer peripheral region 2 includes a p-type connecting layer 15a. The inner edge of the connecting layer 15a is configured to surround the unit region 1, and the outer edge of the connecting layer 15a is configured to the boundary position with the protective ring portion 2a. The connecting layer 15a is formed by extending a first deep layer 15 into the connecting portion 2b, and has the same depth and the same p-type impurity concentration as the first deep layer 15.

[0044] Furthermore, a JFET layer 14 is formed in a portion of the connecting portion 2b in the outer peripheral region 2, specifically on the cell region 1 side of the connecting portion 2b, but not on its outer side. Therefore, at a position where the JFET layer 14 is formed deeper than the first deep layer 15, the JFET layer 14 exists below the cell region 1 side of the connecting layer 15a, but not on the outer edge side of the connecting portion 2b, on the guard ring portion 2a side.

[0045] In addition, a base layer 18, a source region 19, a contact region 20, etc. are formed on the JFET layer 14 and the first deep layer 15 in the cell region 1.

[0046] The base layer 18 is p-type and is formed on the JFET layer 14 and the first deep layer 15. Therefore, the first deep layer 15 is connected to the base layer 18. The base layer 18 has, for example, a p-type impurity concentration of 5.0 × 10⁻⁶. 16 ~2.0×10 19 / cm 3 The thickness is approximately 2.0 μm.

[0047] Source region 19 is n + The type is formed on the surface of the base layer 18. The contact region 20 is p + The n-type impurity is formed on the surface portion of the base layer 18. Specifically, the source region 19 is formed to be in contact with the side of the trench 21 (described later), and the contact region 20 is formed on the opposite side of the trench 21, across the source region 19. In this embodiment, the n-type impurity concentration, i.e., the surface concentration, in the surface portion of the source region 19 is, for example, 1.0 × 10⁻⁶. 18 / cm 3 The thickness is approximately 0.3 μm. The p-type impurity concentration, or surface concentration, of the surface layer in the contact region 20 is, for example, 1.0 × 10⁻⁶. 21 / cm3 The thickness of the low concentration layer 13 is about 0.3 μm. In addition, in the present embodiment, the source region 19 corresponds to the second impurity region.

[0048] The base layer 18, the contact region 20, and the surface layer portion of the low concentration layer 13 are formed on the low concentration layer 13, the JFET layer 14, the first deep layer 15, and the connection layer 15a in the connection portion 2b in the outer peripheral region 2. On the inner edge side in the connection portion 2b, the base layer 18 and the contact region 20 are formed on the connection layer 15a and are provided so as to extend from the cell region 1. In addition, on the outer edge side in the connection portion 2b, the base layer 18 and the contact region 20 are not formed, and the surface layer portion of the low concentration layer 13 is formed. That is, in the present embodiment, the base layer 18 and the contact region 20 in the outer peripheral region 2 are formed so as to extend from the cell region 1 to the middle of the connection portion 2b, and are not formed in the connection portion 2b and the guard ring portion 2a further outward than the middle. Further, from the boundary position between the cell region 1 and the outer peripheral region 2 to the middle of the connection portion 2b, the entire surface of the surface layer of the connection portion 2b is the contact region 20, and further outward than the middle, the entire surface of the surface layer of the connection portion 2b and the guard ring portion 2a is the low concentration layer 13.

[0049] In the present embodiment, as described above, the semiconductor substrate 10 includes the substrate 11, the buffer layer 12, the low concentration layer 13, the JFET layer 14, the first deep layer 15, the base layer 18, the source region 19, the contact region 20, and the like. Further, since each layer constituting the semiconductor substrate 10 is composed of SiC, it can be said that the semiconductor substrate 10 is composed of SiC. In addition, in the present embodiment, on the inner edge side in the cell region 1 and the connection portion 2b, one face 10a of the semiconductor substrate 10 is composed of the source region 19, the contact region 20, and the like, and the other face 10b of the semiconductor substrate 10 is composed of the substrate 11.

[0050] In addition, the JFET layer 14, the first deep layer 15, the connection layer 15a, the guard ring 16, the base layer 18, the source region 19, and the contact region 20 are composed of ion-implanted layers formed by ion implantation in the present embodiment.

[0051] Further, in the cell region 1, a trench 21 is formed in the semiconductor substrate 10, the trench 21 penetrating the source region 19, the base layer 18, and the like and reaching the JFET layer 14 and the first deep layer 15 from the first face 10a side. The trench 21 corresponds to a gate trench and is provided so as to have a depth in which the bottom surface is located inside the JFET layer 14 and the first deep layer 15, and a width of, for example, 0.4 to 0.8 μm.

[0052] In addition, the trench 21 is provided so as to extend in multiple pieces in a manner of extending along the Y-axis direction, and as described above, the trench 21 is provided so as to extend in a manner of extending along the Y-axis direction in the cell region 1 and the outer peripheral region 2. Figure 3As shown, the trenches 21 are formed so as to be arranged at equal intervals in the X-axis direction every interval B1, thereby becoming stripe-shaped. That is, in the present embodiment, the trenches 21 are formed so that the length direction thereof is perpendicular to the length direction of the first deep layer 15.

[0053] At the bottom of the trench 21, a second deep layer 30 that becomes an electric field relaxation layer is formed so as to be in contact with the bottom surface of the trench 21. In the present embodiment, the second deep layer 30 is composed of a p-type layer having a lower impurity concentration than the first deep layer 15. Specifically, the second deep layer 30 is formed along the length direction of the trench 21. That is, the second deep layer 30 is provided so as to extend along the Y-axis direction that intersects the first deep layer 15. Further, the second deep layer 30 of the present embodiment is formed so as to penetrate the JFET layer 14 and the first deep layer 15, thereby having a bottom surface that reaches the low-concentration layer 13.

[0054] By forming the second deep layer 30 along the bottom surface of the trench 21, it is possible to suppress the entry of an electric field into the gate insulating film 22 located at the bottom of the trench 21, and it is possible to suppress the breakdown of the oxide film. Further, by forming the second deep layer 30 so as to be in contact with the bottom surface of the trench 21, it is possible to reduce the electrostatic capacitance, that is, the feedback capacitance, between the gate electrode 23 and the lower electrode 28, and it is possible to improve the switching speed. Further, since the second deep layer 30 is formed so as to penetrate the JFET layer 14 and the first deep layer 15, thereby having a bottom surface that reaches the low-concentration layer 13, the climbing of an electric field into the JFET layer 14 disposed between the second deep layers 30 is suppressed, and it is possible to improve the withstand voltage. Further, when an overvoltage is applied, the breakdown is likely to occur in the second deep layer 30 that protrudes downward, and thus the breakdown is likely to occur in the cell region 1, and it is possible to improve the avalanche withstand amount.

[0055] Further, the second deep layer 30 can also be formed so as to be cut into a plurality of pieces along the Y-axis direction. However, the second deep layer 30 is formed so as to be electrically connected to the base layer 18 via the first deep layer 15.

[0056] Further, the gate insulating film 22 is formed on the one surface 10a of the semiconductor substrate 10 other than the inner wall surface of the trench 21. Also, in the cell region 1, a contact hole 22a is formed in the gate insulating film 22, so as to expose the source region 19 and the contact region 20.

[0057] The gate insulating film 22 is formed on the one surface 10a of the semiconductor substrate 10 other than the inner wall surface of the trench 21. Also, in the cell region 1, a contact hole 22a is formed in the gate insulating film 22, so as to expose the source region 19 and the contact region 20.

[0058] On the one face 10a of the semiconductor substrate 10, a field oxide film 241 is formed so as to surround the outer edge of the cell region 1, and further, an interlayer insulating film 242 is formed so as to cover the gate electrode 23, the gate insulating film 22, the field oxide film 241, and the like. The interlayer insulating film 242 is composed of BPSG (an acronym of Boro phospho silicate Glass) or the like. Further, on the interlayer insulating film 242, a contact hole 242a is formed so as to expose the source region 19 and the contact region 20 in the cell region 1 in communication with the contact hole 22a. Further, on the interlayer insulating film 242, a contact hole 242b is formed so as to expose a portion of the gate electrode 23 extending to the connecting portion 2b. Figure 2 In the present embodiment, the field oxide film 241 and the interlayer insulating film 242 on the side above the one face 10a of the semiconductor substrate 10 are omitted.

[0059] As shown in FIG. 2, on the interlayer insulating film 242, an upper electrode 25 is formed so as to be electrically connected to the source region 19 and the contact region 20 through the contact hole 22a and the contact hole 242a. The upper electrode 25 is capable of electrical connection to the outside. In the present embodiment, the upper electrode 25 corresponds to the first electrode. Further, on the interlayer insulating film 242, a gate wiring 26 is formed so as to be electrically connected to the gate electrode 23 through the contact hole 242b. The gate wiring 26 is not shown in FIG. 2, but is formed along the outer edge portion of the cell region 1, for example, along each side of the right side and the left side and the lower side in the SiC semiconductor device shown in FIG. 1. Figure 3 Figure 4

[0060] On the interlayer insulating film 242, the upper electrode 25 is formed so as to be electrically connected to the source region 19 and the contact region 20 through the contact hole 22a and the contact hole 242a. The upper electrode 25 is capable of electrical connection to the outside. In the present embodiment, the upper electrode 25 corresponds to the first electrode. Further, on the interlayer insulating film 242, a gate wiring 26 is formed so as to be electrically connected to the gate electrode 23 through the contact hole 242b. The gate wiring 26 is not shown in FIG. 2, but is formed along the outer edge portion of the cell region 1, for example, along each side of the right side and the left side and the lower side in the SiC semiconductor device shown in FIG. 1. Figure 1 Figure 1

[0061] As described above, the JFET layer 14 is formed only in the cell region 1 and the cell region 1 side in the connecting portion 2b, but is not disposed below the gate wiring 26. That is, as shown in FIG. 2, the outer peripheral end position Po of the JFET layer 14 on the outer peripheral side of the cell region 1 is on the cell region 1 side more than the inner peripheral end position Pi of the gate wiring 26 on the cell region 1 side. Further, on the outer side of the inner peripheral end position Pi, the connecting layer 15a is formed, or the low concentration layer 13 is formed. Figure 4

[0062] ​​​​​In this embodiment, the upper electrode 25 is made of various metals, such as Ni / Al. Furthermore, the portion of the various metals that contacts the portion constituting the n-type SiC, i.e., the source region 19, is made of a metal capable of ohmic contact with the n-type SiC. Additionally, at least the portion of the various metals that contacts the p-type SiC, i.e., the contact region 20, is made of a metal capable of ohmic contact with the p-type SiC. Moreover, the gate wiring 26 can have the same structure as the upper electrode 25, and can also be made of Al-Si or the like.

[0063] Furthermore, a protective film 27 made of polyimide or the like is formed to cover the connecting portion 2b and the protective ring portion 2a. In this embodiment, in order to suppress surface discharge between the upper electrode 25 and the lower electrode 28 (described later), the protective film 27 is formed from the outer peripheral region 2 to the outer edge of the unit region 1. Specifically, the protective film 27 is formed such that it covers the portion of the upper electrode 25 on the outer peripheral region 2 side in the unit region 1, while exposing the portion of the upper electrode 25 on the inner edge side.

[0064] On the other side 10b of the semiconductor substrate 10, a lower electrode 28 electrically connected to the substrate 11 is formed. Furthermore, in this embodiment, the lower electrode 28 corresponds to a second electrode.

[0065] In the SiC semiconductor device of this embodiment, a MOSFET with a trench gate structure that is an inverted n-channel type is formed by such a structure.

[0066] The above describes the configuration of the SiC semiconductor device in this embodiment. Furthermore, in this embodiment, n - Type, n-type, n + p-type is equivalent to the first conductivity type, p-type, p-type + This type corresponds to the second conductivity type. Next, the operation of the SiC semiconductor device will be explained.

[0067] First, in the off state before a gate voltage is applied to the gate electrode 23, the SiC semiconductor device does not form an inversion layer in the base layer 18. Therefore, even if a positive voltage, such as 1600V, is applied to the lower electrode 28, electrons will not flow from the source region 19 into the base layer 18, and no current will flow between the upper electrode 25 and the lower electrode 28.

[0068] Furthermore, when an electric field is applied between the drain and gate before the gate voltage is applied to the gate electrode 23, an electric field concentration occurs at the bottom of the gate insulating film 22. However, in the SiC semiconductor device, the first deep layer 15 and the JFET layer 14 are located at a depth greater than the trench 21. Therefore, due to the depletion layer formed between the first deep layer 15 and the JFET layer 14, the rise in the equipotential line caused by the drain voltage is suppressed, making it difficult for a high electric field to penetrate the gate insulating film 22. In addition, since a second deep layer 30, which serves as an electric field mitigation layer, is provided at the bottom of the trench 21, it is difficult for a high electric field to penetrate the gate insulating film 22. Therefore, in this embodiment, damage to the gate insulating film 22 can be suppressed.

[0069] Furthermore, if a predetermined gate voltage is applied to the gate electrode 23, a channel is formed on the surface of the base layer 18 that is in contact with the trench 21. Therefore, electrons injected from the upper electrode 25 pass through the channel formed in the base layer 18 from the source region 19, flow through the JFET layer 14 to the low-density layer 13, and then flow to the lower electrode 28 through the substrate 11, which serves as the drain layer. As a result, current flows between the upper electrode 25 and the lower electrode 28, and the SiC semiconductor device becomes conductive. In this embodiment, electrons passing through the channel flow to the substrate 11 through the JFET layer 14 and the low-density layer 13, thus forming a drift layer 17 having the JFET layer 14 and the low-density layer 13.

[0070] Here, as described above, the JFET layer 14 is disposed only on the cell region 1 side of cell region 1 and the connecting portion 2b, and not disposed in a position further outward. By configuring it in this way, the switching tolerance when the vertical MOSFET is turned on and off based on the application of the gate voltage can be improved. The switching tolerance will be explained below.

[0071] Figure 5 This presents a comparative example of a scenario where the JFET layer 14 is formed not only in the cell region 1 but also in the interconnection portion 2b, etc. Figure 5 This indicates the displacement current A1 in the cross section of a SiC semiconductor device that cuts off the adjacent trench gate structures from each other, i.e., at a location that is not a trench gate structure. It refers to the displacement current A1 in the cross section that cuts off the SiC semiconductor device along the Y direction, which is the length direction of the trench gate structure.

[0072] When performing high-speed switching on a vertical MOSFET, such as Figure 5The displacement current A1 flows as shown by the dashed arrow in the diagram. That is, in the outer peripheral region 2, it flows from the lower electrode 28 through the substrate 11, the low-concentration layer 13, and the JFET layer 14 into the interconnecting layer 15a. From there to the base layer 18 and the contact region 20, the displacement current A1 flows upward to the upper electrode 25 while moving along the surface direction of the semiconductor substrate 10 within the contact region 20. The displacement current A1 at this time is proportional to the time change dV / dt of the high voltage generated during switching. Furthermore, the higher the impurity concentration of the p-type and n-type layers constituting the pn junction in the outer peripheral region 2, the larger the source-drain capacitance, and therefore the larger the time change dV / dt, and the larger the displacement current A1. Figure 5 In the comparative example shown, where a JFET layer 14 is formed at the interconnect 2b, the pn junction is composed of the JFET layer 14 and the interconnect layer 15a, resulting in a higher impurity concentration. Therefore, if the displacement current A1 increases, causing electric field concentration, the thin gate insulating film 22 is damaged, and switching capability cannot be achieved. Specifically, insulation breakdown occurs at the boundary RB between the gate insulating film 22 and the field oxide film 241, as shown in the figure.

[0073] If, as in this embodiment, at least the outer edge of the connecting portion 2b is not provided with the JFET layer 14, the pn junction in that portion is composed of a low-concentration layer 13 and a first deep layer 15. Due to this configuration, in this embodiment, compared to the comparative example, the impurity concentrations of the p-type and n-type layers constituting the pn junction are reduced, which can decrease the displacement current A1 generated during voltage surges during switching. Therefore, the electric field concentration caused by the displacement current A1 is mitigated, which can suppress damage to the gate insulating film 22 and improve switching withstand capability.

[0074] In particular, the electric field applied to the gate insulating film 22 tends to increase below the gate wiring 26. Therefore, a JFET layer 14 is not formed below the gate wiring 26, and the outer end position Po of the JFET layer 14, which is the end position of the outer periphery of the cell region 1, is closer to the cell region 1 than the inner end position Pi of the gate wiring 26. With this configuration, damage to the gate insulating film 22 can be further suppressed, and the switching withstand capability can be improved.

[0075] Next, refer to Figures 6A-6E The manufacturing method of the SiC semiconductor device according to this embodiment will be described. Furthermore, Figures 6A-6E It means equivalent to Figure 4 The manufacturing process of the cross-section of unit region 1 and connecting part 2b.

[0076] First, such as Figure 6AAs shown, after preparing the substrate 11, a buffer layer 12 and a low-concentration layer 13 are epitaxially grown on one side of the substrate 11. Then, after placing a mask with a partial opening (not shown) corresponding to the JFET layer 14 on the surface of the low-concentration layer 13, n-type impurities are implanted to form the JFET layer 14.

[0077] Subsequently, after re-forming a mask with partial openings corresponding to the first depth layer 15, p-type impurities are implanted with ions, such as... Figure 6B The first deep layer 15 is formed as shown. At this time, the JFET layer 14 is formed to the portion that becomes the first deep layer 15, but the first deep layer 15 can be formed by backflushing to p-type by increasing the dose of p-type impurities. In addition, after forming a mask (not shown) with a partial opening corresponding to the base layer 18, p-type impurities are implanted to form the base layer 18. Furthermore, p-type impurities are further implanted using a mask with a partial opening corresponding to the contact region 20 to form the contact region 20 on the base layer 18.

[0078] Subsequently, after forming a mask (not shown) with a partial opening corresponding to source region 19, n-type impurities are implanted, such as... Figure 6C The source region 19 is formed as shown. At this time, the contact region 20 is formed to become part of the source region 19, but the source region 19 can be formed by backflushing to n-type by increasing the dose of n-type impurities.

[0079] Next, as Figure 6D As shown, after configuring a mask 50 with a partial opening corresponding to the trench 21, the trench 21 is formed by dry etching. Furthermore, using the same mask 50, p-type impurities are ion implanted to form a second deep layer 30 at the bottom of the trench 21.

[0080] Next, as Figure 6E As shown, after forming the gate insulating film 22 by thermal oxidation or CVD, the gate electrode 23 is formed by forming and patterning doped polysilicon. Then, after forming the field oxide film 241 and the interlayer insulating film 242, contact holes 242a and 242b are formed in the interlayer insulating film 242. Afterwards, the formation of the upper electrode 25, the gate wiring 26, the protective film 27, and the lower electrode 28 on the back side of the substrate 11 are performed using conventional processes. Thus, the SiC semiconductor device of this embodiment is completed.

[0081] The SiC semiconductor device thus formed has a JFET layer 14 formed on the cell region 1 side in the interconnection portion 2b, but no JFET layer 14 formed on its outer side. Furthermore, the JFET layer 14 is not disposed below the gate wiring 26 in the interconnection portion 2b, but is disposed only on the cell region 1 side closer to the gate wiring 26.

[0082] As explained above, in the SiC semiconductor device of this embodiment, a JFET layer 14 is formed on the cell region 1 side of the interconnect 2b, but not on its outer side. Therefore, the pn junction on the outer edge of the interconnect 2b is formed by a low-concentration layer 13 and a first deep layer 15. Due to this configuration, the impurity concentrations of the p-type and n-type layers constituting the pn junction are reduced, which decreases the displacement current A1 generated during voltage surges during switching. Therefore, the electric field concentration caused by the displacement current A1 is mitigated, suppressing damage to the gate insulating film 22 and improving switching withstand capability. Moreover, this effect can be achieved regardless of the location where withstand capability is limited. Therefore, it is possible to create a SiC semiconductor device that improves switching withstand capability regardless of the location where withstand capability is limited. Furthermore, by improving the switching withstand capability, high-speed switching of the vertical MOSFET can be achieved.

[0083] In particular, the electric field applied to the gate insulating film 22 tends to increase below the gate wiring 26, but a JFET layer 14 is not formed in this portion. The outer end position Po of the JFET layer 14 is closer to the cell region 1 than the inner end position Pi of the gate wiring 26. Therefore, damage to the gate insulating film 22 can be further suppressed, and the switching withstand capability can be improved.

[0084] Furthermore, as in Patent Document 1, shortening the current path distance results in denser ends for structures such as source contacts, field oxide films, and trenches, making it difficult to manufacture each structure with high precision, leading to unstable manufacturing processes and reduced yield. However, according to the configuration of this embodiment, the switching capacity can be increased regardless of the current path distance, thus suppressing the decrease in yield.

[0085] Furthermore, by limiting the formation position of the JFET layer 14 to the cell region 1 side in both the cell region 1 and the connecting portion 2b, the switching capacity can be improved. Therefore, compared to conventional manufacturing methods, only the mask used to form the JFET layer 14 needs to be changed. As a result, the manufacturing process can be simplified.

[0086] (Second Implementation) The second embodiment will be described. This embodiment differs from the first embodiment in that the formation range of the JFET layer 14 is changed, but the rest is the same as the first embodiment. Therefore, only the parts that are different from the first embodiment will be described.

[0087] In the first embodiment, a JFET layer 14 is formed on the cell region 1 side of the cell region 1 and the connecting portion 2b. However, in this embodiment, the formation range of the JFET layer 14 is set to only the cell region 1.

[0088] Furthermore, in the first embodiment, the formation ranges of the ion implantation layers used to form the JFET layer 14 and the source region 19 were respectively set. In this embodiment, when viewed in the normal direction relative to the surface of the substrate 11, the formation ranges of the ion implantation layers used to form the JFET layer 14 and the source region 19 are the same.

[0089] Specifically, such as Figure 7 As shown, the JFET layer 14 is formed only in the cell region 1, and the JFET layer 14 is not formed in the outer peripheral region 2, which includes the connecting portion 2b. Furthermore, the ion implantation layer formed during the formation of the JFET layer 14 is limited to the cell region 1. Additionally, as described later... Figure 8B As shown, the ion implantation range of the n-type impurity when forming the source region 19 is the same as the formation range of the JFET layer 14.

[0090] Furthermore, the formation range of the ion implantation layer used to form the JFET layer 14 refers to the entire range of ion implantation of n-type impurities during the formation of the JFET layer 14, viewed from the normal direction of the substrate 11. This range also includes the portion of the first deep layer 15 that becomes p-type due to p-type impurity backlash. Similarly, the formation range of the ion implantation layer when forming the source region 19 refers to the entire range of ion implantation of n-type impurities during the formation of the source region 19, viewed from the normal direction of the substrate 11. This range also includes the portion of the contact region 20 that becomes p-type due to p-type impurity backlash. While it is preferable that the formation ranges of the ion implantation layers be identical, this means that manufacturing with the goal of achieving identical formation ranges may include manufacturing errors. Figure 7 The single-dotted line shown represents the ion implantation range of the n-type impurity when the source region 19 is formed.

[0091] If this makes the formation range of the ion implantation layer consistent when forming the JFET layer 14 and the source region 19, then the ion implantation mask is shared when forming the JFET layer 14 and the source region 19 by ion implantation. (Refer to...) Figures 8A-8E The manufacturing method of the SiC semiconductor device according to this embodiment will be described. Furthermore, Figures 8A-8E It means equivalent to Figure 4 The manufacturing process of the cross-section of unit region 1 and connecting part 2b.

[0092] First of all, Figure 8A In the process shown, with Figure 6A Similarly, after forming a buffer layer 12 and a low-concentration layer 13 on the substrate 11, a JFET layer 14 is formed. At this time, after placing a mask 51 with a partial opening corresponding to the JFET layer 14 on the surface of the low-concentration layer 13, n-type impurities are implanted to form the JFET layer 14, thereby performing ion implantation only on the cell region 1. Next, as...Figure 8B As shown, the source region 19 is formed by ion implantation of n-type impurities using the mask 51 used in the formation of the JFET layer 14. Furthermore, the implantation depth is varied by changing the ion implantation energy in the formation of the JFET layer 14 and the source region 19.

[0093] Subsequently, Figure 8C In the process shown, the execution is with Figure 6C The same process is used to form the first deep layer 15, the base layer 18, and the contact region 20. When forming the contact region 20, the state from the formation of the source region 19 to the formation of the contact region 20 can be achieved by increasing the dose of p-type impurities to backflush to p-type and form the contact region 20.

[0094] In addition, as Figure 8D The process shown is performed in accordance with... Figure 6D The same process is used to form the groove 21, and then the second deep layer 30 is formed. Furthermore, as... Figure 8E The process shown is performed in conjunction with... Figure 6E The same process is then performed, including the formation of the gate insulating film 22, the formation of the gate electrode 23, the formation of the field oxide film 241, the formation of the interlayer insulating film 242, and the formation of contact holes 242a and 242b in the interlayer insulating film 242. Afterwards, the formation of the upper electrode 25, the gate wiring 26, the formation of the protective film 27, and the formation of the lower electrode 28 on the back side of the substrate 11 are performed. Thus, the SiC semiconductor device of this embodiment is completed.

[0095] As explained above, in this embodiment, the formation areas of the ion implantation layers used to form the JFET layer 14 and the source region 19 are consistent. Therefore, the ion implantation masks for the JFET layer 14 and the source region 19 can be shared, simplifying the manufacturing process and reducing manufacturing costs.

[0096] (Other implementation methods) This disclosure describes embodiments, but it should be understood that this disclosure is not limited to those embodiments and structures. This disclosure also includes various modifications and equivalent variations. In addition, various combinations, methods, and other combinations or methods that include only one element or more of them also fall within the scope and spirit of this disclosure.

[0097] For example, in each of the embodiments, the base layer 18 and the contact region 20 are provided on the surface of the low-concentration layer 13 in the connecting portion 2b. However, it is also possible to provide a structure in which one or both of them are not provided in the connecting portion 2b. When the base layer 18 is formed only in the cell region 1, the base layer 18 can be formed using the ion implantation mask of the JFET layer 14 and the source region 19, as in the second embodiment. In this way, the ion implantation mask of the base layer 18 can be shared in addition to the JFET layer 14 and the source region 19, thereby further simplifying the manufacturing process and reducing manufacturing costs.

[0098] In the first embodiment, the outer end position Po of the JFET layer 14 in the connecting portion 2b is closer to the cell region 1 than the inner end position Pi of the gate wiring 26, and a connecting layer 15a or a low-concentration layer 13 is formed on its outer side. That is, the JFET layer 14 is not formed on the outer side of the inner end position Pi of the gate wiring 26. In contrast, the JFET layer 14 can also be formed on the outer side of the inner end position Pi of the gate wiring 26, and the n-type impurity concentration in this part can be lower than the low-concentration layer 13. Even if the JFET layer 14 is formed in this way, as long as the n-type impurity concentration is reduced on the outer side of the position of the p-type layer constituting the pn junction in the outer peripheral region 2, the impurity concentration of the p-type layer and the n-type layer is reduced, and the source-drain capacitance can be reduced. Therefore, the same effect as the first embodiment can be obtained.

[0099] Furthermore, in the described embodiment, the bottom surface of the second deep layer 30 can be made shallow, located within the JFET layer 14 and the first deep layer 15. That is, the second deep layer 30 can be formed so as not to reach the low-concentration layer 13. As a result, the depletion layer is difficult to extend from the second deep layer 30, thereby reducing the on-resistance.

[0100] Furthermore, in the first embodiment, the JFET layer 14, the first deep layer 15, the base layer 18, the contact region 20, or the source region 19 are formed by ion implantation. Alternatively, some or all of them may be composed of epitaxial layers formed by epitaxial growth.

[0101] In this embodiment, a base layer 18 is formed on the surfaces of the JFET layer 14 and the first deep layer 15, but an n-type current dispersing layer with a higher n-type impurity concentration than the low-concentration layer 13 can also be formed between them. In this case, in addition to the current dispersing layer, p-type interconnect layers can be formed on both sides of the trench 21, and the base layer 18 is formed on these current dispersing layers and interconnect layers. In this case, the first deep layer 15 and the base layer 18 are connected by interconnect layers. Furthermore, the low-concentration layer 13, the JFET layer 14, and the current dispersing layer are connected, and they constitute the drift layer 17. In this configuration, the second deep layer 30 can also be formed to a depth greater than the first deep layer 15, or to a depth within the thickness of the first deep layer 15.

[0102] Furthermore, in the above embodiment, a vertical MOSFET with an n-channel trench gate structure, in which the first conductivity type is n-type and the second conductivity type is p-type, is cited as an example of a semiconductor element disposed in cell region 1. However, this is only one example; for example, it could also be a vertical MOSFET with a p-channel trench gate structure, inverting the conductivity types of each component relative to the n-channel type. Furthermore, it could also be a vertical IGBT with the same structure, instead of a vertical MOSFET. In the case of the IGBT, it is the same as the vertical MOSFET described in the above embodiment, except that the conductivity type of the substrate 11 in each embodiment is changed from n-type to p-type.

[0103] Furthermore, when indicating the orientation of a crystal, a hyphen (-) should normally be added above the desired number, but due to limitations in the presentation of electronic applications, a hyphen is added before the desired number in this specification.

Claims

1. A silicon carbide semiconductor device comprising: a unit region (1) having a semiconductor element having a trench gate structure; and a peripheral region (2) having a peripheral withstand voltage structure portion (2a) constituting a peripheral withstand voltage structure (16) surrounding the unit region, and a connecting portion (2b) located between the peripheral withstand voltage structure portion and the unit region, the silicon carbide semiconductor device being characterized in that it has: Substrate (11), which is made of silicon carbide of a first conductivity type or a second conductivity type; and A first impurity region (13) of a first conductivity type is formed on the substrate, and the impurity concentration is lower than that of the substrate. The semiconductor element is formed in the cell region, and the semiconductor element has: A JFET layer (14) made of silicon carbide of the first conductivity type is formed on the surface of the first impurity region, and the impurity concentration is higher than that of the first impurity region. A deep layer (15) made of silicon carbide of the second conductivity type is formed on the surface portion of the first impurity region and is alternately arranged with the JFET layer in the surface direction of the substrate. A base layer (18) of silicon carbide of the second conductivity type is formed on the JFET layer and the deep layer; The trench gate structure has a gate insulating film (22) formed on the inner wall surface of a plurality of gate trenches (21) that are deeper than the base layer and arranged in one direction as the length direction, and a gate electrode (23) formed on the gate insulating film in the gate trenches. A second impurity region (19) composed of silicon carbide of the first conductivity type is formed in the surface portion of the base layer and grounded with the trench gate structure, and the impurity concentration is higher than that of the first impurity region. A first electrode (25) is electrically connected to the second impurity region and the base layer; and The second electrode (28) is disposed on the back side of the substrate and is electrically connected to the substrate. The connecting portion includes: The gate insulating film is formed on the first impurity region by extending from the cell region; The gate electrode is disposed on the gate insulating film extending from the cell region; as well as Gate wiring (26) connected to the gate electrode. The outer peripheral end position (Po) of the cell region in the JFET layer is closer to one side of the cell region than the inner peripheral end position (Pi) of the cell region in the gate wiring.

2. The silicon carbide semiconductor device according to claim 1, characterized in that, The JFET layer is formed only in the cell region.

3. The silicon carbide semiconductor device according to claim 1 or 2, characterized in that, When viewed in the normal direction relative to the surface of the substrate, the formation range of the ion implantation layer used to form the JFET layer is consistent with the formation range of the ion implantation layer used to form the second impurity region.

4. The silicon carbide semiconductor device according to claim 1 or 2, characterized in that, When viewed in the normal direction relative to the surface of the substrate, the formation range of the ion implantation layer for forming the JFET layer, the formation range of the ion implantation layer for forming the second impurity region, and the formation range of the ion implantation layer for forming the base layer are the same.

5. A silicon carbide semiconductor device comprising: a unit region (1) having a semiconductor element having a trench gate structure; and a peripheral region (2) having a peripheral voltage withstand structure portion (2a) constituting a peripheral voltage withstand structure (16) and a connecting portion (2b) located between the peripheral voltage withstand structure portion and the unit region on the periphery surrounding the unit region, the silicon carbide semiconductor device being characterized in that it has: Substrate (11), which is made of silicon carbide of a first conductivity type or a second conductivity type; and A first impurity region (13) of a first conductivity type is formed on the substrate, and the impurity concentration is lower than that of the substrate. The semiconductor element is formed in the cell region, and the semiconductor element has: A JFET layer (14) made of silicon carbide of the first conductivity type is formed on the surface of the first impurity region, and the impurity concentration is higher than that of the first impurity region. A deep layer (15) made of silicon carbide of the second conductivity type is formed on the surface portion of the first impurity region and is alternately arranged with the JFET layer in the surface direction of the substrate. A base layer (18) of silicon carbide of the second conductivity type is formed on the JFET layer and the deep layer; The trench gate structure has a gate insulating film (22) formed on the inner wall surface of a plurality of gate trenches (21) that are deeper than the base layer and arranged in one direction as the length direction, and a gate electrode (23) formed on the gate insulating film in the gate trenches. A second impurity region (19) composed of silicon carbide of the first conductivity type is formed in the surface portion of the base layer and grounded with the trench gate structure, and the impurity concentration is higher than that of the first impurity region. A first electrode (25) is electrically connected to the second impurity region and the base layer; and The second electrode (28) is disposed on the back side of the substrate and is electrically connected to the substrate. The connecting portion includes: The gate insulating film is formed on the first impurity region by extending from the cell region; The gate electrode is disposed on the gate insulating film extending from the cell region; as well as Gate wiring (26) connected to the gate electrode. The JFET layer is formed only on one side of the cell region in the cell region and the connecting portion.

6. A silicon carbide semiconductor device comprising: a unit region (1) having a semiconductor element having a trench gate structure; and a peripheral region (2) having a peripheral voltage withstand structure portion (2a) constituting a peripheral voltage withstand structure (16) and a connecting portion (2b) located between the peripheral voltage withstand structure portion and the unit region on the periphery surrounding the unit region, the silicon carbide semiconductor device being characterized in that it has: Substrate (11), which is made of silicon carbide of a first conductivity type or a second conductivity type; and A first impurity region (13) of a first conductivity type is formed on the substrate, and the impurity concentration is lower than that of the substrate. The semiconductor element is formed in the cell region, and the semiconductor element has: A JFET layer (14) made of silicon carbide of the first conductivity type is formed on the surface of the first impurity region, and the impurity concentration is higher than that of the first impurity region. A deep layer (15) made of silicon carbide of the second conductivity type is formed on the surface portion of the first impurity region and is alternately arranged with the JFET layer in the surface direction of the substrate. A base layer (18) of silicon carbide of the second conductivity type is formed on the JFET layer and the deep layer; The trench gate structure has a gate insulating film (22) formed on the inner wall surface of a plurality of gate trenches (21) that are deeper than the base layer and arranged in one direction as the length direction, and a gate electrode (23) formed on the gate insulating film in the gate trenches. A second impurity region (19) composed of silicon carbide of the first conductivity type is formed in the surface portion of the base layer and grounded with the trench gate structure, and the impurity concentration is higher than that of the first impurity region. A first electrode (25) is electrically connected to the second impurity region and the base layer; and The second electrode (28) is disposed on the back side of the substrate and is electrically connected to the substrate. The connecting portion includes: The gate insulating film is formed on the first impurity region by extending from the cell region; The gate electrode is disposed on the gate insulating film extending from the cell region; as well as Gate wiring (26) connected to the gate electrode. The JFET layer is also formed in the interconnection portion, wherein the first conductivity type impurity concentration of the portion of the JFET layer that is further outward than the end position of the cell region on one side of the gate wiring, i.e., the inner end position (Pi), is below the first conductivity type impurity concentration of the first impurity region.

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