Air conditioner and communication method of air conditioner

Abstract

The invention discloses an air conditioner and a communication method of the air conditioner, the air conditioner comprises a controller, an HBS communication circuit and a home bus, and the controller is in communication connection with the home bus through the HBS communication circuit; the controller processes the to-be-sent data, outputs a driving signal, and analyzes and processes the bus signal to obtain target data; the HBS communication circuit receives the driving signal through the sending unit, outputs a differential level signal to the home bus under the control of the driving signal, obtains a bus signal from the home bus through the receiving unit, and sends the bus signal to the controller; the home bus generates a bus signal based on the differential level signal. Due to the fact that the HBS communication circuit is arranged in the air conditioner, data communication of the air conditioner can be achieved without a special communication chip, the problem that application of air conditioner products is limited is solved, the HBS communication circuit is simple in circuit structure, and reduction of system cost of the air conditioner is facilitated.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to an air conditioner and a communication method for the air conditioner. Background Technology

[0002] In a multi-split air conditioning system, such as a commercial air conditioning system, there is usually one outdoor unit and multiple indoor units. Each outdoor unit and each indoor unit is equipped with an MCU (Microcontroller Unit). The MCUs communicate with each other through a Home Bus interface and use the HBS (Home Bus System) communication protocol to communicate data, thus forming the communication network of the multi-split air conditioning system.

[0003] However, in order to achieve normal data communication between the various MCUs in the outdoor and indoor units, a dedicated communication chip, such as the MM1192 communication chip, needs to be added to each HomeBus interface. This makes the function of the air conditioning system overly dependent on the communication chip, which limits the application of air conditioning products. Summary of the Invention

[0004] This invention provides a communication method between air conditioners to solve the problem that the application of existing air conditioner products is limited because they require a dedicated communication chip to achieve HBS communication.

[0005] In a first aspect, embodiments of the present invention provide an air conditioner, including a controller, an HBS communication circuit, and a home bus, wherein:

[0006] The controller is connected to the home bus via the HBS communication circuit, which includes a transmitting unit and a receiving unit.

[0007] The controller is used to perform data conversion processing on the data to be sent, output drive signals, and parse bus signals to obtain target data.

[0008] The HBS communication circuit is used to receive the drive signal through the transmitting unit, and under the control of the drive signal, output a differential level signal to the home bus.

[0009] The receiving unit acquires the bus signal from the home bus and sends the bus signal to the controller.

[0010] The home bus is used to generate the bus signal based on the differential level signal.

[0011] In an optional embodiment, the transmitting unit includes a logic control subunit and a driving subunit, wherein:

[0012] The logic control subunit is electrically connected to the drive subunit;

[0013] The logic control subunit is used to receive the drive signal and generate a logic control signal according to the level state of the drive signal;

[0014] The driving subunit is used to output the differential level signal under the control of the logic control signal.

[0015] In one optional embodiment, the driving signal includes a first driving sub-signal and a second driving sub-signal; the logic control subunit includes a first logic control branch and a second logic control branch arranged in parallel, wherein:

[0016] The first logic control branch is used to generate a first logic control sub-signal based on the level state of the first driving sub-signal and the level state of the second driving sub-signal, and to generate a second logic control sub-signal based on the level state of the first driving sub-signal.

[0017] The second logic control branch is used to generate a third logic control sub-signal based on the level state of the first driving sub-signal and the level state of the second driving sub-signal, and to generate a fourth logic control sub-signal based on the level state of the second driving sub-signal.

[0018] The logic control signal includes the first logic control sub-signal, the second logic control sub-signal, the third logic control sub-signal, and the fourth logic control sub-signal.

[0019] In an optional embodiment, the first logic control branch includes a first NOR gate, a first OR gate, a first resistor, and a second resistor, wherein:

[0020] The first input terminal of the first NOR gate is electrically connected to the first input terminal of the first OR gate and the first terminal of the second resistor, respectively, for receiving the first driving sub-signal;

[0021] The second input terminal of the first NOR gate is used to receive the second driving sub-signal, and the output terminal of the first NOR gate is electrically connected to the second input terminal of the first OR gate.

[0022] The output terminal of the first OR gate is electrically connected to the first terminal of the first resistor;

[0023] The second end of the first resistor is used to output the first logic control sub-signal, and the second end of the second resistor is used to output the second logic control sub-signal.

[0024] In one optional embodiment, the second logic control branch includes a second NOR gate, a second OR gate, a third resistor, and a fourth resistor, wherein:

[0025] The first input terminal of the second NOR gate is electrically connected to the first input terminal of the second OR gate and the first terminal of the fourth resistor, respectively, for receiving the second driving sub-signal;

[0026] The second input terminal of the second NOR gate is used to receive the first driving sub-signal, and the output terminal of the second NOR gate is electrically connected to the second input terminal of the second OR gate;

[0027] The output terminal of the second OR gate is electrically connected to the first terminal of the third resistor;

[0028] The second end of the third resistor is used to output the third logic control sub-signal, and the second end of the fourth resistor is used to output the fourth logic control sub-signal.

[0029] In one optional embodiment, the differential level signal includes a first level sub-signal output to a first bus in the home bus and a second level sub-signal output to a second bus in the home bus;

[0030] The drive subunit includes a first drive branch and a second drive branch arranged in parallel, wherein:

[0031] The first driving branch is used to output the first level sub-signal under the control of the first logic control sub-signal and the second logic control sub-signal;

[0032] The second driving branch is used to output the second level sub-signal under the control of the third logic control sub-signal and the fourth logic control sub-signal.

[0033] In an optional embodiment, the first driving branch includes a first switching transistor, a second switching transistor, a fifth resistor, and a sixth resistor, wherein:

[0034] The control terminal of the first switch is used to receive the first logic control sub-signal. The first terminal of the first switch and the first terminal of the fifth resistor are used to receive the power supply voltage. The second terminal of the first switch is electrically connected to the first terminal of the second switch, the second terminal of the fifth resistor, and the first terminal of the sixth resistor, respectively, for outputting the first level sub-signal.

[0035] The control terminal of the second switch is used to receive the second logic control sub-signal, and the second terminal of the second switch and the second terminal of the sixth resistor are grounded.

[0036] In an optional embodiment, the second drive branch includes a third switch, a fourth switch, a seventh resistor, and an eighth resistor, wherein:

[0037] The control terminal of the third switch is used to receive the third logic control sub-signal. The first terminal of the third switch and the first terminal of the seventh resistor are used to receive the power supply voltage. The second terminal of the third switch is electrically connected to the first terminal of the fourth switch, the second terminal of the seventh resistor, and the first terminal of the eighth resistor, respectively, for outputting the second level sub-signal.

[0038] The control terminal of the fourth switch is used to receive the fourth logic control sub-signal, and the second terminal of the fourth switch and the second terminal of the eighth resistor are grounded.

[0039] In one optional embodiment, the receiving unit includes a first capacitor, a second capacitor, a ninth resistor, and a tenth resistor, wherein:

[0040] The first terminal of the first capacitor and the first terminal of the second capacitor serve as the input terminals of the receiving unit, used to receive the bus signal;

[0041] The second terminal of the first capacitor is electrically connected to the first terminal of the ninth resistor, and the second terminal of the second capacitor is electrically connected to the first terminal of the tenth resistor.

[0042] The second end of the ninth resistor and the second end of the tenth resistor serve as the output terminals of the receiving unit, used to output the bus signal.

[0043] In a second aspect, embodiments of the present invention provide a communication method for an air conditioner, applied to an air conditioner as described in any of the embodiments of the first aspect above, the method comprising:

[0044] The controller performs data conversion processing on the data to be sent and outputs drive signals.

[0045] Under the control of the drive signal, a differential level signal is output to the home bus through the HBS communication circuit;

[0046] The bus signal is obtained from the home bus through the HBS communication circuit and sent to the controller, wherein the bus signal is generated by the home bus based on the differential level signal;

[0047] The controller parses and processes the bus signals to obtain the target data.

[0048] The technical solutions provided by the embodiments of the present invention bring at least the following beneficial effects:

[0049] In the air conditioner provided in this embodiment of the invention, the controller and the home bus are connected via an HBS communication circuit. The transmitting unit in the HBS communication circuit processes the drive signal output by the controller, generates a differential level signal, and sends it to the home bus. The receiving unit in the HBS communication circuit acquires the bus signal on the home bus and sends it to the controller for processing, thereby realizing data communication for the air conditioner. Because an HBS communication circuit is incorporated into the air conditioner, data communication can be achieved without a dedicated communication chip, solving the problem of limited application for air conditioner products. Furthermore, compared to solutions using communication chips, the HBS communication circuit provided in this embodiment of the invention has a simpler circuit structure, reducing the system cost of the air conditioner and facilitating production. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 A schematic diagram of the circuit structure of an HBS communication circuit provided for related technologies;

[0052] Figure 2 This is a schematic diagram of an application scenario of an air conditioner provided by an embodiment of the present invention;

[0053] Figure 3 This is a schematic diagram illustrating another application scenario of an air conditioner provided by an embodiment of the present invention;

[0054] Figure 4 This is a schematic diagram of the structure of an air conditioner provided in an embodiment of the present invention;

[0055] Figure 5 This is a schematic diagram of the internal structure of an HBS communication circuit provided in an embodiment of the present invention;

[0056] Figure 6 This is a schematic diagram of the internal structure of another HBS communication circuit provided in an embodiment of the present invention;

[0057] Figure 7 A schematic diagram of the circuit structure of a transmitting unit in an HBS communication circuit provided in an embodiment of the present invention;

[0058] Figure 8 A schematic diagram of the circuit structure of a receiving unit in an HBS communication circuit provided in an embodiment of the present invention;

[0059] Figure 9This is a schematic diagram of the internal structure of another HBS communication circuit provided in an embodiment of the present invention;

[0060] Figure 10 A schematic diagram of the DC blocking unit in an HBS communication circuit provided in an embodiment of the present invention;

[0061] Figure 11 A schematic diagram of the overall working process of an air conditioner provided in an embodiment of the present invention;

[0062] Figure 12 A waveform diagram of various signals during the communication process of an air conditioner, provided as an embodiment of the present invention;

[0063] Figure 13 This is a schematic diagram illustrating the workflow of a communication method for an air conditioner provided in an embodiment of the present invention. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0065] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0066] As mentioned earlier, the data communication of a multi-split air conditioning system relies on a dedicated communication chip, such as the MM1192 communication chip.

[0067] Figure 1 An HBS communication circuit for an air conditioner provided by a related technology is shown, such as Figure 1 As shown, the HBS communication circuit 10 is electrically connected to the Home Bus. The HBS communication circuit 10 includes an MCU 11, an OR gate OR01, an HBS communication chip IC1, switching transistors M01 and M02, resistors R01, R02, R03, and R04, and capacitors C01, C02, C03, and C04, wherein:

[0068] The PWM terminal and UART TX terminal of MCU 11 are electrically connected to the two input terminals of OR gate OR01, respectively. The UART RX terminal of MCU 11 is electrically connected to the first output terminal of HBS communication chip IC1, and the output terminal of OR gate OR01 is electrically connected to the first input terminal of HBS communication chip IC1.

[0069] The second output terminal of HBS communication chip IC1 is electrically connected to the first terminal of switch transistor M02, one end of resistor R01, and one end of capacitor C01, respectively. The third output terminal of HBS communication chip IC1 is electrically connected to the first terminal of switch transistor M01, one end of resistor R02, and one end of capacitor C02, respectively. The third output terminal of HBS communication chip IC1 is electrically connected to the control terminal of switch transistor M01. The fourth output terminal of HBS communication chip IC1 is electrically connected to the control terminal of switch transistor M02.

[0070] The second input terminal of HBS communication chip IC1 is electrically connected to one end of resistor R03, and the third input terminal of HBS communication chip IC1 is electrically connected to one end of resistor R04.

[0071] The other end of resistor R01 and the other end of capacitor C01 are both electrically connected to the first bus in the home bus, and the other end of resistor R02 and the other end of capacitor C02 are both electrically connected to the second bus in the home bus.

[0072] One end of capacitor C03 is electrically connected to the first bus, and the other end of capacitor C03 is electrically connected to the other end of resistor R03. One end of capacitor C04 is electrically connected to the second bus, and the other end of capacitor C04 is electrically connected to the other end of resistor R04.

[0073] The second terminal of both switching transistor M01 and switching transistor M02 is grounded.

[0074] However, the above-mentioned method of using HBS communication chips, because its functionality depends on HBS communication chips, will limit the application and cost of air conditioning products.

[0075] Based on this, embodiments of the present invention provide a communication method between air conditioners, which eliminates the need for a communication chip and enables the data communication function of the air conditioner by setting up an HBS communication circuit, thereby solving the problem of limited application of air conditioner products.

[0076] The objectives, functional features, and advantages of this invention will be further explained in conjunction with the embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the invention.

[0077] The possible application scenarios of the air conditioner provided by the present invention are described below with reference to the accompanying drawings:

[0078] The air conditioner provided in this embodiment of the invention can be applied in single-unit system application scenarios, such as household air conditioning systems. Figure 2 This diagram illustrates a structural schematic of an air conditioner application scenario provided by an embodiment of the present invention, in conjunction with... Figure 2 As shown, the air conditioner 200 includes an indoor unit 210 and an outdoor unit 220, which are connected via a HomeBus communication network.

[0079] In specific implementation, both the indoor unit 210 and the outdoor unit 220 are equipped with a controller and an HBS communication circuit (not shown in the figure). In the indoor unit 210, the controller is connected to the home bus via the HBS communication circuit, and in the outdoor unit 220, the controller is also connected to the home bus via the HBS communication circuit. Through the HBS communication protocol and the method provided in this embodiment, the indoor unit 210 can perform normal data communication with the outdoor unit 220.

[0080] The air conditioner provided in this embodiment of the invention can also be applied in multi-split system application scenarios, such as commercial air conditioning systems. Figure 3 This diagram illustrates a structural schematic of another air conditioner application scenario provided by an embodiment of the present invention, in conjunction with... Figure 3 As shown, the air conditioner 200 includes multiple indoor units 211-21k and an outdoor unit 220, and the multiple indoor units 211-21k and the outdoor unit 220 are connected via a Home Bus communication network.

[0081] In specific implementation, multiple indoor units 211-21k and one outdoor unit 220 are each equipped with a controller and an HBS communication circuit (not shown in the figure). In any one of the indoor units, the controller is connected to the home bus via the HBS communication circuit, and in the outdoor unit 220, the controller is also connected to the home bus via the HBS communication circuit. Through the HBS communication protocol and the method provided in this embodiment, any one of the indoor units can perform normal data communication with the outdoor unit 20.

[0082] Of course, the device provided in the embodiments of the present invention is not limited to use in Figure 2 , Figure 3 The application scenarios shown can also be used in other possible application scenarios, and the embodiments of the present invention do not impose limitations.

[0083] After introducing the application scenarios of the embodiments of the present invention, the preferred embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. Furthermore, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0084] The air conditioner provided by the present invention will be described in detail below with reference to the accompanying drawings:

[0085] Figure 4 A schematic diagram of a modular structure for an air conditioner is shown, such as... Figure 4 As shown,

[0086] This invention provides an air conditioner 400, including a controller 410, an HBS communication circuit 420, and a home bus 430, wherein:

[0087] The controller 410 is connected to the home bus 430 via the HBS communication circuit 420, which includes a transmitting unit 4201 and a receiving unit 4202.

[0088] The controller 410 is used to perform data conversion processing on the data to be transmitted, output drive signals, and parse and process bus signals to obtain target data.

[0089] HBS communication circuit 420 is used to receive drive signals through transmission unit 4201, and output differential level signals to home bus 430 under the control of drive signals, and to obtain bus signals from home bus 430 through receiving unit 4202 and send bus signals to controller 410.

[0090] Home Bus 430 is used to generate bus signals based on differential level signals.

[0091] In one or more embodiments, such as Figure 4 As shown, the controller 410 integrates an HBS function module, which is used to convert the data to be transmitted into a drive signal and output it to the transmission unit 4201 of the HBS communication circuit 420 through the output terminal (HBS TX). In addition, the HBS function module is also used to parse and process the bus signal received through the input terminal (HBS RX) to obtain the target data.

[0092] In specific implementation, such as Figure 4 As shown, the output terminal (HBS TX) of the controller 410 is electrically connected to the input terminal of the transmitting unit 4201, and the output terminal of the transmitting unit 4201 is electrically connected to the home bus 430; the input terminal of the receiving unit 4202 is electrically connected to the home bus 430, and the output terminal of the receiving unit 4202 is electrically connected to the input terminal (HBS RX) of the controller 410.

[0093] Preferably, the controller 410 in this embodiment of the invention can be an MCU.

[0094] The air conditioner provided in this embodiment of the invention connects the controller and the Home Bus via an HBS communication circuit. The transmitting unit in the HBS communication circuit processes the drive signal output by the controller to generate a differential level signal and sends it to the Home Bus. The receiving unit in the HBS communication circuit obtains the bus signal on the Home Bus and sends it to the controller for processing, thereby realizing data communication of the air conditioner.

[0095] Because an HBS communication circuit is incorporated into the air conditioner, data communication can be achieved without a dedicated communication chip, thus solving the problem of limited application of air conditioning products. Furthermore, compared to solutions that use communication chips, the HBS communication circuit provided in this embodiment of the invention has a simpler circuit structure, which reduces the system cost of the air conditioner and is beneficial for production.

[0096] The HBS communication circuit 420 in the air conditioner 400 provided in this invention will be described in detail below with reference to the accompanying drawings:

[0097] Figure 5 This diagram illustrates the internal structure of the transmitting unit 4201 in an HBS communication circuit 420 provided in an embodiment of the present invention.

[0098] In one or more embodiments, such as Figure 5 As shown, the transmitting unit 4201 includes a logic control subunit 510 and a driving subunit 520, wherein the logic control subunit 510 and the driving subunit 520 are electrically connected, and:

[0099] The logic control subunit 510 is used to receive the drive signal and generate a logic control signal according to the level state of the drive signal; the drive subunit 520 is used to output a differential level signal under the control of the logic control signal.

[0100] In specific implementation, such as Figure 5 As shown, the input terminal of the logic control subunit 510 serves as the input terminal of the transmitting unit 4201, used to receive driving signals; the output terminal of the logic control subunit 510 is electrically connected to the input terminal of the driving subunit 520; the output terminal of the driving subunit 520 serves as the output terminal of the transmitting unit 4201, used to output differential level signals.

[0101] In one or more embodiments, such as Figure 5 As shown, the home bus includes a first bus and a second bus; the drive signals include a first drive sub-signal DRVA and a second drive sub-signal DRVB; the differential level signals include a first level sub-signal BUS1 output to the first bus in the home bus, and a second level sub-signal BUS2 output to the second bus in the home bus.

[0102] Figure 6This diagram illustrates the internal structure of the transmitting unit 4201 in another HBS communication circuit 420 provided in an embodiment of the present invention.

[0103] In one or more embodiments, such as Figure 6 As shown, the logic control subunit 510 includes a first logic control branch 5101 and a second logic control branch 5102 arranged in parallel, wherein:

[0104] The first logic control branch 5101 is used to generate a first logic control sub-signal based on the level state of the first driving sub-signal DRVA and the level state of the second driving sub-signal DRVB, and to generate a second logic control sub-signal based on the level state of the first driving sub-signal DRVA.

[0105] The second logic control branch 5102 is used to generate a third logic control sub-signal based on the level state of the first driving sub-signal DRVA and the level state of the second driving sub-signal DRVB, and to generate a fourth logic control sub-signal based on the level state of the second driving sub-signal DRVB.

[0106] The logic control signals include a first logic control sub-signal, a second logic control sub-signal, a third logic control sub-signal, and a fourth logic control sub-signal.

[0107] In one or more embodiments, such as Figure 6 As shown, the drive subunit 520 includes a first drive branch 5201 and a second drive branch 5202 arranged in parallel, wherein:

[0108] The first drive branch 5201 is used to output the first level sub-signal BUS1 under the control of the first logic control sub-signal and the second logic control sub-signal.

[0109] The second drive branch 5202 is used to output the second level sub-signal BUS2 under the control of the third logic control sub-signal and the fourth logic control sub-signal.

[0110] The following is about Figure 6 The circuit structure of each sub-unit in the transmitting unit 4201 of the HBS communication circuit 420 shown is described in detail below:

[0111] In one or more embodiments, such as Figure 7 As shown, the first logic control branch 5101 includes a first NOR gate XOR1, a first OR gate OR1, a first resistor R1, and a second resistor R2, wherein:

[0112] The first input terminal of the first NOR gate XOR1 is electrically connected to the first input terminal of the first OR gate OR1 and the first terminal of the second resistor R2, respectively, for receiving the first driving sub-signal DRVA.

[0113] The second input terminal of the first NOR gate XOR1 is used to receive the second driving sub-signal DRVB, and the output terminal of the first NOR gate XOR1 is electrically connected to the second input terminal of the first OR gate OR1.

[0114] The output terminal of the first OR gate OR1 is electrically connected to the first terminal of the first resistor R1;

[0115] The second terminal of the first resistor R1 is used to output the first logic control sub-signal, and the second terminal of the second resistor R2 is used to output the second logic control sub-signal.

[0116] In one or more embodiments, such as Figure 7 As shown, the second logic control branch 5102 includes a second NOR gate XOR2, a second OR gate OR2, a third resistor R3, and a fourth resistor R4, wherein:

[0117] The first input terminal of the second NOR gate XOR2 is electrically connected to the first input terminal of the second OR gate OR2 and the first terminal of the fourth resistor R4, respectively, and is used to receive the second driving sub-signal DRVB.

[0118] The second input terminal of the second NOR gate XOR2 is used to receive the first driving sub-signal DRVA, and the output terminal of the second NOR gate XOR2 is electrically connected to the second input terminal of the second OR gate OR2.

[0119] The output of the second OR gate OR2 is electrically connected to the first terminal of the third resistor R3;

[0120] The second terminal of the third resistor R3 is used to output the third logic control sub-signal, and the second terminal of the fourth resistor R4 is used to output the fourth logic control sub-signal.

[0121] In one or more embodiments, such as Figure 7 As shown, the first drive branch 5201 includes a first switch M1, a second switch M2, a fifth resistor R5, and a sixth resistor R6, wherein:

[0122] The control terminal of the first switching transistor M1 is used to receive the first logic control sub-signal. The first terminal of the first switching transistor M1 and the first terminal of the fifth resistor R5 are used to receive the power supply voltage VCC. The second terminal of the first switching transistor M1 is electrically connected to the first terminal of the second switching transistor M2, the second terminal of the fifth resistor R5 and the first terminal of the sixth resistor R6, respectively, and is used to output the first level sub-signal BUS1.

[0123] The control terminal of the second switch M2 is used to receive the second logic control sub-signal, and the second terminal of the second switch M2 and the second terminal of the sixth resistor R6 are grounded.

[0124] In one or more embodiments, the type of the first switching transistor M1 is different from the type of the second switching transistor M2. Preferably, the first switching transistor M1 is a PNP transistor and the second switching transistor M2 is an NPN transistor.

[0125] In one or more embodiments, such as Figure 7 As shown, the second drive branch 5202 includes a third switch M3, a fourth switch M4, a seventh resistor R7, and an eighth resistor R8, wherein:

[0126] The control terminal of the third switch M3 is used to receive the third logic control sub-signal. The first terminal of the third switch M3 and the first terminal of the seventh resistor R7 are used to receive the power supply voltage VCC. The second terminal of the third switch M3 is electrically connected to the first terminal of the fourth switch M4, the second terminal of the seventh resistor R7 and the first terminal of the eighth resistor R8 respectively, and is used to output the second level sub-signal BUS2.

[0127] The control terminal of the fourth switch M4 is used to receive the fourth logic control sub-signal, and the second terminal of the fourth switch M4 and the second terminal of the eighth resistor R8 are grounded.

[0128] In one or more embodiments, the type of the third switch M3 is different from the type of the fourth switch M4. Preferably, the third switch M3 is a PNP transistor and the fourth switch M4 is an NPN transistor.

[0129] It should be noted that the first switch M1, the second switch M2, the third switch M3, and the fourth switch M4 in the embodiments of the present invention can be transistors, MOS (Metal Oxide Semiconductor Field Effect Transistor), or IGBT (Insulated Gate Bipolar Transistor). The embodiments of the present invention do not impose any restrictions on them.

[0130] Based on such Figure 7 The circuit structure of the transmitting unit 4201 is shown below. The specific working principle of the transmitting unit 4201 is described below:

[0131] The controller 410 outputs the first drive sub-signal DRVA and the second drive sub-signal DRVB to the first logic control branch 5101 and the second logic control branch 5102 through the output terminal (HBS TX). According to the level state of the first drive sub-signal DRVA and the second drive sub-signal DRVB, there are four possible situations:

[0132] Scenario 1:

[0133] If the first driving sub-signal DRVA is low (0) and the second driving sub-signal DRVB is also low (0), then according to the circuit structure of the first logic control branch 5101, the second logic control sub-signal is the first driving sub-signal DRVA, which is low (0). At this time, the second switch M2 is disconnected under the control of the low-level (0) second logic control sub-signal.

[0134] Since both inputs of the first NOR gate XOR1 are low (0), the first NOR gate XOR1 outputs a high level (1) to the first OR gate OR1. At this time, one input of the first OR gate OR1 is low (0) and the other input is high (1). The first OR gate OR1 outputs a high level (1), that is, the first logic control sub-signal is high (1). The first switch M1 is turned off under the control of the high level (1) first logic control sub-signal.

[0135] Therefore, in this case, the first level sub-signal BUS1 output by the first drive branch 5201 is determined by the voltage divider of the supply voltage VCC by the fifth resistor R5 and the sixth resistor R6, and it is at the intermediate level.

[0136] Furthermore, as can be seen from the circuit structure of the second logic control branch 5102, the fourth logic control sub-signal is the second drive sub-signal DRVB, which is at a low level (0). At this time, the fourth switch M4 is disconnected under the control of the low level (0) fourth logic control sub-signal.

[0137] Since both inputs of the second NOR gate XOR2 are low (0), the second NOR gate XOR2 outputs a high level (1) to the second OR gate OR2. At this time, one input of the second OR gate OR2 is low (0) and the other input is high (1). The second OR gate OR2 outputs a high level (1), that is, the third logic control sub-signal is high (1). The third switch M3 is turned off under the control of the high level (1) third logic control sub-signal.

[0138] Therefore, in this case, the second level sub-signal BUS2 output by the second drive branch 5202 is determined by the voltage divider of the supply voltage VCC by the seventh resistor R7 and the eighth resistor R8, and it is at the intermediate level.

[0139] In summary, when the first driving sub-signal DRVA is low (0) and the second driving sub-signal DRVB is also low (0), both the first level sub-signal BUS1 and the second level sub-signal BUS2 exhibit intermediate levels.

[0140] Scenario 2:

[0141] If the first driving sub-signal DRVA is low (0) and the second driving sub-signal DRVB is high (1), then according to the circuit structure of the first logic control branch 5101, the second logic control sub-signal is the first driving sub-signal DRVA, which is low (0). At this time, the second switch M2 is disconnected under the control of the low-level (0) second logic control sub-signal.

[0142] Furthermore, since one input of the first NOR gate XOR1 is low (0) and the other input is high (1), the first NOR gate XOR1 outputs a low level (0) to the first OR gate OR1. At this time, both inputs of the first OR gate OR1 are low (0), and the first OR gate OR1 outputs a low level (0), that is, the first logic control sub-signal is low (0); the first switch M1 is turned on under the control of the low level (0) first logic control sub-signal.

[0143] Therefore, in this case, the first level sub-signal BUS1 output by the first drive branch 5201 is determined by the potential at the connection point of the first switch M1 and the second switch M2. Since the first switch M1 is turned on and the second switch M2 is turned off, the potential at the connection point is equal to the supply voltage VCC, that is, the first level sub-signal BUS1 is high.

[0144] Furthermore, as can be seen from the circuit structure of the second logic control branch 5102, the fourth logic control sub-signal is the second drive sub-signal DRVB, which is at a high level (1). At this time, the fourth switch M4 is turned on under the control of the high level (1) fourth logic control sub-signal.

[0145] Furthermore, since one input of the second NOR gate XOR2 is low (0) and the other input is high (1), the second NOR gate XOR2 outputs low (0) to the second OR gate OR2. At this time, one input of the second OR gate OR2 is low (0) and the other input is high (1), and the second OR gate OR2 outputs high (1), that is, the third logic control sub-signal is high (1); the third switch M3 is disconnected under the control of the high-level (1) third logic control sub-signal.

[0146] Therefore, in this case, the second level sub-signal BUS2 output by the second drive branch 5202 is determined by the potential at the connection point of the third switch M3 and the fourth switch M4. Since the third switch M3 is off and the fourth switch M4 is on, the potential at the connection point is equal to ground, that is, the second level sub-signal BUS2 is low.

[0147] In summary, when the first driving sub-signal DRVA is low (0) and the second driving sub-signal DRVB is high (1), the first level sub-signal BUS1 is high and the second level sub-signal BUS2 is low.

[0148] Scenario 3:

[0149] If the first driving sub-signal DRVA is high (1) and the second driving sub-signal DRVB is low (0), then according to the circuit structure of the first logic control branch 5101, the second logic control sub-signal is the first driving sub-signal DRVA, which is high (1). At this time, the second switch M2 is turned on under the control of the high-level (1) second logic control sub-signal.

[0150] Since one input of the first NOR gate XOR1 is low (0) and the other input is high (1), the first NOR gate XOR1 outputs low (0) to the first OR gate OR1. At this time, one input of the first OR gate OR1 is low (0) and the other input is high (1). The first OR gate OR1 outputs high (1), that is, the first logic control sub-signal is high (1). The first switch M1 is turned off under the control of the high-level (1) first logic control sub-signal.

[0151] Therefore, in this case, the first level sub-signal BUS1 output by the first drive branch 5201 is determined by the potential at the connection point of the first switch M1 and the second switch M2. Since the first switch M1 is off and the second switch M2 is on, the potential at the connection point is equal to ground, that is, the first level sub-signal BUS1 is low.

[0152] Furthermore, as can be seen from the circuit structure of the second logic control branch 5102, the fourth logic control sub-signal is the second drive sub-signal DRVB, which is at a low level (0). At this time, the fourth switch M4 is disconnected under the control of the low level (0) fourth logic control sub-signal.

[0153] Furthermore, since one input of the second NOR gate XOR2 is low (0) and the other input is high (1), the output of the second NOR gate XOR2 is low (0) to the second OR gate OR2. At this time, both inputs of the second OR gate OR2 are low (0), and the output of the second OR gate OR2 is low (0), that is, the third logic control sub-signal is low (0); the third switch M3 is turned on under the control of the low (0) third logic control sub-signal.

[0154] Therefore, in this case, the second level sub-signal BUS2 output by the second drive branch 5202 is determined by the potential at the connection point of the third switch M3 and the fourth switch M4. Since the third switch M3 is turned on and the fourth switch M4 is turned off, the potential at the connection point is equal to the supply voltage VCC, that is, the second level sub-signal BUS2 is high.

[0155] In summary, when the first driving sub-signal DRVA is high (1) and the second driving sub-signal DRVB is low (0), the first level sub-signal BUS1 is low and the second level sub-signal BUS2 is high.

[0156] Scenario 4:

[0157] If the first driving sub-signal DRVA is high (1) and the second driving sub-signal DRVB is also high (1), then according to the circuit structure of the first logic control branch 5101, the second logic control sub-signal is the first driving sub-signal DRVA, which is high (1). At this time, the second switch M2 is turned on under the control of the high-level (1) second logic control sub-signal.

[0158] Since both inputs of the first NOR gate XOR1 are high (1), the first NOR gate XOR1 outputs a low level (0) to the first OR gate OR1. At this time, one input of the first OR gate OR1 is low (0) and the other input is high (1). The first OR gate OR1 outputs a high level (1), that is, the first logic control sub-signal is high (1). The first switch M1 is turned off under the control of the high level (1) first logic control sub-signal.

[0159] Therefore, in this case, the first level sub-signal BUS1 output by the first drive branch 5201 is determined by the potential at the connection point of the first switch M1 and the second switch M2. Since the first switch M1 is off and the second switch M2 is on, the potential at the connection point is equal to ground, that is, the first level sub-signal BUS1 is low.

[0160] Furthermore, as can be seen from the circuit structure of the second logic control branch 5102, the fourth logic control sub-signal is the second drive sub-signal DRVB, which is at a high level (1). At this time, the fourth switch M4 is turned on under the control of the high level (1) fourth logic control sub-signal.

[0161] Since both inputs of the second NOR gate XOR2 are high (1), the second NOR gate XOR2 outputs a low level (0) to the second OR gate OR2. At this time, one input of the second OR gate OR2 is low (0) and the other input is high (1). The second OR gate OR2 outputs a high level (1), that is, the third logic control sub-signal is high (1). The third switch M3 is turned off under the control of the high level (1) third logic control sub-signal.

[0162] Therefore, in this case, the second level sub-signal BUS2 output by the second drive branch 5202 is determined by the potential at the connection point of the third switch M3 and the fourth switch M4. Since the third switch M3 is off and the fourth switch M4 is on, the potential at the connection point is equal to ground, that is, the second level sub-signal BUS2 is low.

[0163] In summary, when the first driving sub-signal DRVA is high (1) and the second driving sub-signal DRVB is also high (1), both the first level sub-signal BUS1 and the second level sub-signal BUS2 are low.

[0164] As can be seen from the above detailed description of the four scenarios, the first level sub-signal BUS1 and the second level sub-signal BUS2 generated by the transmitting unit 4201 are a pair of differential signals. The first level sub-signal BUS1 is sent to the first bus, and the second level sub-signal BUS2 is sent to the second bus. Therefore, the differential level of the home bus is the difference between the first level sub-signal BUS1 and the second level sub-signal BUS2, which can be expressed as: BUS = BUS1 - BUS2.

[0165] In practical implementation, the load capacity of the home bus is determined by the maximum current carrying capacity of the first switch M1, the second switch M2, the third switch M3, and the fourth switch M4, and is not limited by the controller 310. Therefore, selecting switches with high drive capacity can improve the load capacity of the home bus to cope with harsh application scenarios such as a large number of connected nodes (including indoor and outdoor units) and long lines.

[0166] In this embodiment of the invention, simple logical operations are used to generate logic control sub-signals that control the corresponding switching transistors, and the driving function of the switching transistors is used to generate differential level signals. Compared with the prior art that uses dedicated communication chips, the HBS communication circuit in this embodiment of the invention has a simple circuit structure, is easy to implement, and can reduce system costs.

[0167] After introducing the circuit structure of the transmitting unit 4201, the circuit structure of the receiving unit 4202 in the HBS communication circuit 420 will be described in detail below:

[0168] In one or more embodiments, such as Figure 8 As shown, the receiving unit 4202 includes a first capacitor C1, a second capacitor C2, a ninth resistor R9, and a tenth resistor R10, wherein:

[0169] The first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 serve as the input terminals of the receiving unit 4202 for receiving bus signals.

[0170] The second terminal of the first capacitor C1 is electrically connected to the first terminal of the ninth resistor R9, and the second terminal of the second capacitor C2 is electrically connected to the first terminal of the tenth resistor R10.

[0171] The second terminals of the ninth resistor R9 and the tenth resistor R10 serve as the output terminals of the receiving unit 4202, used to output bus signals (HBS_RXN, HBS_RXP).

[0172] In specific implementation, such as Figure 8 As shown, the first terminal of the first capacitor C1 is electrically connected to the first bus, and the first terminal of the second capacitor C2 is electrically connected to the second bus.

[0173] In this embodiment of the invention, since the controller 410 integrates an HBS function module, the receiver unit 4202, which is composed of a simple resistor-capacitor circuit, can receive the bus signal. The circuit is simple and easy to implement.

[0174] In one or more embodiments, such as Figure 9 As shown, the HBS communication circuit 420 also includes a DC blocking unit 4203; wherein, the DC blocking unit 4203 is connected in series between the transmitting unit 4201 and the home bus, and is used to block the DC component in the differential level signal and send the differential level signal after blocking the DC component to the home bus.

[0175] In one or more embodiments, such as Figure 10 As shown, the DC blocking unit 4203 includes a third capacitor C3, a fourth capacitor C4, an eleventh resistor R11, and a twelfth resistor R12, wherein:

[0176] The first terminal of the third capacitor C3 is electrically connected to the first terminal of the eleventh resistor R11 and is used to receive the first level sub-signal BUS1; the second terminal of the third capacitor C3 and the second terminal of the eleventh resistor R11 are both electrically connected to the first bus.

[0177] The first terminal of the fourth capacitor C4 is electrically connected to the first terminal of the twelfth resistor R12 to receive the second level sub-signal BUS2; the second terminal of the fourth capacitor C4 and the second terminal of the twelfth resistor R12 are both electrically connected to the second bus.

[0178] After describing the various possible structures of the air conditioner 400 in the embodiments of the present invention, the following is based on... Figure 10 The structure shown illustrates the working principle of this air conditioner 400, specifically as follows: Figure 11 Execution steps in:

[0179] In step S1101, the controller 410 obtains data to be sent from an external device or generates data internally.

[0180] In specific implementation, such as Figure 12 As shown, the data to be transmitted can be serial data in UART format, where start is used to characterize the start bit of the serial data.

[0181] In step S1102, the controller 410 performs superimposed baud rate clock signal processing on the UART Data to be transmitted to obtain intermediate data.

[0182] In specific implementation, such as Figure 12 As shown, 0s in the data to be transmitted are encoded using a 50% low-level and 50% high-level format, while 1s are encoded using a 100% high-level format, thus obtaining the intermediate data.

[0183] In step S1103, the controller 410 performs data conversion processing on the intermediate data through the HBS function module to generate the first drive sub-signal DRVA and the second drive sub-signal DRVB.

[0184] In step S1104, the transmitting unit 4201 receives the first driving sub-signal DRVA and the second driving sub-signal DRVB, and generates multiple logic control sub-signals according to the level states of the first driving sub-signal DRVA and the second driving sub-signal DRVB through the logic control sub-unit 510.

[0185] In step S1105, the transmitting unit 4201, through the driving sub-unit 520 and under the control of multiple logic control sub-signals, generates a first level sub-signal BUS1 and a second level sub-signal BUS2. The first level sub-signal BUS1 is processed by the DC blocking unit 4203 and then sent to the first bus in the home bus. The second level sub-signal BUS2 is processed by the DC blocking unit 4203 and then sent to the second bus in the home bus.

[0186] In specific implementation, such as Figure 12 As shown, when the first drive sub-signal DRVA is 0 and the second drive sub-signal DRVB is 1, the first level sub-signal BUS1 is high and the second level sub-signal BUS2 is low. At this time, the differential level BUS on the home bus is high.

[0187] When the first drive sub-signal DRVA is 0 and the second drive sub-signal DRVB is 0, the first level sub-signal BUS1 is at the middle level and the second level sub-signal BUS2 is at the middle level. At this time, the differential level BUS on the home bus is at the middle level.

[0188] When the first drive sub-signal DRVA is 1 and the second drive sub-signal DRVB is 0, the first level sub-signal BUS1 is low and the second level sub-signal BUS2 is high. At this time, the differential level BUS on the home bus is low.

[0189] In step S1106, the home bus generates a bus signal based on the first level sub-signal BUS1 and the second level sub-signal BUS2, and according to the HBS communication protocol.

[0190] In step S1107, the receiving unit 4202 acquires the bus signal and transmits the bus signal to the controller 410.

[0191] In step S1108, the controller 410 processes the bus signal through the HBS function module to obtain the target data in order to achieve data communication.

[0192] Based on the same concept, this embodiment of the invention also provides a communication method for an air conditioner, which is applied to the air conditioner provided in any of the above embodiments. Since this method is the same method executed by the air conditioner in this embodiment of the invention, and the principle of solving the problem by this method is similar to that of the air conditioner, the implementation of this method can refer to the implementation of the air conditioner, and the repeated parts will not be described again.

[0193] like Figure 13 As shown, the method includes the following steps:

[0194] Step S1301: The controller performs data conversion processing on the data to be sent and outputs a drive signal;

[0195] Step S1302: Under the control of the drive signal, a differential level signal is output to the home bus through the HBS communication circuit of the home bus system;

[0196] Step S1303: Obtain bus signal from home bus through HBS communication circuit and send bus signal to controller, wherein bus signal is generated by home bus based on differential level signal;

[0197] Step S1304: The controller parses and processes the bus signal to obtain the target data.

[0198] In specific implementations, in the embodiments of the present invention, the air conditioner can be a household air conditioner, a commercial air conditioner, or other similar products. Other essential components of this air conditioner are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting the present invention.

[0199] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0200] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An air conditioner, characterized in that, Includes the controller, HBS communication circuitry for the home bus system, and the home bus, among which: The controller is connected to the home bus via the HBS communication circuit, which includes a transmitting unit and a receiving unit. The controller is used to perform data conversion processing on the data to be sent, output drive signals, and parse bus signals to obtain target data. The HBS communication circuit is used to receive the drive signal through the transmitting unit, and under the control of the drive signal, output a differential level signal to the home bus. The receiving unit acquires the bus signal from the home bus and sends the bus signal to the controller. The home bus is used to generate the bus signal based on the differential level signal.

2. The air conditioner as described in claim 1, characterized in that, The transmitting unit includes a logic control subunit and a driver subunit, wherein: The logic control subunit is electrically connected to the drive subunit; The logic control subunit is used to receive the drive signal and generate a logic control signal according to the level state of the drive signal; The driving subunit is used to output the differential level signal under the control of the logic control signal.

3. The air conditioner as described in claim 2, characterized in that, The driving signal includes a first driving sub-signal and a second driving sub-signal; the logic control sub-unit includes a first logic control branch and a second logic control branch arranged in parallel, wherein: The first logic control branch is used to generate a first logic control sub-signal based on the level state of the first driving sub-signal and the level state of the second driving sub-signal, and to generate a second logic control sub-signal based on the level state of the first driving sub-signal. The second logic control branch is used to generate a third logic control sub-signal based on the level state of the first driving sub-signal and the level state of the second driving sub-signal, and to generate a fourth logic control sub-signal based on the level state of the second driving sub-signal. The logic control signal includes the first logic control sub-signal, the second logic control sub-signal, the third logic control sub-signal, and the fourth logic control sub-signal.

4. The air conditioner as described in claim 3, characterized in that, The first logic control branch includes a first NOR gate, a first OR gate, a first resistor, and a second resistor, wherein: The first input terminal of the first NOR gate is electrically connected to the first input terminal of the first OR gate and the first terminal of the second resistor, respectively, for receiving the first driving sub-signal; The second input terminal of the first NOR gate is used to receive the second driving sub-signal, and the output terminal of the first NOR gate is electrically connected to the second input terminal of the first OR gate. The output terminal of the first OR gate is electrically connected to the first terminal of the first resistor; The second end of the first resistor is used to output the first logic control sub-signal, and the second end of the second resistor is used to output the second logic control sub-signal.

5. The air conditioner as described in claim 3, characterized in that, The second logic control branch includes a second NOR gate, a second OR gate, a third resistor, and a fourth resistor, wherein: The first input terminal of the second NOR gate is electrically connected to the first input terminal of the second OR gate and the first terminal of the fourth resistor, respectively, for receiving the second driving sub-signal; The second input terminal of the second NOR gate is used to receive the first driving sub-signal, and the output terminal of the second NOR gate is electrically connected to the second input terminal of the second OR gate; The output terminal of the second OR gate is electrically connected to the first terminal of the third resistor; The second end of the third resistor is used to output the third logic control sub-signal, and the second end of the fourth resistor is used to output the fourth logic control sub-signal.

6. The air conditioner as described in claim 3, characterized in that, The differential level signal includes a first level sub-signal output to the first bus in the home bus, and a second level sub-signal output to the second bus in the home bus; The drive subunit includes a first drive branch and a second drive branch arranged in parallel, wherein: The first driving branch is used to output the first level sub-signal under the control of the first logic control sub-signal and the second logic control sub-signal; The second driving branch is used to output the second level sub-signal under the control of the third logic control sub-signal and the fourth logic control sub-signal.

7. The air conditioner as described in claim 6, characterized in that, The first driving branch includes a first switching transistor, a second switching transistor, a fifth resistor, and a sixth resistor, wherein: The control terminal of the first switch is used to receive the first logic control sub-signal. The first terminal of the first switch and the first terminal of the fifth resistor are used to receive the power supply voltage. The second terminal of the first switch is electrically connected to the first terminal of the second switch, the second terminal of the fifth resistor, and the first terminal of the sixth resistor, respectively, for outputting the first level sub-signal. The control terminal of the second switch is used to receive the second logic control sub-signal, and the second terminal of the second switch and the second terminal of the sixth resistor are grounded.

8. The air conditioner as described in claim 6, characterized in that, The second drive branch includes a third switch, a fourth switch, a seventh resistor, and an eighth resistor, wherein: The control terminal of the third switch is used to receive the third logic control sub-signal. The first terminal of the third switch and the first terminal of the seventh resistor are used to receive the power supply voltage. The second terminal of the third switch is electrically connected to the first terminal of the fourth switch, the second terminal of the seventh resistor, and the first terminal of the eighth resistor, respectively, for outputting the second level sub-signal. The control terminal of the fourth switch is used to receive the fourth logic control sub-signal, and the second terminal of the fourth switch and the second terminal of the eighth resistor are grounded.

9. The air conditioner as described in any one of claims 1 to 8, characterized in that, The receiving unit includes a first capacitor, a second capacitor, a ninth resistor, and a tenth resistor, wherein: The first terminal of the first capacitor and the first terminal of the second capacitor serve as the input terminals of the receiving unit, used to receive the bus signal; The second terminal of the first capacitor is electrically connected to the first terminal of the ninth resistor, and the second terminal of the second capacitor is electrically connected to the first terminal of the tenth resistor. The second end of the ninth resistor and the second end of the tenth resistor serve as the output terminals of the receiving unit, used to output the bus signal.

10. A communication method for an air conditioner, characterized in that, Applied to an air conditioner as described in any one of claims 1 to 9, the method comprises: The controller performs data conversion processing on the data to be sent and outputs drive signals. Under the control of the drive signal, a differential level signal is output to the home bus via the HBS communication circuit of the home bus system; The bus signal is obtained from the home bus through the HBS communication circuit and sent to the controller, wherein the bus signal is generated by the home bus based on the differential level signal; The controller parses and processes the bus signals to obtain the target data.

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