A method for testing the electrical conductivity of a chip interconnect material

Abstract

The application discloses a method for testing the conductive performance of a chip interconnection material, which comprises the following steps: forming a sintering layer pattern on an insulating substrate, wherein the sintering layer pattern comprises an interconnection layer pattern and two test leads respectively extending outward from two width edges of the interconnection layer pattern; placing a cover chip on the interconnection layer pattern, wherein the length edge of the cover chip is equal in length to and aligned with the length edge of the interconnection layer pattern, and the width edge of the cover chip is equal in length to and aligned with the width edge of the interconnection layer pattern; sintering the interconnection layer pattern and the two test leads under predetermined sintering conditions; respectively measuring the thickness of the sintered interconnection layer pattern and the test lead area; measuring the resistance value between the two test leads; and calculating the resistivity in the interconnection layer pattern according to the measured thickness, resistance value and a correction factor determined by the length and width parameters of the sintering layer pattern. The technical scheme of the application can accurately evaluate the resistivity of the interconnection material under the condition of reproducing the solvent volatilization path in actual installation.

Description

Technical Field

[0001] This invention relates to the field of resistivity testing technology for interconnect materials, and more particularly to a method for testing the conductivity of chip interconnect materials. Background Technology

[0002] As chips become increasingly smaller, their integration and power density are also increasing. Consequently, chip operating temperatures are rising, making the heat dissipation capabilities of packaging structures increasingly crucial. As a vital bridge connecting the chip and the heat dissipation structure, the thermal conductivity of chip interconnect materials is receiving growing attention. The thermal conductivity and electrical conductivity of metallic materials are highly correlated, making the measurement of the resistivity of interconnect materials an important basis for evaluating their thermal conductivity. A common method involves fabricating the interconnect material into a square thin-film pattern, then measuring the sheet resistance of the film using the four-probe method, and finally measuring the film thickness to calculate its resistivity.

[0003] However, this testing method has a problem: the solvent in the interconnect material paste can evaporate directly from above the thin film pattern. In actual use, due to the chip covering it, the solvent can only evaporate from the edges of the paste, and the evaporation rate gradually decreases with increasing chip size. Even using the same curing temperature profile, differences in solvent evaporation conditions can cause significant differences in material sintering. On the one hand, different temperatures at which solvent evaporation is complete result in different proportions of different sintering mechanisms occurring during material heating and curing. The interconnect material covered by the chip may be more porous or denser than the thin film pattern. On the other hand, some solvent in the interconnect material covered by the chip may not have completely evaporated, or even remain in large quantities, forming voids and defects. In this case, using the resistivity of the thin film pattern to describe the material's electrical and thermal conductivity is inappropriate. Therefore, if the differences in solvent evaporation paths can be eliminated, the measured resistivity will more accurately reflect the electrical and thermal conductivity of the interconnect layer under different sintering conditions and chip sizes. Summary of the Invention

[0004] The main objective of this invention is to solve the technical problem that the resistivity measured by the existing four-probe method for evaluating the resistivity of interconnect materials is difficult to accurately reflect the electrical / thermal conductivity of the interconnect layer under different chip sizes and sintering conditions.

[0005] To achieve the above objectives, embodiments of this application provide a method for testing the conductivity of chip interconnect materials, including:

[0006] A sintered layer pattern is formed on an insulating substrate, the sintered layer pattern including an interconnect layer pattern and two test leads extending outward from the two width sides of the interconnect layer pattern, respectively;

[0007] A cover chip is placed on the interconnect layer pattern, wherein the length side of the cover chip is equal to and aligned with the length side of the interconnect layer pattern, and the width side of the cover chip is equal to and aligned with the width side of the interconnect layer pattern.

[0008] The interconnect layer pattern and the two test leads are sintered according to predetermined sintering conditions;

[0009] The thicknesses of the interconnect layer pattern and the test lead area after sintering were measured respectively.

[0010] Measure the resistance between the two test leads;

[0011] The resistivity within the interconnect layer pattern is calculated based on the measured thickness, resistance value, and correction factors determined by the length and width parameters of the sintered layer pattern.

[0012] The technical solution provided in this application constructs the structure under test (SUT) with boundary conditions consistent with the actual packaging and completes quantization calculations. Specifically, an interconnect layer pattern is formed on an insulating substrate, and two test leads are formed by extending outward from its two width sides; a cover chip is placed on the interconnect layer pattern, with its length side aligned and equal in length to the length side of the interconnect layer pattern, and its width side aligned and equal in length to the width side of the interconnect layer pattern; the interconnect layer pattern and the two test leads are sintered under predetermined sintering conditions; the thickness of the sintered interconnect layer pattern and the thickness of the test lead region are obtained respectively, and the resistance value between the two test leads is measured; the resistivity within the interconnect layer pattern is calculated by combining the measured thickness, resistance value, and correction factors determined by the length and width parameters of the interconnect layer pattern and the test leads.

[0013] The above process addresses the inconsistency between solvent evaporation directly above the chip and evaporation from the coated edges. Aligning the edges of the chip and interconnect pattern creates a top-level coverage boundary, allowing solvent to escape only along the edges. This evaporation path mirrors the chip coverage in the package, and its length varies with the pattern width. This reconstructs the same evaporation rate, densification rhythm, and porosity formation conditions as in actual applications during sintering. Test leads are positioned along the width edge, ensuring current flows through the covered area along the length of the interconnect pattern during measurement, avoiding current distribution deviations caused by lateral current diversion. The thicknesses of the interconnect pattern and test leads are measured separately, enabling subsequent calculations to distinguish the cross-sectional differences between the covered and lead areas. A correction factor determined by length and width parameters is then used to geometrically eliminate current diffusion in the lead series portion and transition region of the end-to-end resistance, extracting the equivalent number of blocks in the covered area and converting it to resistivity. The resulting resistivity corresponds to the sintering density and porosity characteristics under actual packaging conditions, maintaining comparability and representativeness under different chip sizes and temperature profiles. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of an embodiment of the conductivity performance testing method for chip interconnect materials according to the present invention;

[0016] Figure 2 This is a schematic diagram of the structures involved in the testing process of this invention;

[0017] Figure 3 A schematic diagram showing the names of the various dimensions of the structures involved in the testing process;

[0018] Figure 4 The graph of the C value as a function of D0 / D1.

[0019] Explanation of icon numbers:

[0020] 1. Cover chip; 2. Interconnect layer pattern; 3. Test leads; 4. Insulating substrate

[0021] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0023] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0024] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the term "and / or" throughout the text includes three solutions; taking A and / or B as an example, it includes technical solution A, technical solution B, and a technical solution that simultaneously satisfies A and B. Furthermore, the technical solutions of various embodiments can be combined with each other, provided that they are feasible for those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0025] One embodiment of this application provides a method for testing the conductivity of chip interconnect materials. Figure 1 This is a flowchart illustrating a method for testing the conductivity of chip interconnect materials according to an embodiment of this application. In this embodiment, the method includes:

[0026] A sintering layer pattern is formed on an insulating substrate 4. The sintering layer pattern includes an interconnect layer pattern 2 and two test leads 3 extending outward from the two width sides of the interconnect layer pattern 2, respectively.

[0027] A cover chip 1 is placed on the interconnect layer pattern 2, wherein the length side of the cover chip 1 is equal to and aligned with the length side of the interconnect layer pattern 2, and the width side of the cover chip 1 is equal to and aligned with the width side of the interconnect layer pattern 2.

[0028] The interconnect layer pattern 2 and the two test leads 3 are sintered according to the predetermined sintering conditions;

[0029] The thicknesses of the interconnect layer pattern 2 and the test lead 3 regions after sintering were measured respectively.

[0030] Measure the resistance between the two test leads 3;

[0031] The resistivity within the interconnect layer pattern 2 is calculated based on the measured thickness, resistance value, and correction factors determined by the length and width parameters of the sintered layer pattern.

[0032] Specifically, the interconnect layer pattern 2 and the test lead 3 are preferably printed or dispensed from the same batch of metal interconnect material paste to ensure that the composition and curing process are consistent. The material can be silver or copper sintering paste, metal brazing filler metal, or other all-metal systems suitable for pressureless or pressure sintering.

[0033] Please see Figure 2Subsequently, a cover chip 1 is placed on the interconnect layer pattern 2, aligning its two length sides with the two length sides of the interconnect layer pattern 2, and the same applies to its width side. Placement can be done manually, using a jig, or with a surface mount device. Alignment is achieved using machine vision with alignment marks on the substrate / pattern. If necessary, height-limiting spacers can be used to control parallelism and prevent local thickness anomalies caused by compression. The cover chip 1 can be an inert cover material (such as silicon, ceramic, or glass sheet) with the same shape as the target chip, or it can be the functional chip body itself; both serve as the upper cover boundary in this method to allow solvent to escape from the periphery of the pattern. If the interconnect layer pattern 2 is not a standard rectangle, the "width side" can be understood as a pair of equivalent opposite sides orthogonal to the main current channel, and two test leads 3 are set on these equivalent opposite sides. The cover chip 1 is then selected from a cover material with the same or equivalent shape as the planar shape, so that it coincides with the pattern boundary under planar projection, thereby maintaining a consistent definition of the evaporation channel.

[0034] After placement, the interconnect layer pattern 2 and the two test leads 3 are sintered according to predetermined sintering conditions. The sintering conditions correspond to the temperature-time curve, atmosphere, and pressure mode used in the packaging process, specifically, pressureless sintering under an inert atmosphere or pressure-assisted sintering. After sintering, the thickness of the interconnect layer pattern 2 and the test lead 3 regions are measured respectively. The thickness measurement is based on the substrate surface to obtain the average value of the region, which is used to reflect the difference in volatilization path and densification between the covered and uncovered areas. Subsequently, the resistance value is obtained between the two test leads 3. Since the test leads 3 and the interconnect layer pattern 2 are integrally formed, the measured end-to-end resistance includes the series contribution of the lead segment and the covered area, as well as the current diffusion effect caused by the geometric transition. Therefore, a correction factor determined by the length and width parameters of the interconnect layer pattern 2 and the test leads 3 is introduced in the subsequent calculation, and combined with the aforementioned thickness and resistance value, the resistivity within the interconnect layer pattern 2 is obtained. By establishing the coverage boundary, the solvent evaporation path is restricted to lateral edge escape, consistent with the actual packaging. By arranging integrated test leads 3 on the width side and independently measuring the thickness of each region, the resistance conversion can isolate the influence of lead segments and geometric transitions, and only restore the equivalent number of blocks in the coverage area. Therefore, the obtained resistivity corresponds to the actual densification state under different chip sizes and different temperature rise curves, and can be used to reliably compare the conductivity of interconnect materials and the thermal conductivity inferred from them.

[0035] In one embodiment of the present invention, the insulating substrate 4 is made of a rigid material and has a uniform thickness.

[0036] It should be noted that in this method, the insulating substrate 4 not only serves as the base for carrying the interconnect layer pattern 2, but also defines the sintering conditions and provides a geometric reference. The insulating substrate 4 is made of a rigid material, typically silicon wafers, ceramic wafers, alumina substrates, glass wafers, etc. These materials have high dimensional stability during heating and will not cause geometric deformation of the interconnect layer pattern 2 due to thermal expansion or softening, thus ensuring that the alignment between the cover chip 1 and the interconnect layer pattern 2 remains consistent during the sintering process. The use of rigid materials can also effectively prevent warping or local collapse of the substrate under pressure sintering conditions, avoiding distortion of the thickness distribution in the test area.

[0037] Uniform thickness ensures a consistent reference plane across the entire substrate surface during sintering and measurement. When using the substrate surface as a reference for thickness measurement, significant variations in substrate thickness can introduce measurement errors and affect resistivity calculations. Thickness uniformity also helps maintain consistent overall thermal conduction and heat dissipation conditions, ensuring that the interconnect materials are heated as uniformly as possible across different regions, thus avoiding localized temperature gradients caused by substrate thickness differences that could affect the sintering density of the material.

[0038] Therefore, the use of rigid materials and uniform thickness of the insulating substrate 4 can provide reliable support for subsequent steps in terms of mechanical strength, thermal stability and measurement accuracy, so that the interconnect layer pattern 2 can maintain consistency and repeatability during formation, sintering and electrical testing, thereby improving the accuracy and comparability of resistivity measurement results.

[0039] In one embodiment of the present invention, the surface of the insulating substrate 4 that contacts the interconnect layer pattern 2 is a polished surface.

[0040] Interconnect materials are typically deposited on the substrate surface in slurry or paste form, requiring a uniform adhesion interface from the substrate surface during molding and sintering. If the substrate surface is rough or uneven, the slurry may accumulate locally or have uneven thickness during deposition, leading to inaccurate thickness measurements after sintering and errors in resistivity calculations. Polishing significantly improves the flatness of the substrate surface, resulting in more uniform spreading of the interconnect layer pattern 2 and ensuring consistent thickness distribution.

[0041] Furthermore, a smooth interface reduces the formation of interfacial gaps and voids, improving the adhesion between the interconnect layer pattern 2 and the substrate, and minimizing interference from the bottom interface when the solvent evaporates from the edges during heating. This adhesion is particularly important after the cover chip 1 is placed, as the sintering state of the interconnect material is highly dependent on the solvent evaporation path and the uniformity of material heating. The polished surface ensures that no additional non-uniformity is introduced from the substrate side, allowing the sintered structure to more accurately reflect the morphology and density of the interconnect layer under chip packaging conditions.

[0042] Therefore, processing the side of the insulating substrate 4 that contacts the interconnect layer pattern 2 into a polished surface can improve the forming quality and thickness uniformity of the interconnect layer pattern 2, and at the same time provide a stable and reliable basis for subsequent thickness measurement and resistivity calculation, thereby improving the accuracy and repeatability of the entire test method.

[0043] It should be noted that various processing methods can be used to form the polished surface of the insulating substrate 4, depending on the characteristics of different materials. If the substrate is a silicon wafer, the mature chemical mechanical polishing method in semiconductor technology can be used to remove microscopic protrusions on the surface through the synergistic effect of abrasive and chemical reaction, resulting in a surface with high flatness and low roughness. If the substrate is ceramic or glass, mechanical grinding combined with fine polishing slurry treatment can be used, supplemented by chemical etching polishing if necessary, to achieve a uniform and smooth interface. For hard ceramics such as alumina and aluminum nitride, diamond grinding discs or ultrasonic vibration polishing can also be used to achieve the flatness requirements that meet the slurry spreading and thickness uniformity requirements.

[0044] The surface roughness of the polished surface obtained by the above process can usually be controlled at the micron or submicron level. Such flatness ensures that the interconnect material paste can be evenly spread and tightly adhered to the substrate surface during deposition, thereby establishing stable interface conditions for subsequent sintering and electrical testing.

[0045] In one embodiment of the present invention, the cover chip 1 is made of a rigid material and has a uniform thickness.

[0046] In this method, the cover chip 1 is made of a rigid material and maintains a uniform thickness, primarily to more accurately simulate the actual chip packaging conditions during testing. After the cover chip 1 is placed on the interconnect layer pattern 2, its main function is to limit the solvent evaporation path of the interconnect material, ensuring that the solvent can only slowly escape from the edges of the interconnect layer pattern 2, rather than evaporating directly upwards like an exposed film. Only when the cover chip 1 possesses sufficient hardness and dimensional stability can it maintain a tight fit with the interconnect layer pattern 2 during the sintering heating process, preventing warping or gaps due to thermal stress or its own deformation, thus ensuring the authenticity and consistency of the coverage state.

[0047] If the chip thickness varies, local tilting or uneven contact may occur during placement, altering the pressure distribution and solvent escape path within the interconnect material and affecting sintering density. Uniform thickness ensures a parallel and stable coverage relationship between the entire chip 1 and the interconnect layer pattern 2, avoiding structural stress concentration or test condition deviations caused by local thickness unevenness.

[0048] The cover chip 1 can be a specially fabricated "dummy chip," such as a standard rigid material like a silicon wafer, glass sheet, or ceramic sheet, or it can be a real functional chip. The former facilitates the reproducible construction of the test environment under laboratory conditions, while the latter more closely resembles the operating conditions under actual packaging. Regardless of the form used, the requirements for rigid materials and thickness uniformity ensure that the cover chip 1 provides stable and repeatable boundary conditions during testing, thereby making the resistivity test results more representative and reliable.

[0049] In one embodiment of the present invention, the surface of the cover chip 1 that contacts the interconnect layer pattern 2 is a polished surface. This is to ensure that the cover chip 1 can fit tightly against the interconnect layer pattern 2 during placement, without creating local gaps. If the contact surface is rough or uneven, the interconnect paste is prone to forming localized voids or uneven thickness during sintering, leading to unstable solvent escape paths and affecting the accuracy of test results. Therefore, preparing the contact surface of the cover chip 1 as a polished surface can significantly improve the interface bonding quality, making the state of the interconnect layer during actual heating and densification processes closer to the real packaging environment.

[0050] A polished surface can be obtained through various methods. For cases where a silicon wafer is used as the cover chip 1, chemical mechanical polishing (CMP), a common process in semiconductor manufacturing, can be used to remove microscopic protrusions on the surface through abrasive particles and chemical reactions, resulting in a highly smooth surface. For glass or ceramic cover chips 1, a smooth and flat interface can be obtained by combining mechanical grinding with fine polishing slurry treatment, followed by chemical polishing or acid etching. If the cover chip 1 is made of metal or other high-hardness materials, diamond grinding, ion beam polishing, or ultrasonic-assisted polishing can be used. Through these processes, the contact surface of the cover chip 1 can achieve micron-level or even submicron-level surface flatness, enabling a stable and uniform bonding state when covering the interconnect layer pattern 2, thereby ensuring the reliability and repeatability of subsequent electrical tests.

[0051] In one embodiment of the present invention, the resistivity ρ within the interconnect layer pattern 2 is calculated using the following formula:

[0052] ;

[0053] Wherein, R is the resistance value between the two test leads 3, L0 is the length of the cover chip 1, D0 is the width of the cover chip 1, and L0≥D0, T0 is the thickness of the interconnect layer pattern 2 after sintering, L0 is the length of the test lead 3 after sintering, D1 is the width of the test lead 3 after sintering, T1 is the thickness of the test lead 3 after sintering, and C is a correction factor determined according to the ratio of D0 to D1.

[0054] Please see Figure 3 and Figure 4 The meaning of each parameter and how to obtain it are as follows:

[0055] R is the resistance value measured between the two test leads 3. This value can be obtained by directly contacting the midpoint of the two test leads 3 with a probe station and measuring it with a resistance meter, or by soldering leads onto the test leads 3 and then connecting them to a four-terminal measurement system.

[0056] L0 is the length of the cover chip 1. This parameter can be determined directly by the design dimensions of the cover chip 1, or the length of the area covered by the interconnect layer pattern 2 can be measured by a microscope or image measuring instrument after the chip is placed.

[0057] D0 represents the width of the coverage area for chip 1. This value can be obtained directly from the chip layout design data, or it can be measured using optical measurement methods such as a contour projector or a scanning electron microscope.

[0058] T0 represents the thickness of interconnect layer pattern 2 after sintering. This value can be obtained by measuring the cross-section under a microscope after slicing, or by using non-destructive testing methods such as white light interferometer or laser confocal microscope to scan and measure the local thickness.

[0059] L0 represents the length of test lead 3 after sintering. This parameter can be measured directly through the pattern boundary under an optical microscope, or it can be read from the design drawing of the test mask or printing plate.

[0060] D1 is the width of test lead 3 after sintering. This parameter can also be directly measured by an image measuring device, or it can be obtained before sintering based on the design dimensions of the printed pattern and corrected for the sintering shrinkage rate.

[0061] T1 represents the thickness of test lead 3 after sintering. This value can be obtained by observing and measuring the test lead 3 area using an electron microscope after local slicing, or by non-destructive testing using equipment such as a profilometer or laser interferometer.

[0062] C is a correction factor, the value of which is determined based on the ratio of the width D0 of the cover chip 1 to the width D1 of the test lead 3. (See attached image) Figure 4 The curve showing the relationship between the correction factor C and the ratio of D0 to D1 is presented. When the ratio of D0 to D1 is small, the current diffusion effect is significant, and the correction factor is close to zero. As the ratio of D0 to D1 increases, the correction factor gradually increases and eventually tends to saturate. This curve can provide corresponding correction values ​​for interconnect layer patterns 2 and lead structures with different geometric ratios, ensuring that the influence of geometric current diffusion can be eliminated in resistivity calculations.

[0063] The resistivity calculation using this formula not only considers the resistance contribution of the interconnect layer pattern 2 region, but also incorporates the influence of the length, width, and thickness differences of the test lead 3 on the overall resistance, and compensates for the current diffusion effect through a correction factor. This avoids miscalculating the series resistance and geometric factors of the leads into the resistivity of the interconnect layer, thus making the calculation results more accurately reflect the conductivity of the interconnect layer material itself under the condition of covering chip 1. This method maintains good applicability and accuracy under different chip sizes and different geometric parameters of the test lead 3, improving the reliability of conductivity performance testing.

[0064] In one embodiment of the present invention, the test lead 3 extends outward from the width edge of the interconnect layer pattern 2 by a length of 1 mm to 3 mm.

[0065] If the extension length is too short, for example less than 1 mm, then during the actual test, the contact position between the probe or lead and the test lead 3 is too close to the main body of the interconnect layer pattern 2, which is easily blocked and interfered with by the edge of the covered chip 1, resulting in insufficient contact stability. Furthermore, the diffusion of the test current before entering the interconnect layer area has not been fully completed, thus making the measured resistance value unstable.

[0066] Conversely, if the extension length is too long, for example, exceeding 3 mm, the series resistance of the test lead 3 itself increases significantly, easily accounting for a large proportion of the total measured resistance. Even if compensation is made subsequently through a correction factor, additional uncertainty will be introduced. Furthermore, excessively long leads increase the error caused by uneven sintering shrinkage and thickness variations, reducing the accuracy of the resistivity calculation in the interconnect layer region.

[0067] By limiting the extension length of the test lead 3 to the range of 1mm to 3mm (in actual implementation, it can be 1mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm, 1.5mm, 1.6mm, 1.7mm, 1.8mm, 1.9mm, 2mm, 2.1mm, 2.2mm, 2.3mm, 2.4mm, 2.5mm, 2.6mm, 2.7mm, 2.8mm, 2.9mm or 3mm), on the one hand, it ensures that the probe can obtain a stable contact platform during resistance measurement, avoiding excessively close interference with the interconnect layer body. On the other hand, it controls the contribution of the lead to the resistance value, ensuring that it is neither too small to lose contact stability, nor too large to obscure the true resistance characteristics of the interconnect layer pattern 2 area, thereby ensuring that the calculated resistivity can more accurately reflect the conductivity of the interconnect layer under chip coverage conditions.

[0068] In one embodiment of the present invention, the width of the test lead 3 is 0.5 mm to 1 mm.

[0069] When the width of test lead 3 is less than 0.5 mm, the printing, screen printing, or dispensing processes place high demands on the resolution and uniformity of the lines, which can easily lead to unstable line width or breakage. During sintering, excessively narrow leads may also break due to material shrinkage or sintering defects, affecting reliable contact with the test probe. In addition, narrow lines lack sufficient mechanical strength and are easily crushed when the probe contacts them, resulting in unstable contact resistance during the measurement process.

[0070] If the width of test lead 3 exceeds 1 mm, the current will diffuse laterally in the transition region between the lead and interconnect pattern 2, increasing the correction amount of the correction factor and complicating the calculation model. Wider leads will also introduce additional lateral current channels in the measurement, so that the end-to-end resistance value no longer reflects only the longitudinal resistance contribution of interconnect pattern 2, thereby reducing the accuracy of the test results.

[0071] Therefore, limiting the width of test lead 3 to 0.5mm to 1mm (in practice, it can be 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, or 1mm) not only ensures the integrity of the process and after sintering, but also provides sufficient platform size for probe contact, avoiding measurement deviations caused by excessively narrow or wide lines. Within this range, the contribution of lead resistance and the geometric current diffusion effect are both controllable. Combined with the compensation of the correction factor, this ensures that the final resistivity calculation is more reliable and stable.

[0072] In one embodiment of the present invention, electrical contact points are respectively set at the midpoints of the length directions of the two test leads 3, and the resistance value is the resistance measured between the two electrical contact points.

[0073] Specifically, if the electrical contact point is close to the boundary region between the test lead 3 and the interconnect layer pattern 2, the local current density distribution will be uneven due to the diffusion and convergence of current in this region. The measured resistance value will contain obvious boundary effects, which is not conducive to accurately separating the resistance contribution of the interconnect layer pattern 2 region. Conversely, if the electrical contact point is too close to the far end of the test lead 3, the resistance of the lead segment itself will account for a larger proportion of the total resistance, increasing the complexity of subsequent correction factor calculation and compensation. It may also lead to additional parasitic resistance due to excessive contact distance.

[0074] By placing the electrical contact point at the midpoint of the length of the two test leads 3, it ensures that the contact point is far from the boundary region of the interconnect layer pattern 2, avoiding interference from boundary diffusion effects on the measurement data. Furthermore, it avoids excessive lead resistance superposition, ensuring that the measured resistance value remains within a controllable correction range. This arrangement also maintains geometric symmetry in the contributions of the leads on both sides, thereby improving the repeatability of the measured resistance value and the representativeness of the resistivity of the interconnect layer region.

[0075] The implementation of electrical contacts can take many forms, such as direct contact with the lead surface via probes, or pre-soldering metal leads at the midpoint and then connecting them to external test circuitry. Regardless of the method used, this arrangement helps stabilize the current path and voltage sampling points, making the calculated resistivity closer to the actual electrical performance of the interconnect layer material under the condition of covering chip 1.

[0076] In one embodiment of the present invention, after sintering the interconnect layer pattern 2 and the two test leads 3 according to predetermined sintering conditions, the method further includes:

[0077] Remove the interconnect layer material located outside the orthographic projection formed by the cover chip 1 on the surface of the insulating substrate 4.

[0078] Specifically, the cover chip 1 forms a clear orthographic projection area on the surface of the insulating substrate 4. This area corresponds precisely to the part where the chip directly contacts the interconnect layer, and is also the effective working area of ​​the interconnect layer in actual operation. The interconnect layer material located outside the orthographic projection does not have a direct covering relationship with the chip in actual chip packaging applications. During the sintering process, its heating conditions and solvent evaporation paths differ from those of the covered area, often resulting in differences in sintering density and resistance characteristics compared to the interconnect layer under actual application conditions. Retaining this portion of material may introduce additional conductive paths during resistance measurements, thus affecting the accurate reflection of the resistivity of the interconnect layer region.

[0079] By removing the interconnect layer material located outside the chip projection, interference from the non-covered areas on the current distribution can be effectively avoided, allowing the current to flow primarily through the covered areas, thereby improving the relevance and accuracy of resistance measurements. This approach is equivalent to simulating the operating conditions of the interconnect layers in actual applications during testing, enabling measurement results to more closely approximate the electrical and thermal conductivity performance of interconnect materials under real chip packaging conditions.

[0080] The removal methods can be varied, including mechanical etching, laser removal, or selective chemical etching. These methods can effectively remove irrelevant materials while ensuring the integrity of the main interconnect layer area, thus ensuring that resistivity calculations are based on the effective interconnect layer area under chip 1.

[0081] Example 1:

[0082] The insulating substrate used in the test structure was a 10mm × 10mm × 0.4mm square single-sided polished silicon wafer, and the cover chip was a 4mm × 2mm × 0.4mm rectangular single-sided polished silicon wafer. The interconnect layer material was a high thermal conductivity pressureless sintered silver paste, which consisted of spherical silver nanoparticles, spherical submicron particles, and organic solvents. The sintered layer pattern was formed by printing with a 0.08mm thick stencil, with each test lead being 2mm long and 0.5mm wide.

[0083] Before placing the cover chip, its thickness is precisely measured using a thickness gauge to an accuracy of 0.001 mm. Alignment and placement of the cover chip and interconnect layer material are completed using a semi-automatic pick-and-place machine with a placement height set to 0.06 mm to ensure full contact between the cover chip and the interconnect layer.

[0084] The sintering process conditions are as follows: the furnace temperature is raised to 200℃ in air atmosphere and held for 30 minutes, with a heating rate of 5℃ / min.

[0085] After sintering, the interconnect layer material exceeding the orthographic projection of the cover chip is manually removed. The total thickness of the cover chip and interconnect layer after sintering is measured using a 3D optical profilometer, and the chip thickness is subtracted to obtain the interconnect layer thickness. At the same time, the thickness of the test lead area is measured to an accuracy of 0.001 mm.

[0086] The total resistance R between the test leads was then measured using a micro-ohmmeter, accurate to 0.001Ω, and the resistivity of the interconnect layer was calculated using the formula.

[0087] Example 2:

[0088] The difference from Example 1 is that the size of the cover chip is changed to 6mm×6mm×0.4mm, while the other conditions remain the same.

[0089] Example 3:

[0090] The difference from Example 1 is that the test structure does not include a cover chip. The interconnect layer material is directly printed and sintered on the insulating substrate. The sintering conditions and test methods are the same as in Example 1.

[0091] Example 4:

[0092] The difference from Example 1 is that a different pressureless sintering silver paste is used as the interconnect layer material. The main body of this silver paste consists of spherical submicron silver particles, spherical micron silver particles and organic solvent. The sintering conditions are: heating to 230°C in an air atmosphere and holding for 60 minutes, with a heating rate of 5°C / min. The other conditions are the same as in Example 1.

[0093] Comparative Example 1:

[0094] Unlike Example 1, instead of placing a cover chip, an 8mm × 8mm square interconnect layer pattern is directly printed on an insulating substrate, with a stencil thickness of 0.06mm.

[0095] The sintering conditions were the same as in Example 1. After sintering, the thickness of the interconnect layer pattern was measured using a 3D optical profilometer, and the sheet resistance of the solidified interconnect layer pattern was measured using a four-probe tester. The resistivity of the interconnect layer was then calculated by combining the thickness data.

[0096] Comparative Example 2:

[0097] It is basically the same as Comparative Example 1, except that the interconnect layer material and sintering conditions are the same as in Example 4.

[0098] The test results are shown in Table 1:

[0099]

[0100] The data in the table shows that comparing Example 4 and Comparative Example 2 with other results reveals that the test method provided in this patent is consistent with the traditional four-probe test method in terms of the strength of conductivity between different materials. Similarly, comparing Example 3 (without a covered chip) with Comparative Example 1 shows that the calculated resistivity is the closest among all results, indicating that the test method provided in this patent can obtain accurate interconnect layer resistivity values. Further comparing the results of Comparative Example 1 with Examples 1 and 2 shows that covering the chip does indeed affect the conductivity of the interconnect layer. This effect can be positive (as in Example 1) or negative (as in Example 2), which is related to factors such as the proportion of particle sintering mechanism and solvent residue. This indicates that the results measured using the method of this patent can reflect the actual conductivity of the interconnect layer caused by factors such as chip size and heating conditions. Compared with the traditional thin film pattern combined with four-probe test method, it can more accurately reflect the electrical and thermal conductivity of materials in a certain structure.

[0101] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A method for testing the electrical properties of a chip interconnect material, characterized by, The method comprises: forming a sintering layer pattern on an insulating substrate, the sintering layer pattern comprising an interconnection layer pattern and two test leads respectively extending outward from two width edges of the interconnection layer pattern; placing a cover chip on the interconnection layer pattern, wherein a length edge of the cover chip is equal in length to and aligned with a length edge of the interconnection layer pattern, and a width edge of the cover chip is equal in length to and aligned with a width edge of the interconnection layer pattern; sintering the interconnection layer pattern and the two test leads under predetermined sintering conditions; measuring the thickness of the sintered interconnection layer pattern and the test lead regions respectively; measuring the resistance value between the two test leads; calculating the resistivity in the interconnection layer pattern according to the measured thickness, resistance value, and a correction factor determined by the length and width parameters of the sintering layer pattern, the calculation of the resistivity in the interconnection layer pattern ρ using the following formula: ； wherein R is the resistance value between the two test leads, L0 is the length of the cover chip, D0 is the width of the cover chip, and L0≥D0, T0 is the thickness of the sintered interconnection layer pattern, L1 is the length of the sintered test lead, D1 is the width of the sintered test lead, T1 is the thickness of the sintered test lead, and C is a correction factor determined according to the ratio of D0 to D1.

2. The method for testing the electrical properties of a chip interconnect material according to claim 1, wherein, The insulating substrate is made of hard material and has a uniform thickness.

3. The method for testing the electrical properties of a chip interconnect material according to claim 1, wherein, The surface of the insulating substrate in contact with the interconnection layer pattern is a polished surface.

4. The method for testing the electrical properties of a chip interconnect material according to claim 1, wherein, The cover chip is made of hard material and has a uniform thickness.

5. The method for testing the electrical properties of a chip interconnect material according to claim 1, wherein, The surface of the cover chip in contact with the interconnection layer pattern is a polished surface.

6. The method for testing the electrical properties of a chip interconnect material according to claim 1, wherein, The test leads extend outward from the width edges of the interconnection layer pattern by a length of 1mm to 3mm.

7. The method for testing the electrical properties of a chip interconnect material according to claim 1, wherein, The width of the test leads is 0.5mm to 1mm.

8. The method for testing the electrical properties of a chip interconnect material according to claim 1, wherein, Electrical contact points are respectively provided at the lengthwise midpoints of the two test leads, and the resistance value is measured between the two electrical contact points.

9. The method for testing the electrical properties of a chip interconnect material according to claim 1, wherein, After sintering the interconnection layer pattern and the two test leads under predetermined sintering conditions, the method further comprises: removing the interconnection layer material outside the orthographic projection of the cover chip on the surface of the insulating substrate.

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