Extreme environment test method and system for power semiconductor

Abstract

The invention relates to the technical field of semiconductor testing, in particular to an extreme environment testing method and system for a power semiconductor, and the method comprises the steps: determining the extreme temperature, extreme humidity and peak current based on a semiconductor, an analyzer and a thermal infrared imager, fixing the semiconductor on a testing platform in a testing environment, obtaining a fixed semiconductor, and carrying out the testing of the fixed semiconductor; determining a target control box and a target cycle index based on the extreme temperature, the extreme humidity and the temperature and humidity control box; a termination semiconductor and a final cycle index are determined based on a standard threshold voltage, a standard on resistance, a standard leakage current, a peak current, a power cycle device in a test environment, a plurality of cycle index test values and a target semiconductor. And determining the extreme environment parameters of the semiconductor based on the termination semiconductor, the extreme temperature, the extreme humidity, the peak current and the final cycle times, and completing the extreme environment test of the power semiconductor. According to the invention, the reliability of the power semiconductor extreme environment test can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and in particular to an extreme environment testing method and system for power semiconductors. Background Technology

[0002] With the development of modern industry, power semiconductor devices, as core components in power electronic systems, are widely used in new energy vehicles, photovoltaics, and industrial control. As application scenarios become more complex, these devices often suffer from the combined effects of extreme environments such as high temperature, high humidity, and high current during long-term operation, and their reliability issues have gradually become a key factor affecting system stability and safety.

[0003] Existing power semiconductor testing methods are mostly focused on parameter detection under single environmental conditions, while some methods introduce temperature cycling or damp heat stress to further test power semiconductors in extreme environments.

[0004] While the methods described above can test the extreme environments of power semiconductors, they fail to simultaneously consider the coupling effects of multiple stresses such as temperature, humidity, current, and cycle count. This leads to discrepancies between the test results and actual application conditions, and lacks records of the dynamic evolution process under standard semiconductor parameters. Consequently, it is difficult to accurately reflect the failure mechanisms and lifespan characteristics of devices under extreme environments. Therefore, there is an urgent need for a testing method for power semiconductors in extreme environments that can comprehensively consider multiple environmental factors and achieve reliable and accurate assessment. Summary of the Invention

[0005] This invention provides a method for testing power semiconductors under extreme environments and a computer-readable storage medium, the main purpose of which is to improve the reliability of power semiconductor testing under extreme environments.

[0006] To achieve the above objectives, the present invention provides an extreme environment testing method for power semiconductors, comprising:

[0007] Acquire semiconductors and confirm the testing environment, which includes: a testing platform, an analyzer, a temperature and humidity control chamber, an infrared thermal imager, and a power cycling device;

[0008] Extreme temperatures, extreme humidity levels, and peak currents were identified using semiconductors, analyzers, and infrared thermal imagers.

[0009] A semiconductor is fixed on a test platform in a test environment to obtain a fixed semiconductor;

[0010] Based on the preset standard temperature, temperature and humidity control chamber, analyzer and fixed semiconductor in the test environment, the parameters of the semiconductor under test and the standard semiconductor are identified. The standard semiconductor parameters include: standard threshold voltage, standard on-resistance and standard leakage current.

[0011] The target control box was identified based on extreme temperature, extreme humidity, and temperature and humidity control boxes.

[0012] The target semiconductor is obtained by applying environmental conditions to the semiconductor under test using a target control box.

[0013] The target number of loops is determined, and multiple test values ​​for the number of loops are determined based on the target number of loops and the preset loop interval;

[0014] Based on standard threshold voltage, standard on-resistance, standard leakage current, peak current, power cycling device in the test environment, multiple cycle count test values, and target semiconductor, the termination semiconductor and final cycle count are identified.

[0015] Based on the termination of the semiconductor, extreme temperature, extreme humidity, peak current, and final cycle count, the extreme environmental parameters of the semiconductor are determined, and the extreme environmental test of the power semiconductor is completed.

[0016] Optionally, the identification of extreme temperature, extreme humidity, and peak current based on semiconductors, analyzers, and infrared thermal imagers includes:

[0017] Obtain semiconductor basic parameters, including: maximum junction temperature, thermal resistance, on-resistance, transient thermal resistance image, and extreme humidity.

[0018] The semiconductor is tested for its rated parameters using an analyzer to obtain the test current and test voltage drop;

[0019] Calculate the extreme temperature based on the test current, test voltage drop, and thermal resistance;

[0020] The allowable increase in junction temperature is calculated based on the maximum junction temperature.

[0021] The pulse width was determined based on semiconductors, analyzers, maximum junction temperature, and infrared thermal imagers.

[0022] The transient thermal resistance was determined based on the pulse width and transient thermal resistance images;

[0023] The allowable power is calculated based on the allowable rising junction temperature and transient thermal resistance;

[0024] Calculate the peak current based on the allowable power and on-resistance.

[0025] Optionally, determining the pulse width based on the semiconductor, analyzer, maximum junction temperature, and infrared thermal imager includes:

[0026] Obtain the power pulse source and determine the pulse control range based on the power pulse source;

[0027] The pulse control range is divided according to the preset pulse division interval to obtain multiple pulse test values;

[0028] For each of the multiple pulse test values, perform the following operation:

[0029] The target pulse source was identified based on the pulse test values ​​and the power pulse source.

[0030] The initial temperature of the semiconductor is obtained by measuring its temperature using an infrared thermal imager.

[0031] A pulsed semiconductor is obtained by applying a pulse to a semiconductor using a target pulse source.

[0032] The pulse temperature is obtained by measuring the temperature of the pulse semiconductor using an infrared thermal imager.

[0033] The rise junction temperature was determined based on the initial temperature and the pulse temperature, where the rise junction temperature is the difference between the pulse temperature and the initial temperature.

[0034] The pulse on-resistance was obtained by measuring the parameters of the pulse semiconductor using an analyzer.

[0035] The test data is obtained by combining the pulse test value, the increased junction temperature, and the pulse on-resistance.

[0036] Summarize the test data to obtain multiple test data sets;

[0037] The pulse width was determined based on multiple test data and the maximum junction temperature.

[0038] Optionally, determining the pulse width based on multiple test data and the maximum junction temperature includes:

[0039] Extracting the first from multiple test data The test data and the first There are 10 test data sets, among which... The initial value is 1;

[0040] According to the The pulse on-resistance in the test data and the first Calculate the rate of change of electrical parameters from the pulse on-resistance in each test data set;

[0041] Compare the rate of change of electrical parameters with a preset threshold. If the rate of change of electrical parameters is less than or equal to the threshold, then adjust the value of the electrical parameter corresponding to the rate of change. One set of test data was used as the filtering data;

[0042] make ,Will As Returning to the extraction of the first from multiple test data The test data and the first The steps for each test data point, until... The filtered data is summarized to obtain multiple filtered data sets, among which... The number of test data points in a set of test data;

[0043] The junction temperature threshold range was determined based on the maximum junction temperature.

[0044] Perform the following operation on each of the multiple filtered data points:

[0045] Determine whether the increased junction temperature in the filtered data is within the junction temperature threshold range. If the increased junction temperature in the filtered data is within the junction temperature threshold range, then use the pulse test value in the filtered data as the filtered pulse width.

[0046] Summarize the filter pulse widths to obtain multiple filter pulse widths;

[0047] The pulse width is determined based on multiple filtering pulse widths, where the pulse width is the median of the multiple filtering pulse widths.

[0048] Optionally, the step of determining the parameters of the semiconductor under test and the standard semiconductor based on a preset standard temperature, temperature and humidity control chamber, analyzer in the test environment, and fixed semiconductor includes:

[0049] The control box was identified based on the standard temperature and humidity control box.

[0050] The semiconductor to be tested is obtained by placing the fixed semiconductor in the control box;

[0051] The semiconductor under test is statically measured using an analyzer in the test environment to obtain standard semiconductor parameters, including standard threshold voltage, standard on-resistance, and standard leakage current.

[0052] Optionally, the step of identifying the termination semiconductor and the final number of cycles based on standard threshold voltage, standard on-resistance, standard leakage current, peak current, power cycling device in the test environment, multiple cycle count test values, and the target semiconductor includes:

[0053] The target cycling device was identified based on peak current and power cycling device in the test environment.

[0054] Extracting the first from multiple test values ​​of loop counts The number of test values ​​for each loop iteration, among which... The initial value is 1;

[0055] Start the target loop device, apply power to the target semiconductor using the started target loop device, and record the number of loops simultaneously;

[0056] When the number of loops equals the first When testing for a certain number of cycles, the analyzer in the test environment is used to perform parameter analysis on the target semiconductor to obtain the test threshold voltage, test on-resistance and test leakage current.

[0057] The failure index was determined based on standard threshold voltage, standard on-resistance, standard leakage current, test threshold voltage, test on-resistance, and test leakage current.

[0058] Compare the failure index with the preset failure index threshold. If the failure index is greater than or equal to the failure index threshold, stop the target cycle device and obtain the termination semiconductor and the final cycle number.

[0059] If the failure index is less than the index threshold, then let ,Will As Returning the result extracted from the test values ​​of multiple loop counts. The step of testing the value for each loop iteration continues until... Stop the target loop device to obtain the termination semiconductor and the final number of loops, where, The number of test values ​​for multiple iterations.

[0060] Optionally, the determination of the failure index based on standard threshold voltage, standard on-resistance, standard leakage current, test threshold voltage, test on-resistance, and test leakage current includes:

[0061] Calculate the threshold voltage change value based on the standard threshold voltage and the test threshold voltage;

[0062] The change in on-resistance was determined based on the standard on-resistance and the tested on-resistance.

[0063] The leakage current variation was confirmed based on the standard leakage current and the test leakage current.

[0064] The failure index is calculated based on the changes in threshold voltage, on-resistance, and leakage current, using the following formula:

[0065] ,

[0066] in, Indicates the failure index. This indicates the change in on-resistance. This represents the threshold voltage change value. This indicates the change in leakage current. It represents the natural logarithm.

[0067] Optionally, the determination of semiconductor extreme environment parameters based on the terminated semiconductor, extreme temperature, extreme humidity, peak current, and final cycle number includes:

[0068] The total volume, length, and high-resolution X-CT of the chip are obtained. The termination semiconductor is then scanned using high-resolution X-CT to obtain multiple scan images.

[0069] A pre-built iterative reconstruction algorithm is used to reconstruct multiple scanned images to obtain a 3D image. The 3D image includes multiple voxels, and each voxel includes a voxel gray value.

[0070] Threshold segmentation is performed on multiple voxels in a 3D image based on a preset grayscale threshold to obtain multiple defect voxels.

[0071] For each of the multiple defective voxels, perform the following operation:

[0072] Data measurements were performed on the defect voxels to obtain the defect volume and the maximum size of the defect.

[0073] By summing the defect volume and the maximum size of the defect, we can obtain multiple defect volumes and multiple maximum size of the defect.

[0074] The total defect volume is determined based on multiple defect volumes, where the total defect volume is the sum of the multiple defect volumes;

[0075] The maximum defect maximum edge is determined based on the maximum edge of multiple defects, where the maximum defect maximum edge is the largest among the multiple maximum edge of defects.

[0076] The damage index is calculated based on the total chip volume, chip length, total defect volume, and the maximum edge size of the largest defect. The calculation formula is as follows:

[0077] ,

[0078] in, Indicates the damage index. Indicates the total volume of the chip. Represents the total defect volume. Indicates chip length. This indicates the largest defect and the largest edge.

[0079] The extreme environmental parameters of the semiconductor were determined based on the damage index, extreme temperature, extreme humidity, peak current, and final cycle number.

[0080] Optionally, the threshold segmentation of multiple voxels in the 3D image based on a preset grayscale threshold to obtain multiple defect voxels includes:

[0081] Perform the following operation on each of the multiple voxels in the 3D image:

[0082] Compare the voxel gray value with the gray value threshold. If the voxel gray value is less than the gray value threshold, then the voxel is regarded as a defective voxel.

[0083] By summing up the defect voxels, multiple defect voxels are obtained.

[0084] To achieve the above objectives, the present invention also provides an extreme environment testing system for power semiconductors, comprising:

[0085] The basic parameter confirmation module is used to acquire semiconductors and confirm the test environment, which includes: test platform, analyzer, temperature and humidity control box, infrared thermal imager and power cycling device. Based on the semiconductors, analyzer and infrared thermal imager, extreme temperature, extreme humidity and peak current are confirmed.

[0086] The standard parameter verification module is used to fix the semiconductor on the test platform in the test environment to obtain a fixed semiconductor. Based on the preset standard temperature, temperature and humidity control box, analyzer in the test environment and fixed semiconductor, the parameters of the semiconductor under test and the standard semiconductor are verified. The standard semiconductor parameters include: standard threshold voltage, standard on-resistance and standard leakage current.

[0087] The extreme environment testing module is used to identify the target control box based on extreme temperature, extreme humidity and temperature and humidity control box, use the target control box to load the environment of the semiconductor under test, obtain the target semiconductor, identify the target number of cycles, and identify multiple cycle test values ​​based on the target number of cycles and the preset cycle interval.

[0088] The environmental parameter acquisition module is used to identify the termination semiconductor and the final number of cycles based on standard threshold voltage, standard on-resistance, standard leakage current, peak current, power cycling device in the test environment, multiple cycle test values ​​and target semiconductor. Based on the termination semiconductor, extreme temperature, extreme humidity, peak current and final number of cycles, the module identifies the extreme environmental parameters of the semiconductor and completes the extreme environmental test of the power semiconductor.

[0089] To address the above problems, the present invention also provides an electronic device, the electronic device comprising:

[0090] Memory, storing at least one instruction; and

[0091] The processor executes instructions stored in the memory to implement the extreme environment testing method for power semiconductors described above.

[0092] To address the aforementioned problems, the present invention also provides a computer-readable storage medium storing at least one instruction, which is executed by a processor in an electronic device to implement the above-described extreme environment testing method for power semiconductors.

[0093] To address the problems described in the background section, this invention obtains a semiconductor and identifies the testing environment. The testing environment includes a testing platform, an analyzer, a temperature and humidity control chamber, an infrared thermal imager, and a power cycling device. This invention provides a material basis for subsequent extreme environment testing of the semiconductor by obtaining the semiconductor and identifying the testing environment. Furthermore, based on the semiconductor, the analyzer, and the infrared thermal imager, extreme temperatures, extreme humidity levels, and peak currents are identified. This invention utilizes the analyzer to analyze the parameters of the semiconductor in its initial state, thereby obtaining initial parameters for extreme environment testing. This facilitates the subsequent identification of final extreme environment test parameters based on these initial parameters, improving the efficiency of extreme environment testing for power semiconductors. To assess reliability, the semiconductor is fixed on a test platform within a testing environment, resulting in a fixed semiconductor. This embodiment of the invention fixes the semiconductor on the test platform for subsequent extreme environment testing. Based on a preset standard temperature, a temperature and humidity control chamber, an analyzer in the test environment, and the fixed semiconductor, the parameters of the semiconductor under test and the standard semiconductor are determined. The standard semiconductor parameters include: standard threshold voltage, standard on-resistance, and standard leakage current. This embodiment of the invention utilizes a temperature and humidity control chamber to apply environmental conditions to the semiconductor at a preset standard temperature, thereby confirming the semiconductor parameters under standard conditions. This facilitates subsequent comparison with the semiconductor parameters after extreme testing, allowing for the calculation of the semiconductor's damage level. This invention improves the reliability of extreme environment testing for power semiconductors. Based on extreme temperature, extreme humidity, and a temperature and humidity control box, a target control box is identified. This embodiment of the invention sets the temperature and humidity of the temperature and humidity control box to extreme conditions to apply environmental stress to the semiconductor. The target control box is then used to apply environmental stress to the semiconductor under test, resulting in the target semiconductor. This embodiment of the invention simulates extreme operating conditions for the semiconductor by applying extreme temperature and humidity to the test semiconductor, identifying the target number of cycles. Based on the target number of cycles and a preset cycle interval, multiple cycle count test values ​​are identified. This identification of multiple cycle count test values ​​facilitates the subsequent determination of the final cycle count, improving the reliability of power semiconductor testing. The reliability of extreme environment testing is determined based on standard threshold voltage, standard on-resistance, standard leakage current, peak current, power cycling device in the test environment, multiple cycle counts, and the target semiconductor. The termination semiconductor and the final cycle count are then identified. This embodiment of the invention applies power cycling to the target semiconductor using a power cycling device to obtain the final cycle count. Based on the termination semiconductor, extreme temperature, extreme humidity, peak current, and the final cycle count, the extreme environment parameters of the semiconductor are determined, thus completing the extreme environment testing of the power semiconductor. Therefore, this embodiment of the invention comprehensively determines the extreme environment parameters of the semiconductor by testing and analyzing the termination semiconductor and combining extreme temperature, extreme humidity, peak current, and the final cycle count.This invention improves the reliability of power semiconductor testing under extreme environments. Attached Figure Description

[0094] Figure 1 This is a flowchart illustrating an extreme environment testing method for power semiconductors provided in an embodiment of the present invention.

[0095] Figure 2 A functional block diagram of an extreme environment testing system for power semiconductors provided in an embodiment of the present invention;

[0096] Figure 3 This is a schematic diagram of an electronic device that implements the extreme environment testing method for the power semiconductor according to an embodiment of the present invention.

[0097] Explanation of reference numerals in the attached figures:

[0098] 10. Electronic device; 11. Processor; 12. Memory; 13. Bus.

[0099] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0100] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0101] This application provides a method for testing power semiconductors under extreme environments. The execution entity of this method includes, but is not limited to, at least one electronic device configured to execute the method provided in this application, such as a server or a terminal. In other words, the method for testing power semiconductors under extreme environments can be executed by software or hardware installed on a terminal device or a server device, where the software may be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0102] Reference Figure 1 The diagram shown is a flowchart illustrating an extreme environment testing method for power semiconductors according to an embodiment of the present invention. In this embodiment, the extreme environment testing method for power semiconductors includes:

[0103] S1. Obtain semiconductors and confirm the test environment, which includes: test platform, analyzer, temperature and humidity control chamber, infrared thermal imager and power cycling device.

[0104] For example, Xiao Zhang is a worker at a power semiconductor testing factory and needs to conduct extreme environment tests on power semiconductors. Xiao Zhang obtains semiconductors for subsequent extreme environment testing, and the test environment is the necessary environment for testing power semiconductors. This embodiment of the invention identifies the test environment so that the semiconductor can be tested under extreme conditions using a test platform, analyzer, temperature and humidity control chamber, infrared thermal imager, and power cycling device within that environment, thereby obtaining the extreme environment parameters of the semiconductor. A detailed explanation of the extreme environment parameters is provided in subsequent embodiments.

[0105] It should be explained that a semiconductor is a semiconductor device; optionally, the Shanghai Huihao Industrial IGBT power module CM300DY-24NF discrete semiconductor component is used as the semiconductor. The test environment refers to a set of equipment and supporting measures configured to complete extreme environment testing of semiconductors. The test environment includes: a test platform, an analyzer, a temperature and humidity control chamber, an infrared thermal imager, and a power cycling device. The test platform is a test fixture; optionally, a PCBA circuit board test fixture frame is used as the test platform. The analyzer is a parameter analyzer; optionally, a Keithley 4200A-SCS parameter analyzer is used. The temperature and humidity control chamber is a high-temperature and high-humidity chamber; optionally, a WBE-SDJ408L high-temperature and high-humidity test chamber is used. The infrared thermal imager is a thermal imager; optionally, a Keyence digital infrared temperature sensor is used. The power cycling device is an IGBT power cycling and thermal resistance testing device; optionally, a Simcenter T3Ster SI thermal transient tester is used as the power cycling device.

[0106] S2. Extreme temperatures, extreme humidity, and peak currents are identified based on semiconductors, analyzers, and infrared thermal imagers.

[0107] Specifically, the identification of extreme temperatures, extreme humidity, and peak current based on semiconductors, analyzers, and infrared thermal imagers includes:

[0108] Obtain semiconductor basic parameters, including: maximum junction temperature, thermal resistance, on-resistance, transient thermal resistance image, and extreme humidity.

[0109] The semiconductor is tested for its rated parameters using an analyzer to obtain the test current and test voltage drop;

[0110] The extreme temperature is calculated based on the test current, test voltage drop, and thermal resistance. The calculation formula is shown below:

[0111] ,

[0112] in, Indicates extreme temperatures. Indicates the test current. Indicates the test voltage drop. Indicates thermal resistance. The preset ambient temperature;

[0113] The allowable increase in junction temperature is calculated based on the maximum junction temperature, using the following formula:

[0114] ,

[0115] in, This indicates that the junction temperature is allowed to rise. Indicates the maximum junction temperature;

[0116] The pulse width was determined based on semiconductors, analyzers, maximum junction temperature, and infrared thermal imagers.

[0117] The transient thermal resistance was determined based on the pulse width and transient thermal resistance images;

[0118] The allowable power is calculated based on the allowable rising junction temperature and transient thermal resistance, using the following formula:

[0119] ,

[0120] in, Indicates the allowable power. Indicates transient thermal resistance;

[0121] The peak current is calculated based on the allowable power and on-resistance, using the following formula:

[0122] ,

[0123] in, Indicates peak current. This indicates the on-resistance.

[0124] It should be explained that semiconductor fundamental parameters refer to parameters that characterize the most basic electrical, thermal, and structural properties of semiconductors. These parameters include: maximum junction temperature, thermal resistance, on-resistance, transient thermal resistance graph, and extreme humidity. Maximum junction temperature refers to the highest temperature that the junction region of a semiconductor chip can withstand; the junction region refers to the active region of the chip. Thermal resistance refers to the thermal impedance between the junction region and the casing. On-resistance refers to the equivalent resistance of the semiconductor in the on-state. The transient thermal resistance graph is the curve showing the relationship between the transient thermal resistance and time under different pulse widths, used to evaluate the temperature rise characteristics of the device under pulsed power. Extreme humidity refers to the humidity level that poses the greatest challenge to semiconductor reliability during extreme environmental testing. The use of an analyzer to perform rated parameter testing on the semiconductor refers to measuring the semiconductor's current and voltage drop using an analyzer. The method for measuring the semiconductor's current and voltage drop using an analyzer is existing technology and will not be elaborated here. The measured semiconductor current is the test current, and the measured semiconductor voltage is the test voltage drop. Extreme temperature refers to the highest temperature used for semiconductor extreme environmental testing. The maximum junction temperature, thermal resistance, humidity limit, maximum leakage current, on-resistance, transient thermal resistance images, and extreme humidity can all be obtained from the technical manuals provided by the semiconductor product manufacturer. The ambient temperature is a value manually set by the staff of the power semiconductor testing facility based on the temperature of the test environment. For example, if the temperature of the test environment is 25 degrees Celsius, then the ambient temperature is 25 degrees Celsius.

[0125] Understandably, the allowable rise in junction temperature refers to the temperature at which the junction region of the semiconductor is allowed to rise during semiconductor testing. The determination of transient thermal resistance based on pulse width and transient thermal resistance image means: reading the transient thermal resistance value corresponding to the pulse width from the transient thermal resistance image; this transient thermal resistance value corresponding to the pulse width is the transient thermal resistance. Allowable power refers to the maximum power permitted during semiconductor testing, and peak current refers to the current during semiconductor testing.

[0126] Specifically, the determination of the pulse width based on semiconductors, analyzers, maximum junction temperature, and infrared thermal imagers includes:

[0127] Obtain the power pulse source and determine the pulse control range based on the power pulse source;

[0128] The pulse control range is divided according to the preset pulse division interval to obtain multiple pulse test values;

[0129] For each of the multiple pulse test values, perform the following operation:

[0130] The target pulse source was identified based on the pulse test values ​​and the power pulse source.

[0131] The initial temperature of the semiconductor is obtained by measuring its temperature using an infrared thermal imager.

[0132] A pulsed semiconductor is obtained by applying a pulse to a semiconductor using a target pulse source.

[0133] The pulse temperature is obtained by measuring the temperature of the pulse semiconductor using an infrared thermal imager.

[0134] The rise junction temperature was determined based on the initial temperature and the pulse temperature, where the rise junction temperature is the difference between the pulse temperature and the initial temperature.

[0135] The pulse on-resistance was obtained by measuring the parameters of the pulse semiconductor using an analyzer.

[0136] The test data is obtained by combining the pulse test value, the increased junction temperature, and the pulse on-resistance.

[0137] Summarize the test data to obtain multiple test data sets;

[0138] The pulse width was determined based on multiple test data and the maximum junction temperature.

[0139] It should be explained that the power pulse source is a high-power pulse power supply. Optionally, the ZH900PG high-voltage pulse power supply can be used as the power pulse source. The pulse control range determined based on the power pulse source means: referring to the product technical manual provided by the power pulse source manufacturer to obtain the adjustable range of the pulse current of the power pulse source. The adjustable range of the pulse current of the power pulse source is the pulse control range.

[0140] For example, if the pulse control range is 0.5-1 milliseconds and the pulse segmentation interval is 0.1 milliseconds, then after dividing the pulse control range according to the preset pulse segmentation interval, six pulse test values ​​are obtained: 0.5 milliseconds, 0.6 milliseconds, 0.7 milliseconds, 0.8 milliseconds, 0.9 milliseconds, and 1.0 milliseconds.

[0141] It is understood that identifying the target pulse source based on the pulse test value and the power pulse source means setting the pulse current output value of the power pulse source as the pulse test value, and the target pulse source refers to a power pulse source whose pulse current output value is the pulse test value. Measuring the temperature of the semiconductor using an infrared thermal imager means measuring the temperature of the semiconductor surface using an infrared thermal imager; the temperature of the semiconductor surface is the initial temperature. The method for measuring the temperature of the semiconductor surface using an infrared thermal imager is existing technology and will not be elaborated here. Applying a pulse to the semiconductor using the target pulse source means applying a current pulse to the semiconductor using the target pulse source. The method for applying a current pulse to the semiconductor using the target pulse source is existing technology and will not be elaborated here. A pulsed semiconductor refers to a target semiconductor to which a current pulse has been applied. The method for measuring the temperature of the pulsed semiconductor using an infrared thermal imager to obtain the pulse temperature is the same as the method for measuring the temperature of the semiconductor using an infrared thermal imager to obtain the initial temperature, and will not be elaborated here. The parameter determination of the pulse semiconductor using an analyzer refers to measuring the on-resistance of the pulse semiconductor using an analyzer. The on-resistance of the pulse semiconductor is the pulse on-resistance. The method of measuring the on-resistance of the pulse semiconductor using an analyzer is existing technology and will not be described in detail here.

[0142] For example, if the pulse test value is 1 millisecond, the rise junction temperature is 10 degrees Celsius, and the pulse on-resistance is 10 ohms, then the test data obtained by combining the pulse test value, the rise junction temperature, and the pulse on-resistance is: (1 millisecond, 10 degrees Celsius, 10 ohms).

[0143] Specifically, the pulse width determination based on multiple test data and the maximum junction temperature includes:

[0144] Extracting the first from multiple test data The test data and the first There are 10 test data sets, among which... The initial value is 1;

[0145] According to the The pulse on-resistance in the test data and the first The rate of change of electrical parameters is calculated from the pulse on-resistance in each test data set, using the following formula:

[0146] ,

[0147] in, Indicates the rate of change of electrical parameters. Indicates the first The pulse on-resistance in each test data point Indicates the first The pulse on-resistance in each test data point;

[0148] Compare the rate of change of electrical parameters with a preset threshold. If the rate of change of electrical parameters is less than or equal to the threshold, then adjust the value of the electrical parameter corresponding to the rate of change. One set of test data was used as the filtering data;

[0149] make ,Will As Returning to the extraction of the first from multiple test data The test data and the first The steps for each test data point, until... The filtered data is summarized to obtain multiple filtered data sets, among which... The number of test data points in a set of test data;

[0150] The junction temperature threshold range was determined based on the maximum junction temperature.

[0151] Perform the following operation on each of the multiple filtered data points:

[0152] Determine whether the increased junction temperature in the filtered data is within the junction temperature threshold range. If the increased junction temperature in the filtered data is within the junction temperature threshold range, then use the pulse test value in the filtered data as the filtered pulse width.

[0153] Summarize the filter pulse widths to obtain multiple filter pulse widths;

[0154] The pulse width is determined based on multiple filtering pulse widths, where the pulse width is the median of the multiple filtering pulse widths.

[0155] For example, if multiple test data are: (1 ms, 10 degrees Celsius, 10 ohms), (2 ms, 12 degrees Celsius, 12 ohms), (3 ms, 13 degrees Celsius, 13 ohms), (4 ms, 14 degrees Celsius, 14 ohms), then the first and second test data extracted from the multiple test data are: (1 ms, 10 degrees Celsius, 10 ohms), (2 ms, 12 degrees Celsius, 12 ohms).

[0156] It should be explained that the rate of change of electrical parameters reflects the degree of change in pulse on-resistance in the test data. The larger the rate of change of electrical parameters, the greater the degree of change in pulse on-resistance in the test data. The change threshold is a value manually set by the staff of the power semiconductor testing plant; optionally, the change threshold is 5%. Screened data refers to the electrical parameter change rate corresponding to the [number]th [parameter] change rate that is less than or equal to the change threshold. The test data is as follows. The formula for calculating the junction temperature threshold range is shown below: In degrees Celsius, for example, if the maximum junction temperature is 200 degrees Celsius, then the junction temperature threshold range is: Celsius.

[0157] Understandably, the screening pulse width refers to the pulse test value in the screening data where the junction temperature is increased to within the junction temperature threshold range.

[0158] S3. Fix the semiconductor on the test platform in the test environment to obtain a fixed semiconductor. Based on the preset standard temperature, temperature and humidity control box, analyzer in the test environment and fixed semiconductor, confirm the parameters of the semiconductor under test and the standard semiconductor. The standard semiconductor parameters include: standard threshold voltage, standard on-resistance and standard leakage current.

[0159] It should be explained that fixed semiconductors refer to semiconductors that are fixed on the test platform.

[0160] In detail, the parameters of the semiconductor under test and the standard semiconductor are determined based on a preset standard temperature, a temperature and humidity control chamber, an analyzer in the test environment, and a fixed semiconductor, including:

[0161] The control box was identified based on the standard temperature and humidity control box.

[0162] The semiconductor to be tested is obtained by placing the fixed semiconductor in the control box;

[0163] The semiconductor under test is statically measured using an analyzer in the test environment to obtain standard semiconductor parameters, including standard threshold voltage, standard on-resistance, and standard leakage current.

[0164] It should be understood that the "confirmation of the control box based on standard temperature and humidity control box" means: setting the temperature of the temperature and humidity control box to a standard temperature. The temperature and humidity control box with the temperature set to the standard temperature is the control box. The semiconductor under test refers to a fixed semiconductor placed in the control box. The "static measurement of the semiconductor under test using an analyzer in the test environment" means: using an analyzer to test the threshold voltage, on-resistance, and leakage current of the semiconductor under test. The threshold voltage, on-resistance, and leakage current of the semiconductor under test are the standard threshold voltage, standard on-resistance, and standard leakage current. Furthermore, the method of using an analyzer to test the threshold voltage, on-resistance, and leakage current of the semiconductor under test is existing technology, and will not be described in detail here.

[0165] S4. Based on extreme temperature, extreme humidity, and temperature and humidity control boxes, the target control box is identified. The target control box is used to apply environmental load to the semiconductor under test to obtain the target semiconductor.

[0166] It should be explained that, regarding the identification of the target control box based on extreme temperature, extreme humidity, and a temperature and humidity control box, this means setting the temperature and humidity of the temperature and humidity control box to extreme temperatures and humidity levels. The target control box refers to a temperature and humidity control box with its temperature and humidity set to extreme temperatures and humidity levels. The phrase "using the target control box to apply environmental load to the semiconductor under test to obtain the target semiconductor" means using the target control box to maintain the semiconductor under test in an environment with extreme temperatures and humidity levels. The target semiconductor refers to the semiconductor under test under extreme temperature and humidity conditions.

[0167] S5. Determine the target number of loops, and based on the target number of loops and the preset loop interval, determine multiple test values ​​for the number of loops.

[0168] It should be explained that the target number of cycles is a value set manually by the staff of the power semiconductor testing plant. Optionally, the target number of cycles is 10,000.

[0169] For example, if the target number of loops is 10,000 and the loop interval is 1,000, then the multiple loop test values ​​determined based on the target number of loops and the preset loop interval are: 1,000, 2,000, 3,000, 4,000, 5,000, 6,000, 7,000, 8,000, 9,000, and 10,000.

[0170] S6. Based on standard threshold voltage, standard on-resistance, standard leakage current, peak current, power cycling device in the test environment, multiple cycle count test values, and target semiconductor, identify the termination semiconductor and final cycle count.

[0171] In detail, the process of identifying the termination semiconductor and the final number of cycles based on standard threshold voltage, standard on-resistance, standard leakage current, peak current, power cycling device in the test environment, multiple cycle count test values, and the target semiconductor includes:

[0172] The target cycling device was identified based on peak current and power cycling device in the test environment.

[0173] Extracting the first from multiple test values ​​of loop counts The number of test values ​​for each loop iteration, among which... The initial value is 1;

[0174] Start the target loop device, apply power to the target semiconductor using the started target loop device, and record the number of loops simultaneously;

[0175] When the number of loops equals the first When testing for a certain number of cycles, the analyzer in the test environment is used to perform parameter analysis on the target semiconductor to obtain the test threshold voltage, test on-resistance and test leakage current.

[0176] The failure index was determined based on standard threshold voltage, standard on-resistance, standard leakage current, test threshold voltage, test on-resistance, and test leakage current.

[0177] Compare the failure index with the preset failure index threshold. If the failure index is greater than or equal to the failure index threshold, stop the target cycle device and obtain the termination semiconductor and the final cycle number.

[0178] If the failure index is less than the index threshold, then let ,Will As Returning the result extracted from the test values ​​of multiple loop counts. The step of testing the value for each loop iteration continues until... Stop the target loop device to obtain the termination semiconductor and the final number of loops, where, The number of test values ​​for multiple iterations.

[0179] It should be explained that the "target cycling device" identified based on peak current and the power cycling device in the test environment refers to setting the pulse current output value of the power cycling device to the peak current, and the target cycling device refers to the power cycling device whose pulse current output value is set to the peak current.

[0180] For example, if multiple loop count test values ​​are: 1000 times, 2000 times, 3000 times, 4000 times, 5000 times, 6000 times, 7000 times, 8000 times, 9000 times, and 10000 times, then the second loop count test value of 2000 times is extracted from the multiple loop count test values.

[0181] It is understood that applying power cycles to the target semiconductor using the target cycling device after startup and simultaneously recording the number of cycles means applying current pulse cycles to the target semiconductor using the target cycling device after startup, and recording the number of cycles for each current pulse cycle applied. The number of cycles refers to the number of times the current pulse cycles are applied. The method of using an analyzer in the test environment to analyze the parameters of the target semiconductor to obtain the test threshold voltage, test on-resistance, and test leakage current is the same as the method of using an analyzer in the test environment to perform static measurements on the semiconductor under test to obtain standard semiconductor parameters, and will not be repeated here. Terminating the semiconductor refers to the target semiconductor obtained after stopping the target cycling device when the failure index is greater than or equal to the failure index threshold. The final number of cycles refers to the number of cycles recorded when the failure index is greater than or equal to the failure index threshold.

[0182] Specifically, the failure index determined based on standard threshold voltage, standard on-resistance, standard leakage current, test threshold voltage, test on-resistance, and test leakage current includes:

[0183] The threshold voltage change is calculated based on the standard threshold voltage and the test threshold voltage, using the following formula:

[0184] ,

[0185] in, This represents the threshold voltage change value. Indicates the test threshold voltage. Indicates the standard threshold voltage;

[0186] The change in on-resistance was determined based on the standard on-resistance and the tested on-resistance.

[0187] The leakage current variation was confirmed based on the standard leakage current and the test leakage current.

[0188] The failure index is calculated based on the changes in threshold voltage, on-resistance, and leakage current, using the following formula:

[0189] ,

[0190] in, Indicates the failure index. This indicates the change in on-resistance. This represents the threshold voltage change value. This indicates the change in leakage current. It represents the natural logarithm.

[0191] It should be explained that the threshold voltage change reflects the degree of difference between the threshold voltage and the test threshold voltage. A larger threshold voltage change indicates a greater difference between the threshold voltage and the test threshold voltage. The methods for determining the on-resistance change based on the standard on-resistance and the test on-resistance, and for determining the leakage current change based on the standard leakage current and the test leakage current, are the same as the methods for calculating the threshold voltage change based on the standard threshold voltage and the test threshold voltage, and will not be repeated here. The on-resistance change reflects the degree of difference between the standard on-resistance and the test on-resistance; a larger on-resistance change indicates a greater difference between the standard on-resistance and the test on-resistance. Similarly, the leakage current change reflects the degree of difference between the standard leakage current and the test leakage current; a larger leakage current change indicates a greater difference between the standard leakage current and the test leakage current. The failure index reflects the degree of damage to the termination semiconductor after extreme environment testing; a larger failure index indicates a greater degree of damage to the termination semiconductor after extreme environment testing.

[0192] S7. Based on the termination semiconductor, extreme temperature, extreme humidity, peak current and final cycle number, the extreme environment parameters of the semiconductor are determined, and the extreme environment test of the power semiconductor is completed.

[0193] Specifically, the determination of extreme environmental parameters for the semiconductor based on the termination semiconductor, extreme temperature, extreme humidity, peak current, and final cycle count includes:

[0194] The total volume, length, and high-resolution X-CT of the chip are obtained. The termination semiconductor is then scanned using high-resolution X-CT to obtain multiple scan images.

[0195] A pre-built iterative reconstruction algorithm is used to reconstruct multiple scanned images to obtain a 3D image. The 3D image includes multiple voxels, and each voxel includes a voxel gray value.

[0196] Threshold segmentation is performed on multiple voxels in a 3D image based on a preset grayscale threshold to obtain multiple defect voxels.

[0197] For each of the multiple defective voxels, perform the following operation:

[0198] Data measurements were performed on the defect voxels to obtain the defect volume and the maximum size of the defect.

[0199] By summing the defect volume and the maximum size of the defect, we can obtain multiple defect volumes and multiple maximum size of the defect.

[0200] The total defect volume is determined based on multiple defect volumes, where the total defect volume is the sum of the multiple defect volumes;

[0201] The maximum defect maximum edge is determined based on the maximum edge of multiple defects, where the maximum defect maximum edge is the largest among the multiple maximum edge of defects.

[0202] The damage index is calculated based on the total chip volume, chip length, total defect volume, and the maximum edge size of the largest defect. The calculation formula is as follows:

[0203] ,

[0204] in, Indicates the damage index. Indicates the total volume of the chip. Represents the total defect volume. Indicates chip length. This indicates the largest defect and the largest edge.

[0205] The extreme environmental parameters of the semiconductor were determined based on the damage index, extreme temperature, extreme humidity, peak current, and final cycle number.

[0206] It should be explained that the total chip volume refers to the volume of the semiconductor chip, and the chip length refers to the length of the semiconductor chip. Both the total chip volume and chip length can be obtained from the product technical manuals provided by the semiconductor product manufacturer. High-resolution X-CT is a type of CT scanner; optionally, the inspeXio SMX-225CT FPD HR Plus is used as the high-resolution X-CT. Scanning the terminating semiconductor using high-resolution X-CT means scanning each facet of the terminating semiconductor with high-resolution X-CT, resulting in multiple scanned images. Reconstructing multiple scanned images using a pre-built iterative reconstruction algorithm means inputting the multiple scanned images into the iterative reconstruction algorithm, reconstructing and synthesizing the multiple images to obtain a 3D image. Optionally, the FBP (Filtered Back Projection) algorithm is used as the iterative reconstruction algorithm. The image obtained after reconstructing and synthesizing multiple images using the iterative reconstruction algorithm is the 3D image. A voxel is the smallest volume unit in three-dimensional space, used to represent local information about the internal structure of a semiconductor. The voxel gray value is used to characterize the X-ray absorption intensity at the corresponding spatial location of the voxel, thereby reflecting the material density characteristics at that location.

[0207] It is understood that the data measurement of the defect voxel refers to measuring the volume of the defect voxel and the side length of the largest bounding rectangle of the defect voxel. The volume of the defect voxel is the defect volume, and the side length of the largest bounding rectangle of the defect voxel is the largest side length of the defect. The damage index reflects the degree of damage to the semiconductor as a whole. The larger the damage index, the greater the degree of damage to the semiconductor as a whole.

[0208] For example, if the damage index is 0.4, the extreme temperature is 175 degrees Celsius, the extreme humidity is 85%, the peak current is 0.8A, and the final cycle count is 5500, then the semiconductor extreme environment parameters determined based on the damage index, extreme temperature, extreme humidity, peak current, and final cycle count are: (0.4, 175 degrees Celsius, 85%, 0.8A, 5500 cycles). After obtaining the semiconductor extreme environment parameters, Xiao Zhang completed the extreme environment test of the power semiconductor.

[0209] Specifically, the threshold segmentation of multiple voxels in the 3D image based on a preset grayscale threshold yields multiple defect voxels, including:

[0210] Perform the following operation on each of the multiple voxels in the 3D image:

[0211] Compare the voxel gray value with the gray value threshold. If the voxel gray value is less than the gray value threshold, then the voxel is regarded as a defective voxel.

[0212] By summing up the defect voxels, multiple defect voxels are obtained.

[0213] It should be explained that the grayscale threshold is a value set manually by the staff of the power semiconductor testing factory. Optionally, the grayscale threshold is 400HU. Defect voxels refer to voxels whose grayscale value is less than the grayscale threshold.

[0214] To address the problems described in the background section, this invention obtains a semiconductor and identifies the testing environment. The testing environment includes a testing platform, an analyzer, a temperature and humidity control chamber, an infrared thermal imager, and a power cycling device. This invention provides a material basis for subsequent extreme environment testing of the semiconductor by obtaining the semiconductor and identifying the testing environment. Furthermore, based on the semiconductor, the analyzer, and the infrared thermal imager, extreme temperatures, extreme humidity levels, and peak currents are identified. This invention utilizes the analyzer to analyze the parameters of the semiconductor in its initial state, thereby obtaining initial parameters for extreme environment testing. This facilitates the subsequent identification of final extreme environment test parameters based on these initial parameters, improving the efficiency of extreme environment testing for power semiconductors. To assess reliability, the semiconductor is fixed on a test platform within a testing environment, resulting in a fixed semiconductor. This embodiment of the invention fixes the semiconductor on the test platform for subsequent extreme environment testing. Based on a preset standard temperature, a temperature and humidity control chamber, an analyzer in the test environment, and the fixed semiconductor, the parameters of the semiconductor under test and the standard semiconductor are determined. The standard semiconductor parameters include: standard threshold voltage, standard on-resistance, and standard leakage current. This embodiment of the invention utilizes a temperature and humidity control chamber to apply environmental conditions to the semiconductor at a preset standard temperature, thereby confirming the semiconductor parameters under standard conditions. This facilitates subsequent comparison with the semiconductor parameters after extreme testing, allowing for the calculation of the semiconductor's damage level. This invention improves the reliability of extreme environment testing for power semiconductors. Based on extreme temperature, extreme humidity, and a temperature and humidity control box, a target control box is identified. This embodiment of the invention sets the temperature and humidity of the temperature and humidity control box to extreme conditions to apply environmental stress to the semiconductor. The target control box is then used to apply environmental stress to the semiconductor under test, resulting in the target semiconductor. This embodiment of the invention simulates extreme operating conditions for the semiconductor by applying extreme temperature and humidity to the test semiconductor, identifying the target number of cycles. Based on the target number of cycles and a preset cycle interval, multiple cycle count test values ​​are identified. This identification of multiple cycle count test values ​​facilitates the subsequent determination of the final cycle count, improving the reliability of power semiconductor testing. The reliability of extreme environment testing is determined based on standard threshold voltage, standard on-resistance, standard leakage current, peak current, power cycling device in the test environment, multiple cycle counts, and the target semiconductor. The termination semiconductor and the final cycle count are then identified. This embodiment of the invention applies power cycling to the target semiconductor using a power cycling device to obtain the final cycle count. Based on the termination semiconductor, extreme temperature, extreme humidity, peak current, and the final cycle count, the extreme environment parameters of the semiconductor are determined, thus completing the extreme environment testing of the power semiconductor. Therefore, this embodiment of the invention comprehensively determines the extreme environment parameters of the semiconductor by testing and analyzing the termination semiconductor and combining extreme temperature, extreme humidity, peak current, and the final cycle count.This invention improves the reliability of power semiconductor testing under extreme environments.

[0215] like Figure 2 The diagram shown is a functional block diagram of an extreme environment testing system for power semiconductors provided in an embodiment of the present invention.

[0216] The extreme environment testing system 100 for power semiconductors described in this invention can be installed in an electronic device. Depending on the functions implemented, the extreme environment testing system 100 for power semiconductors may include a basic parameter verification module 101, a standard parameter verification module 102, an extreme environment testing module 103, and an environmental parameter acquisition module 104. The module described in this invention can also be referred to as a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and which are stored in the memory of the electronic device.

[0217] The basic parameter confirmation module 101 is used to acquire semiconductors and confirm the test environment, wherein the test environment includes: test platform, analyzer, temperature and humidity control box, infrared thermal imager and power cycling device, and confirms extreme temperature, extreme humidity and peak current based on semiconductors, analyzer and infrared thermal imager.

[0218] The standard parameter confirmation module 102 is used to fix the semiconductor on the test platform in the test environment to obtain a fixed semiconductor. Based on the preset standard temperature, temperature and humidity control box, analyzer in the test environment and fixed semiconductor, the parameters of the semiconductor under test and the standard semiconductor are confirmed. The standard semiconductor parameters include: standard threshold voltage, standard on-resistance and standard leakage current.

[0219] The extreme environment testing module 103 is used to identify the target control box based on extreme temperature, extreme humidity and temperature and humidity control box, use the target control box to apply environmental load to the semiconductor under test to obtain the target semiconductor, identify the target number of cycles, and identify multiple cycle number test values ​​based on the target number of cycles and the preset cycle number interval.

[0220] The environmental parameter acquisition module 104 is used to identify the termination semiconductor and the final number of cycles based on standard threshold voltage, standard on-resistance, standard leakage current, peak current, power cycling device in the test environment, multiple cycle test values ​​and target semiconductor, and to identify the extreme environmental parameters of the semiconductor based on the termination semiconductor, extreme temperature, extreme humidity, peak current and final number of cycles, thereby completing the extreme environmental test of the power semiconductor.

[0221] In detail, the modules in the extreme environment testing system 100 for power semiconductors described in this embodiment of the invention employ the same methods as described above during use. Figure 1 The extreme environment testing method for power semiconductors described herein uses the same technical means and can produce the same technical effect, so it will not be repeated here.

[0222] like Figure 3 The diagram shown is a schematic representation of an electronic device that implements an extreme environment testing method for power semiconductors according to an embodiment of the present invention.

[0223] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as a method program for extreme environment testing of power semiconductors.

[0224] The memory 11 includes at least one type of readable storage medium, such as flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as a portable hard drive. In other embodiments, the memory 11 can be an external storage device of the electronic device 1, such as a plug-in portable hard drive, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the electronic device 1. Furthermore, the memory 11 includes both internal storage units and external storage devices of the electronic device 1. The memory 11 can be used not only to store application software and various types of data installed on the electronic device 1, such as the code of extreme environment testing methods for power semiconductors, but also to temporarily store data that has been output or will be output.

[0225] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the memory 11 (e.g., extreme environment testing methods for power semiconductors) and calls data stored in the memory 11 to perform various functions of the electronic device 1 and process data.

[0226] The bus 12 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize the connection and communication between the memory 11 and at least one processor 10, etc.

[0227] Figure 3 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 3 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0228] For example, although not shown, the electronic device 1 may also include a power supply (such as a battery) to power the various components. Preferably, the power supply can be logically connected to the at least one processor 10 through a power management device, thereby enabling functions such as charging management, discharging management, and power consumption management. The power supply may also include one or more DC or AC power supplies, recharging devices, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0229] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, a Bluetooth interface, etc.), which is typically used to establish communication connections between the electronic device 1 and other electronic devices.

[0230] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), and optionally, a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device 1 and to display a visual user interface.

[0231] The extreme environment testing method program for power semiconductors stored in the memory 11 of the electronic device 1 is a combination of multiple instructions, which, when run in the processor 10, can achieve the following:

[0232] Acquire semiconductors and confirm the testing environment, which includes: a testing platform, an analyzer, a temperature and humidity control chamber, an infrared thermal imager, and a power cycling device;

[0233] Extreme temperatures, extreme humidity levels, and peak currents were identified using semiconductors, analyzers, and infrared thermal imagers.

[0234] A semiconductor is fixed on a test platform in a test environment to obtain a fixed semiconductor;

[0235] Based on the preset standard temperature, temperature and humidity control chamber, analyzer and fixed semiconductor in the test environment, the parameters of the semiconductor under test and the standard semiconductor are identified. The standard semiconductor parameters include: standard threshold voltage, standard on-resistance and standard leakage current.

[0236] The target control box was identified based on extreme temperature, extreme humidity, and temperature and humidity control boxes.

[0237] The target semiconductor is obtained by applying environmental conditions to the semiconductor under test using a target control box.

[0238] The target number of loops is determined, and multiple test values ​​for the number of loops are determined based on the target number of loops and the preset loop interval;

[0239] Based on standard threshold voltage, standard on-resistance, standard leakage current, peak current, power cycling device in the test environment, multiple cycle count test values, and target semiconductor, the termination semiconductor and final cycle count are identified.

[0240] Based on the termination of the semiconductor, extreme temperature, extreme humidity, peak current, and final cycle count, the extreme environmental parameters of the semiconductor are determined, and the extreme environmental test of the power semiconductor is completed.

[0241] Specifically, the processor 10's implementation method for the above instructions can be found in [reference needed]. Figures 1 to 3 The descriptions of the relevant steps in the corresponding embodiments are not repeated here.

[0242] Furthermore, if the modules / units integrated in the electronic device 1 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0243] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor of an electronic device, can perform the following:

[0244] Acquire semiconductors and confirm the testing environment, which includes: a testing platform, an analyzer, a temperature and humidity control chamber, an infrared thermal imager, and a power cycling device;

[0245] Extreme temperatures, extreme humidity levels, and peak currents were identified using semiconductors, analyzers, and infrared thermal imagers.

[0246] A semiconductor is fixed on a test platform in a test environment to obtain a fixed semiconductor;

[0247] Based on the preset standard temperature, temperature and humidity control chamber, analyzer and fixed semiconductor in the test environment, the parameters of the semiconductor under test and the standard semiconductor are identified. The standard semiconductor parameters include: standard threshold voltage, standard on-resistance and standard leakage current.

[0248] The target control box was identified based on extreme temperature, extreme humidity, and temperature and humidity control boxes.

[0249] The target semiconductor is obtained by applying environmental conditions to the semiconductor under test using a target control box.

[0250] The target number of loops is determined, and multiple test values ​​for the number of loops are determined based on the target number of loops and the preset loop interval;

[0251] Based on standard threshold voltage, standard on-resistance, standard leakage current, peak current, power cycling device in the test environment, multiple cycle count test values, and target semiconductor, the termination semiconductor and final cycle count are identified.

[0252] Based on the termination of the semiconductor, extreme temperature, extreme humidity, peak current, and final cycle count, the extreme environmental parameters of the semiconductor are determined, and the extreme environmental test of the power semiconductor is completed.

[0253] In the embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and actual implementations may have other classification methods.

[0254] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0255] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0256] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0257] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for testing power semiconductors under extreme environments, characterized in that, The method includes: Acquire semiconductors and confirm the testing environment, which includes: a testing platform, an analyzer, a temperature and humidity control chamber, an infrared thermal imager, and a power cycling device; Extreme temperatures, extreme humidity levels, and peak currents were identified using semiconductors, analyzers, and infrared thermal imagers. A semiconductor is fixed on a test platform in a test environment to obtain a fixed semiconductor; Based on the preset standard temperature, temperature and humidity control chamber, analyzer and fixed semiconductor in the test environment, the parameters of the semiconductor under test and the standard semiconductor are identified. The standard semiconductor parameters include: standard threshold voltage, standard on-resistance and standard leakage current. The target control box was identified based on extreme temperature, extreme humidity, and temperature and humidity control boxes. The target semiconductor is obtained by applying environmental conditions to the semiconductor under test using a target control box. The target number of loops is determined, and multiple test values ​​for the number of loops are determined based on the target number of loops and the preset loop interval; Based on standard threshold voltage, standard on-resistance, standard leakage current, peak current, power cycling device in the test environment, multiple cycle count test values, and target semiconductor, the termination semiconductor and final cycle count are identified. Based on the termination of the semiconductor, extreme temperature, extreme humidity, peak current, and final cycle count, the extreme environmental parameters of the semiconductor are determined, and the extreme environmental test of the power semiconductor is completed.

2. The extreme environment testing method for power semiconductors as described in claim 1, characterized in that, The identification of extreme temperatures, extreme humidity levels, and peak currents based on semiconductors, analyzers, and infrared thermal imagers includes: Obtain semiconductor basic parameters, including: maximum junction temperature, thermal resistance, on-resistance, transient thermal resistance image, and extreme humidity. The semiconductor is tested for its rated parameters using an analyzer to obtain the test current and test voltage drop; Calculate the extreme temperature based on the test current, test voltage drop, and thermal resistance; The allowable increase in junction temperature is calculated based on the maximum junction temperature. The pulse width was determined based on semiconductors, analyzers, maximum junction temperature, and infrared thermal imagers. The transient thermal resistance was determined based on the pulse width and transient thermal resistance images; The allowable power is calculated based on the allowable rising junction temperature and transient thermal resistance; Calculate the peak current based on the allowable power and on-resistance.

3. The extreme environment testing method for power semiconductors as described in claim 2, characterized in that, The pulse width determination based on semiconductors, analyzers, maximum junction temperature, and infrared thermal imagers includes: Obtain the power pulse source and determine the pulse control range based on the power pulse source; The pulse control range is divided according to the preset pulse division interval to obtain multiple pulse test values; For each of the multiple pulse test values, perform the following operation: The target pulse source was identified based on the pulse test values ​​and the power pulse source. The initial temperature of the semiconductor is obtained by measuring its temperature using an infrared thermal imager. A pulsed semiconductor is obtained by applying a pulse to a semiconductor using a target pulse source. The pulse temperature is obtained by measuring the temperature of the pulse semiconductor using an infrared thermal imager. The rise junction temperature was determined based on the initial temperature and the pulse temperature, where the rise junction temperature is the difference between the pulse temperature and the initial temperature. The pulse on-resistance was obtained by measuring the parameters of the pulse semiconductor using an analyzer. The test data is obtained by combining the pulse test value, the increased junction temperature, and the pulse on-resistance. Summarize the test data to obtain multiple test data sets; The pulse width was determined based on multiple test data and the maximum junction temperature.

4. The extreme environment testing method for power semiconductors as described in claim 3, characterized in that, The pulse width was determined based on multiple test data and the maximum junction temperature, including: Extracting the first from multiple test data The test data and the first There are 10 test data sets, among which... The initial value is 1; According to the The pulse on-resistance in the test data and the first Calculate the rate of change of electrical parameters from the pulse on-resistance in each test data set; Compare the rate of change of electrical parameters with a preset threshold. If the rate of change of electrical parameters is less than or equal to the threshold, then adjust the value of the electrical parameter corresponding to the rate of change. One set of test data was used as the filtering data; make ,Will As Returning to the extraction of the first from multiple test data The test data and the first The steps for each test data point, until... The filtered data is summarized to obtain multiple filtered data sets, among which... The number of test data points in a set of test data; The junction temperature threshold range was determined based on the maximum junction temperature. Perform the following operation on each of the multiple filtered data points: Determine whether the increased junction temperature in the filtered data is within the junction temperature threshold range. If the increased junction temperature in the filtered data is within the junction temperature threshold range, then use the pulse test value in the filtered data as the filtered pulse width. Summarize the filter pulse widths to obtain multiple filter pulse widths; The pulse width is determined based on multiple filtering pulse widths, where the pulse width is the median of the multiple filtering pulse widths.

5. The extreme environment testing method for power semiconductors as described in claim 4, characterized in that, The parameters of the semiconductor under test and the standard semiconductor are determined based on the preset standard temperature, temperature and humidity control chamber, analyzer and fixed semiconductor in the test environment, including: The control box was identified based on the standard temperature and humidity control box. The semiconductor to be tested is obtained by placing the fixed semiconductor in the control box; The semiconductor under test is statically measured using an analyzer in the test environment to obtain standard semiconductor parameters, including standard threshold voltage, standard on-resistance, and standard leakage current.

6. The extreme environment testing method for power semiconductors as described in claim 5, characterized in that, The determination of the termination semiconductor and the final number of cycles based on standard threshold voltage, standard on-resistance, standard leakage current, peak current, power cycling device in the test environment, multiple cycle count test values, and the target semiconductor includes: The target cycling device was identified based on peak current and power cycling device in the test environment. Extracting the first from multiple test values ​​of loop counts The number of test values ​​for each loop iteration, among which... The initial value is 1; Start the target loop device, apply power to the target semiconductor using the started target loop device, and record the number of loops simultaneously; When the number of loops equals the first When testing for a certain number of cycles, the analyzer in the test environment is used to perform parameter analysis on the target semiconductor to obtain the test threshold voltage, test on-resistance and test leakage current. The failure index was determined based on standard threshold voltage, standard on-resistance, standard leakage current, test threshold voltage, test on-resistance, and test leakage current. Compare the failure index with the preset failure index threshold. If the failure index is greater than or equal to the failure index threshold, stop the target cycle device and obtain the termination semiconductor and the final cycle number. If the failure index is less than the index threshold, then let ,Will As Returning the result extracted from the test values ​​of multiple loop counts. The step of testing the value for each loop iteration continues until... Stop the target loop device to obtain the termination semiconductor and the final number of loops, where, The number of test values ​​for multiple iterations.

7. The extreme environment testing method for power semiconductors as described in claim 6, characterized in that, The failure index, determined based on standard threshold voltage, standard on-resistance, standard leakage current, test threshold voltage, test on-resistance, and test leakage current, includes: Calculate the threshold voltage change value based on the standard threshold voltage and the test threshold voltage; The change in on-resistance was determined based on the standard on-resistance and the tested on-resistance. The leakage current variation was confirmed based on the standard leakage current and the test leakage current. The failure index is calculated based on the changes in threshold voltage, on-resistance, and leakage current, using the following formula: ， in, Indicates the failure index. This indicates the change in on-resistance. This represents the threshold voltage change value. This indicates the change in leakage current. It represents the natural logarithm.

8. The extreme environment testing method for power semiconductors as described in claim 7, characterized in that, The extreme environmental parameters of the semiconductor, determined based on the termination semiconductor, extreme temperature, extreme humidity, peak current, and final cycle number, include: The total volume, length, and high-resolution X-CT of the chip are obtained. The termination semiconductor is then scanned using high-resolution X-CT to obtain multiple scan images. A pre-built iterative reconstruction algorithm is used to reconstruct multiple scanned images to obtain a 3D image. The 3D image includes multiple voxels, and each voxel includes a voxel gray value. Threshold segmentation is performed on multiple voxels in a 3D image based on a preset grayscale threshold to obtain multiple defect voxels. For each of the multiple defective voxels, perform the following operation: Data measurements were performed on the defect voxels to obtain the defect volume and the maximum size of the defect. By summing the defect volume and the maximum size of the defect, we can obtain multiple defect volumes and multiple maximum size of the defect. The total defect volume is determined based on multiple defect volumes, where the total defect volume is the sum of the multiple defect volumes; The maximum defect maximum edge is determined based on the maximum edge of multiple defects, where the maximum defect maximum edge is the largest among the multiple maximum edge of defects. The damage index is calculated based on the total chip volume, chip length, total defect volume, and the maximum edge size of the largest defect. The calculation formula is as follows: ， in, Indicates the damage index. Indicates the total volume of the chip. Represents the total defect volume. Indicates chip length. This indicates the largest defect and the largest edge. The extreme environmental parameters of the semiconductor were determined based on the damage index, extreme temperature, extreme humidity, peak current, and final cycle number.

9. The extreme environment testing method for power semiconductors as described in claim 8, characterized in that, The threshold segmentation of multiple voxels in the 3D image based on a preset grayscale threshold yields multiple defect voxels, including: Perform the following operation on each of the multiple voxels in the 3D image: Compare the voxel gray value with the gray value threshold. If the voxel gray value is less than the gray value threshold, then the voxel is regarded as a defective voxel. By summing up the defect voxels, multiple defect voxels are obtained.

10. An extreme environment testing system for power semiconductors, characterized in that, The system includes: The basic parameter confirmation module is used to acquire semiconductors and confirm the test environment, which includes: test platform, analyzer, temperature and humidity control box, infrared thermal imager and power cycling device. Based on the semiconductors, analyzer and infrared thermal imager, extreme temperature, extreme humidity and peak current are confirmed. The standard parameter verification module is used to fix the semiconductor on the test platform in the test environment to obtain a fixed semiconductor. Based on the preset standard temperature, temperature and humidity control box, analyzer in the test environment and fixed semiconductor, the parameters of the semiconductor under test and the standard semiconductor are verified. The standard semiconductor parameters include: standard threshold voltage, standard on-resistance and standard leakage current. The extreme environment testing module is used to identify the target control box based on extreme temperature, extreme humidity and temperature and humidity control box, use the target control box to load the environment of the semiconductor under test, obtain the target semiconductor, identify the target number of cycles, and identify multiple cycle test values ​​based on the target number of cycles and the preset cycle interval. The environmental parameter acquisition module is used to identify the termination semiconductor and the final number of cycles based on standard threshold voltage, standard on-resistance, standard leakage current, peak current, power cycling device in the test environment, multiple cycle test values ​​and target semiconductor. Based on the termination semiconductor, extreme temperature, extreme humidity, peak current and final number of cycles, the module identifies the extreme environmental parameters of the semiconductor and completes the extreme environmental test of the power semiconductor.

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