Host-implemented memory operation program

Abstract

The invention relates to a host-implemented memory operation program. In some embodiments, a host device may receive instructions to execute commands associated with a memory device. The host device may identify a memory operation program corresponding to the command, where the memory operation program combines a plurality of memory commands supported by firmware of the memory device, and where the memory operation program is unavailable by the firmware of the memory device. The host device may transmit the plurality of memory commands to the memory device. The host device may receive, from the memory device, a plurality of responses related to execution of the plurality of memory commands by the memory device.

Description

[0001] Cross-reference of related applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 650,208, filed May 21, 2024, entitled "HOST-Implemented Memory Operation Procedures," assigned to its assignee. The disclosure of the prior application is considered part of this patent application and is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to memory devices, memory device operations, and, for example, to memory operation programs implemented by a host. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices. A memory device comprises memory cells. A memory cell is an electronic circuit that can be programmed into a data state of two or more data states. For example, a memory cell can be programmed to represent a single binary value (typically represented by a binary "1" or binary "0"). As another example, a memory cell can be programmed to represent a small value (e.g., 0.5, 1.5, or similar). To store information, an electronic device can write to or program a set of memory cells. To access the stored information, the electronic device can read from or sense the stored state of the set of memory cells.

[0005] Various types of memory devices exist, including Random Access Memory (RAM), Read-Only Memory (ROM), Dynamic RAM (DRAM), Static RAM (SRAM), Synchronous Dynamic RAM (SDRAM), Ferroelectric RAM (FeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Holographic RAM (HRAM), Flash memory (such as NAND and NOR memory), and others. Memory devices can be volatile or non-volatile. Non-volatile memory (such as flash memory) can store data for extended periods, even without external power. Volatile memory (such as DRAM) loses stored data over time unless refreshed by power. Summary of the Invention

[0006] On one hand, this disclosure provides a host system comprising: a host processor configured to: receive instructions to execute commands associated with a memory device; identify a memory operation program corresponding to the commands, wherein the memory operation program combines a plurality of memory commands supported by firmware of the memory device, and wherein the memory operation program is unavailable via the firmware of the memory device; transmit the plurality of memory commands to the memory device; and receive from the memory device a plurality of responses associated with the execution of the plurality of memory commands by the memory device.

[0007] On the other hand, this disclosure provides a method comprising: receiving, by a host device, instructions to execute commands associated with a memory device; transmitting, by the host device, a plurality of memory commands corresponding to the commands and a memory operation program, wherein the memory operation program is not natively supported by the memory device, and wherein the plurality of memory commands are natively supported by the memory device; and receiving, by the host device, a plurality of responses related to the execution of the plurality of memory commands by the memory device.

[0008] On the other hand, this disclosure provides a system comprising: a host device configured to: receive instructions to execute commands; identify a memory operation program corresponding to the commands, wherein the memory operation program combines a plurality of memory commands; and transmit the plurality of memory commands; and a memory device communicatively coupled to the host device, configured to: receive the plurality of memory commands; execute the plurality of memory commands; and transmit a plurality of responses related to the execution of the plurality of memory commands.

[0009] On the other hand, this disclosure provides an apparatus comprising: means for receiving instructions for executing commands associated with a memory device; means for transmitting to the memory device a plurality of memory commands corresponding to the commands, wherein the memory commands are unavailable via firmware of the memory device; means for receiving from the memory device information related to the execution of the plurality of memory commands by the memory device; and means for analyzing the information to generate diagnostic data associated with the memory device.

[0010] On the other hand, this disclosure provides a memory device including: one or more components configured to: receive from a host device a plurality of memory commands of a memory operation program, wherein the memory operation program is not natively supported by the memory device; and execute the plurality of memory commands. Attached Figure Description

[0011] Figure 1This is a diagram illustrating an example system capable of performing host-implemented memory operation programs.

[0012] Figure 2 This is a diagram of an example of a memory operation program implemented by the host.

[0013] Figure 3 It is a flowchart of an instance method associated with a memory operation procedure implemented by the host.

[0014] Figure 4 It is a flowchart of an instance method associated with a memory operation procedure implemented by the host. Detailed Implementation

[0015] Memory devices may have embedded firmware for operating and maintaining the memory device. Developing firmware for a memory device requires incorporating complex features to meet diverse requirements and / or address specific nuances of memory operation. However, implementing complex features directly within the firmware can be a complex and inefficient process, involving extensive design and verification phases that hinder the development of memory technology. In some cases, vulnerabilities or issues associated with the firmware may be discovered after deployment. Timely firmware updates to address these issues can be complicated by the embeddedness of the firmware and its architectural constraints, requiring additional design and verification layers.

[0016] Some of the implementations described herein allow for the simple and efficient extension of the functionality of a memory device by enabling the execution of complex features and procedures not natively supported by the memory device's firmware. In some implementations, the host device can execute software tools that configure complex memory operation procedures, each combining multiple basic memory commands. The host device can receive instructions via a software interface to execute commands concerning the memory device. These commands may correspond to memory operation procedures that, while not natively supported by the memory device's firmware, combine multiple memory commands natively supported by the memory device's firmware. Therefore, the host device can issue multiple memory commands to the memory device to implement the memory operation procedures. The memory operation procedures can facilitate diagnostic analysis of the memory device and / or provide solutions to known vulnerabilities or problems in the memory device's firmware.

[0017] In this way, the implementation of complex features and procedures is moved from embedded memory firmware to software on the host system, thereby reducing the complexity, resource requirements, and time needed to design and verify new memory features and procedures. By decoupling the memory operating procedures from the firmware, the techniques described herein improve the system's adaptability to functional changes or additions without requiring a full firmware overhaul. Furthermore, the techniques described herein enable efficient deployment of updates to quickly address known vulnerabilities or issues in the firmware.

[0018] Figure 1This is a diagram illustrating an example system 100 capable of performing host-implemented memory operations. System 100 may include one or more means, devices, and / or components for performing the operations described herein. For example, system 100 may include a host system 105 and a memory system 110. Memory system 110 may include a memory system controller 115 and one or more memory devices 120, shown as memory devices 120-1 to 120-N (where N≥1). Memory devices may include a local controller 125 and one or more memory arrays 130. Host system 105 may communicate with memory system 110 (e.g., memory system controller 115 of memory system 110) via a host interface 140. Memory system controller 115 and memory devices 120 may communicate via corresponding memory interfaces 145 (shown as memory interfaces 145-1 to 145-N (where N≥1)).

[0019] System 100 can be any electronic device configured to store data in memory. For example, system 100 can be a computer, mobile phone, wired or wireless communication device, network device, server, device in a data center, device in a cloud computing environment, vehicle (e.g., car or airplane), and / or Internet of Things (IoT) device. Host system 105 may include host processor 150. Host processor 150 may include one or more processors configured to execute instructions and store data in memory system 110. For example, host processor 150 may include a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and / or another type of processing component.

[0020] The memory system 110 can be any electronic device or apparatus configured to store data in memory. For example, the memory system 110 can be a hard disk drive, a solid-state drive (SSD), a flash memory system (such as a NAND flash memory system or a NOR flash memory system), a universal serial bus (USB) drive, a memory card (such as a secure digital card (SD) card), an auxiliary storage device, a non-volatile memory fast (NVMe) device, an embedded multimedia card (eMMC) device, a dual in-line memory module (DIMM), a universal flash memory (UFS) system, and / or a random access memory (RAM) device, such as a dynamic RAM (DRAM) device or a static RAM (SRAM) device.

[0021] The memory system controller 115 may be any device configured to control the operation of the memory system 110 and / or the operation of the memory device 120. For example, the memory system controller 115 may include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some embodiments, the memory system controller 115 may communicate with the host system 105 and may instruct one or more memory devices 120 regarding memory operations performed by these memory devices 120 based on one or more instructions from the host system 105. For example, the memory system controller 115 may provide instructions to a local controller 125 regarding memory operations performed by the local controller 125 in conjunction with corresponding memory devices 120.

[0022] Memory device 120 may include a local controller 125 and one or more memory arrays 130. In some embodiments, memory device 120 includes a single memory array 130. In some embodiments, each memory device 120 of memory system 110 may be implemented in a separate semiconductor package or on a separate die, the die including the corresponding local controller 125 and corresponding memory array 130 of that memory device 120. Memory system 110 may include multiple memory devices 120.

[0023] The local controller 125 may be any device configured to control memory operations of the memory device 120 containing the local controller 125 (e.g., without controlling memory operations of other memory devices 120). For example, the local controller 125 may include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some embodiments, the local controller 125 may communicate with the memory system controller 115 and may control operations performed on the memory array 130 coupled to the local controller 125 based on one or more instructions from the memory system controller 115. As an example, the memory system controller 115 may be an SSD controller, and the local controller 125 may be a NAND controller.

[0024] Memory array 130 may include an array of memory cells configured to store data. For example, memory array 130 may include a non-volatile memory array (e.g., a NAND memory array or a NOR memory array) or a volatile memory array (e.g., an SRAM array or a DRAM array). In some embodiments, memory system 110 may include one or more volatile memory arrays 135. Volatile memory array 135 may include SRAM arrays and / or DRAM arrays, and other examples. One or more volatile memory arrays 135 may be included in memory system controller 115, one or more memory devices 120, and / or both memory system controller 115 and one or more memory devices 120. In some embodiments, memory system 110 may include both non-volatile memory capable of retaining stored data after power failure of memory system 110 and volatile memory (e.g., volatile memory array 135) requiring power to retain stored data and losing stored data after power failure of memory system 110. For example, the volatile memory array 135 may cache data read from or written to non-volatile memory, and / or cache instructions to be executed by the controller of the memory system 110.

[0025] Host interface 140 enables communication between host system 105 (e.g., host processor 150) and memory system 110 (e.g., memory system controller 115). Host interface 140 may include, for example, a Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Fast (PCIe) interface, NVMe interface, USB interface, Universal Flash Storage (UFS) interface, eMMC interface, Double Data Rate (DDR) interface, and / or DIMM interface.

[0026] Memory interface 145 enables communication between memory system 110 and memory device 120. Memory interface 145 may include a non-volatile memory interface (e.g., for communicating with non-volatile memory), such as a NAND interface or a NOR interface. Alternatively, memory interface 145 may include a volatile memory interface (e.g., for communicating with volatile memory), such as a DDR interface.

[0027] Although the above-described example memory system 110 includes a memory system controller 115, in some embodiments, the memory system 110 does not include a memory system controller 115. For example, an external controller (e.g., included in host system 105) and / or one or more local controllers 125 included in one or more corresponding memory devices 120 may perform the operations described herein as being performed by the memory system controller 115. Furthermore, as used herein, "controller" may refer to memory system controller 115, local controller 125, or external controller. In some embodiments, a set of operations described herein as being performed by a controller may be performed by a single controller. For example, the entire set of operations may be performed by a single memory system controller 115, a single local controller 125, or a single external controller. Alternatively, a set of operations described herein as being performed by a controller may be performed by more than one controller. For example, a first subset of operations may be performed by memory system controller 115 and a second subset of operations may be performed by local controller 125. Furthermore, depending on the context, the term "memory device" may refer to memory system 110 or memory device 120.

[0028] A controller (e.g., memory system controller 115, local controller 125, or external controller) can control operations performed on memory (e.g., memory array 130), such as by executing one or more instructions. For example, memory system 110 and / or memory device 120 may store one or more instructions as firmware in memory, and the controller may execute these instructions. Alternatively, the controller may receive one or more instructions from host system 105 and / or from memory system controller 115, and may execute these instructions. In some embodiments, a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory) may store a set of instructions (e.g., one or more instructions or codes) for execution by the controller. The controller may execute the set of instructions to perform one or more operations or methods described herein. In some embodiments, execution of the set of instructions by the controller causes the controller, memory system 110, and / or memory device 120 to perform one or more operations or methods described herein. In some embodiments, a hardwired circuit system is used in place of or in combination with one or more instructions to perform one or more operations or methods described herein. Alternatively or concurrently, the controller may be configured to perform one or more operations or methods described herein. Instructions are sometimes referred to as “commands”.

[0029] For example, a controller (e.g., memory system controller 115, local controller 125, or external controller) may transmit signals to and / or receive signals from a memory (e.g., one or more memory arrays 130) based on one or more instructions, such as transferring (e.g., writing or programming) data to all or part of the memory (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes), transferring (e.g., reading) data from all or part of the memory, erasing all or part of the memory, and / or refreshing all or part of the memory. Alternatively or additionally, the controller may be configured to control access to the memory and / or provide a translation layer (e.g., for mapping logical addresses to physical addresses of the memory array 130) between the host system 105 and the memory. In some embodiments, the controller may translate host interface commands (e.g., commands received from the host system 105) into memory interface commands (e.g., commands for performing operations on the memory array 130).

[0030] In some implementation schemes, Figure 1 One or more systems, apparatuses, devices, components and / or controllers may be configured to: receive instructions to execute commands associated with a memory device; identify a memory operation program corresponding to the command, wherein the memory operation program combines multiple memory commands supported by the firmware of the memory device, and wherein the memory operation program is unavailable through the firmware of the memory device; transmit multiple memory commands to the memory device; and receive multiple responses from the memory device associated with the execution of the multiple memory commands by the memory device.

[0031] In some implementation schemes, Figure 1 One or more systems, apparatuses, devices, components and / or controllers may be configured to: receive instructions to execute commands associated with a memory device; transmit to the memory device a plurality of memory commands corresponding to the commands, wherein the memory commands are not natively supported by the memory device and wherein the plurality of memory commands are natively supported by the memory device; and receive from the memory device a plurality of responses associated with the execution of the plurality of memory commands by the memory device.

[0032] In some implementation schemes, Figure 1 One or more systems, apparatuses, devices, components and / or controllers may be configured to: receive instructions to execute commands; identify memory operation programs corresponding to commands, wherein the memory operation programs combine multiple memory commands; and transmit multiple memory commands, and / or may be configured to: receive multiple memory commands; execute multiple memory commands; and transmit multiple responses related to the execution of multiple memory commands.

[0033] In some implementation schemes, Figure 1One or more systems, apparatuses, devices, components and / or controllers may be configured to: receive instructions to execute commands associated with a memory device; transmit multiple memory commands corresponding to memory operating procedures, wherein the memory operating procedures are available via the firmware of the memory device; receive information from the memory device related to the execution of multiple memory commands by the memory device; and analyze the information to generate diagnostic data associated with the memory device.

[0034] In some implementation schemes, Figure 1 One or more systems, apparatuses, devices, components and / or controllers may be configured to: receive multiple memory commands from a host device, wherein the memory commands are not natively supported; and execute the multiple memory commands.

[0035] Figure 1 The number and arrangement of components shown are for illustrative purposes only. In reality, the actual number and arrangement of components are... Figure 1 Compared to the components shown, there may be additional components, fewer components, different components, or components arranged differently. Furthermore, Figure 1 The two or more components shown can be implemented within a single component, or Figure 1 The single component shown can be implemented as multiple distributed components. Alternatively, Figure 1 The set of components shown (e.g., one or more components) can be described as being by Figure 1 The other set of components shown in the diagram performs one or more operations.

[0036] Figure 2 This is a diagram of an example 200 of a memory operation program implemented by a host. As shown, example 200 includes a host device 202 and a memory device 204. Host device 202 may correspond to or may include host system 105 and / or host processor 150. Host device 202 may implement an application (e.g., a user software tool) that configures one or more memory operations (e.g., test streams, program streams, or the like). Each memory operation program may combine multiple memory operations (e.g., sequentially). Each memory operation program can be run on host device 202 using a single command issued by the application program. Memory device 204 may correspond to or may include memory system 110, memory system controller 115, memory device 120, and / or local controller 125. In some embodiments, memory device 204 may include a managed NAND (mNAND) memory device. Memory device 204 may implement firmware configured to support multiple memory commands.

[0037] As illustrated by reference numeral 206, host device 202 may receive instructions to execute commands associated with memory device 204 (e.g., a single command to simplify user-side use). For example, the command may be executed via an application, causing host device 202 to receive instructions to execute the command. In some embodiments, the instructions to execute the command may be based on user input from a user interface associated with the application. In some embodiments, the instructions to execute the command may be automatically generated by host device 202 or other systems based on configuration time intervals or in response to events (e.g., turning on or restarting host device 202 and / or memory device 204).

[0038] As illustrated by reference numeral 208, in response to receiving a command, host device 202 (e.g., using an application) can identify a memory operation procedure (e.g., a single test stream or program stream) corresponding to the command. For example, each memory operation procedure configured in the application can be invoked using a corresponding command. Memory operation procedures can combine multiple memory commands (e.g., in a specific sequence). For example, memory commands can be basic commands combined into more complex memory operation procedures. Commands and memory operation procedures may not be natively supported by memory device 204. For example, memory operation procedures may be non-native operations of memory device 204. As an example, memory operation procedures may be made unavailable through the firmware of memory device 204 (e.g., memory operation procedures may implement features that are unavailable through firmware, such as for memory debugging or use). Specifically, the firmware of memory device 204 may not be configured (e.g., programmed) to implement a specific combination of memory commands of memory operation procedures as a single program. In contrast, memory commands may be natively supported by memory device 204. For example, memory commands may be supported by the firmware of memory device 204. Specifically, the firmware of memory device 204 can be configured (e.g., programmed) to individually implement the operation of memory commands (e.g., but not as part of a single program). As an example, memory commands can be vendor-defined commands or commands defined by standards organizations (e.g., the Joint Electronic Devices Engineering Committee (JEDEC)). For example, memory commands may include read, write, erase, status check, wear leveling, block protection, and / or secure erase commands.

[0039] The host device 202 can use multiple memory commands to dynamically construct a memory operation program. For example, instead of issuing a single command representing a program to the memory device 204, the host device 202 can construct the memory operation program in real time by combining memory commands (e.g., when a command is received by the host device 202). In some embodiments, the host device 202 can recognize a sequence of memory commands (e.g., which may be indicated in the configuration of the memory operation program provided in the application), and the host device 202 can construct the memory operation program based on the sequence.

[0040] In some implementations, the memory operator may be configured to address (e.g., parse) defects (e.g., vulnerabilities or other problems) in the firmware of the memory device 204 (e.g., the memory operator may provide contingency plans for vulnerabilities or other problems). For example, the memory operator may modify the state or operating state of the memory device 204 to provide a secure operating state for the memory device 204 (e.g., an operating state that prevents or mitigates platform failures, data loss, and / or data corruption). In some implementations, the memory operator may be configured to obtain specific information from the memory device 204 that can be used for diagnostic or similar purposes.

[0041] As illustrated by reference numeral 210, host device 202 (e.g., using an application) can transmit, and memory device 204 can receive, multiple memory commands of a memory operation program (e.g., on a bus from host device 202 to memory device 204). In some embodiments, host device 202 can transmit memory commands according to a sequence identified for the memory commands. In some embodiments, host device 202 can sequentially transmit memory commands (e.g., regardless of whether according to a particular sequence) after transmitting each of the memory commands, with or without waiting for a response from memory device 204. In some embodiments, host device 202 can transmit memory commands concurrently (e.g., in parallel or as part of a single instruction), such that a response from memory device 204 may not be transmitted between memory commands.

[0042] In some embodiments, host device 202 may transmit and memory device 204 may receive one or more first memory commands of a memory operation procedure (e.g., as a first step of the memory operation procedure). Memory device 204 may execute the first memory commands, and memory device 204 may transmit and host device 202 may receive one or more initial responses associated with the execution of the first memory commands. Based on the initial responses, host device 202 may determine one or more second memory commands of the memory operation procedure to be executed by memory device 204. For example, if the initial response contains a first indication or first information, then host device 202 may determine (e.g., select) a specific memory command to be executed by memory device 204. In some embodiments, host device 202 may process the first indication or first information to generate data (e.g., diagnostic data, analytical data, or the like), and host device may determine (e.g., select) a specific memory command based on the data (e.g., data-based analysis). Continuing with the example, if the initial response contains a second indication or second information, then host device 202 may determine (e.g., select) a different specific memory command to be executed by memory device 204. Based on the determination of the second memory command, the host device 202 can transmit and the memory device 204 can receive the second memory command (e.g., as a second step in a memory operation procedure).

[0043] As illustrated by reference numeral 212, memory device 204 can execute memory commands of a memory operation program (e.g., as a single memory operation program or as multiple steps of a memory operation program). For example, memory device 204 can execute memory commands as if it were any memory commands natively supported by memory device 204. In some embodiments, memory device 204 can execute memory commands in a sequence in which memory device 204 receives memory commands. In some embodiments, executing a memory command can cause memory device 204 to retrieve or collect information stored by memory device 204 according to the memory command (e.g., the memory command can command specific data to be read from memory device 204). In some embodiments, executing a memory command can cause memory device 204 to modify the state or operating state of memory device 204 according to the memory command (e.g., the memory command can command specific data to be written to memory device 204), which can resolve faults in the firmware of memory device 204 and / or achieve a safe operating state for memory device 204.

[0044] As illustrated by reference numeral 214, memory device 204 can transmit, and host device 202 (e.g., using an application) can receive, multiple responses (e.g., feedback) related to memory device 204 executing memory commands. In some embodiments, the responses may indicate information from memory device 204 (e.g., retrieved from memory device 204) related to the execution of memory commands, which may be used for diagnostic or similar purposes. For example, the information may include virtual block information (e.g., a set of parameters indicating the “dirtiness” of memory device 204) or other information (e.g., parameters) related to the state, performance, and / or capacity of memory device 204, and other instances. Host device 202 may map the information to memory commands transmitted by host device 202 (e.g., according to the sequence of transmitted memory commands) to identify the corresponding portion (e.g., the corresponding parameters) of the information in response to the corresponding transmitted memory command. In some embodiments, the responses may indicate that memory device 204 successfully executed (or in some cases failed) a memory command. For example, the response could indicate that the state or operating state of the memory device 204 has been modified according to a memory command, or that a defect in the firmware of the memory device 204 has been resolved (e.g., patched) according to a memory command, or something similar. In this way, memory commands of the firmware of the memory device 204 can be used without exposing sensitive information related to the firmware structure to the user of the application.

[0045] As illustrated by reference numeral 216, host device 202 (e.g., using an application) can generate output based on a response from memory device 204. For example, the application can process or otherwise use the response to generate output that can be consumed by other applications or systems of host device 202. In some embodiments, if the response from memory device 204 merely indicates successful execution of a memory command, then host device 202 can generate output indicating the completion of the memory operation. In some embodiments, if the response from memory device 204 indicates information from memory device 204, then host device 202 (e.g., using an application) can analyze the information (e.g., the information can be used to perform one or more calculations). Furthermore, based on the analyzed information, host device 202 can generate diagnostic data related to memory device 204. For example, the diagnostic data can facilitate troubleshooting or performance optimization of memory device 204.

[0046] By decoupling the memory operating system from the firmware, the techniques described in this paper improve the system's adaptability to functional changes or additions without requiring a full firmware overhaul. Furthermore, the techniques described in this paper enable efficient deployment of updates to quickly resolve known vulnerabilities or issues in the firmware.

[0047] As indicated above, Figure 2 For illustrative purposes only. Other examples can be found in the section on... Figure 2The descriptions are different.

[0048] Figure 3 This is a flowchart of an example method 300 associated with a memory operation program implemented by a host. In some embodiments, a host system (e.g., host system 105) is executable or configurable to perform method 300. In some embodiments, another device or group of devices (e.g., memory system 110) separate from or including the host system is executable or configurable to perform method 300. Alternatively or additionally, one or more components of the host system (e.g., host processor 150) are executable or configurable to perform method 300. Thus, the components for performing method 300 may include the host system and / or one or more components of the host system. Alternatively or additionally, a non-transitory computer-readable medium may store one or more instructions that, when executed by the host system, cause the host system to perform method 300.

[0049] like Figure 3 As shown, method 300 may include receiving instructions (block 310) to execute commands related to the memory device. Figure 3 As further shown, method 300 may include identifying a memory operator corresponding to a command, wherein the memory operator combines multiple memory commands supported by the firmware of the memory device, and wherein the memory operator is unavailable via the firmware of the memory device (box 320). Figure 3 As further shown in the diagram, method 300 may include transmitting multiple memory commands to a memory device (block 330). Figure 3 As further shown in the diagram, method 300 may include receiving multiple responses from the memory device in relation to the execution of multiple memory commands by the memory device (block 340).

[0050] Method 300 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere herein.

[0051] In the first aspect, identifying multiple memory commands includes identifying a sequence of multiple memory commands, and transmitting multiple memory commands includes transmitting multiple memory commands according to the sequence.

[0052] In the second aspect, either alone or in conjunction with the first aspect, transmitting a plurality of memory commands includes: transmitting one or more first memory commands to a memory device; receiving one or more initial responses from the memory device in relation to the memory device executing one or more first memory commands; determining one or more second memory commands to be transmitted to the memory device based on the one or more initial responses; and transmitting one or more second memory commands to the memory device.

[0053] In the third aspect, either alone or in combination with one or more of the first and second aspects, multiple responses may contain information from a memory device.

[0054] In the fourth aspect, method 300 includes using information to generate diagnostic data, either alone or in combination with one or more of the first to third aspects.

[0055] In the fifth aspect, either alone or in combination with one or more of the first to fourth aspects, multiple responses indicate that the memory device has successfully executed multiple memory commands.

[0056] In the sixth aspect, either alone or in combination with one or more of the first to fifth aspects, method 300 includes generating output indicating the completion of a memory operation procedure.

[0057] In the seventh aspect, the memory operating procedure, alone or in combination with one or more of the first to sixth aspects, will resolve defects in the firmware of the memory device.

[0058] In the eighth aspect, the memory operating procedure modifies the state or operating state of the memory device, either alone or in combination with one or more of the first to seventh aspects.

[0059] In the ninth aspect, the memory device includes an mNAND memory device, either alone or in combination with one or more of the first to eighth aspects.

[0060] although Figure 3 The example box for method 300 is shown, but in some implementations, it is different from... Figure 3 Compared to the boxes depicted herein, method 300 may include additional boxes, fewer boxes, different boxes, or boxes with different arrangements. Alternatively, two or more boxes of method 300 may be executed in parallel. Method 300 is an example of a method that can be performed by one or more means described herein. These means may perform or be configured to perform one or more other methods based on the operations described herein.

[0061] Figure 4This is a flowchart of an example method 400 associated with a memory operation program implemented by a host. In some embodiments, a memory system (e.g., memory system 110) is executable or configurable to perform method 400. In some embodiments, another device or group of devices (e.g., host system 105) separate from or including the memory system is executable or configurable to perform method 400. Alternatively or additionally, one or more components of the memory system (e.g., memory system controller 115, memory device 120, and / or local controller 125) are executable or configurable to perform method 400. Thus, the components for performing method 400 may include the memory system and / or one or more components of the memory system. Alternatively or additionally, a non-transitory computer-readable medium may store one or more instructions that, when executed by the memory system, cause the memory system to perform method 400.

[0062] like Figure 4 As shown, method 400 may include receiving multiple memory commands from a memory operation procedure, wherein the memory operation procedure is not natively supported by the memory device (box 410). Figure 4 As further shown in the diagram, method 400 may include executing multiple memory commands (block 420).

[0063] Method 400 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere herein.

[0064] In the first aspect, method 400 includes transmitting multiple responses related to the execution of multiple memory commands.

[0065] In the second aspect, either alone or in combination with the first aspect, multiple responses contain information from the memory device.

[0066] In the third aspect, either alone or in combination with one or more of the first and second aspects, multiple responses indicate that the memory device has successfully executed multiple memory commands.

[0067] In the fourth aspect, the memory operating procedure, alone or in combination with one or more of the first to third aspects, will resolve defects in the firmware of the memory device.

[0068] In the fifth aspect, executing multiple memory commands, either alone or in combination with one or more of the first to fourth aspects, includes modifying the state or operational state of the memory device according to the multiple memory commands.

[0069] In the sixth aspect, receiving multiple memory commands, either alone or in combination with one or more of the first to fifth aspects, includes sequentially receiving multiple memory commands.

[0070] In the seventh aspect, receiving a plurality of memory commands, either alone or in combination with one or more of the first to sixth aspects, includes: receiving one or more first memory commands among the plurality of memory commands; transmitting one or more initial responses related to the execution of one or more first memory commands; and receiving one or more second memory commands among the plurality of memory commands.

[0071] although Figure 4 The example box for method 400 is shown, but in some implementations, it is different from... Figure 4 Compared to the boxes depicted herein, method 400 may include additional boxes, fewer boxes, different boxes, or boxes with different arrangements. Alternatively, two or more boxes of method 400 may be executed in parallel. Method 400 is an example of a method that can be performed by one or more means described herein. These means may perform or be configured to perform one or more other methods based on the operations described herein.

[0072] In some embodiments, a host system includes a host processor configured to: receive instructions to execute commands associated with a memory device; identify a memory operation program corresponding to the commands, wherein the memory operation program combines a plurality of memory commands supported by the firmware of the memory device, and wherein the memory operation program is unavailable through the firmware of the memory device; transmit the plurality of memory commands to the memory device; and receive from the memory device a plurality of responses associated with the execution of the plurality of memory commands by the memory device.

[0073] In some implementations, a method includes: receiving instructions from a host device to execute commands associated with a memory device; transmitting from the host device to the memory device a plurality of memory commands corresponding to the commands, wherein the memory commands are not natively supported by the memory device, and wherein the plurality of memory commands are natively supported by the memory device; and receiving from the memory device a plurality of responses associated with the execution of the plurality of memory commands by the memory device.

[0074] In some embodiments, a system includes: a host device configured to: receive instructions to execute commands; identify a memory operation program corresponding to the commands, wherein the memory operation program combines a plurality of memory commands; and transmit the plurality of memory commands; and a memory device communicatively coupled to the host device, configured to: receive the plurality of memory commands; execute the plurality of memory commands; and transmit a plurality of responses associated with the execution of the plurality of memory commands.

[0075] In some embodiments, an apparatus includes: means for receiving instructions to execute commands associated with a memory device; means for transmitting to the memory device a plurality of memory commands corresponding to the commands, wherein the memory commands are unavailable via firmware of the memory device; means for receiving from the memory device information related to the execution of the plurality of memory commands by the memory device; and means for analyzing the information to generate diagnostic data associated with the memory device.

[0076] In some embodiments, a memory device includes one or more components configured to: receive from a host device a plurality of memory commands of a memory operation program, wherein the memory operation program is not natively supported by the memory device; and execute the plurality of memory commands.

[0077] The above disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations may be made in light of the above disclosure or from the practice of the implementation described herein.

[0078] Even though a particular combination of features is recited in the claims and / or disclosed in the specification, such combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features can be combined in ways not specifically recited in the claims and / or not disclosed in the specification. For example, this disclosure includes each dependent claim in a group of claims in combination with each other individual claim in the group of claims and each combination of multiple claims in the group of claims. As used herein, the phrase “at least one of” in the list of items refers to any combination of these items, including a single member. As an example, “at least one of a, b, or c” is intended to cover a, b, c, a+b, a+c, b+c, and a+b+c, as well as any combination having multiple identical elements (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c or any other ordering of a, b, and c).

[0079] When “a component” or “one or more components” (or another element, such as “a controller” or “one or more controllers”) is described or claimed (within a single claim or across multiple claims) as performing or configured to perform multiple operations, this term is intended to broadly encompass a variety of architectures and environments. For example, unless explicitly claimed otherwise (e.g., by using “first component” and “second component” or other terms distinguishing components in the claims), this term is intended to cover a single component performing or configured to perform all operations, a group of components jointly performing or configured to perform all operations, a first component performing or configured to perform a first operation and a second component performing or configured to perform a second operation, or any combination of components performing or configured to perform operations. For example, when a claim has the form “one or more components configured to: perform X; perform Y; and perform Z”, this claim should be interpreted as meaning “one or more components configured to perform X; one or more (possibly different) components configured to perform Y; and one or more (possibly different) components configured to perform Z.”

[0080] No element, action, or instruction as used herein should be construed as critical or essential unless explicitly stated otherwise. Furthermore, as used herein, the article “a” is intended to include one or more items and is interchangeable with “one or more.” Additionally, as used herein, the article “described” is intended to include one or more items referenced by the article “described” and is interchangeable with “described one or more.” When only one item is desired, the phrases “only one,” “single,” or similar terms are used. Furthermore, as used herein, the term “having” or similar terms are intended to be open-ended terms that do not limit their modification (e.g., an element “having” A may also have B). Furthermore, the phrase “based on” is intended to mean “at least partially based on,” unless explicitly stated otherwise. As used herein, the term “multiple” can be replaced with “a plurality of,” and vice versa. Furthermore, as used herein, the term “or” is intended to be inclusive when used in series and is interchangeable with “and / or” unless otherwise expressly stated (e.g., if used in combination with “(two)... either one” or “... only one of”).

Claims

1. A host system comprising: The host processor is configured to: Receive instructions to execute commands related to memory devices; Identify the memory operation program corresponding to the command. The memory operation program combines multiple memory commands supported by the firmware of the memory device, and The memory operating program is unavailable via the firmware of the memory device. Transmit the plurality of memory commands to the memory device; and Receive multiple responses from the memory device related to the execution of the multiple memory commands by the memory device.

2. The host system of claim 1, wherein, in order to identify the plurality of memory commands, the host processor is configured to identify a sequence of the plurality of memory commands, and In order to transmit the plurality of memory commands, the host processor is configured to transmit the plurality of memory commands according to the sequence.

3. The host system of claim 1, wherein, in order to transmit the plurality of memory commands, the host processor is configured to: Transmit one or more first memory commands from the plurality of memory commands to the memory device; Receive one or more initial responses from the memory device in relation to the execution of the one or more first memory commands by the memory device; Based on the one or more initial responses, one or more second memory commands will be determined from the plurality of memory commands to be transmitted to the memory device; and Transmit one or more second memory commands to the memory device.

4. The host system of claim 1, wherein the plurality of responses include information from the memory device.

5. The host system of claim 4, wherein the host processor is further configured to: The information is used to generate diagnostic data.

6. The host system of claim 1, wherein the plurality of responses indicate that the memory device has successfully executed the plurality of memory commands.

7. The host system of claim 6, wherein the host processor is further configured to: Generates output indicating the completion of the memory operation procedure.

8. The host system of claim 1, wherein the memory operating program resolves defects in the firmware of the memory device.

9. The host system of claim 1, wherein the memory operating program modifies the state or operating state of the memory device.

10. The host system of claim 1, wherein the memory device comprises a managed NAND mNAND memory device.

11. A method comprising: The host device receives instructions to execute commands related to the memory device; The host device transmits multiple memory commands, corresponding to the memory operation program of the command, to the memory device. The memory operation program is not natively supported by the memory device, and The aforementioned multiple memory commands are natively supported by the memory device; and The host device receives multiple responses from the memory device related to the execution of the multiple memory commands by the memory device.

12. The method of claim 11, further comprising: Identify the memory operation program corresponding to the command.

13. The method of claim 11, wherein transmitting the plurality of memory commands comprises: The memory commands are transmitted sequentially after each of the plurality of memory commands without waiting for a response from the memory device.

14. The method of claim 11, wherein transmitting the plurality of memory commands comprises: Transmit one or more first memory commands from the plurality of memory commands; Receive one or more initial responses from the memory device in relation to the execution of the one or more first memory commands by the memory device; Based on the one or more initial responses, one or more second memory commands are determined from the plurality of memory commands to be executed by the memory device; and Transmit one or more second memory commands to the memory device.

15. The method of claim 11, wherein the memory operating program is configured to execute on the host device.

16. The method of claim 11, further comprising: The memory operation program is dynamically constructed using the plurality of memory commands.

17. The method of claim 11, wherein the memory operating procedure implements a safe operating state for the memory device.

18. A system comprising: The host device, configured to: Receive instructions to execute commands; Identify the memory operation program corresponding to the command. The memory operation program combines multiple memory commands; and Transmit the multiple memory commands; and A memory device, communicatively coupled to the host device, configured to: Receive the plurality of memory commands; Execute the plurality of memory commands; and Multiple responses related to the transmission and execution of the multiple memory commands.

19. The system of claim 18, wherein the memory operation procedure is a non-native operation of the memory device.

20. The system of claim 18, wherein the memory operating program is unavailable via the firmware of the memory device.

21. The system of claim 20, wherein the plurality of memory commands are supported by the firmware of the memory device.

22. The system of claim 18, wherein the plurality of responses includes information from the memory device, and The host device is further configured to: The information is used to generate diagnostic data.

23. The system of claim 18, wherein the memory device comprises a managed NAND mNAND memory device.

24. An apparatus comprising: A component for receiving instructions that execute commands related to a memory device; A component for transmitting multiple memory commands, corresponding to the memory operation program of the command, to the memory device. The memory operating program is not available via the firmware of the memory device; A component for receiving information related to the execution of the plurality of memory commands from the memory device; and Components for analyzing the information to generate diagnostic data related to the memory device.

25. The device according to claim 24, further comprising: A component used to identify the memory operation program corresponding to the command.

26. The device of claim 24, wherein the plurality of memory commands are supported by the firmware of the memory device.

27. The device of claim 24, wherein the memory operating procedure modifies the state or operating state of the memory device.

28. A memory device comprising: One or more components, configured to: Receive multiple memory commands from the host device's memory operation program. The memory operation program is not natively supported by the memory device. and Execute the plurality of memory commands.

29. The memory device of claim 28, wherein the one or more components are further configured to: Multiple responses related to the transmission and execution of the multiple memory commands.

30. The memory device of claim 29, wherein the plurality of responses comprise information from the memory device.

31. The memory device of claim 29, wherein the plurality of responses indicate that the memory device has successfully executed the plurality of memory commands.

32. The memory device of claim 28, wherein the memory operating procedure resolves defects in the firmware of the memory device.

33. The memory device of claim 28, wherein, in order to execute the plurality of memory commands, the one or more components are configured to: The state or operating state of the memory device is modified according to the plurality of memory commands.

34. The memory device of claim 28, wherein, in order to receive the plurality of memory commands, the one or more components are configured to: The plurality of memory commands are received sequentially.

35. The memory device of claim 28, wherein, in order to receive the plurality of memory commands, the one or more components are configured to: Receive one or more first memory commands from the plurality of memory commands; Transmit one or more initial responses related to the execution of the one or more first memory commands; and Receive one or more second memory commands from the plurality of memory commands.

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