Method and system for checking NAND Flash storage chip

Abstract

The invention relates to the technical field of NAND Flash storage chip verification, and particularly discloses a NAND Flash storage chip verification method and system, and the method comprises the steps: bad block scanning and marking, data fragmentation and distribution, parallel verification execution, and verification frequency adaptive adjustment. The method comprises the following steps: performing full-slice scanning detection, marking bad blocks, generating a bad block distribution diagram, dynamically adjusting the sizes of slices according to the bad block distribution diagram, allocating the slices to different verification channels, performing rapid verification and deep verification through parallel verification, monitoring the processing progress of the verification channels in real time, and adjusting an allocation strategy by adopting a load balancing algorithm. And the verification frequency is dynamically adjusted according to the physical characteristics of the storage unit. The method can comprehensively and accurately detect bad blocks, reasonably allocate verification resources, improve verification efficiency and data reliability, improve the overall performance of the system, adapt to different working environments and use scenes, and have wide application prospects.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of verification of NAND Flash memory chips, and relates to a verification method and system for NAND Flash memory chips. BACKGROUND

[0002] In modern electronic devices, NAND Flash memory chips are widely used due to their high storage density, non-volatility, and other advantages. As the storage density of NAND Flash memory chips continues to increase, the size of the storage units continues to decrease, leading to a decrease in the reliability of the storage units and the easy occurrence of bad blocks. At the same time, in the long-term use process, the storage units will gradually wear out due to continuous erase and write operations, and changes in operating temperature will also affect the performance of the storage units. These factors will all lead to a decrease in the reliability of data storage. Therefore, effective verification of NAND Flash memory chips is the key to ensuring data reliability.

[0003] The existing technology still has the following problems: 1. In the data fragmentation process, a fixed fragmentation size is used, which cannot be dynamically adjusted according to actual conditions such as bad block density, leading to unreasonable fragmentation and affecting verification efficiency.

[0004] 2. The allocation of verification channels lacks scientific basis and cannot be reasonably allocated according to the risk level of the fragments, leading to excessive load on some verification channels and the idling of other channels, resulting in low overall verification efficiency.

[0005] 3. The verification strategy is fixed and cannot be dynamically adjusted according to the physical characteristics of the storage units (such as the number of erase and write operations, operating temperature, etc.), making it difficult to adapt to different working environments and usage scenarios, and the data reliability cannot be effectively guaranteed. SUMMARY

[0006] In view of this, in order to solve the problems raised in the background art, a verification method and system for NAND Flash memory chips are proposed.

[0007] The purpose of the application can be achieved through the following technical solutions: The first aspect of the application provides a verification method for a NAND Flash memory chip, comprising: S1, bad block scanning and marking: performing full-chip scanning on the NAND Flash chip, detecting and marking bad blocks, and generating a bad block distribution map.

[0008] S2, data fragmentation and allocation: according to the bad block distribution map, allocating sizes to each fragment in the NAND Flash chip, and allocating each fragment to different verification channels.

[0009] S3, parallel verification execution: sequentially performing fast verification and deep verification on each fragment data through the verification channel, and monitoring the processing progress data of each verification channel in real time, and dynamically adjusting the allocation strategy of subsequent fragments by using a load balancing algorithm.

[0010] S4, adaptive adjustment of verification frequency: extracting the current verification frequency of each partition, monitoring the physical characteristics of the storage units of each partition in real time, and dynamically adjusting the verification frequency of each partition according to the monitoring results.

[0011] The second aspect of the present application provides a verification system of a NAND Flash memory chip, comprising: a bad block scanning and marking module, which scans the NAND Flash chip, detects and marks bad blocks, and generates a bad block distribution map.

[0012] A data fragment and allocation module allocates sizes to each fragment in the NAND Flash chip according to the bad block distribution map, and allocates each fragment to different verification channels.

[0013] A parallel verification execution module sequentially performs fast verification and deep verification on each fragment data through the verification channel, and monitors the processing progress data of each verification channel in real time, and dynamically adjusts the allocation strategy of subsequent fragments by using a load balancing algorithm.

[0014] An adaptive adjustment module extracts the current verification frequency of each partition, monitors the physical characteristics of the storage units of each partition in real time, and dynamically adjusts the verification frequency of each partition according to the monitoring results.

[0015] Compared with the prior art, the embodiments of the present application have at least the following advantages or beneficial effects: (1) The present application dynamically adjusts the fragment size according to the number of bad blocks and the fragment capacity in the bad block distribution map, so that the fragment is more reasonable, and the verification efficiency is improved.

[0016] (2) The present application performs risk analysis based on the average boundary distance and the bad block density of each fragment, obtains the risk index of each fragment, and accordingly allocates different verification channels to each fragment, so as to realize the reasonable allocation of the verification channels and improve the overall verification efficiency.

[0017] (3) The present application monitors the processing progress data of each verification channel in real time, dynamically adjusts the allocation strategy of subsequent fragments by using a load balancing algorithm, avoids the overload of part of the verification channels, and improves the overall performance of the system.

[0018] (4) The present application monitors the physical characteristics of the storage units of each partition in real time, dynamically adjusts the verification frequency according to the monitoring results, so that the verification strategy is more scientific and reasonable, and the reliability of data storage is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the method steps of the present invention.

[0021] Figure 2 This is a schematic diagram of the system structure connection of the present invention.

[0022] Figure 3 This is a schematic diagram of the verification channel allocation steps of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Please see Figure 1 As shown, the first aspect of the present invention provides a method for verifying a NAND Flash memory chip, including: S1, bad block scanning and marking: performing a full-chip scan on the NAND Flash chip, detecting and marking bad blocks, and generating a bad block distribution map.

[0025] In a specific embodiment of the present invention, the specific method for detecting and marking bad blocks is as follows: after initialization is completed on the NAND Flash chip and a communication connection with the main control chip is established, the main control chip sends a full-chip erase verification command to the NAND Flash chip.

[0026] During the full-chip erase verification process of the NAND Flash chip, the erase operation is performed on each storage block of the NAND Flash chip and it is checked whether it can be successfully erased to a state of all "1". If a storage block cannot be erased to a state of all "1", then the storage block is determined to be a suspected bad block, thereby obtaining each suspected bad block of the NAND Flash chip.

[0027] It should be noted that in the NAND Flash memory chip, the "1" in the "all '1' state" represents the binary data state of the storage unit. Specifically, the NAND Flash represents data through the threshold voltage of the storage unit, and when the storage unit does not store charge (i.e., in the erased state), its threshold voltage corresponds to binary logic "1", and when storing charge, it corresponds to "0". In the full chip erase verification operation, if the storage block can be successfully erased to the all "1" state, it means that all storage units in the block are in the uncharged erased state, and the data is effectively cleared. If a storage block cannot reach all "1", it indicates that there is a charge retention anomaly in the internal storage unit, which cannot be normally erased, so it is determined to be a suspected bad block.

[0028] For each suspected bad block, the host chip records the physical address of each suspected bad block to the bad block table area preset in the NAND Flash chip. At the same time, the host chip maps the addresses of the suspected bad blocks to the invalid address interval by modifying the address mapping table of the NAND Flash chip.

[0029] It should be noted that the bad block table is like a "blacklist" that records problem storage blocks. Subsequently, when performing data reading and writing, checking and other operations, the system will first check this table and directly skip the marked bad blocks to avoid wasting time and resources in these unreliable areas.

[0030] S2, data fragmentation and allocation: according to the bad block distribution map, the size of each fragment in the NAND Flash chip is allocated, and each fragment is allocated to different checking channels.

[0031] In an embodiment of the present application, the specific way of allocating the size of each fragment in the NAND Flash chip is: extracting the number of bad blocks and the capacity of each fragment from the bad block distribution map, and taking the ratio between the number of bad blocks and the capacity of each fragment as the bad block density of each fragment.

[0032] The bad block density of each fragment is compared with the bad block density interval corresponding to the size of each fragment stored in the database. If the bad block density of a certain fragment is within the bad block density interval corresponding to the size of the fragment, the size of the fragment is taken as the size of the fragment. Thus, the size of each fragment in the NAND Flash chip is obtained.

[0033] In an embodiment of the present application, when the bad block rate of a fragment is greater than 5%, the size of the fragment is set to 128KB, when the bad block rate is between 1% and 5%, the size of the fragment is set to 512KB, and when the bad block rate is less than 1%, the size of the fragment is set to 1MB.

[0034] The embodiment of the present application adjusts the size of the slices dynamically according to the number of bad blocks and the slice capacity of each slice in the bad block distribution diagram, so that the slices are more reasonable, and the checking efficiency is improved.

[0035] Please refer to Figure 3 In the embodiment of the present application, the specific process of distributing each slice to different checking channels is as follows: the distance between each bad block in each slice and the slice boundary is extracted from the bad block distribution diagram, and the average boundary distance of each slice is obtained by mean calculation.

[0036] Risk analysis is performed based on the average boundary distance and the bad block density of each slice, and the risk index of each slice is obtained.

[0037] It should be noted that the specific way of obtaining the risk index of each slice is to subtract the average boundary distance of each slice from the set reference boundary distance, and to obtain the boundary distance ratio result of each slice by ratio of the difference value to the set reference boundary distance.

[0038] The difference between the bad block density of each slice and the set reference bad block density is subtracted, and the bad block density ratio result of each slice is obtained by ratio of the difference value to the set reference bad block density.

[0039] The boundary distance deviation ratio result of each slice and the bad block density deviation ratio result are added to obtain the risk index of each slice.

[0040] The risk index of each slice is matched with the risk index interval corresponding to the high risk level, the medium risk level and the low risk level stored in the database, so as to obtain the risk level of each slice.

[0041] It should be noted that the specific way of obtaining the risk level of each slice is as follows: if the risk index of a slice is located in the risk index interval corresponding to the high risk level, the risk level of the slice is recorded as the high risk level; if the risk index of a slice is located in the risk index interval corresponding to the medium risk level, the risk level of the slice is recorded as the medium risk level; if the risk index of a slice is located in the risk index interval corresponding to the low risk level, the risk level of the slice is recorded as the low risk level.

[0042] The risk level of each slice is matched with the checking channel corresponding to the high risk level, the medium risk level and the low risk level stored in the database, so as to obtain the checking channel corresponding to each slice.

[0043] The embodiment of the present application performs risk analysis based on the average boundary distance and the bad block density of each slice to obtain the risk index of each slice, and accordingly allocates different checking channels for each slice, so as to realize reasonable allocation of checking channels and improve the overall checking efficiency.

[0044] S3, parallel verification execution: sequentially performing fast verification and deep verification on each fragment data through the verification channel, and monitoring the processing progress data of each verification channel in real time, and dynamically adjusting the allocation strategy of subsequent fragments by using a load balancing algorithm.

[0045] In specific embodiments of the application, the specific manner of sequentially performing fast verification and deep verification on each fragment data is that the fast verification uses CRC verification, the deep verification uses multi-level error correction code, the fast verification is used to detect single-bit errors, and the deep verification is used to correct multi-bit errors.

[0046] It should be noted that the CRC verification (cyclic redundancy check) is calculated by a specific algorithm to generate a fixed-length check code, and the receiving end compares the calculated check code with the check code of the sending end to detect whether the data has errors. It can detect multiple bit errors and has fast calculation speed, so it is suitable as a preliminary fast verification method. The multi-level error correction code such as BCH code and LDPC code has strong error correction capability. BCH code can add a certain number of check bits in the data according to the set error correction capability, and through complex calculation, it can correct multiple error bits in the data. LDPC code uses sparse matrix for encoding and decoding, and can achieve efficient error correction at high data transmission rate.

[0047] In specific embodiments of the application, the specific process of dynamically adjusting the allocation strategy of subsequent fragments by using a load balancing algorithm is that the total number of fragments, the number of fragments that have completed verification, and the verification time consumption are extracted from the processing progress data of each verification channel.

[0048] The difference between the total number of fragments and the number of fragments that have completed verification of each verification channel is taken as the number of fragments to be verified of each verification channel.

[0049] The number of fragments that have completed verification and the verification time consumption of each verification channel are compared to obtain the processing efficiency of each verification channel.

[0050] Based on the number of fragments to be verified and the processing efficiency of each verification channel, it is comprehensively judged whether each verification channel is overloaded, the verification channels that are overloaded are recorded as heavily loaded verification channels, and the remaining verification channels are recorded as target verification channels.

[0051] In the embodiment of the present application, the specific way of comprehensively judging whether each verification channel is overloaded is: comparing the number of to-be-verified fragments and the processing efficiency of each verification channel with the threshold of the number of to-be-verified fragments and the threshold of the processing efficiency stored in the database, if the number of to-be-verified fragments of a certain verification channel is greater than the threshold of the number of to-be-verified fragments and the processing efficiency is less than the threshold of the processing efficiency, it indicates that the verification channel is overloaded, thereby the overloading of each verification channel can be judged.

[0052] Based on the number of to-be-verified fragments and the processing efficiency of each target verification channel, coupling analysis is performed to obtain the data processing health index of each target verification channel.

[0053] It should be noted that the specific way of obtaining the data processing health index of each target verification channel is: subtracting the threshold of the number of to-be-verified fragments from the number of to-be-verified fragments of each target verification channel, and then taking the ratio of the difference value to the threshold of the number of to-be-verified fragments to obtain the number of to-be-verified fragment deviation ratio of each target verification channel.

[0054] The processing efficiency of each target verification channel is subtracted from the threshold of the processing efficiency, and then the ratio of the difference value to the threshold of the processing efficiency is taken to obtain the processing efficiency deviation ratio of each target verification channel.

[0055] The number of to-be-verified fragment deviation ratio and the processing efficiency deviation ratio of each target verification channel are added to obtain the data processing health index of each target verification channel.

[0056] The data processing health indexes of each target verification channel are sorted in descending order to obtain the sorted target verification channels, and the main control chip assigns the new fragments to the sorted target verification channels in turn and prohibits assigning to each heavily loaded verification channel.

[0057] The embodiment of the present application avoids the overloading of part of the verification channels by real-time monitoring the processing progress data of each verification channel and dynamically adjusting the allocation strategy of subsequent fragments by using the load balancing algorithm, thereby improving the overall performance of the system.

[0058] S4, verification frequency adaptive adjustment: extracting the current verification frequency of each partition, real-time monitoring the physical characteristics of the storage units of each partition, and dynamically adjusting the verification frequency of each partition according to the monitoring result.

[0059] It should be noted that the current verification frequency of each partition can be extracted from the configuration register of the main control chip.

[0060] In the embodiment of the present application, the specific process of dynamically adjusting the verification frequency of each partition according to the monitoring result is: extracting the number of erasing and writing times and the working temperature of each storage unit from the physical characteristics of the storage units of each partition, and analyzing the performance health index corresponding to each partition according to the same.

[0061] It should be noted that the number of erasing and writing times of each partition storage unit is monitored by a wear count module built in the NAND Flash chip, which automatically adds the P / ECycle count of the corresponding storage block at each erasing and writing operation and stores it in the OOB area, and the working temperature is collected in real time by the temperature sensor integrated in the chip, the sensor converts the temperature signal into an electrical signal and transmits it to the ADC (analog-to-digital converter) of the master chip, and the actual temperature value is obtained after calibration calculation, and the above data are synchronized to the state register of the master chip at regular intervals for the system to read.

[0062] In a specific embodiment of the present application, the specific process of analyzing the performance health index of each partition is as follows: the number of erasing and writing times of each storage unit of each partition is subtracted from the number of erasing and writing rated times stored in the database, and the difference is divided by the number of erasing and writing rated times to obtain the wear degree of each storage unit of each partition, and the wear degree of each partition is obtained by mean calculation.

[0063] The working temperature deviation of adjacent storage units of each partition is obtained, the working temperature deviations of all adjacent storage units are summed, and the sum is divided by the number of storage unit intervals to obtain the working temperature deviation of each partition, which is subtracted from the working temperature deviation of the set reference, and the difference is divided by the working temperature deviation of the set reference to obtain the working temperature deviation degree of each partition.

[0064] The wear degree and working temperature deviation degree of each partition are respectively weighted and summed with the corresponding proportion weight, and the negative value of the sum is taken as the performance health index corresponding to each partition.

[0065] In a specific embodiment of the present application, when calculating the performance health index of each partition, the size of the proportion weight needs to be determined according to the physical characteristics and application scenarios of the NAND Flash chip: if the chip working environment temperature fluctuates greatly (such as industrial grade equipment), the proportion weight of the working temperature deviation degree is larger, because it has a more significant impact on the stability of the threshold voltage of the storage unit, and if the chip is in a long-term high-frequency read-write scenario (such as a data center), the proportion weight of the wear degree is larger, because it directly determines the remaining life of the storage unit. Generally, the NAND Flash in the industrial or automotive electronics field will give a higher weight to the working temperature deviation degree, and the consumer grade equipment will focus more on the weight of the wear degree.

[0066] The performance health index corresponding to each partition is compared with the set reference performance health index, and if the performance health index corresponding to a certain partition is greater than or equal to the set reference performance health index, the current check frequency of the partition is kept unchanged.

[0067] If the performance health index corresponding to a partition is less than the set reference performance health index, the set reference performance health index is subtracted from the performance health index corresponding to the partition to obtain the performance health index deviation corresponding to the partition, and the product of the unit performance health index deviation corresponding to the required promotion check frequency stored in the database is taken as the required promotion check frequency corresponding to the partition, and the sum of the current check frequency of the partition and the required promotion check frequency is taken as the check frequency corresponding to the partition.

[0068] The check frequencies of the partitions are obtained.

[0069] The embodiment of the application adjusts the check frequency dynamically according to the monitoring result by monitoring the physical characteristics of the storage units of the partitions in real time, so that the check strategy is more scientific and reasonable, and the reliability of data storage is improved.

[0070] Referring to Figure 2 The second aspect of the application provides a check system of a NAND Flash memory chip, which comprises a bad block scanning and marking module, a data slicing and distribution module, a parallel check execution module and a check frequency self-adaptive adjustment module.

[0071] It should be noted that the application also comprises a database for storing the bad block density interval corresponding to the size of each slice, the risk index interval and the check channel corresponding to the high-risk level, the medium-risk level and the low-risk level respectively, the threshold of the number of slices to be checked, the threshold of processing efficiency, the required promotion check frequency corresponding to the unit performance health index deviation and the erasing and writing rated number.

[0072] The bad block scanning and marking module is connected with the data slicing and distribution module, the data slicing and distribution module is connected with the parallel check execution module, and the data slicing and distribution module, the parallel check execution module and the check frequency self-adaptive adjustment module are all connected with the database.

[0073] The bad block scanning and marking module performs full-slice scanning on the NAND Flash chip, detects and marks the bad blocks, and generates a bad block distribution map.

[0074] The data slicing and distribution module allocates the size of each slice in the NAND Flash chip according to the bad block distribution map, and allocates each slice to different check channels.

[0075] The parallel check execution module sequentially performs fast check and deep check on the data of each slice through the check channels, and monitors the processing progress data of each check channel in real time, and dynamically adjusts the allocation strategy of subsequent slices by using a load balancing algorithm.

[0076] The check frequency adaptive adjustment module extracts the current check frequency of each partition, monitors the physical characteristics of the storage units of each partition in real time, and dynamically adjusts the check frequency of each partition according to the monitoring result.

[0077] The above is only an example and a description of the concept of the present application. Those skilled in the art can make various modifications or supplements to the described specific embodiments or use similar ways to replace them, as long as they do not deviate from the concept of the present application or exceed the scope defined by the present application.

Claims

1. A method for checking a NAND Flash memory chip, characterized in that, The method comprises the following steps: S1, bad block scanning and marking: scanning the whole chip, detecting and marking bad blocks, and generating a bad block distribution map; S2, data slicing and allocation: allocating sizes to each slice in the NAND Flash chip according to the bad block distribution map, and allocating each slice to different check channels; S3, parallel check execution: sequentially executing fast check and deep check on each slice data through the check channels, and monitoring the processing progress data of each check channel in real time, and dynamically adjusting the allocation strategy of subsequent slices by using a load balancing algorithm; S4, adaptive adjustment of check frequency: extracting the current check frequency of each partition, monitoring the physical characteristics of the storage units of each partition in real time, and dynamically adjusting the check frequency of each partition according to the monitoring results.

2. The method of claim 1, wherein the method further comprises: The specific way of detecting and marking bad blocks is as follows: After the initialization of the NAND Flash chip and the establishment of the communication connection with the host chip, the host chip sends a full chip erase verification command to the NAND Flash chip; During the full chip erase verification process, the NAND Flash chip performs an erase operation on each storage block of the NAND Flash chip and checks whether it can be successfully erased to a full "1" state. If a storage block cannot be erased to a full "1", it is determined that the storage block is a suspected bad block, and thus the NAND Flash chip obtains each suspected bad block; For each suspected bad block, the host chip records the physical address of each suspected bad block in the bad block table area preset in the NAND Flash chip, and at the same time, the host chip maps the addresses of the suspected bad blocks to an invalid address interval by modifying the address mapping table of the NAND Flash chip.

3. The method of claim 1, wherein the method further comprises: determining whether the data stored in the memory cell is valid; and if the data stored in the memory cell is valid, reading the data stored in the memory cell. The specific way of allocating sizes to each slice in the NAND Flash chip is as follows: Extract the number of bad blocks and the slice capacity of each slice from the bad block distribution map, and take the ratio between the number of bad blocks and the slice capacity of each slice as the bad block density of each slice; Compare the bad block density of each slice with the bad block density interval corresponding to the size of each slice stored in the database. If the bad block density of a slice is within the bad block density interval corresponding to the size of the slice, the size of the slice is taken as the size of the slice, and thus the size of each slice in the NAND Flash chip is obtained.

4. The method of claim 3, wherein the method further comprises: The specific process of allocating each slice to different check channels is as follows: Extract the distance between each bad block and the slice boundary in each slice from the bad block distribution map, and calculate the average boundary distance of each slice by averaging the distances; Based on the average boundary distance and the bad block density of each slice, risk analysis is performed to obtain the risk index of each slice; Match the risk index of each slice with the risk index interval corresponding to the high-risk level, the medium-risk level and the low-risk level respectively stored in the database, so as to obtain the risk level of each slice; Match the risk level of each slice with the check channel corresponding to the high-risk level, the medium-risk level and the low-risk level respectively stored in the database, so as to obtain the check channel corresponding to each slice.

5. The method of claim 2, wherein the method further comprises: determining whether the data stored in the memory cell is valid; and if the data stored in the memory cell is valid, reading the data stored in the memory cell. The specific manners of sequentially performing the quick check and the deep check on each piece of data are as follows: the quick check adopts a CRC check, the deep check adopts a multi-level error correction code, the quick check is used for detecting single-bit errors, and the deep check is used for correcting multi-bit errors.

6. The method of claim 5, wherein the method further comprises: The specific process of dynamically adjusting the allocation strategy of the subsequent pieces of data by using the load balancing algorithm is as follows: extracting the total number of pieces of data, the number of pieces of data that have been checked, and the time consumed for checking from the processing progress data of each check channel; taking the difference between the total number of pieces of data and the number of pieces of data that have been checked of each check channel as the number of pieces of data to be checked of each check channel; taking the number of pieces of data that have been checked and the time consumed for checking of each check channel as a ratio to obtain the processing efficiency of each check channel; comprehensively judging whether each check channel is overloaded based on the number of pieces of data to be checked and the processing efficiency of each check channel, marking the check channels that are overloaded as overloaded check channels, and marking the remaining check channels as target check channels; performing coupling analysis based on the number of pieces of data to be checked and the processing efficiency of each target check channel to obtain a data processing health index of each target check channel; sequentially assigning new pieces of data to the sorted target check channels, and prohibiting the assignment to the overloaded check channels.

7. The method of claim 6, wherein the method further comprises: determining whether the read data is correct or not; and if the read data is not correct, performing a read operation again on the read data block. 7 The specific manner of comprehensively judging whether each check channel is overloaded is as follows: comparing the number of pieces of data to be checked and the processing efficiency of each check channel with the number of pieces of data to be checked threshold and the processing efficiency threshold stored in the database respectively, and if the number of pieces of data to be checked of a certain check channel is greater than the number of pieces of data to be checked threshold and the processing efficiency is less than the processing efficiency threshold, it indicates that the check channel is overloaded, and thus whether each check channel is overloaded can be judged.

8. The method of claim 1, wherein the method further comprises: determining whether the data stored in the memory cell is valid; and if the data stored in the memory cell is not valid, then performing a read operation on the memory cell to obtain the data stored in the memory cell. The specific process of dynamically adjusting the check frequency of each partition according to the monitoring result is as follows: extracting the number of erasing and writing times and the working temperature of each storage unit from the physical characteristics of each storage unit in each partition, and analyzing the performance health index corresponding to each partition based thereon; comparing the performance health index corresponding to each partition with the set reference performance health index, and if the performance health index corresponding to a certain partition is greater than or equal to the set reference performance health index, maintaining the current check frequency of the partition unchanged; if the performance health index corresponding to a certain partition is less than the set reference performance health index, performing a subtraction between the set reference performance health index and the performance health index corresponding to the partition to obtain the performance health index deviation corresponding to the partition, taking the product between the unit performance health index deviation corresponding to the required check frequency and the required check frequency of the partition as the required check frequency of the partition, and taking the sum of the current check frequency of the partition and the required check frequency as the check frequency corresponding to the partition; obtaining the check frequency of each partition.

9. The method of claim 8, wherein the method further comprises: determining whether the read data is correct or not; and if the read data is not correct, performing a read operation again on the read data block. 9 The specific process of analyzing the performance health index corresponding to each partition is as follows: The wear degree of each storage unit in each partition is obtained by subtracting the number of erasing and writing times of each storage unit in each partition from the number of erasing and writing times stored in the database, and by dividing the difference by the number of erasing and writing times; and the wear degree of each partition is obtained by averaging the wear degrees of the storage units in each partition. The working temperature deviation of each partition is obtained by obtaining the working temperature deviation of adjacent storage units in each partition, summing the working temperature deviations of all adjacent storage units, dividing the sum by the number of storage unit intervals, and subtracting the set reference working temperature deviation from the working temperature deviation of each partition, and dividing the difference by the set reference working temperature deviation. The wear degree and the working temperature deviation of each partition are respectively weighted and summed by using the corresponding proportion weight, and the negative value of the sum is used as the performance health index corresponding to each partition.

10. A check system of a NAND Flash memory chip, characterized by, It comprises: a bad block scanning and marking module, which scans the NAND Flash chip, detects and marks bad blocks, and generates a bad block distribution map; a data slicing and allocation module, which allocates sizes to each slice in the NAND Flash chip according to the bad block distribution map, and allocates each slice to different check channels; a parallel check execution module, which sequentially performs fast check and deep check on each slice data through the check channels, and dynamically adjusts the allocation strategy of subsequent slices by using a load balancing algorithm according to the processing progress data of each check channel; a check frequency adaptive adjustment module, which extracts the current check frequency of each partition, monitors the physical characteristics of the storage units in each partition in real time, and dynamically adjusts the check frequency of each partition according to the monitoring result.

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