Metal element diffusion method and manufacturing method of semiconductor device

Abstract

The invention provides a metal element diffusion method of a semiconductor device and a manufacturing method thereof. The method comprises the following steps: forming a metal layer on the front surface of a semiconductor layer; enabling the metal layer to react with silicon to form a metal silicification layer; removing the unreacted residual metal layer, and reserving the metal silicification layer as a diffusion source; and heating the metal silicification layer by adopting microwave annealing or laser annealing, so that the metal elements in the diffusion source are diffused into the semiconductor layer. Through a low thermal budget process of a metal silicide solid-state source and microwave / laser annealing, precise and local diffusion of metal elements such as platinum, gold and molybdenum is realized on the front surface of the wafer on which the contact hole is formed, so that the service life of minority carriers in a drift region is controllably reduced, and subsequent ohmic contact preparation is compatible.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device manufacturing, and more specifically, to a method for diffusion of metal elements into semiconductor devices and a method for manufacturing the same. Background Technology

[0002] As power semiconductor devices evolve towards higher voltages, lower losses, and faster switching speeds, precisely controlling the minority carrier lifetime in the drift region has become a key technology. Traditional gold and platinum diffusion processes typically employ a high-temperature furnace tube approach with prolonged exposure (tens of minutes to several hours) to introduce deep-level impurities such as gold and platinum into the silicon or silicon carbide drift region, thereby creating recombination centers and shortening the carrier lifetime.

[0003] However, prolonged high temperatures can lead to impurity redistribution, making it difficult to precisely control the diffusion depth, and may activate unwanted doping, affecting the device's breakdown voltage and threshold stability. Prolonged high-temperature processing can also cause wafer warping, and a slow cooling rate may cause diffused metal elements to re-precipitate from the wafer surface at higher temperatures.

[0004] Therefore, the industry urgently needs a metal element diffusion method with low thermal budget, controllable diffusion depth and good uniformity to accurately introduce recombination centers in the drift region of power devices, achieve fast soft recovery, low reverse recovery charge (Qrr) and high switching speed, while maintaining the breakdown voltage and reliability of the device. Summary of the Invention

[0005] This disclosure provides a method for diffusing metal elements into a semiconductor device and a method for manufacturing the same, aiming to solve the problems caused by prolonged high temperatures in the prior art.

[0006] According to one aspect of the embodiments of this disclosure, a method for metal element diffusion in a semiconductor device is provided, comprising:

[0007] A metal layer is formed on the front side of the semiconductor layer;

[0008] The metal layer reacts with silicon to form a metal silicide layer;

[0009] Remove the unreacted residual metal layer, retaining the metal silicide layer as a diffusion source; and

[0010] The metal silicide layer is heated by microwave annealing or laser annealing, so that the metal elements in the diffusion source diffuse into the semiconductor layer.

[0011] Optionally, the metal layer is formed on the surface of the semiconductor layer using a vapor deposition process.

[0012] Optionally, the material of the metal layer includes at least one of platinum, gold, and molybdenum.

[0013] Optionally, reacting the metal layer with silicon to form a metal silicide layer includes: using rapid thermal annealing to react the metal layer with silicon to form a metal silicide layer.

[0014] Optionally, the rapid thermal annealing process temperature ranges from 550°C to 600°C, and the process time ranges from 10 seconds to 60 seconds.

[0015] Optionally, the power density range of the laser annealing is 10. 4 W / cm²–10 6 W / cm², pulse width in milliseconds.

[0016] Optionally, prior to the step of forming the metal layer on the surface of the semiconductor layer, a dielectric layer with vias is formed on the front side of the semiconductor layer, with a portion of the semiconductor layer exposed through the vias.

[0017] The metal layer is in contact with the semiconductor layer through the via.

[0018] Optionally, it further includes forming the metal layer on the back side of the semiconductor layer.

[0019] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, including the metal element diffusion method described above.

[0020] Optionally, it further includes: after heating the metal silicide layer using microwave annealing or laser annealing, performing ion implantation on the semiconductor layer through the via to form an ohmic contact region at the bottom of the via.

[0021] One of the above technical solutions has the following beneficial effects:

[0022] By forming a metal silicide layer between the metal and semiconductor layers as a solid-state diffusion source for metal elements, precise diffusion control is achieved. Microwave or laser annealing is used instead of traditional furnace tube thermal annealing, significantly reducing the process temperature while achieving impurity activation and lattice repair, effectively alleviating wafer warpage issues.

[0023] Microwave or laser annealing, with its millisecond-level ultrafast heating and cooling characteristics, enables impurity activation and lattice repair at relatively low temperatures. This not only avoids the risk of metal elements precipitating from the wafer surface under high temperatures but also significantly reduces the process thermal budget, thereby mitigating the adverse effects of thermal processes on device structural integrity. Furthermore, compared to sputtering, using evaporation to form the metal layer reduces the process requirements for contact hole morphology and improves the uniformity of metal layer deposition. Additionally, evaporation equipment is significantly less expensive than sputtering equipment, contributing to lower overall manufacturing costs.

[0024] Furthermore, by adjusting the ion implantation process to occur after metal diffusion, the impact of the high-temperature process on the junction depth of the contact region is effectively avoided, ensuring the stability of the doping distribution in the ohmic contact region. This optimized process timing, combined with the synergistic effect of the metal silicide solid-state source, enables the device to achieve more reliable ohmic contacts while maintaining low reverse recovery charge (Qrr) characteristics, resolving the contradiction between carrier lifetime control and contact process compatibility in existing technologies. Moreover, this approach also leverages these technical advantages when applied to the back side of the device, providing process compatibility assurance for novel device structures such as 3D packaging. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0026] Figures 1 to 8 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present disclosure during a certain stage of the manufacturing process is shown. Detailed Implementation

[0027] The present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.

[0028] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0029] To describe a situation where it is directly above another layer or another area, this article will use expressions such as "directly above" or "above and adjacent to".

[0030] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.

[0031] The following will combine Figures 1 to 8 The manufacturing steps of the power module disclosed herein, especially the metal element diffusion step, are described in detail.

[0032] like Figure 1 As shown, a plurality of trench gate structures 120 are formed in the semiconductor layer 101. A dielectric layer 102 with vias 103 is formed on the front side 11 of the semiconductor layer 101, and a portion of the semiconductor layer 101 is exposed to the vias 103.

[0033] Furthermore, a metal layer 104 is formed on the front side 11 of the semiconductor layer 101, such as... Figure 2 As shown.

[0034] In this step, for example, a vapor deposition process is used to deposit metal material on the surface of the dielectric layer 102 and the inner wall of the via 103, forming a continuously covering metal layer 104. This process heats the metal source to the evaporation temperature, causing metal atoms to deposit in a straight path in the target area under vacuum. Compared with sputtering, the metal layer 104 formed by vapor deposition has better thickness uniformity and lower cost. Since the vapor deposition process is more adaptable to the aspect ratio morphology of the via 103, it can also avoid the problem of metal layer breakage caused by poor step coverage. In specific implementations, the metal layer 104 can be one or more combinations of platinum, gold, or molybdenum. In some preferred embodiments, the surface of the semiconductor layer 101 needs to be pretreated before forming the metal layer 140 to remove the native oxide layer and improve the interfacial reactivity between the metal and the silicon substrate.

[0035] Furthermore, the metal layer 104 reacts with the silicon in the semiconductor layer 101 to form a metal silicide layer 130.

[0036] In this step, a rapid thermal annealing (RTA) process is used to induce a silicide reaction at the contact area between the metal layer 104 and the semiconductor layer 101. The process is maintained at 550°C-600°C for 10-60 seconds, causing the metal atoms to form a uniform metal silicide layer 130 at the interface with the silicon substrate. The material of the metal silicide layer 130 includes at least one of Pt-Si alloy, Au-Si alloy, and Mo-Si alloy.

[0037] Furthermore, the unreacted residual metal layer 104 is removed, leaving the metal silicide layer 130 as a diffusion source, such as... Figure 4 As shown.

[0038] In this step, the metal layer 104 is completely stripped using a selective etching solution (such as aqua regia or thiocyanate solution) while avoiding damage to the metal silicide layer 130. Since the metal silicide layer 130 has higher chemical stability than the original metal layer 104, it can act as a diffusion source to precisely control the total amount of metal element diffusion, and local diffusion can be achieved without the need for an additional mask layer. Subsequently, the metal silicide layer 130 is heated using microwave annealing or laser annealing to rapidly diffuse platinum, gold, or molybdenum elements from the solid source into the drift region of the semiconductor layer 101. Microwave annealing generates heat by exciting the internal dipole vibration of the material with a 2.45 GHz electromagnetic wave, achieving the activation and migration of metal atoms at a temperature of 300℃-500℃; laser annealing utilizes a pulsed laser with a wavelength of 532 nm or 1064 nm at a 10 4 W / cm²–10 6 With a power density of W / cm² and millisecond-level pulse width, instantaneous high-temperature gradients are created in localized areas to drive diffusion. Both processes can complete the diffusion process in an extremely short time (less than 5 seconds), reducing the thermal budget by more than 90% compared to traditional furnace tube annealing, effectively suppressing wafer warpage and preventing metal element precipitation during cooling. Furthermore, the aforementioned metal element diffusion step can also be used on the back side 12 of semiconductor layer 101. For example, a metal layer 104 can be further formed on the back side 12 of semiconductor layer 101. The metal layer 104 on the back side 12 and the metal layer 104 on the front side 11 simultaneously undergo the aforementioned rapid thermal annealing to form a metal silicide layer, remove unreacted residual metal layers, and heat-treat the metal silicide layer using microwave annealing or laser annealing.

[0039] Furthermore, after the metal element diffusion is complete, an ion implantation process is performed on the semiconductor layer 101 through the via 103 to form an ohmic contact region 140 at the bottom of the via 103, such as... Figure 5 As shown.

[0040] In this step, for example, BF2⁺ or As⁺ is used as the dopant ion, the implantation energy is controlled in the range of 5keV-30keV, and the dose is 1×10¹. 5 cm⁻²-5×10¹ 5 cm⁻², through subsequent annealing activation, forms a low-resistivity ohmic contact interface. Adjusting the ion implantation process to after metal diffusion avoids thermal disturbances to the junction depth of the contact area during high-temperature processes, ensuring the stability of the doping distribution in the ohmic contact region 140.

[0041] Furthermore, a conductive plug 151 is formed in the through hole 103, such as... Figure 6 As shown.

[0042] In this step, for example, tungsten metal is filled into the via 103 using a chemical vapor deposition process, followed by chemical mechanical polishing to remove excess tungsten layer from the surface, forming a conductive plug 151 that is in close contact with the ohmic contact region 140. During this process, the retained metal silicide layer 130 not only continues to function as a solid-state diffusion source for the metal element, but the gradient interface formed between it and the silicon substrate effectively alleviates the thermal stress mismatch between the tungsten plug and the silicon substrate. By integrating the metal silicide layer 130 with the conductive plug 151, a high-strength bond between the plug and the silicon substrate can be achieved without introducing an additional titanium / titanium nitride adhesion layer, thereby simplifying the process and reducing the interface resistivity.

[0043] Furthermore, metal wiring 152 is formed on the dielectric layer 102, such as... Figure 7 As shown.

[0044] In this step, for example, an aluminum-copper alloy layer is formed on the surface of the dielectric layer 102 using a physical vapor deposition process, and the pattern of the metal wiring 152 is defined by photolithography and dry etching processes, wherein the metal wiring 152 is connected to the conductive plug 151.

[0045] Furthermore, a PV layer 161 and a PI layer 162 are deposited on the metal wiring 152, such as Figure 8 As shown.

[0046] In this step, for example, a plasma-enhanced chemical vapor deposition (PECVD) process is used to sequentially deposit a silicon nitride passivation layer (PV layer 161) and a polyimide insulating layer (PI layer 162) on the surface of the metal wiring 152. This stacked structure of PV layer 161 and PI layer 162 not only provides mechanical and humidity protection for the device, but its unique gradient modulus design (the elastic modulus of the silicon nitride layer is approximately 300 GPa, and that of the polyimide layer is approximately 3 GPa) effectively alleviates the problem of thermal stress concentration during subsequent packaging processes. After deposition, bonding windows are formed in the PI layer 162 using photolithography and dry etching processes, exposing the pad areas of the metal wiring 152 and preparing it for subsequent packaging processes.

[0047] By forming a metal silicide layer between the metal and semiconductor layers as a solid-state diffusion source for metal elements, precise diffusion control is achieved. Microwave or laser annealing is used instead of traditional furnace tube thermal annealing, significantly reducing the process temperature while achieving impurity activation and lattice repair, effectively alleviating wafer warpage issues.

[0048] Microwave or laser annealing offers millisecond-level ultrafast heating and cooling, avoiding the risk of metal elements precipitating from the wafer surface under high temperatures and significantly reducing the process thermal budget, thus mitigating the adverse effects of thermal processes on device structural integrity. Furthermore, compared to sputtering, evaporation processes for forming metal layers reduce the requirements for contact hole morphology and improve the uniformity of metal layer deposition. Additionally, evaporation equipment is significantly less expensive than sputtering equipment, contributing to lower overall manufacturing costs.

[0049] Furthermore, by adjusting the ion implantation process to occur after metal diffusion, the impact of the high-temperature process on the junction depth of the contact region is effectively avoided, ensuring the stability of the doping distribution in the ohmic contact region. This optimized process timing, combined with the synergistic effect of the metal silicide solid-state source, enables the device to achieve more reliable ohmic contacts while maintaining low reverse recovery charge (Qrr) characteristics, resolving the contradiction between carrier lifetime control and contact process compatibility in existing technologies. Moreover, this approach also leverages these technical advantages when applied to the back side of the device, providing process compatibility assurance for novel device structures such as 3D packaging.

Claims

1. A method for metal element diffusion in a semiconductor device, comprising: A metal layer is formed on the front side of the semiconductor layer; The metal layer reacts with silicon to form a metal silicide layer; Remove the unreacted residual metal layer, retaining the metal silicide layer as a diffusion source; as well as The metal silicide layer is heated by microwave annealing or laser annealing, so that the metal elements in the diffusion source diffuse into the semiconductor layer.

2. The metal element diffusion method according to claim 1, wherein, The metal layer is formed on the surface of the semiconductor layer using a vapor deposition process.

3. The metal element diffusion method according to claim 1, wherein, The material of the metal layer includes at least one of platinum, gold, and molybdenum.

4. The metal element diffusion method according to claim 1, wherein, The process of reacting the metal layer with silicon to form a metal silicide layer includes: heating the metal layer using rapid thermal annealing to cause the metal layer to react with silicon to form a metal silicide layer.

5. The metal element diffusion method according to claim 4, wherein, The rapid thermal annealing process has a temperature range of 550°C to 600°C and a time range of 10 seconds to 60 seconds.

6. The metal element diffusion method according to claim 1, wherein, The power density range of the laser annealing is 10. 4 W / cm²–10 6 W / cm², pulse width in milliseconds.

7. The metal element diffusion method according to claim 1, wherein, Prior to the step of forming the metal layer on the surface of the semiconductor layer, a dielectric layer with vias is formed on the front side of the semiconductor layer, a portion of the semiconductor layer is exposed through the vias, and the metal layer contacts the semiconductor layer through the vias.

8. The metal element diffusion method according to claim 1, further comprising: The metal layer is further formed on the back side of the semiconductor layer.

9. A method for manufacturing a semiconductor device, comprising the metal element diffusion method as described in any one of claims 1 to 7.

10. The manufacturing method according to claim 9, further comprising: After heating the metal silicide layer using microwave annealing or laser annealing, ion implantation is performed on the semiconductor layer through the via to form an ohmic contact region at the bottom of the via.

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