Semiconductor package and manufacturing method thereof

Abstract

The invention provides a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a first semiconductor chip having a first surface provided with a first connection pad and a second surface opposite to the first surface; a second semiconductor chip on the second surface and having a third surface provided with a second connection pad and a fourth surface opposite the third surface; a connection structure on the first surface, including a redistribution layer connected to the first connection pad and the second connection pad, a fifth surface facing the first surface, a sixth surface opposite to the fifth surface, and a ground pad; a first connection line connecting the first connection pad and the redistribution layer; a second connection line connecting the second connection pad and the redistribution layer; a shield plate on the fourth surface; and a shield line connecting the shield plate and the ground pad.

Description

Cross Reference to Related Applications

[0001] This application claims priority to and all the benefits of Korean Patent Application No. 10-2024-0066465, filed on May 22, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor package and a manufacturing method thereof. BACKGROUND

[0003] As electronic devices become smaller and more high-performance, the distance between components thereof is reduced, and the operation speed is significantly increased. This has caused a device malfunction problem due to electromagnetic interference (EMI) between components. Accordingly, there is an increasing interest in EMI shielding technology. In the case of a smart phone, the EMI shielding technology was initially applied only to certain chips, such as early communication chips. However, recently, the application of the EMI shielding technology has been extended to include an application processor (AP) and a radio frequency (RF) chip.

[0004] The EMI shielding technology mainly uses a metal can structure or a deposition method such as sputtering. When the EMI shielding is implemented by a deposition method such as sputtering, an additional sputtering process is required after the semiconductor chip is manufactured. Accordingly, there is an increasing demand for an EMI shielding structure capable of reducing manufacturing costs. SUMMARY

[0005] Aspects of the present disclosure provide a semiconductor package having an effective electromagnetic interference (EMI) shielding structure.

[0006] Aspects of the present disclosure also provide a method of manufacturing a semiconductor package having an effective EMI shielding structure.

[0007] However, aspects of the present disclosure are not limited to what is described herein but cover both the fair scope of the application and the equivalents thereof. The above and other aspects of the present disclosure will become more apparent by describing in detail the following embodiments thereof with reference to the attached drawings, giving examples.

[0008] According to aspects of the disclosure, a semiconductor package includes: a first semiconductor chip including a first surface disposed with a first connection pad and a second surface opposite the first surface in a first direction; a second semiconductor chip on the second surface and including a third surface disposed with a second connection pad and a fourth surface opposite the third surface in the first direction; and a connection structure on the first surface of the first semiconductor chip, the connection structure including: a redistribution layer connected to the first connection pad and the second connection pad, a fifth surface facing the first surface, a sixth surface opposite the fifth surface in the first direction, and a ground pad; a first connection line connecting the first connection pad and the redistribution layer and extending in the first direction; a second connection line connecting the second connection pad and the redistribution layer and extending in the first direction; a shield plate on the fourth surface of the second semiconductor chip; and a shield line connecting the shield plate and the ground pad and extending longitudinally in the first direction.

[0009] According to other aspects of the disclosure, a semiconductor package includes: a first semiconductor chip including a first surface disposed with a first connection pad and a second surface opposite the first surface in a first direction; a second semiconductor chip including: a third surface facing the second surface of the first semiconductor chip, and a fourth surface opposite the second surface in the first direction, the third surface including a first region at least partially overlapping the first semiconductor chip in the first direction, a second region without the first semiconductor chip, and a second connection pad disposed on the third surface and in the second region; a connection structure including a fifth surface facing the first surface of the first semiconductor chip, a sixth surface opposite the fifth surface, and a plurality of ground pads on the fifth surface; a first connection line between the first semiconductor chip and the connection structure and contacting the first connection pad and the connection structure; a second connection line between the second semiconductor chip and the connection structure and contacting the second connection pad and the connection structure; a shield plate on the fourth surface of the second semiconductor chip; and a plurality of shield lines between the shield plate and the connection structure, the plurality of shield lines at least partially surrounding the first semiconductor chip and the second semiconductor chip, and each shield line including a first end connected to the shield plate and a second end connected to a respective ground pad of the plurality of ground pads.

[0010] According to other aspects of this disclosure, a method of manufacturing a semiconductor package includes: providing a carrier; attaching a molding film to the carrier; disposing a shielding plate on the molding film; disposing a first semiconductor chip on the shielding plate such that a second surface of the first semiconductor chip faces the shielding plate, the first semiconductor chip including a first surface having a first connection pad and a second surface opposite to the first surface in a first direction; disposing a second semiconductor chip on the first semiconductor chip such that a fourth surface of the second semiconductor chip faces the first semiconductor chip, the second semiconductor chip including a third surface having a second connection pad and a fourth surface opposite to the third surface in a first direction; connecting a first connection line extending in a first direction to the first connection pad; connecting a second connection line extending in the first direction to the second connection pad; connecting a shielding line extending in the first direction to the shielding plate; and disposing a connection structure on the second semiconductor chip, the connection structure including a redistribution layer and a ground pad, the redistribution layer being connected to the first connection pad via the first connection line and to the second connection pad via the second connection line, the ground pad being connected to the shielding plate via the shielding line.

[0011] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will become apparent from the following description. Attached Figure Description

[0012] The above and other aspects and features of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0013] Figures 1 to 4 A semiconductor package according to an embodiment of the present disclosure is shown.

[0014] Figure 5 This is a flowchart illustrating an example method for manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0015] Figures 6 to 15 An example intermediate stage of a method for manufacturing a semiconductor package according to embodiments of the present disclosure is shown.

[0016] Figure 16 and Figure 17 Example steps for manufacturing a semiconductor package according to embodiments of the present disclosure are shown.

[0017] Figure 18 This is a block diagram illustrating an example configuration of a semiconductor package according to an embodiment of the present disclosure.

[0018] Figure 19 This is a block diagram illustrating an example configuration of a semiconductor package according to an embodiment of the present disclosure. Detailed Implementation

[0019] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become apparent from the embodiments described in detail below with reference to the accompanying drawings. However, the embodiments of this disclosure are not limited to those disclosed herein, but can be implemented in various different forms. Therefore, these embodiments are set forth only to implement this disclosure and to inform those skilled in the art of the scope of this disclosure, which is limited only by the scope of the claims.

[0020] For the sake of simplicity and clarity, the elements in the accompanying drawings are not necessarily drawn to scale. The same reference numerals in different drawings denote the same or similar elements and therefore perform similar functions. Furthermore, for the sake of simplicity, descriptions and details of well-known steps and elements have been omitted. In addition, numerous specific details are set forth in the following detailed description of this disclosure to provide a thorough understanding of the disclosure. However, it should be understood that this disclosure can be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of this disclosure. Examples of various embodiments are further shown and described below. It should be understood that the description herein is not intended to limit the claims to the specific embodiments described. Rather, it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of this disclosure as defined by the appended claims.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular constructions of “a” and “an” are intended to also include the plural constructions, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” “having,” and “containing,” when used in this specification, indicate the presence of the stated features, integers, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, operations, elements, components, and / or combinations thereof. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” following a list of elements may modify the entire list of elements, rather than individual elements in the list. Errors or tolerances may be introduced when interpreting numerical values, even without explicit description.

[0022] It will also be understood that when a first element or layer is referred to as existing "on" a second element or layer, the first element may be directly disposed on the second element or may be indirectly disposed on the second element, wherein a third element or layer is disposed between the first element or layer and the second element or layer. It will also be understood that when a first element or layer is referred to as existing "below" a second element or layer, the first element may be directly disposed below the second element or may be indirectly disposed below the second element, wherein a third element or layer is disposed between the first element or layer and the second element or layer. It will be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it may be directly connected to or coupled to the other element or layer, or one or more intermediate elements or layers may exist therein.

[0023] Furthermore, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or there may be one or more intermediate elements or layers in between.

[0024] Furthermore, as used herein, when a layer, film, region, plate, etc., is disposed "on" or "on top" of another layer, film, region, plate, etc., the former can directly contact the latter, or another layer, film, region, plate, etc., can be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc., is directly disposed "on" or "on top" of another layer, film, region, plate, etc., the former can directly contact the latter, and no other layer, film, region, plate, etc., is disposed between the former and the latter. Furthermore, as used herein, when a layer, film, region, plate, etc., can be disposed "below" or "under" another layer, film, region, plate, etc., the former can directly contact the latter, or another layer, film, region, plate, etc., can be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc., is directly disposed "below" or "under" another layer, film, region, plate, etc., the former directly contacts the latter, and no other layer, film, region, plate, etc., is disposed between the former and the latter.

[0025] In descriptions of temporal relationships, such as the chronological order between two events, such as "after", "next", "before", etc., another event may occur in between, unless it is specified that "immediately after", "following", or "just before".

[0026] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion.

[0027] Spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” “upper,” etc., are used herein to describe the relationship of one element or feature relative to other elements or features, as shown in the accompanying drawings. It will be understood that spatial relative terms are intended to encompass not only the orientations shown in the drawings but also the different orientations of the device in use or operation. For example, when the device in the drawings can be flipped, an element described as being “below,” “below,” or “below” other elements or features will be oriented “above” other elements or features. Thus, the example terms “below” and “below” can encompass both the orientations above and below. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0028] The term “upper part” (or “upper surface”) may be defined based on a first direction D1, and the term “lower part” (or “lower surface”) may be defined based on a direction opposite to the first direction D1.

[0029] As used herein, terms such as “example,” “example,” “aspect,” etc., should not be construed as indicating that any aspect or design described is superior to other aspects or designs.

[0030] Furthermore, the term "or" means "inclusive or," not "exclusive or." That is, unless the context otherwise indicates or explicitly states otherwise, the statement "x uses a or b" means any of the naturally inclusive permutations.

[0031] As used herein, an element or region that “covers”, “surrounds”, or “fills” another element or region may completely or partially cover, surround, or fill that other element or region.

[0032] In this document, the term "exposed" (or similar term) may be used to describe relationships between components and / or to refer to intermediate processes in the manufacture of semiconductor devices, but may not require that a particular component be exposed in the finished device. Similarly, the term "not exposed" may be used to describe relationships between components and / or to refer to intermediate processes in the manufacture of semiconductor devices, but may not require that a particular component be unexposed in the finished device.

[0033] The features of the various embodiments of this disclosure can be combined with each other in part or in whole, and can be technically related to or operable on each other. The various embodiments can be implemented independently of each other, or they can be implemented together through association.

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an ideal or overly formal meaning, unless expressly defined herein.

[0035] Embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0036] Figures 1 to 4 A semiconductor package 1000 according to an embodiment of the present disclosure is shown.

[0037] Figure 1 and Figure 2 This is a plan view showing a portion of a semiconductor package 1000 according to an embodiment of the present disclosure. Figure 3 This is a front view of a semiconductor package 1000, and Figure 4 This is a perspective view of semiconductor package 1000. The following will refer to... Figures 1 to 4 Describe semiconductor package 1000.

[0038] like Figures 1 to 4 As shown, according to an embodiment of this disclosure, a semiconductor package 1000 may include: a stacked chip structure VCS, including a plurality of first semiconductor chips 100, second semiconductor chips 200, third semiconductor chips 300 and fourth semiconductor chips 400; a connection structure 500; a first connection line CW1, a second connection line CW2, a third connection line CW3 and a fourth connection line CW4; a shielding plate 600; a shielding line SW; a bump UBP; and a connection terminal 900.

[0039] In some embodiments, the semiconductor package 1000 may be a stacked fan-out wafer-level semiconductor package. In some embodiments, the semiconductor package 1000 may include a plurality of first semiconductor chips 100, second semiconductor chips 200, third semiconductor chips 300, and fourth semiconductor chips 400 sequentially stacked along a direction opposite to the first direction D1. In some embodiments, the first semiconductor chips 100, second semiconductor chips 200, third semiconductor chips 300, and fourth semiconductor chips 400 may be stacked on a shielding plate 600 in a stepped structure.

[0040] For example, a fourth semiconductor chip 400 can be first stacked on a shielding plate 600. Figure 3 As shown, in some embodiments, the fourth semiconductor chip 400 may include an eleventh surface S11 and a twelfth surface S12 that are opposite to each other in the first direction D1. In some embodiments, the fourth semiconductor chip 400 may be disposed on a shielding plate 600 such that the twelfth surface S12 can face the shielding plate 600.

[0041] Subsequently, the third semiconductor chip 300 can be stacked on top of the fourth semiconductor chip 400. The third semiconductor chip 300 may include a ninth surface S9 and a tenth surface S10 opposite to each other in the first direction D1. The third semiconductor chip 300 can be stacked on top of the fourth semiconductor chip 400 such that the tenth surface S10 can face the eleventh surface S11 of the fourth semiconductor chip 400. Compared to the fourth semiconductor chip 400, the third semiconductor chip 300 can be configured to protrude further in a direction opposite to the second direction D2.

[0042] The ninth surface S9 of the third semiconductor chip 300 may include a third region R3 and a fourth region R4. The third region R3 may be a region that at least partially overlaps with the second semiconductor chip 200 in the first direction D1, and the fourth region R4 may be a region exposed to the second semiconductor chip 200 (i.e., the fourth region R4 may be a region in the first direction D1 where the second semiconductor chip 200 is not located).

[0043] The eleventh surface S11 of the fourth semiconductor chip 400 may include a fifth region R5 and a sixth region R6. The fifth region R5 may be a region that at least partially overlaps with the third semiconductor chip 300 in the first direction D1, and the sixth region R6 may be a region exposed to the third semiconductor chip 300 (i.e., the sixth region R6 may be a region where the third semiconductor chip 300 is not present in the first direction D1).

[0044] Subsequently, the second semiconductor chip 200 can be stacked on the third semiconductor chip 300. The second semiconductor chip 200 may include a third surface S3 and a fourth surface S4 opposite to each other in the first direction D1. The second semiconductor chip 200 can be stacked on the third semiconductor chip 300 such that the fourth surface S4 can face the ninth surface S9 of the third semiconductor chip 300. Compared to the third semiconductor chip 300, the second semiconductor chip 200 can be configured to protrude further in a direction opposite to the second direction D2.

[0045] The third surface S3 of the second semiconductor chip 200 may include a first region R1 and a second region R2. The first region R1 may be a region that at least partially overlaps with the first semiconductor chip 100 in the first direction D1, and the second region R2 may be a region exposed by the first semiconductor chip 200 (i.e., the second region R2 may be a region where the first semiconductor chip 100 is not present in the first direction D1).

[0046] The first semiconductor chip 100 may include a first surface S1 and a second surface S2 that are opposite to each other in a first direction D1, and the first semiconductor chip 100 may be stacked on the second semiconductor chip 200 such that the second surface S2 can face the third surface S3 of the second semiconductor chip 200. When the first semiconductor chip 100 is stacked on the second semiconductor chip 200, the first semiconductor chip 100 may be configured to protrude further in a direction opposite to the second direction D2 compared to the second semiconductor chip 200.

[0047] The first surface S1 of the first semiconductor chip 100 may include a first connection pad CP1 and a first chip pad CPD1. The first connection pad CP1 may be disposed near the edge of the first surface S1. In some embodiments, a second connection pad CP2 may be disposed in a second region R2 of the third surface S3 of the second semiconductor chip, the second region R2 being a part of the third surface S2, which does not overlap with the first semiconductor chip 100 in the first direction D1 and is exposed by the first semiconductor chip 100 (i.e., the second region R2 is the region without the first semiconductor chip 100 in the first direction D1). A plurality of first chip pads CPD1 may be formed in the generally central portion and / or adjacent edge portion of the first surface S1. The first chip pads CPD1 of the first semiconductor chip 100 may be rewired via the connection structure 500 and connected to the connection terminals 900 disposed in the fan-out region FO.

[0048] The first semiconductor chip 100, the second semiconductor chip 200, the third semiconductor chip 300, and the fourth semiconductor chip 400 can be stacked and attached to each other by an adhesive layer disposed between them. The adhesive layer can be formed of materials such as non-conductive film (NCF), anisotropic conductive film (ACF), ultraviolet (UV) film, instant adhesive, thermosetting adhesive, laser-curing adhesive, ultrasonic-curing adhesive, or non-conductive paste (NCP).

[0049] The first semiconductor chip 100, the second semiconductor chip 200, the third semiconductor chip 300, and the fourth semiconductor chip 400 may be volatile memory chips, such as dynamic random access memory (DRAM), but this disclosure is not limited thereto. Alternatively, at least one of the first semiconductor chip 100, the second semiconductor chip 200, the third semiconductor chip 300, and the fourth semiconductor chip 400 may be a logic chip or a non-volatile memory chip.

[0050] Figures 1 to 4 The diagram illustrates a stacked chip structure VCS of semiconductor package 1000 including four semiconductor chips 100, 200, 300, and 400, but this disclosure is not limited thereto. That is, the number of semiconductor chips included in semiconductor package 1000 may be less than or greater than four. For convenience, the following description will primarily focus on an embodiment where semiconductor package 1000 includes four semiconductor chips (i.e., a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, and a fourth semiconductor chip 400).

[0051] In some embodiments, the connection structure 500 may include a fan-in region FI and a fan-out region FO. The fan-out region FO may be configured to at least partially surround the fan-in region FI. A first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, and a fourth semiconductor chip 400 may be disposed in the fan-in region FI. The fan-out region FO may include a configuration for rerouting first connection pads CP1, second connection pads CP2, third connection pads CP3, and fourth connection pads CP4 of the first to fourth semiconductor chips 100, 200, 300, and 400 to the outside of the first to fourth semiconductor chips 100, 200, 300, and 400 (e.g., the external environment of the semiconductor package 1000).

[0052] In some embodiments, the connection structure 500 may include an insulating layer IL, a first wiring layer W1 and a second wiring layer W2, a first via V1, a second via V2, and a third via V3. The connection structure 500 may have a fifth surface S5 and a sixth surface S6 opposite to each other in a first direction D1. The connection structure 500 may be configured such that the fifth surface S5 can face the first surface S1 of the first semiconductor chip 100. The connection structure 500 may be configured to rewire the first chip pad CPD1 and the first connection pad CP1, the second connection pad CP2, the third connection pad CP3, and the fourth connection pad CP4.

[0053] In some embodiments, the connection structure 500 may include a first ground pad GP1, a second ground pad GP2, a second chip pad CPD2, and a fifth connection pad CP5, a sixth connection pad CP6, a seventh connection pad CP7, and an eighth connection pad CP8, all disposed on a fifth surface S5. The first ground pad GP1 and the second ground pad GPS2 may be patterned on the fifth surface S5 of the connection structure 500. The first ground pad GP1 and the second ground pad GPS2 may be formed on the connection structure 500 such that their top surfaces are at least partially exposed without protruding from the fifth surface S5. In this case, the first ground pad GP1 and the second ground pad GPS2 may be integrally formed with a ground layer within the connection structure 500. The first ground pad GP1 and the second ground pad GPS2 may be patterned near the outer edge of the fifth surface S5 extending in a third direction D3 of the connection structure 500. The first ground pad GP1 and the second ground pad GP2 may be formed as solid lines or hidden lines. The first ground pad GP1 and the second ground pad GPS2 may be connected to a ground line GL patterned within an insulating layer IL.

[0054] refer to Figure 4 The first grounding pad GP1 can be arranged in a row adjacent to the outer edge of the connection structure 500 and extending in a third direction D3, and the second grounding pad GP2 can be arranged in a row adjacent to the opposite outer edge of the connection structure 500 and extending in a third position D3.

[0055] In some embodiments, a bump UBP may be disposed between a first surface S1 of the first semiconductor 100 and a fifth surface S5 of the connection structure 500. The first (e.g., upper) surface of the bump UBP may contact a first chip pad CPD1, and the second opposing (e.g., lower) surface of the bump UBP may connect to a second chip pad CPD2. The bump UBP may physically support the first semiconductor chip 100 and electrically connect the first semiconductor chip 100 to the connection structure 500.

[0056] The insulating layer IL may include an insulating material, such as a photoimaging dielectric (PID). A first wiring layer W1, a second wiring layer W2, a first via V1, a second via V2, and a third via V3 may be patterned within the insulating layer IL. The first wiring layer W1, the second wiring layer W2, the first via V1, the second via V2, and the third via V3 may form a redistribution layer RDL. The first wiring layer W1 and the second wiring layer W2 may extend in a second direction D2, and the first wiring layer W1, the second wiring layer W2, the first via V1, the second via V2, and the third via V3 may extend in a first direction D1. The first via V1 can connect the second chip pad CPD2 to the first wiring layer W1. The second via V2 can connect the first wiring layer W1 to the second wiring layer W2. The third via V3 can connect the second wiring layer W2 to the under-bump metallization (UBM).

[0057] However, the configuration of the connection structure 500 is not limited to the above. Alternatively, for example, the insulating layer IL of the connection structure 500 may be multi-layered, and the first wiring layer W1 and the second wiring layer W2 may also be multi-layered. In this case, the first via V1, the second via V2, and the third via V3 may also be multi-layered to electrically connect wiring layers from different layers.

[0058] In some embodiments, a passivation layer PL may be disposed on a sixth surface S6 of the connection structure 500. The passivation layer PL can protect the connection structure 500 from potential external physical and / or chemical damage. The passivation layer PL may include openings that expose at least a portion of the redistribution layer RDL of the connection structure 500. Tens to thousands of openings may be formed in the passivation layer PL. The passivation layer PL may include an insulating resin and inorganic fillers. A surface treatment layer such as nickel (Ni) / gold (Au) may be formed on the exposed surface of the redistribution layer RDL.

[0059] The under-bump metallization (UBM) can be connected to the redistribution layer RDL of the connection structure 500 and exposed through an opening in the passivation layer PL. The UBM can be formed in the opening of the passivation layer PL using a metallization method with a metallic material.

[0060] Connection terminals 900 can be attached to the surface of the under-bump metallization (UBM). Connection terminals 900 can physically and / or electrically connect the semiconductor package 1000 to the external environment. For example, the semiconductor package 1000 can be mounted on the motherboard of an electronic device via connection terminals 900. Connection terminals 900 can be formed of a low-melting-point metal (e.g., tin (Sn) or an alloy thereof). For example, connection terminals 900 can be formed using solder, but this disclosure is not limited thereto. Connection terminals 900 can be in the form of pads, balls, leads, or other shapes. Connection terminals 900 can be formed as multiple layers or a single layer. If connection terminals 900 are formed as multiple layers, they can include copper pillars and solder. Alternatively, if connection terminals 900 are formed as a single layer, they can include tin (Sn)-silver (Ag) solder or copper (Cu). Depending on the number of under-bump metallization (UBMs), tens to thousands of connection terminals 900 can be formed, but this disclosure is not limited thereto.

[0061] In some embodiments, the second connection pad CP2 may be disposed on the third surface S3 of the second semiconductor chip 200, specifically, formed to be adjacent to the edge of the third surface S3. The third connection pad CP3 may be disposed on the ninth surface S9 of the third semiconductor chip 300, specifically, formed to be adjacent to the edge of the ninth surface S8. For example, the third connection pad CP3 may be located in the fourth region R4 of the ninth surface S9 of the third semiconductor chip 300, which is exposed by the second semiconductor chip 200 (i.e., without the second semiconductor chip 200) and does not overlap with the second semiconductor chip 200 in the first direction D1. The fourth connection pad CP4 may be disposed on the eleventh surface S11 of the fourth semiconductor chip 400, specifically, formed to be adjacent to the edge of the eleventh surface S11. For example, the fourth connection pad CP4 may be located in the sixth region R6 of the eleventh surface S11 of the fourth semiconductor chip 400, which is exposed by the third semiconductor chip 300 (i.e., without the third semiconductor chip 300) and does not overlap with the third semiconductor chip 300 in the first direction D1.

[0062] The first connection line CW1 can extend longitudinally along a first direction D1. The first connection line CW1 can extend longitudinally in a direction perpendicular to the first surface S1 of the first semiconductor chip 100 and the fifth surface S5 of the connection structure 500, respectively. The first connection line CW1 can connect the first connection pad CP1 and the fifth connection pad CP5. A first end of the first connection line CW1 can contact the surface of the first connection pad CP1 (e.g., the lower surface), and a second end of the first connection line CW1 can contact the surface of the fifth connection pad CP5 (e.g., the upper surface). The fifth connection pad CP5 can be electrically connected to the connection terminal 900 via a redistribution layer RDL patterned in the insulating layer IL, the redistribution layer RDL including a first via V1, a first wiring layer W1, a second via V2, a second wiring layer W2, and a third via V3. That is, the first connection line CW1 can be configured to physically and electrically connect the first semiconductor chip 100 to the outside of the semiconductor package 1000.

[0063] The second connection line CW2 can extend longitudinally along the first direction D1. The second connection line CW2 can extend longitudinally in directions perpendicular to the third surface S3 of the second semiconductor chip 200 and the fifth surface S5 of the connection structure 500, respectively. The second connection line CW2 can connect the second connection pad CP2 and the sixth connection pad CP6. The first end of the second connection line CW2 can contact the bottom surface of the second connection pad CP2, and the second end of the second connection line CW2 can contact the upper surface of the sixth connection pad CP6. The sixth connection pad CP6 can be electrically connected to the connection terminal 900 through a redistribution layer RDL patterned in the insulating layer IL, the redistribution layer RDL including a first via V1, a first wiring layer W1, a second via V2, a second wiring layer W2, and a third via V3. That is, the second connection line CW2 can be configured to physically and electrically connect the second semiconductor chip 200 to the outside of the semiconductor package 1000 (e.g., the external environment of the semiconductor package 1000).

[0064] The third connection line CW3 can extend longitudinally along the first direction D1. The third connection line CW3 can extend longitudinally in a direction perpendicular to the fifth surface S5 of the connection structure 500 and the ninth surface S9 of the third semiconductor chip 300, respectively. The third connection line CW3 can connect the third connection pad CP3 and the seventh connection pad CP7. The first end of the third connection line CW3 can contact the surface of the third connection pad CP3 (e.g., the lower surface), and the second end of the third connection line CW3 can contact the surface of the seventh connection pad CP7 (e.g., the upper surface). The seventh connection pad CP7 can be electrically connected to the connection terminal 900 via a redistribution layer RDL patterned in the insulating layer IL, the redistribution layer RDL including a first via V1, a first wiring layer W1, a second via V2, a second wiring layer W2, and a third via V3. That is, the third connection line CW3 can be configured to physically and electrically connect the third semiconductor chip 300 to the outside of the semiconductor package 1000 (e.g., the external environment of the semiconductor package 1000).

[0065] The fourth connection line CW4 can extend longitudinally along the first direction D1. The fourth connection line CW4 can extend longitudinally in directions corresponding to the fifth surface S5 of the connection structure 500 and the eleventh surface S11 of the fourth semiconductor chip 400, respectively. The fourth connection line CW4 can connect the fourth connection pad CP4 and the eighth connection pad CP8. The first end of the fourth connection line CW4 can contact the surface of the fourth connection pad CP4 (e.g., the lower surface), and the second end of the fourth connection line CW4 can contact the surface of the eighth connection pad CP8 (e.g., the upper surface). The eighth connection pad CP8 can be electrically connected to the connection terminal 900 via a redistribution layer RDL patterned in the insulating layer IL, the redistribution layer RDL including a first via V1, a first wiring layer W1, a second via V2, a second wiring layer W2, and a third via V3. That is, the fourth connection line CW4 can be configured to physically and electrically connect the fourth semiconductor chip 400 to the outside of the semiconductor package 1000.

[0066] A shielding plate 600 may be disposed on the fourth semiconductor chip 400. The shielding plate 600 may include a seventh surface S7 and an eighth surface S8 opposite to each other in the first direction D1. The seventh surface S7 of the shielding plate 600 may face the twelfth surface S12 of the fourth semiconductor chip 400, and the eighth surface S8 of the shielding plate 600 may be opposite to the twelfth surface S12 of the fourth semiconductor chip 400. The shielding plate 600 may include a metallic material. The shielding plate 600 may have a rectangular plate shape.

[0067] refer to Figure 2The shielding plate 600 may include a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4. The first edge E1 and the second edge E2 may extend in a second direction D2 and may be spaced apart from each other in a third direction D3. The third edge E3 and the fourth edge E4 may extend in a third direction D3 and may be spaced apart in the second direction D2. Multiple shielding lines SW (e.g., SW1, SW2, SW3, SW4) extending longitudinally along the first direction D1 may be provided on the seventh surface S7 of the shielding plate 600.

[0068] The shielding line SW can be disposed between the shielding plate 600 and the connecting structure 500, and perpendicular to the seventh surface S7 of the shielding plate 600 and the fifth surface S5 of the connecting structure 500. The shielding line SW can be arranged in the fan-out region FO and at least partially surround the stacked chip structure VCS. (Reference) Figure 2 The shielded wire SW can be divided into a first group G1, a second group G2, a third group G3, and a fourth group G4. The first group G1 may include the first shielded wire SW1, the second group G2 may include the second shielded wire SW2, the third group G3 may include the third shielded wire SW3, and the fourth group G4 may include the fourth shielded wire SW4.

[0069] The first group G1 can be configured to correspond to the first edge E1 of the shielding plate 600, the second group G2 to the second edge E2 of the shielding plate 600, the third group G3 to the third edge E3 of the shielding plate 600, and the fourth group G4 to the fourth edge E4 of the shielding plate 600. The first shielding lines SW1 in the first group G1 can be spaced apart from each other in the second direction D2 and are adjacent to the first edge E1 of the shielding plate 600. The second shielding lines SW2 in the second group G2 can be spaced apart from each other in the second direction D2 and are adjacent to the second edge E2 of the shielding plate 600. The third shielding lines SW3 in the third group G3 can be spaced apart from each other in the third direction D3 and are adjacent to the third edge E3 of the shielding plate 600. The fourth shielding lines SW4 in the fourth group G4 can be spaced apart from each other in the third direction D3 and are adjacent to the fourth edge E4 of the shielding plate 600.

[0070] The first end of each shielded wire SW can be connected to the shielding plate 600, and the second end of each shielded wire SW can be connected to the first grounding pad GP1 or the second grounding pad GP2. For example, refer to... Figure 3 and Figure 4The second end of the first shielding wire SW1 can be electrically connected to either the first grounding pad GP1 or the second grounding pad GP2 via the grounding wire GL. Similarly, the second end of the second shielding wire SW2 can be electrically connected to either the first grounding pad GP1 or the second grounding pad GP2 via the grounding wire GL. The second end of the third shielding wire SW3 can be grounded to the first grounding pad GP1, and the second end of the fourth shielding wire SW4 can be grounded to the second grounding pad GP2.

[0071] The shielding wire SW can extend longitudinally along the first direction D1. The shielding wire SW can extend in a direction perpendicular to the fifth surface S5 of the connecting structure 500 and the seventh surface S7 of the shielding plate 600.

[0072] The shielding plate 600 and the shielding line SW can be configured as an electrically shielded semiconductor package 1000, which is a stacked fan-out wafer-level package. In the semiconductor package 1000, the shielding plate 600 and the connection structure 500 can be spaced apart from each other in a first direction D1, and a stacked chip structure VCS is located between the shielding plate 600 and the connection structure 500. The shielding line SW can electrically connect the shielding plate 600 to a first ground pad GP1 and a second ground pad GP2 formed on the connection structure 500, thereby forming an electromagnetic interference (EMI) shielding structure.

[0073] In some embodiments, the semiconductor package 1000 may further include a molding film 700 and a molding layer 800. The molding film 700 may be disposed on the eighth surface S8 of the shielding plate 600. The molding layer 800 may be formed to fill the space between the connection structure 500 and the shielding plate 600. The molding layer 800 may at least partially cover the fifth surface S5 of the connection structure 500, the shielding line SW, the first connection line CW1, the second connection line CW2, the third connection line CW3 and the fourth connection line CW4, the stacked chip structure VCS, and the seventh surface S7 of the shielding plate 600.

[0074] In some embodiments, the molding film 700 may surround and seal the eighth surface S8 of the shielding plate 600, and the molding layer 800 may surround and seal the stacked chip structure VCS. The molding film 700 and the molding layer 800 may include insulating materials, such as inorganic fillers and insulating resins. For example, thermosetting resins (e.g., epoxy resins), thermoplastic resins (e.g., polyimide), or resins containing reinforcing materials (e.g., inorganic fillers) (particularly ABF, FR-4, BT resins, etc.) may be used as insulating materials. Additionally, molding materials such as epoxy molding compounds (EMCs) may be used. If necessary, photosensitive materials, such as photographic imaging sealants (PIEs), may also be used. If desired, insulating resins, such as thermosetting or thermoplastic resins impregnated with inorganic fillers and / or reinforcing materials such as glass fibers (e.g., glass cloth or glass fabric), may also be used.

[0075] Figure 5 This is a flowchart illustrating an example method for manufacturing a semiconductor package according to an embodiment of the present disclosure. Figures 6 to 15 An example intermediate stage of a method for manufacturing a semiconductor package according to embodiments of the present disclosure is shown. Reference will be made below. Figures 5 to 15 A method for manufacturing a semiconductor package according to embodiments of the present disclosure is described.

[0076] First, refer to Figure 5 and Figure 6 In some embodiments, a carrier CR (S100) may be provided. On the carrier CR, a stacked chip structure ( Figure 1 The “VCS” in this context can be set to wafer-level. The carrier CR can be formed from materials such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), metal, glass, plastic, or ceramic substrate, but this disclosure is not limited thereto. In some embodiments, the carrier CR can be in the form of a wafer.

[0077] Subsequently, refer to Figure 5 and Figure 7 In some embodiments, the molded film 700 may be attached to the carrier CR (S110). Then, refer to Figure 5 and Figure 8 In some embodiments, the shielding plate 600 may be disposed on the molding film 700 (S120). The shielding plate 600 may be disposed on the molding film 700 such that the eighth surface S8 of the shielding plate 600 may face the molding film 700, and the seventh surface S7 of the shielding plate 600 may be opposite to the molding film 700.

[0078] Subsequently, refer to Figure 5 and Figure 9 In some embodiments, the fourth semiconductor chip 400 may be disposed on the seventh surface S7 of the shielding plate 600 (S130). The fourth semiconductor chip 400 may be disposed on the shielding plate 600 such that the twelfth surface S12 of the fourth semiconductor chip 400 may face the seventh surface S7 of the shielding plate 600. Subsequently, in some embodiments, the third semiconductor chip 300, the second semiconductor chip 200, and the first semiconductor chip 100 may be sequentially disposed on the fourth semiconductor chip 400 (S140). Therefore, the fourth semiconductor chip 400, the third semiconductor chip 300, the second semiconductor chip 200, and the first semiconductor chip 100 may be sequentially stacked on the shielding plate 600, forming a stepped structure on the shielding plate 600.

[0079] When the third semiconductor chip 300 is stacked on the fourth semiconductor chip 400, the third semiconductor chip 300 can be configured to protrude in a direction opposite to the second direction D2 compared to the fourth semiconductor chip 400, such that the third connection pad CP3 formed on the ninth surface S9 of the third semiconductor chip 300 can be exposed to the outside of the stacked chip structure VCS.

[0080] Similarly, when the second semiconductor chip 200 and the first semiconductor chip 100 are sequentially stacked on the third semiconductor chip 300, the second semiconductor chip 200 can be configured to protrude in a direction opposite to the second direction D2 compared to the third semiconductor chip 300, so that the second connection pad CP2 can be exposed to the outside of the stacked chip structure VCS, and the first semiconductor chip 100 can be configured to protrude in a direction opposite to the second direction D2 compared to the second semiconductor chip 200, so that the first connection pad CP1 can be exposed to the outside of the stacked chip structure VCS.

[0081] refer to Figure 5 and Figure 10 In some embodiments, the first connection line CW1, the second connection line CW2, the third connection line CW3, and the fourth connection line CW4 can be connected to the first connection pad CP1, the second connection pad CP2, the third connection pad CP3, and the fourth connection pad CP4, respectively (S150, S160, S170, and S180). The order in which the first connection line CW1, the second connection line CW2, the third connection line CW3, and the fourth connection line CW4 are connected to the first connection pad CP1, the second connection pad CP2, the third connection pad CP3, and the fourth connection pad CP4 is not limited to this. Figure 5 As shown in the diagram.

[0082] The first connecting line CW1, the second connecting line CW2, the third connecting line CW3, and the fourth connecting line CW4 can extend longitudinally in the first direction D1, and the direction in which the first connecting line CW1, the second connecting line CW2, the third connecting line CW3, and the fourth connecting line CW4 extend can be perpendicular to the seventh surface S7 of the shielding plate 600. In some embodiments, the first ends of the first connecting line CW1, the second connecting line CW2, the third connecting line CW3, and the fourth connecting line CW4 can respectively contact the first connecting pad CP1, the second connecting pad CP2, the third connecting pad CP3, and the fourth connecting pad CP4, and the second ends of the first connecting line CW1, the second connecting line CW2, the third connecting line CW3, and the fourth connecting line CW4 can face the direction opposite to the first direction D1.

[0083] refer to Figure 5 and Figure 11In some embodiments, the shielding wire SW can be connected to the shielding plate 600 (S190). The shielding wire SW can extend longitudinally along the first direction D1, and the direction in which the shielding wire SW extends can be perpendicular to the seventh surface S7 of the shielding plate 600. The first end of the shielding wire SW can contact the seventh surface S7 of the shielding plate 600, and the shielding wire SW can be electrically connected to the shielding plate 600. The second end of the shielding wire SW can face the direction opposite to the first direction D1.

[0084] Subsequently, refer to Figure 12 The bump UBP can be attached to the first chip pad CPD1 disposed on the first surface S1 of the first semiconductor chip 100. Then, refer to Figure 13 A molding layer 800 can be formed on the seventh surface S7 of the shielding plate 600. In some embodiments, the molding layer 800 can at least partially cover the seventh surface S7 of the shielding plate 600, the shielding line SW, the first to fourth connection lines CW1, CW2, CW3 and CW4, the stacked chip structure VCS, and the seventh surface S7 of the shielding plate 600.

[0085] Subsequently, refer to Figure 5 and Figure 14 In some embodiments, the connection structure 500 may be disposed on the first semiconductor chip 100 (S200). The connection structure 500 may be disposed on the first semiconductor chip 100 such that the first ground pad GP1 disposed on the fifth surface S5 of the connection structure 500 can be connected to the corresponding third shield line SW3, and the second ground pad GP2 can be connected to the corresponding fourth shield line SW4. Furthermore, in some embodiments, the first shield line SW1 and the second shield line SW2 may be connected to the ground line GL patterned in the insulating layer IL.

[0086] Furthermore, in some embodiments, the connection structure 500 may be disposed on the first semiconductor chip 100, such that the second chip pad CPD2 disposed on the fifth surface S5 of the connection structure 500 can be connected to the bump UBP. Furthermore, in some embodiments, the connection structure 500 may be disposed on the first semiconductor chip 100, such that the fifth connection pad CP5, the sixth connection pad CP6, the seventh connection pad CP7, and the eighth connection pad CP8 disposed on the fifth surface S5 of the connection structure 500 can be connected to the first connection line CW1, the second connection line CW2, the third connection line CW3, and the fourth connection line CW4, respectively.

[0087] Subsequently, refer to Figure 15In some embodiments, the connection terminal 900 may be attached to the under-bump metallization (UBM) formed on the sixth surface S6 of the connection structure 500. Therefore, in some embodiments, the first connection pads CP1, CP2, CP3, and CP4 of the first semiconductor chip 100, second semiconductor chip 200, third semiconductor chip 300, and fourth semiconductor chip 400 arranged in the fan-in region FI can be rewired through the connection structure 500, thereby connecting to the connection terminal 900 provided in the fan-out region FO.

[0088] Figure 16 and Figure 17 This is a diagram illustrating example steps of manufacturing a semiconductor package according to embodiments of the present disclosure.

[0089] Figure 16 This is a diagram illustrating a method of manufacturing a semiconductor package 100, which is a stacked fan-out wafer-level semiconductor package according to embodiments of the present disclosure. Multiple semiconductor chips (e.g., on silicon (Si) via wafer fabrication processes) can be fabricated on silicon (Si) (e.g., on a Si wafer). Figures 1 to 4 VCS (Video Stacked Chip Structure)

[0090] refer to Figure 16 Stacked chip structure Figure 1 The “VCS” in this context can be arranged at the wafer level on a carrier CR. The carrier CR can be, for example,... Figure 16 The wafer form is shown. The area where the stacked chip structure VCS is arranged on the carrier CR can be a fan-in region FI. The periphery of each fan-in region FI can be defined as a fan-out region FO. That is, the stacked chip structure VCS can be set in the fan-in region FI of the carrier CR, and the area at least partially surrounding the fan-in region FI can be defined as the fan-out region FO.

[0091] Figure 15 The illustration shows a single stacked chip structure VCS comprising a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, and a fourth semiconductor chip 400 arranged on a carrier CR. However, in practice, multiple stacked chip structures VCS can be arranged on the carrier CR, such as... Figure 16 As shown. After completing the step of attaching the connection terminal 900, as... Figure 15 As shown, the carrier CR can be removed, and the wafer can be separated into individual chips through a monolithic process. Through this monolithic process, the final manufactured semiconductor package can have… Figure 17 The shape of the semiconductor package 1000 shown.

[0092] According to this disclosure, EMI shielding can be achieved during the manufacturing process of semiconductor package 1000 by adding a shielding plate 600 and shielding lines SW, wherein the stacked chip structure VCS is connected to the connection structure 500 via vertical connecting lines (CW1, CW2, CW3, and CW4), without requiring additional processes to provide EMI shielding. As a result, the manufacturing time and cost of semiconductor package 1000 of this disclosure can be reduced.

[0093] Figure 18 This is a block diagram illustrating an example configuration of a semiconductor package 2000 according to an embodiment of the present disclosure.

[0094] refer to Figure 18 Semiconductor package 2000 can correspond to reference Figures 1 to 17 The semiconductor package 1000 is described. In some embodiments, the semiconductor package 2000 may include a first package 2030 and a second package 2040. The first package 2030 may include a controller (e.g., a controller chip) 2020, and the second package 2040 may include a first memory device (e.g., a memory chip) 2041, a second memory device (e.g., a memory chip) 2045, and a memory controller 2043. The first memory device 2041 and the second memory device 2045 may correspond to a stacked chip structure VCS (e.g., as referenced herein). Figures 1 to 17 The semiconductor package 2000 includes a semiconductor chip. The semiconductor package 2000 may also include a power management integrated circuit (PMIC) 2022, which provides operating voltage and current to the controller chip 2020, the first memory device 2041, the second memory device 2045, and the memory controller 2043, respectively. These operating voltages may be designed to be the same or different.

[0095] The semiconductor package 2000 disclosed herein can be implemented as included in a personal computer (PC) or mobile device. The mobile device can be a laptop computer, mobile phone, smartphone, tablet PC, personal digital assistant (PDA), enterprise digital assistant (EDA), digital still camera, digital video camera, portable multimedia player (PMP), personal navigation device (PND), portable navigation device, handheld game console, mobile internet device (MID), wearable computer, Internet of Things (IoT) device, Internet of Everything (IoE) device, or drone.

[0096] The controller 2020 can control the operation of the first storage device 2041, the second storage device 2045, and the memory controller 2043. For example, the controller 2020 can be implemented as an integrated circuit (IC), a system-on-a-chip (SoC), an application processor (AP), a mobile AP, a chipset, or a set of chips. The controller 2020 may include a central processing unit (CPU), a graphics processing unit (GPU), and / or a modem. In some embodiments, the controller 2020 can perform the functions of both a modem and an AP.

[0097] The memory controller 2043 can control the second memory device 2045 under the control of the controller 2020. The first memory device 2041 and the second memory device 2045 can be implemented as volatile memory devices. The volatile memory devices can be implemented as random access memory (RAM), dynamic RAM (DRAM), or static RAM (SRAM), but this disclosure is not limited thereto.

[0098] In some embodiments, at least one of the first storage device 2041 and the second storage device 2045 may be implemented as a storage-type storage device. The storage-type storage device may be implemented as a non-volatile storage device. The storage-type storage device may be implemented as a flash memory-based storage device, but this disclosure is not limited thereto. At least one of the first storage device 2041 and the second storage device 2045 may be implemented as a NAND flash memory device. The NAND flash memory device may include a two-dimensional (2D) memory cell array or a three-dimensional (3D) memory cell array. The 2D memory cell array or the 3D memory cell array may include a plurality of memory cells, each memory cell may store one bit of information or two or more bits of information.

[0099] When at least one of the first device 2041 and the second storage device 2045 is implemented as a flash-based storage device, the memory controller 2043 may use (or support) a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, or a universal flash memory (UFS) interface, but this disclosure is not limited thereto.

[0100] Figure 19 This is a block diagram illustrating an example configuration of a semiconductor package 2100 according to an embodiment of the present disclosure.

[0101] refer to Figure 19Semiconductor package 2100 may include a microprocessor unit (MPU) 2110, memory 2120, interface 2130, GPU 2140, function block 2150, and system bus 2160, the system bus 2160 connecting MPU 2110, memory 2120, interface 2130, GPU 2140, and function block 2150. Semiconductor package 2100 may include both MPU 2110 and GPU 2140, or only one of MPU 2110 and GPU 2140.

[0102] MPU 2110 may include cores and cache. For example, MPU 2110 may have multiple cores. The cores of MPU 2110 may have the same or different performance capabilities. Furthermore, the cores of MPU 2110 may be activated simultaneously or at different times. Memory 2120 may store processing results from function block 2150 under the control of MPU 2110. For example, the contents stored in the cache of MPU 2110 may be refreshed and stored in memory 2120. Interface 2130 may handle interaction with external devices. For example, interface 2130 may perform interface connections with cameras, liquid crystal displays (LCDs), and speakers.

[0103] GPU 2140 can perform graphics functions. For example, GPU 2140 can perform video codecs or process 3D graphics. Function block 2150 can perform various functions. For example, if semiconductor package 2100 is used as an access point (AP) in a mobile device, some of the function blocks 2150 can handle communication functions.

[0104] Semiconductor package 2100 can correspond to reference Figures 1 to 17 The semiconductor package 1000 is described. The MPU 2110 and / or GPU 2140 may correspond to the reference. Figure 18 The first package 2030 is described. The memory 2120 may correspond to the reference. Figure 18 The second package 2040 is described. Interface 2130 and function block 2150 can correspond to the reference. Figure 18 The first package 2030 is described.

[0105] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments, but can be implemented in various different forms. Those skilled in the art will understand that the present disclosure can be implemented in other specific forms without changing the technical spirit or essential characteristics of the present disclosure. Therefore, it should be understood that the above embodiments are illustrative in all respects and are not restrictive.

Claims

1. A semiconductor package, comprising: A first semiconductor chip includes a first surface having a first connection pad and a second surface opposite to the first surface in a first direction; The second semiconductor chip is located on the second surface of the first semiconductor chip and includes a third surface having a second bonding pad and a fourth surface opposite to the third surface in the first direction. A connection structure is provided on the first surface of the first semiconductor chip. The connection structure includes: a redistribution layer connected to the first connection pad and the second connection pad, a fifth surface facing the first surface of the first semiconductor chip, a sixth surface opposite to the fifth surface in the first direction, and a ground pad. A first connection line connects the first connection pad and the redistribution layer, and extends along the first direction; The second connection line connects the second connection pad and the redistribution layer, and extends along the first direction; A shielding plate on the fourth surface of the second semiconductor chip; and A shielding wire connects the shielding plate and the grounding pad, and extends longitudinally along the first direction.

2. The semiconductor package according to claim 1, wherein, The first connecting line extends in a direction perpendicular to the first surface of the first semiconductor chip and the fifth surface of the connecting structure.

3. The semiconductor package according to claim 1, wherein, The second connecting line extends in a direction perpendicular to the third surface of the second semiconductor chip and the fifth surface of the connecting structure.

4. The semiconductor package according to claim 1, wherein, The shielding plate includes a seventh surface facing the sixth surface of the connection structure, and an eighth surface opposite the seventh surface in the first direction. The shielding line extends in a direction perpendicular to the fifth surface of the connection structure and the seventh surface of the shielding plate.

5. The semiconductor package according to claim 4, further comprising: A molded layer on the eighth surface of the shielding plate.

6. The semiconductor package according to claim 1, further comprising: Multiple shielded cables, including: The shielding plate includes a first edge and a second edge, the first edge and the second edge each extending in a second direction intersecting the first direction, and wherein... The first edge and the second edge are spaced apart from each other on a third direction intersecting the first direction and the second direction.

7. The semiconductor package according to claim 6, wherein, The multiple shielded wires include a first group and a second group, wherein the first group includes a first shielded wire and the second group includes a second shielded wire. The first shielding lines in the first group are spaced apart from each other in the second direction and are adjacent to the first edge of the shielding plate. The second shielding lines in the second group are spaced apart from each other in the second direction and are adjacent to the second edge of the shielding plate.

8. The semiconductor package according to claim 7, wherein, The shielding plate further includes a third edge and a fourth edge, each extending along the third direction, and The third edge and the fourth edge are spaced apart from each other in the second direction.

9. The semiconductor package according to claim 8, wherein, The plurality of shielded wires also includes a third group and a fourth group, wherein the third group includes a third shielded wire and the fourth group includes a fourth shielded wire. The third shielding lines in the third group are spaced apart from each other in the third direction and are adjacent to the third edge of the shielding plate. The fourth shielding lines in the fourth group are spaced apart from each other in the third direction and are adjacent to the fourth edge of the shielding plate.

10. The semiconductor package according to claim 1, further comprising: A molded layer is located in the space between the shielding plate and the connecting structure.

11. The semiconductor package of claim 10, wherein, The molding layer at least partially covers the first semiconductor chip, the second semiconductor chip, the first connecting line, the second connecting line, and multiple shielding lines.

12. A semiconductor package, comprising: A first semiconductor chip includes a first surface having a first connection pad and a second surface opposite to the first surface in a first direction; The second semiconductor chip includes: a third surface facing the second surface of the first semiconductor chip, and a fourth surface opposite to the third surface in the first direction, the third surface including a first region that at least partially overlaps with the first semiconductor chip in the first direction, a second region without the first semiconductor chip, and a second connection pad disposed on the third surface and in the second region. The connection structure includes a fifth surface facing the first surface of the first semiconductor chip, a sixth surface opposite to the fifth surface, and a plurality of ground pads on the fifth surface; A first connection line is located between the first semiconductor chip and the connection structure, and contacts the first connection pad and the connection structure. A second connection line is located between the second semiconductor chip and the connection structure, and contacts the second connection pad and the connection structure. A shielding plate on the fourth surface of the second semiconductor chip; and Multiple shielding lines are provided between the shielding plate and the connection structure, the multiple shielding lines at least partially surrounding the first semiconductor chip and the second semiconductor chip, and each shielding line includes a first end connected to the shielding plate and a second end connected to a corresponding ground pad among the multiple ground pads.

13. The semiconductor package according to claim 12, wherein, The first connecting line, the second connecting line, and the plurality of shielding lines extend along the first direction.

14. The semiconductor package of claim 12, wherein, The connection structure includes an insulating layer and a wiring layer, the wiring layer being located within the insulating layer and extending in a second direction intersecting the first direction. The wiring layer connects the first connection line and the second connection line.

15. The semiconductor package of claim 14, wherein, The connection structure further includes a via located within the insulating layer and extending along the first direction, and a third connection pad located on the fifth surface of the connection structure. The via connects the wiring layer and the third connection pad.

16. The semiconductor package of claim 12, wherein, The multiple shielded wires include a first shielded wire, a second shielded wire, a third shielded wire, and a fourth shielded wire. The shielding plate includes a first edge and a second edge extending in a second direction intersecting the first direction, and a third edge and a fourth edge extending upward in a third direction intersecting the first direction and the second direction, respectively. The first shielding lines are spaced apart from each other in the second direction and are adjacent to the first edge. The second shielding lines are spaced apart from each other in the second direction and are adjacent to the second edge. The third shielding lines are spaced apart from each other in the third direction and are adjacent to the third edge. The fourth shielding lines are spaced apart from each other in the third direction and are adjacent to the fourth edge.

17. The semiconductor package of claim 12, further comprising: Multiple bumps are located between the first surface of the first semiconductor chip and the fifth surface of the connection structure. as well as Multiple connection terminals are located on the sixth surface of the connection structure.

18. A method for manufacturing a semiconductor package, the method comprising: Provide a carrier; The molded film is attached to the carrier; The shielding plate is arranged on the molded membrane; A first semiconductor chip is disposed on the shielding plate such that the second surface of the first semiconductor chip faces the shielding plate. The first semiconductor chip includes a first surface with a first connecting pad and a second surface opposite to the first surface in a first direction. A second semiconductor chip is disposed on the first semiconductor chip such that a fourth surface of the second semiconductor chip faces the first semiconductor chip, and the second semiconductor chip includes a third surface provided with a second connection pad and a fourth surface opposite to the third surface in the first direction; Connect the first connecting line extending along the first direction to the first connecting pad; Connect the second connection line extending along the first direction to the second connection pad; Connect the shielding wire extending along the first direction to the shielding plate; as well as A connection structure is arranged on the second semiconductor chip. The connection structure includes a redistribution layer and a ground pad. The redistribution layer is connected to the first connection pad via a first connection line and to the second connection pad via a second connection line. The ground pad is connected to the shielding plate via the shielding line.

19. The method of claim 18, further comprising: Before the connection structure is arranged on the second semiconductor chip, a molding layer is formed to at least partially cover the first semiconductor chip, the second semiconductor chip, the first connection line, the second connection line, the shielding line, and the shielding plate.

20. The method according to claim 18, wherein, The connection structure includes a fifth surface facing the second semiconductor chip and a sixth surface opposite to the fifth surface in the first direction, and The method further includes: after arranging the connection structure on the second semiconductor chip, arranging a plurality of connection terminals on the sixth surface of the connection structure.

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