Pulse generation circuit for serdes transmitter

Abstract

The application relates to the technical field of integrated circuits, and discloses a pulse generation circuit for a Serdes transmitter, which comprises a single-pulse generation module, a pseudo-static selector and a current mode drive module. The single-pulse generation module comprises first to fourth transistors, the gate of the first transistor receives a data signal, and the source is connected to a ground terminal; the gate of the fourth transistor receives one phase clock signal in a multi-phase clock signal, and the gates of the second and third transistors receive another phase clock signal; the drains of the second to fourth transistors are connected to each other and output a non-full-swing single-pulse signal; the pseudo-static selector comprises fifth to seventh transistors, the gate of the fifth transistor receives a reset signal, and the source is connected to a lifting voltage; the gates of the sixth and seventh transistors are respectively connected to the output ends of one single-pulse generation module, and the drains of the fifth to seventh transistors are connected to each other and output a full-swing single-pulse signal; the current mode drive module comprises eighth to tenth transistors, the gates of the eighth and ninth transistors are respectively connected to the output ends of the pseudo-static selector, the gate of the eighth transistor is connected to a bias voltage, and the source outputs a drive current. The application can improve the speed of pulse establishment, and reduce the complexity and cost of the drive module circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a pulse generation circuit for a Serdes transmitter and a Serdes transmitter including the pulse generation circuit. Background Technology

[0002] With the development of big data, cloud computing, and artificial intelligence, data centers, supercomputing clusters, and high-performance networks are placing increasingly higher demands on data transmission rates. The transmission rate of single-channel SerDes (Serializer / Deserializer) has gradually increased from 25Gbps and 56Gbps to 112Gbps and higher. Against this backdrop, the high-speed SerDes transmitter, as the core interface circuit, directly determines the data transmission capability and signal integrity of the entire link.

[0003] In high-speed SerDes transmitters, the multi-phase clock and 1-UI (Unit Interval) pulse generation circuitry is responsible for recombining multiple low-speed parallel data streams into full-speed serial data. For example, in a 1 / 8 rate architecture, an 8-phase clock signal needs to be sampled sequentially and alternately combined with 8 data streams to generate a full-speed serial signal. However, as data rates continue to increase, the 1-UI time has been reduced to the order of 8 ps. Accurately generating high-speed pulses and effectively driving subsequent transistors within such a narrow time window has become one of the technical bottlenecks in achieving high-speed and reliable transmission.

[0004] On the other hand, to improve bandwidth utilization, PAM4 (Pulse Amplitude Modulation 4-Level) modulation is widely used in high-speed interconnects. Compared with traditional NRZ (binary) modulation, PAM4 effectively improves data throughput by transmitting two bits of information at each UI. However, PAM4 drivers need to accurately output four high-speed signals, which places more stringent requirements on circuit linearity, common-mode level control, output swing, and bandwidth. Existing current-mode modulation (CML) transmitter driver structures often rely on additional common-mode current sources to achieve multi-level output, leading to increased power consumption and circuit complexity. Furthermore, in ultra-high-speed scenarios, they are prone to insufficient voltage margin and bandwidth limitations.

[0005] Therefore, designing a circuit structure in an ultra-high-speed (>56Gbps) SerDes transmitter that can efficiently generate high-speed 1-UI pulses and drive large-amplitude, highly linear PAM4 signals has become an important research direction in the design of high-speed interface chips. Summary of the Invention

[0006] The purpose of this application is to provide a pulse generation circuit for a Serdes transmitter, which generates a boost voltage through an operational amplifier feedback loop, effectively raising the low-level amplitude, improving the speed of 1-UI pulse establishment, and eliminating the need for additional transistors to provide the common-mode current of the drive module, thereby reducing the complexity and cost of the circuit.

[0007] In a first aspect, this application provides a pulse generation circuit for a SerDes transmitter, comprising:

[0008] At least four non-full-swing single-pulse generation modules are provided. Each single-pulse generation module includes a first to a fourth transistor, wherein: the gate of the first transistor receives a data signal, the source is connected to ground, and the drain is connected to the source of the second transistor; the gate of the fourth transistor receives one phase clock signal from the multi-phase clock signals, and the gates of the second and third transistors each receive another phase clock signal from the multi-phase clock signals; the sources of the third and fourth transistors are connected to a voltage source, and the drains of the second to fourth transistors are all connected and output a non-full-swing single-pulse signal.

[0009] At least two pseudo-static selectors are provided, each comprising a fifth to a seventh transistor, wherein: the gate of the fifth transistor receives a reset signal, and its source is connected to a boost voltage; the gates of the sixth and seventh transistors are each connected to the output of a single-pulse generation module, and the drains of the fifth to seventh transistors are all connected and output a full-swing single-pulse signal; wherein the potential of the boost voltage is higher than the potential of the ground terminal; and

[0010] At least one current-mode drive module, each current-mode drive module including an eighth to a tenth transistor, wherein: the gates of the eighth transistor and the ninth transistor are each connected to the output terminal of a pseudo-static selector, the sources of the eighth transistor and the ninth transistor are both connected to the ground terminal, the drains of the eighth transistor and the ninth transistor and the source of the tenth transistor are all connected; the gate of the eighth transistor is connected to a bias voltage, and the source of the eighth transistor outputs a drive current.

[0011] In a preferred embodiment, the system further includes a boost voltage generation module, which includes an operational amplifier and an eleventh transistor. The inverting input of the operational amplifier is connected to a reference voltage, the output of the operational amplifier is connected to the gate of the eleventh transistor, the source of the eleventh transistor is connected to ground, and the non-inverting input of the operational amplifier is connected to the drain of the eleventh transistor to output the boost voltage.

[0012] In a preferred embodiment, the reference voltage ranges from 0.1V to 0.2V.

[0013] In a preferred embodiment, the reference voltage is 0.15V.

[0014] In a preferred embodiment, the eleventh transistor is an NMOS transistor.

[0015] In a preferred embodiment, the first and second transistors are NMOS transistors, and the third and fourth transistors are PMOS transistors.

[0016] In a preferred embodiment, the sixth and seventh transistors are PMOS transistors, and the fifth transistor is an NMOS transistor.

[0017] In a preferred embodiment, the eighth to tenth transistors are NMOS transistors.

[0018] In a preferred embodiment, when the multi-phase clock signal is a four-phase clock signal, the pulse generation circuit includes four non-full-swing single-pulse generation modules, two pseudo-static selectors, and one current-mode drive module, wherein every two non-full-swing single-pulse generation modules are connected to one pseudo-static selector, and every two pseudo-static selectors are connected to one current-mode drive module.

[0019] In a preferred embodiment, the first single-pulse generation module receives a 0° phase clock signal and a 270° phase clock signal, the second single-pulse generation module receives a 90° phase clock signal and a 180° phase clock signal, the third single-pulse generation module receives a 180° phase clock signal and a 90° phase clock signal, and the fourth single-pulse generation module receives a 270° phase clock signal and a 0° phase clock signal; the first and second single-pulse generation modules are correspondingly connected to a first pseudo-static selector, and the third and fourth single-pulse generation modules are correspondingly connected to a second pseudo-static selector.

[0020] In a preferred embodiment, when the multi-phase clock signal is an eight-phase clock signal, the pulse generation circuit includes eight non-full-swing single-pulse generation modules, four pseudo-static selectors, and two current-mode drive modules, wherein every two non-full-swing single-pulse generation modules are connected to one pseudo-static selector, and every two pseudo-static selectors are connected to one current-mode drive module.

[0021] In a preferred embodiment, the first single-pulse generation module receives a 0° phase clock signal and a 225° phase clock signal; the second single-pulse generation module receives a 45° phase clock signal and a 270° phase clock signal; the third single-pulse generation module receives a 90° phase clock signal and a 315° phase clock signal; the fourth single-pulse generation module receives a 135° phase clock signal and a 0° phase clock signal; the fifth single-pulse generation module receives a 180° phase clock signal and a 45° phase clock signal; the sixth single-pulse generation module receives a 225° phase clock signal and a 90° phase clock signal; and the seventh single-pulse generation module receives a 270° phase clock signal. The first and second single-pulse generation modules are connected to the first pseudo-static selector, the third and fourth single-pulse generation modules are connected to the second pseudo-static selector, the fifth and sixth single-pulse generation modules are connected to the third pseudo-static selector, and the seventh and eighth single-pulse generation modules are connected to the fourth pseudo-static selector. The first and second pseudo-static selectors are connected to the first current-mode drive module, and the third and fourth pseudo-static selectors are connected to the second current-mode drive module.

[0022] In a preferred embodiment, when the multi-phase clock signal is an eight-phase clock signal, the phase of one phase clock signal in the multi-phase clock signal is 225° earlier than the phase of the other clock signal;

[0023] When the data signal transitions to a high level, and both the one-phase clock signal and the other-phase clock signal are at a low level, the fourth transistor is turned on, and the output of the single-pulse generation module is charged and held at a high level. When the other-phase clock signal transitions to a high level, the second transistor is turned on, and the output of the single-pulse generation module is pre-discharged to an intermediate potential. When the one-phase clock signal transitions to a high level, the fourth transistor is turned off, and the output of the single-pulse generation module is further discharged to a low potential. When the other-phase clock signal transitions to a low level, the output of the single-pulse generation module is recharged to a high level. After charging, pre-discharging, discharging, and recharging, the single-pulse generation module outputs the non-full-swing single-pulse signal.

[0024] In a second aspect, this application provides a SerDes transmitter, comprising:

[0025] Clock generation circuit;

[0026] Reset signal generation circuit;

[0027] Bias voltage generation circuit; and

[0028] The pulse generation circuit described above includes a clock generation circuit connected to the pulse generation circuit and providing a multi-phase clock signal to the pulse generation circuit; a reset signal generation circuit connected to the pulse generation circuit and providing a reset signal to the pulse generation circuit; and a bias voltage generation circuit connected to the pulse generation circuit and providing a bias voltage to the pulse generation circuit.

[0029] Compared with the prior art, this application has at least the following technical effects:

[0030] 1. By introducing a raised level VSSH generated by the operational amplifier feedback loop into the 1-UI pulse generation circuit, the low-level amplitude is effectively increased, the charging and discharging time of the node voltage is shortened, and the 1-UI pulse can be quickly established within an 8ps time window, which improves the 1-UI pulse establishment speed and significantly enhances the timing margin and stability of the ultra-high-speed SerDes transmitter.

[0031] 2. Innovatively, the raised 1-UI pulse level is used to realize common-mode current, avoiding the need for additional common-mode current source transistors, allowing the driver current source transistor to operate in a better state, maintaining a higher bandwidth, and improving the driver bandwidth; at the same time, the output current of the driver is increased, the voltage margin is smaller, and the driving capability of large swing signals is enhanced.

[0032] 3. By utilizing the 1-UI pulse itself to achieve common-mode current, the driver architecture is simplified, reducing additional transistors and bias circuitry, and lowering overall power consumption and area.

[0033] 4. The high-level pulse combined with the optimized current-mode structure makes the linearity of the PAM4 four-level signal output by the driver better, reduces inter-symbol interference (ISI) and nonlinear distortion, and significantly improves the eye diagram quality of the high-speed PAM4 signal and the decision margin at the receiver.

[0034] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the pulse generation circuit for a Serdes transmitter according to one embodiment of this application.

[0036] Figure 2 This is a schematic diagram of the structure of a non-full-amplitude single-pulse generation module according to one embodiment of this application.

[0037] Figure 3 This is a schematic diagram of the structure of a pseudo-static selector according to one embodiment of this application.

[0038] Figure 4 This is a schematic diagram of the structure of a current-mode drive module according to one embodiment of this application.

[0039] Figure 5 This is a schematic diagram of the structure of the voltage boosting generation module according to one embodiment of this application.

[0040] Figure 6 This is a timing diagram of a key node of a pulse generation circuit according to one embodiment of this application. Detailed Implementation

[0041] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0042] Explanation of some concepts:

[0043] In digital communication systems, the unit interval (UI) represents the duration of one data bit. In this application, 1-UI refers to the minimum time unit required to transmit a single data bit, which can be as small as 10 picoseconds in ultra-high-speed scenarios.

[0044] A full-swing signal is a signal whose voltage swings completely between the voltage source and ground potential. Compared to non-full-swing signals, full-swing signals have greater noise margin and better signal integrity, which is crucial for ensuring reliable data transmission.

[0045] The following is a brief summary of some of the innovative aspects of the embodiments of this application:

[0046] Existing ultra-high-speed SerDes transmitters, at data rates of 56G / 112G and higher, have a 1-UI time on the order of only 8ps. Traditional 1-UI pulse generation circuits struggle to quickly establish an effective pulse within such a narrow time window, resulting in insufficient timing margin. Meanwhile, existing PAM4 drivers typically rely on independent common-mode current sources, increasing circuit complexity and power consumption. Furthermore, they are prone to insufficient voltage margin and poor linearity when outputting large-swing multi-level signals, making it difficult to meet the demands of ultra-high-speed, high-bandwidth applications.

[0047] This invention provides a 1-UI pulse generation circuit and a PAM4 driver for ultra-high-speed SerDes transmitters. The 1-UI pulse generation circuit employs a multi-phase clock with alternating discharge / pull-up structure, recombining low-speed parallel data into a non-full-swing pulse signal with a 1-UI width under a high-speed clock. A boost level generated by the operational amplifier feedback loop is introduced to raise the pulse low level, shortening the node charging and discharging time, allowing the 1-UI pulse to be rapidly established within an 8ps time window. The PAM4 driver uses a current-mode differential structure, utilizing the raised 1-UI pulse itself to provide common-mode current, eliminating the need for a separate common-mode current source transistor, simplifying the driver architecture. Combined with multi-level signal synthesis and high-level pulse driving, it achieves larger output current and smaller voltage margin occupancy, significantly improving the linearity and eye diagram quality of the PAM4 signal, meeting the requirements of large-swing, high-speed transmission.

[0048] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0049] One embodiment of this application relates to a pulse generation circuit for a Serdes transmitter, the structure of which is as follows: Figure 1As shown, the structure includes: at least four non-full-swing single-pulse generation modules 101, at least two pseudo-static selectors 102, and at least one current-mode drive module 103. The single-pulse generation modules 101 are coupled to the pseudo-static selectors 102. The pseudo-static selectors 102 are coupled to the current-mode drive module 103. The number of single-pulse generation modules 101, pseudo-static selectors 102, and current-mode drive modules 103 depends on the rate requirements of the SerDes transmitter, as described below.

[0050] refer to Figure 2 As shown, each single-pulse generation module 101 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. In one embodiment, the first transistor M1 and the second transistor M2 can be NMOS transistors, and the third transistor M3 and the fourth transistor M4 can be PMOS transistors. The gate of the first transistor M1 receives the data signal Din, its source is connected to ground VSSL, and its drain is connected to the source of the second transistor M2. The gate of the fourth transistor M4 receives one phase clock signal from a multi-phase clock signal, such as clock signal CK1. The gates of the second transistor M2 and the third transistor M3 both receive another phase clock signal from the multi-phase clock signal, such as clock signal CK2. The sources of the third transistor M3 and the fourth transistor M4 are connected to a voltage source VDDL, and the drains of the second transistor M2, the third transistor M3, and the fourth transistor M4 are all connected and serve as the output terminals of the single-pulse generation module 101. The single-pulse generation module 101 is used to output a non-full-swing single-pulse signal.

[0051] It should be noted that the multi-phase clock signal is provided by a clock signal generation circuit, which can be generated by any clock signal generation circuit or method known in the art, and the present invention does not limit this.

[0052] refer to Figure 3 As shown, each pseudo-static selector 102 includes a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. In one embodiment, the sixth transistor M6 and the seventh transistor M7 can be PMOS transistors, and the fifth transistor M5 can be an NMOS transistor. The gate of the fifth transistor M5 receives a reset signal RST, and its source is connected to a boost voltage VDDH. The gates of the sixth transistor M6 and the seventh transistor M7 are each connected to the output of a single-pulse generation module 101, for example, receiving a non-full-swing single-pulse signal D1 and D2, respectively. The drains of the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all connected and serve as the output of the pseudo-static selector 102. The pseudo-static selector 102 is used to output a full-swing single-pulse signal 1-UI pulse. The potential of the boost voltage VSSH is higher than the potential of the ground terminal VSSL.

[0053] In this embodiment, the pseudo-static selector 102 has a 2:1 selectivity. It alternately turns on the sixth transistor M6 and the seventh transistor M7 according to the two non-full-swing single-pulse signals D1 and D2, thereby combining the two non-full-swing single-pulse signals D1 and D2 that are not enabled at the same time into a single signal line for output.

[0054] refer to Figure 4 As shown, each current-mode drive module 103 includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. In one embodiment, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 can be NMOS transistors. The gates of the eighth transistor M8 and the ninth transistor M9 are each connected to the output of a pseudo-static selector 102, i.e., each receives a full-swing single-pulse signal to drive the transistor to turn on. The sources of the eighth transistor M8 and the ninth transistor M9 are both connected to ground VSSL, and the drains of the eighth transistor M8 and the ninth transistor M9, as well as the source of the tenth transistor M10, are all connected together. The gate of the eighth transistor M8 is connected to a bias voltage vb1, and the source of the eighth transistor M8 serves as the output of the current-mode drive module 103, outputting a drive current Iout.

[0055] In this embodiment, the current-mode drive module 103 alternately activates the ninth transistor M9 and the tenth transistor M10 based on the two full-swing single-pulse signals output by the pseudo-static selector 102, thereby combining the two non-simultaneously enabled full-swing single-pulse signals into a single output, thus realizing the transmission function of ultra-high-speed signals. It should be noted that the bias voltage vb1 is provided by a bias voltage generation circuit, and can be generated using any bias voltage generation circuit or method known in the art; this invention does not limit this.

[0056] Compared to traditional source-switched CML transmitter driver circuits, the common-mode current (Icm) of the driver circuit in this invention is no longer provided by an additional transistor. Instead, it uses a raised 1-UI pulse signal to achieve the corresponding common-mode current in the switching transistor, thereby maintaining the bandwidth of the current source transistor. Furthermore, benefiting from the raised 1-UI pulse level, the output current Iout of this driver circuit is larger, the voltage margin is smaller, and the linearity is better, making it more suitable for transmitting large-swing, high-speed signals. These features of this structure can be applied to high-speed time-interleaved digital-to-analog converters, enabling the transmission of higher-quality PAM4 signals.

[0057] refer to Figure 5As shown, the pulse generation circuit also includes a boost voltage generation module. The boost voltage generation module includes an operational amplifier (OPA) and an eleventh transistor (M11). In one embodiment, the eleventh transistor M11 is an NMOS transistor. The inverting input of the operational amplifier (OPA) is connected to a reference voltage VSSH_REF, the output of the operational amplifier (OPA) is connected to the gate of the eleventh transistor (M11), the source of the eleventh transistor (M11) is connected to ground VSSL, and the non-inverting input of the operational amplifier (OPA) and the drain of the eleventh transistor (M11) are connected together to output the boost voltage VSSH.

[0058] In one embodiment, the reference voltage VSSH_REF ranges from 0.1V to 0.2V. For example, 0.15V is preferred. That is, the boost voltage VSSH is the value of ground VSSL plus the reference voltage VSSH_REF.

[0059] It should be noted that in this embodiment, VDDL refers to the low-voltage power supply, VSSL refers to ideal (i.e., 0V), and VSSH refers to the voltage after passing through the ground. Figure 5 The operational amplifier feedback loop shown generates a 0.15V potential. The main purpose of this potential is to raise the low-level amplitude of 1-UI, thereby accelerating the establishment speed of the 1-UI pulse.

[0060] In one embodiment, the multi-phase clock signal can be a four-phase clock signal, i.e., a clock signal including 0°, 90°, 180°, and 270° phases. The pulse generation circuit includes four non-full-swing single-pulse generation modules, two pseudo-static selectors, and one current-mode drive module. Each pair of non-full-swing single-pulse generation modules is connected to one pseudo-static selector, and each pair of pseudo-static selectors is connected to one current-mode drive module.

[0061] Specifically, the first single-pulse generation module receives a 0° phase clock signal and a 270° phase clock signal; the second single-pulse generation module receives a 90° phase clock signal and a 180° phase clock signal; the third single-pulse generation module receives a 180° phase clock signal and a 90° phase clock signal; and the fourth single-pulse generation module receives a 270° phase clock signal and a 0° phase clock signal. These two phase clock signals are used respectively as… Figure 2 As shown in the diagram, CK1 and CK2, for example, in the second single-pulse generation module, the 90° phase clock signal is used as CK1 and the 180° phase clock signal is used as CK2; in the third single-pulse generation module, the 180° phase clock signal is used as CK1 and the 90° phase clock signal is used as CK2, and so on. The first and second single-pulse generation modules are connected to the first pseudo-static selector, and the third and fourth single-pulse generation modules are connected to the second pseudo-static selector.

[0062] In another embodiment, the multi-phase clock signal can be an eight-phase clock signal, i.e., a clock signal including 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315° phases. The pulse generation circuit includes eight non-full-swing single-pulse generation modules, four pseudo-static selectors, and two current-mode drive modules. Each pair of non-full-swing single-pulse generation modules is connected to one pseudo-static selector. Each pair of pseudo-static selectors is connected to one current-mode drive module.

[0063] Specifically, the first single-pulse generation module receives a 0° phase clock signal and a 225° phase clock signal; the second single-pulse generation module receives a 45° phase clock signal and a 270° phase clock signal; the third single-pulse generation module receives a 90° phase clock signal and a 315° phase clock signal; the fourth single-pulse generation module receives a 135° phase clock signal and a 0° phase clock signal; the fifth single-pulse generation module receives a 180° phase clock signal and a 45° phase clock signal; the sixth single-pulse generation module receives a 225° phase clock signal and a 90° phase clock signal; the seventh single-pulse generation module receives a 270° phase clock signal and a 135° phase clock signal; and the eighth single-pulse generation module receives a 315° phase clock signal and a 180° phase clock signal. The two phase clock signals are used respectively as… Figure 2 As shown in the diagram, CK1 and CK2, for example, in the second single-pulse generation module, a 45° phase clock signal is used as CK1 and a 270° phase clock signal is used as CK2; in the third single-pulse generation module, a 90° phase clock signal is used as CK1 and a 315° phase clock signal is used as CK2, and so on. The first and second single-pulse generation modules are connected to the first pseudo-static selector, the third and fourth single-pulse generation modules are connected to the second pseudo-static selector, the fifth and sixth single-pulse generation modules are connected to the third pseudo-static selector, and the seventh and eighth single-pulse generation modules are connected to the fourth pseudo-static selector; the first and second pseudo-static selectors are connected to the first current-mode drive module, and the third and fourth pseudo-static selectors are connected to the second current-mode drive module.

[0064] The following explanation uses an eight-phase clock signal as an example of a multi-phase clock signal. (Reference) Figure 2 and Figure 6As shown, for example, CK1 is a 0° phase clock signal, and CK2 is a 225° phase clock signal. The phase of the CK1 phase clock signal is 225° earlier than the other CK2 phase clock signal. When the data signal Din jumps to a high level, and both the CK1 and CK2 clock signals are low, the fourth transistor M4 is turned on, and the output D1 of the single-pulse generation module is charged and held at a high level. When the CK2 clock signal jumps to a high level, the second transistor M2 is turned on, and the output D1 of the single-pulse generation module is pre-discharged to an intermediate potential. When the CK1 clock signal jumps to a high level, the fourth transistor M4 is turned off, and the output D1 of the single-pulse generation module is further discharged to a low potential (i.e., close to 0 potential). When the CK2 clock signal jumps to a low level, the output D1 of the single-pulse generation module is recharged to a high level, i.e., pulled up to a high level. Therefore, after charging, pre-discharging, discharging, and recharging, the single-pulse generation module outputs a non-full-swing single-pulse signal D1.

[0065] For example, when low-speed data at 1 / 8 speed enters the circuit, it is first captured by the pre-discharge of CK2. At this time, CK1 is low and CK2 is high, and node D1 is slowly discharged to an intermediate level. When CK1 turns high, node D1 is discharged to near 0 potential, and then CK2, which turns low, pulls node D1 up, realizing a non-full-swing 1-UI data pulse. D2 is generated by another single-pulse generation module through a similar process. After passing through a pseudo-static two-to-one multiplexer circuit, D1 / D2 is combined to realize the synthesis of the two data streams and finally fed to the current-mode driver to realize the transmission function of ultra-high-speed signals.

[0066] Other embodiments of this application also provide a SerDes transmitter, including a clock generation circuit, a reset signal generation circuit, a bias voltage generation circuit, and the pulse generation circuit described above. The clock generation circuit is connected to the pulse generation circuit and provides a multi-phase clock signal to the pulse generation circuit; the reset signal generation circuit is connected to the pulse generation circuit and provides a reset signal to the pulse generation circuit; and the bias voltage generation circuit is connected to the pulse generation circuit and provides a bias voltage to the pulse generation circuit.

[0067] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0068] The term “coupled to” and its derivatives may be used in this document. “Coupled” can mean two or more elements in direct physical or electrical contact. However, “coupled” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements coupled or connected between elements referred to as being coupled to each other.

[0069] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

Claims

1. A pulse generation circuit for a SerDes transmitter, characterized in that, include: At least four non-full-swing single-pulse generation modules are provided. Each single-pulse generation module includes a first to a fourth transistor, wherein: the gate of the first transistor receives a data signal, the source is connected to ground, and the drain is connected to the source of the second transistor; the gate of the fourth transistor receives one phase clock signal from a multi-phase clock signal, and the gates of the second and third transistors each receive another phase clock signal from the multi-phase clock signal; the sources of the third and fourth transistors are connected to a voltage source, and the drains of the second to fourth transistors are all connected and output a non-full-swing single-pulse signal. At least two pseudo-static selectors are provided, each comprising a fifth to a seventh transistor, wherein: the gate of the fifth transistor receives a reset signal, and its source is connected to a boost voltage; the gates of the sixth and seventh transistors are each connected to the output of a single-pulse generation module, and the drains of the fifth to seventh transistors are all connected and output a full-swing single-pulse signal; wherein the potential of the boost voltage is higher than the potential of the ground terminal; and At least one current-mode drive module, each current-mode drive module including an eighth to a tenth transistor, wherein: the gates of the tenth transistor and the ninth transistor are each connected to the output terminal of a pseudo-static selector, the sources of the tenth transistor and the ninth transistor are both connected to the ground terminal, the drains of the tenth transistor and the ninth transistor and the source of the eighth transistor are all connected; the gate of the eighth transistor is connected to a bias voltage, and the source of the eighth transistor outputs a drive current.

2. The pulse generation circuit as described in claim 1, characterized in that, Also includes: A voltage boosting module is provided, comprising an operational amplifier and an eleventh transistor. The inverting input of the operational amplifier is connected to a reference voltage, the output of the operational amplifier is connected to the gate of the eleventh transistor, the source of the eleventh transistor is connected to ground, and the non-inverting input of the operational amplifier is connected to the drain of the eleventh transistor and outputs the boosted voltage.

3. The pulse generation circuit as described in claim 2, characterized in that, The reference voltage ranges from 0.1V to 0.2V.

4. The pulse generation circuit as described in claim 2, characterized in that, The eleventh transistor is an NMOS transistor.

5. The pulse generation circuit as described in claim 1, characterized in that, When the multi-phase clock signal is a four-phase clock signal, the pulse generation circuit includes four non-full-swing single-pulse generation modules, two pseudo-static selectors, and one current-mode drive module. Each pair of non-full-swing single-pulse generation modules is connected to one pseudo-static selector, and each pair of pseudo-static selectors is connected to one current-mode drive module.

6. The pulse generation circuit as described in claim 5, characterized in that, The first single-pulse generation module receives a 0° phase clock signal and a 270° phase clock signal; the second single-pulse generation module receives a 90° phase clock signal and a 180° phase clock signal; the third single-pulse generation module receives a 180° phase clock signal and a 90° phase clock signal; and the fourth single-pulse generation module receives a 270° phase clock signal and a 0° phase clock signal. The first and second single-pulse generation modules are connected to the first pseudo-static selector, and the third and fourth single-pulse generation modules are connected to the second pseudo-static selector.

7. The pulse generation circuit as described in claim 1, characterized in that, When the multi-phase clock signal is an eight-phase clock signal, the pulse generation circuit includes eight non-full-swing single-pulse generation modules, four pseudo-static selectors, and two current-mode drive modules. Each pair of non-full-swing single-pulse generation modules is connected to one pseudo-static selector, and each pair of pseudo-static selectors is connected to one current-mode drive module.

8. The pulse generation circuit as described in claim 7, characterized in that, The first single-pulse generation module receives a 0° phase clock signal and a 225° phase clock signal; the second single-pulse generation module receives a 45° phase clock signal and a 270° phase clock signal; the third single-pulse generation module receives a 90° phase clock signal and a 315° phase clock signal; the fourth single-pulse generation module receives a 135° phase clock signal and a 0° phase clock signal; the fifth single-pulse generation module receives a 180° phase clock signal and a 45° phase clock signal; the sixth single-pulse generation module receives a 225° phase clock signal and a 90° phase clock signal; and the seventh single-pulse generation module receives a 270° phase clock signal and a 135° phase clock signal. The eighth single-pulse generation module receives a 315° phase clock signal and a 180° phase clock signal; the first and second single-pulse generation modules are connected to the first pseudo-static selector, the third and fourth single-pulse generation modules are connected to the second pseudo-static selector, the fifth and sixth single-pulse generation modules are connected to the third pseudo-static selector, and the seventh and eighth single-pulse generation modules are connected to the fourth pseudo-static selector; the first and second pseudo-static selectors are connected to the first current-mode drive module, and the third and fourth pseudo-static selectors are connected to the second current-mode drive module.

9. The pulse generation circuit as described in claim 1, characterized in that, When the multi-phase clock signal is an eight-phase clock signal, the phase of one phase clock signal in the multi-phase clock signal is 225° earlier than the phase clock signal of the other phase clock signal; When the data signal transitions to a high level, and both the one-phase clock signal and the other-phase clock signal are at a low level, the fourth transistor is turned on, and the output of the single-pulse generation module is charged and held at a high level. When the other-phase clock signal transitions to a high level, the second transistor is turned on, and the output of the single-pulse generation module is pre-discharged to an intermediate potential. When the one-phase clock signal transitions to a high level, the fourth transistor is turned off, and the output of the single-pulse generation module is further discharged to a low potential. When the other-phase clock signal transitions to a low level, the output of the single-pulse generation module is recharged to a high level. After charging, pre-discharging, discharging, and recharging, the single-pulse generation module outputs the non-full-swing single-pulse signal.

10. A SerDes transmitter, characterized in that, include: Clock generation circuit; Reset signal generation circuit; Bias voltage generation circuit; as well as The pulse generation circuit according to any one of claims 1 to 9, wherein the clock generation circuit is connected to the pulse generation circuit and provides a multi-phase clock signal to the pulse generation circuit, the reset signal generation circuit is connected to the pulse generation circuit and provides a reset signal to the pulse generation circuit, and the bias voltage generation circuit is connected to the pulse generation circuit and provides a bias voltage to the pulse generation circuit.

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