Embedded circuit board, method of manufacturing the same, and electronic device

Abstract

The application discloses an embedded circuit board, a manufacturing method thereof and an electronic device, and belongs to the technical field of circuit boards. The embedded circuit board comprises a mother board, and a blind groove is arranged on the mother board. A daughter board is arranged in the blind groove. A build-up plate is arranged on the surface of the mother board and the daughter board. The build-up plate is provided with an interconnection area covering the surface of the daughter board. A third circuit and a fourth circuit perpendicular to the surface of the daughter board are arranged in the interconnection area, and a fifth circuit is arranged in the daughter board. The third circuit, the fifth circuit and the fourth circuit are sequentially connected to form an interconnection circuit. The interconnection circuit is used for connecting a first component and a second component arranged on the surface of the build-up plate. In the application, the interconnection area of the daughter board and the build-up plate forms a larger longitudinal space, vertical wiring is used in the longitudinal space, wiring density is dispersed, and the layout of the circuit is optimized. In the application of connecting a BGA chip, the length of the neckdown line in the BGA area can be reduced, and the signal integrity can be improved.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and in particular to an embedded circuit board, its manufacturing method, and electronic devices. Background Technology

[0002] As data transmission rates continue to increase, more components need to be accommodated within a unit area, leading to increasingly smaller PCB (Printed Circuit Board) spacing and thinner traces. When multiple components are integrated on a PCB, internal wiring is often used to achieve conductivity and signal transmission between them. However, with increasing PCB integration density, more and more chips may need to be connected, placing higher demands on PCB trace density. Higher wiring density may not meet trace width and spacing requirements, leading to increased signal interference between traces. Summary of the Invention

[0003] The purpose of this application is to provide an embedded circuit board, its manufacturing method, and electronic devices to solve the problem of difficult electrical interconnection of components on a PCB in related technologies.

[0004] To solve the above-mentioned technical problems, this application adopts the following technical solution:

[0005] In a first aspect, this application provides an embedded circuit board, comprising:

[0006] Mother plate, wherein the mother plate is provided with blind groove;

[0007] Sub-plate, wherein the sub-plate is disposed within the blind slot;

[0008] An add-in board, the add-in board comprising one or more add-in structures, the add-in board being disposed on the surfaces of the mother board and the daughter board, the add-in board having an interconnection area covering the surface of the daughter board;

[0009] The interconnection area is provided with a third line and a fourth line perpendicular to the surface of the sub-board, and a fifth line is provided in the sub-board. The third line, the fifth line and the fourth line are connected in sequence to form an interconnection line. The interconnection line is used to connect the first component and the second component located on the surface of the layer board.

[0010] Optionally, the fifth line is connected to the third line via the first pad and to the fourth line via the second pad;

[0011] The first pad and the second pad are disposed on the surface of the sub-board near the side of the add-on board.

[0012] Optionally, the fifth line has a U-shaped structure.

[0013] Optionally, the interconnecting lines are multiple, and the multiple interconnecting lines are arranged in a hierarchical nested manner.

[0014] Optionally, a dielectric layer is filled between the sub-board and the motherboard.

[0015] Optionally, the medium layer is a resin material layer.

[0016] Optionally, the added-layer structure includes: a prepreg and a copper foil stacked together.

[0017] Optionally, the add-on board may further include a first chip region and a second chip region located on both sides of the interconnect region;

[0018] The first chip area is provided with a first line for connecting the first component and the motherboard, and the second chip area is provided with a second line for connecting the second component and the motherboard.

[0019] Secondly, this application provides a method for manufacturing an embedded circuit board, the method comprising:

[0020] A blind groove is formed on the mother plate;

[0021] A sub-board with a fifth circuit is installed in the blind slot;

[0022] One or more layers are added to the surface of the motherboard to form the added layer board. After each addition, the added layer structure is drilled and electroplated to fill the holes to form the third and fourth lines. The third, fifth and fourth lines are connected in sequence to form interconnecting lines.

[0023] Thirdly, this application provides an electronic device, including an embedded circuit board according to the first aspect of this application, or an embedded circuit board prepared by the method according to the second aspect of this application.

[0024] Compared with existing technologies, the beneficial effects achieved by this application are as follows: In this embodiment, a sub-board is embedded in the motherboard, and an add-on board is provided on the surfaces of the motherboard and the sub-board. A larger vertical space is formed by stacking the sub-board and the add-on board. A third and fourth circuit perpendicular to the surface of the sub-board are arranged in this vertical space. The third and fourth circuits are respectively perpendicularly connected to the first component and the second component, and are connected through a fifth circuit disposed in the sub-board, realizing the interconnection of the first component and the second component. Vertical wiring can disperse wiring density, optimize circuit layout, achieve better linewidth design, ensure stable signal transmission, and effectively solve the problems of limited wiring and signal loss in high-density integrated PCB circuits. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the wiring connection between the BGA chip and the optical module in the related technology provided in this application;

[0027] Figure 2 This is a schematic diagram of the embedded circuit board structure of Embodiment 1 or Embodiment 2 provided in this application;

[0028] Figure 3 This is a schematic diagram of the motherboard structure of Embodiment 1 or Embodiment 2 provided in this application;

[0029] Figure 4 This is a schematic diagram of the interconnection lines in Embodiment 1 or Embodiment 2 provided in this application;

[0030] Figure 5 This is a schematic diagram of the connection of the fifth line, the first pad, and the second pad in Embodiment 2 provided in this application;

[0031] Figure 6 This is a schematic diagram of the sub-plate structure of Embodiment 2 provided in this application.

[0032] Explanation of reference numerals in the attached diagram: 1-Mother board; 2-Daughter board; 3-Dielectric layer; 4-Addition layer board; 5-Interconnect line; 6-First component; 7-Second component; 11-Blind slot; 21-First pad; 22-Second pad; 51-Third line; 52-Fourth line; 53-Fifth line. Detailed Implementation

[0033] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure / application, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this application or its application or use.

[0034] As PCB integration density increases, interconnecting components on a PCB becomes increasingly difficult. When multiple components on a PCB are connected to a single component, such as a BGA (Ball Grid Array) chip connecting multiple optical modules, wiring is often used to connect the other modules outwards from the perimeter of the BGA chip. See the appendix for details. Figure 1Fan-out routing can improve connection density to some extent, but it cannot be further increased due to limitations in BGA chip design size and trace width / spacing requirements. Furthermore, as routing density increases, signal interference between traces also increases. To avoid signal interference, traces must detour around certain areas, resulting in inconsistent trace routing. Related technologies use layer addition to gradually reduce the BGA area. However, excessive layer addition increases the overall PCB manufacturing process, increases the transmission path of SI signals, increases signal loss, and also affects chip-PCB soldering.

[0035] To address the aforementioned problems, this application provides an embedded circuit board and its manufacturing method. The specific structure of the embedded circuit board and its manufacturing method are described below using different embodiments as examples and in conjunction with the accompanying drawings.

[0036] Example 1

[0037] This embodiment provides an embedded circuit board, referenced... Figure 2 and Figure 3 The embedded circuit board in this embodiment includes: a motherboard 1; the motherboard 1 is an A-board or an A+B board with completed circuit fabrication. The motherboard 1 is suitable for connecting the various components that need to be interconnected. A blind slot 11 is provided on the motherboard 1. A daughterboard 2 is provided within the blind slot 11, and the daughterboard 2 is a multilayer board with completed circuit fabrication. An add-on board 4 is provided on the surfaces of the motherboard 1 and the daughterboard 2. The add-on board 4 includes one or more add-on structures, which is not limited in this embodiment. In some embodiments, the add-on structure includes a prepreg and copper foil stacked together. The add-on board 4 can be formed by sequentially laminating. Reference Figure 4 Furthermore, the add-on board 4 has an interconnection area covering the surface of the sub-board 2. Within the interconnection area, a third line 51 and a fourth line 52 perpendicular to the surface of the sub-board 2 are provided, and a fifth line 53 is provided within the sub-board 2. The third line 51, the fifth line 53, and the fourth line 52 are sequentially connected to form interconnection lines 5. Interconnection lines 5 are used to connect the first component 6 and the second component 7 disposed on the surface of the add-on board 4.

[0038] In this embodiment, a sub-board 2 is embedded in the motherboard 1, and an add-on board 4 is provided on the surfaces of the motherboard 1 and the sub-board 2. A large vertical space is formed by stacking the sub-board 2 and the add-on board 4. A third line 51 and a fourth line 52, perpendicular to the surface of the sub-board 2, are arranged in this vertical space. The third line 51 and the fourth line 52 can respectively vertically connect the first component 6 and the second component 7, realizing vertical wiring; and can be connected through a fifth line 53 provided in the sub-board 2, thereby realizing the interconnection of the first component 6 and the second component 7. This embodiment optimizes the circuit layout through vertical wiring, ensuring stable signal transmission and effectively solving the problems of limited wiring and signal loss in high-density integrated PCB circuits. When this application is used to connect multiple optical modules to a BGA chip, it eliminates the need to reduce the BGA area through add-on layers. The larger vertical wiring space reduces the neckdown length of the BGA area, which is beneficial for improving signal integrity.

[0039] Example 2

[0040] Based on the same inventive concept as Embodiment 1, refer to Figures 4 to 6 In this embodiment, the fifth line 53 has a U-shaped structure. One end of the fifth line 53 is connected to the third line 51 via the first pad 21, and the other end is connected to the fourth line 52 via the second pad 22. The first pad 21 and the second pad 22 are disposed on the surface of the sub-board 2 near the add-on board 4. The U-shaped structure extends the vertical wiring length of the third line 51 and the fourth line 52.

[0041] Furthermore, in this embodiment, there are multiple interconnecting lines 5, which are arranged in a layered and nested manner. This layered arrangement in the vertical space avoids signal interference between the interconnecting lines 5.

[0042] In this embodiment, a dielectric layer 3 is filled between the daughter board 2 and the mother board 1. The dielectric layer 3 is an insulating layer, and it is made of resin material, specifically epoxy resin or polyimide resin. The dielectric layer 3 is used to separate the mother board 1 from the daughter board 2, and to separate the daughter board 2 from the extension plate 4. Furthermore, the upper surface of the dielectric layer 3 is flush with the upper surface of the mother board 1 to facilitate the installation of the extension plate 4.

[0043] Furthermore, in some embodiments, the add-on board 4 may not be provided on the surfaces of the mother board 1 and the daughter board 2. The first component 6 and the second component 7 are respectively connected to the first pad 21 and the second pad 22 to achieve interconnection.

[0044] Example 3

[0045] This embodiment provides a method for preparing the embedded circuit board in Embodiment 1, including the following steps:

[0046] Step 1: Form a blind groove 11 on the mother plate 1;

[0047] Step 2: Install a sub-board 2 with the fifth line 53 inside the blind slot 11;

[0048] Step 3: Perform one or more layering operations on the surface of the motherboard 1 to form an extension board 4. After each layering operation, the extension structure is drilled and electroplated to fill the holes to form the third line 51 and the fourth line 52. The third line 51, the fifth line 53 and the fourth line 52 are connected in sequence to form an interconnecting line 5.

[0049] Example 4

[0050] This embodiment provides a method for preparing the embedded circuit board in Embodiment 2, wherein the add-on board 4 in this embodiment includes a multi-layer add-on structure, and the method includes the following steps:

[0051] Step 1: Make the mother board 1 and daughter board 2 according to the information.

[0052] In the process of manufacturing sub-board 2, the fifth circuit 53 is manufactured according to the number and position of the interconnection parts (such as solder balls, pins, etc.) of the components.

[0053] Step 2: Set the first pad 21 and the second pad 22 on the sub-board 2.

[0054] As an optional implementation, after the pattern route of the sub-board 2 is made, electroplating is performed on the surface of the sub-board 2. After electroplating, the first pad 21 and the second pad 22 are milled out by a pick.

[0055] Step 3: Form blind groove 11 on mother plate 1.

[0056] As an alternative implementation, blind grooves 11 are formed on the mother plate 1 by mechanical or laser means.

[0057] Step 4: Install a sub-board 2 with the fifth line 53 inside the blind slot 11.

[0058] As an optional implementation, the daughter plate 2 is embedded in the blind groove 11 by means of an insulating medium, so that the daughter plate 2 is flush with the upper surface of the mother plate 1. The insulating medium covers the surface of the daughter plate 2 to form a dielectric layer 3.

[0059] Step 5: Perform one or more layering operations on the surface of the motherboard 1 to form the layered board 4. After each layering operation, the layered structure is drilled and electroplated to fill the holes to form the third line 51 and the fourth line 52. The third line 51, the fifth line 53 and the fourth line 52 are connected in sequence to form the interconnecting line 5.

[0060] As an optional implementation, after the first layer addition, through-holes communicating with the first pad 21 and the second pad 22 are laser-etched into the add-on structure and dielectric layer 3. After each subsequent layer addition, through-holes overlapping with those on adjacent add-on structures are laser-etched onto the outermost add-on structure. The through-holes communicating with the first pad 21 together form the first through-hole, and the through-holes communicating with the second pad 22 together form the second through-hole.

[0061] After each layer is added, the through holes formed on the outermost layer structure are electroplated to fill them and form a conductive layer. The conductive layers in the first through hole together form the third circuit 51, and the conductive layers in the second through hole together form the fourth circuit 52.

[0062] After each layer is added, circuitry is fabricated on the outermost layer to form the first layer circuitry and the second layer circuitry. The first layer circuitry on several layers of the added structure together forms the first circuitry, and the second layer circuitry on several layers of the added structure together forms the second circuitry.

[0063] Example 5

[0064] Based on the same inventive concept as Embodiment 3, this embodiment takes the process of adding three layers on the surface of the mother plate 1 as an example to specifically illustrate the process of step 5.

[0065] The layered plate 4 includes a first layered structure, a second layered structure, and a third layered structure that are pressed together in sequence.

[0066] After the first add-on structure is laminated onto the motherboard 1, through holes of the first add-on structure and the dielectric layer 3 are simultaneously laser-drilled; the laser-drilled holes are electroplated to fill them, and the circuitry of the first add-on structure is fabricated.

[0067] After the second layer of the additive structure is laminated onto the motherboard 1, the through holes on the first additive structure are superimposed, and the through holes of the second additive structure are laser-cut; the laser-cut holes are electroplated to fill the holes, and the circuit of the second additive structure is fabricated.

[0068] After the third layer of the additive structure is laminated onto the motherboard 1, the through holes on the second additive structure are superimposed, and the through holes of the third additive structure are laser-cut; the laser-cut holes are electroplated to fill the holes, and the circuit of the third additive structure is fabricated.

[0069] The third circuit 51 and the fourth circuit 52 can be obtained by laser-stitched holes. The first circuit and the second circuit can be obtained by layering the circuits.

[0070] Example 6

[0071] This embodiment provides an electronic device, including any of the embedded circuit boards in Embodiments 1 and 2, or including embedded circuit boards prepared by any of the methods in Embodiments 3 to 5.

[0072] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of this disclosure / application, and these improvements and modifications should also be considered within the protection scope of this disclosure / application.

Claims

1. An embedded circuit board, characterized in that, include: Mother plate (1), the mother plate (1) is provided with blind groove (11); Sub-plate (2), the sub-plate (2) is disposed in the blind groove (11); Addition plate (4), the addition plate (4) includes one or more addition structures, the addition plate (4) is disposed on the surface of the mother plate (1) and the daughter plate (2), the addition plate (4) is provided with an interconnection area covering the surface of the daughter plate (2); The interconnection area is provided with a third line (51) and a fourth line (52) perpendicular to the surface of the sub-board (2). The sub-board (2) is provided with a fifth line (53). The third line (51), the fifth line (53) and the fourth line (52) are connected in sequence to form an interconnection line (5). The interconnection line (5) is used to connect the first component (6) and the second component (7) provided on the surface of the layer board (4).

2. The embedded circuit board according to claim 1, characterized in that, The fifth line (53) is connected to the third line (51) through the first pad (21) and to the fourth line (52) through the second pad (22); The first pad (21) and the second pad (22) are disposed on the surface of the sub-board (2) near the layering board (4).

3. The embedded circuit board according to claim 1, characterized in that, The fifth line (53) has a U-shaped structure.

4. The embedded circuit board according to claim 1, characterized in that, The interconnecting line (5) has multiple lines, and the multiple interconnecting lines (5) are arranged in a layered nested manner.

5. The embedded circuit board according to claim 1, characterized in that, A dielectric layer (3) is filled between the sub-plate (2) and the mother plate (1).

6. The embedded circuit board according to claim 5, characterized in that, The medium layer (3) is a resin material layer.

7. The embedded circuit board according to claim 1, characterized in that, The layered structure includes: a prepreg and a copper foil stacked together.

8. The embedded circuit board according to claim 1, characterized in that, The add-in board (4) is further provided with a first chip region and a second chip region located on both sides of the interconnection region respectively; The first chip area is provided with a first line for connecting the first component (6) and the motherboard (1), and the second chip area is provided with a second line for connecting the second component (7) and the motherboard (1).

9. A method for manufacturing an embedded circuit board as described in any one of claims 1-8, characterized in that, include: A blind groove (11) is formed on the mother plate (1); A sub-board (2) with a fifth line (53) is provided in the blind slot (11); One or more layers are added on the surface of the motherboard (1) to form the layered board (4). After each layering, the layered structure is drilled and electroplated to fill the holes to form the third line (51) and the fourth line (52). The third line (51), the fifth line (53) and the fourth line (52) are connected in sequence to form the interconnecting line (5).

10. An electronic device, characterized in that, Includes the embedded circuit board according to any one of claims 1-8, or includes the embedded circuit board prepared by the method of claim 9.

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