Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the following steps: providing a semiconductor substrate comprising an active region and an isolation structure; performing a well region implantation on the semiconductor substrate to form a well region in the active region; generating a gate material layer on the semiconductor substrate; generating a patterned second mask layer on the gate material layer; trimming the patterned second mask layer to expose an edge region of the active region adjacent to the isolation structure; forming a complementary doping region under the mask of the patterned second mask layer; and performing a patterning process on the gate material layer to form a gate electrode, the gate electrode extending in a first direction and covering part of the complementary doping region; wherein the conductive type of the complementary doping region is the same as that of the well region adjacent to the complementary doping region and located below the gate electrode, so that the complementary doping region can improve the double peak effect of the semiconductor device. The semiconductor device is manufactured by using the above manufacturing method.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] In existing shallow trench isolation (STI) technology, on the one hand, the top corners of the shallow trenches are not well rounded; on the other hand, the stress in the shallow trench isolation structure causes the gate oxide layer at the top corners to be thinner than in other areas. This often results in leakage current phenomena caused by devices near the top corners of the shallow trench turning on prematurely under conditions below the threshold voltage (Vt). Figure 1 As shown, the Id-Vg plot exhibits two peaks ( Figure 1 Within the dashed box area, this is the so-called double-hump effect of the device, where Id is the drain current, Vg is the gate voltage, and Vb is the body electrode voltage.

[0003] Meanwhile, thermal activation causes the dopant in the device well to diffuse into the shallow trench isolation structure, reducing the doping concentration in the edge region of the well area near the shallow trench isolation structure. This results in the threshold voltage Vt of the parasitic MOSFET at the top corner of the shallow trench being lower than that of the main MOSFET. The premature turn-on of the parasitic MOSFET causes the device near the top corner of the shallow trench to turn on prematurely under conditions below the threshold voltage, resulting in leakage current. This exacerbates the double-peak effect of the device and affects its electrical performance. Summary of the Invention

[0004] This invention provides a semiconductor device and its fabrication method, which can improve the bimodal effect of the semiconductor device and enhance its electrical performance.

[0005] To achieve the above objectives, this embodiment provides a method for fabricating a semiconductor device. The method includes: providing a semiconductor substrate, the semiconductor substrate including an isolation structure and an active region defined by the isolation structure; performing well region implantation on the semiconductor substrate to form a well region in the active region; forming a gate material layer on the semiconductor substrate, the gate material layer covering the semiconductor substrate; forming a patterned second mask layer on the gate material layer, the patterned second mask layer covering the active region but not covering the isolation structure; trimming the patterned second mask layer to expose the edge region of the active region adjacent to the isolation structure; forming a supplementary doped region on top of the edge region of the active region by an ion implantation process under the masking of the patterned second mask layer; patterning the gate material layer to form a gate electrode, the gate electrode extending in a first direction and covering a portion of the supplementary doped region; and forming source / drain regions in the active region on both sides of the gate electrode in a second direction; wherein the conductivity type of the supplementary doped region is the same as the conductivity type of the well region adjacent to the supplementary doped region and located below the gate electrode.

[0006] Optionally, the method of providing a semiconductor substrate includes: forming a patterned first mask layer on the semiconductor substrate; etching the semiconductor substrate to form shallow trenches under the masking of the patterned first mask layer; and forming an isolation structure within the shallow trenches using an isolation material; wherein the patterned first mask layer and the patterned second mask layer are formed using the same photomask.

[0007] Optionally, the method for trimming the patterned second mask layer includes: using a plasma etching process to remove part of the patterned second mask layer to enlarge the opening of the patterned second mask layer.

[0008] Optionally, the material of the patterned second mask layer includes photoresist, and the plasma used in the plasma etching process includes oxygen plasma.

[0009] Optionally, the supplementary doped region is located near the edge of the isolation structure in the well region.

[0010] Optionally, the conductivity type of the supplementary doped region is opposite to that of the source / drain region.

[0011] Optionally, the semiconductor device is an NMOS device, and the dopant in the supplementary doping region includes boron or indium; or, the semiconductor device is a PMOS device, and the dopant in the supplementary doping region includes phosphorus.

[0012] Optionally, the thickness of the gate material layer is greater than or equal to 80 nm and less than or equal to 200 nm, and the implantation energy used in the ion implantation process is greater than or equal to 10 keV and less than or equal to 180 keV.

[0013] Optionally, before forming a gate material layer on the semiconductor substrate, a gate oxide layer is formed on the semiconductor substrate, the gate oxide layer covering the active region.

[0014] The present invention also provides a semiconductor device. The semiconductor device is manufactured using the semiconductor device fabrication method described above.

[0015] In the semiconductor device and its fabrication method provided by this invention, after forming a gate material layer on a semiconductor substrate, a supplementary doped region is formed at the top of the edge region of the active region near the isolation structure using an ion implantation process. Then, the gate material layer is patterned to form a gate electrode. The gate electrode extends in a first direction and partially covers the supplementary doped region. The conductivity type of the supplementary doped region is the same as that of the well region adjacent to the supplementary doped region and located below the gate electrode. In this way, the edge of the channel region below the gate electrode near the top corner of the isolation structure can be supplemented with well region doping concentration through the supplementary doped region. This increases the threshold voltage of the parasitic transistor near the top corner of the isolation structure, suppressing premature turn-on of the parasitic transistor, thereby reducing leakage current in the semiconductor device, improving the bimodal effect, and enhancing the electrical conductivity of the semiconductor device. Electrical performance; After forming the gate material layer, an additional doped region is formed on top of the edge region of the active region adjacent to the isolation structure through ion implantation. In this way, the ion implantation process can also adjust the work function of the gate electrode region, which is beneficial to further improve the bimodal effect and improve the electrical performance of the semiconductor device; After forming the gate material layer, a patterned second mask layer is generated on the gate material layer. The patterned second mask layer covers the active region but does not cover the isolation structure. Then, the patterned second mask layer is trimmed to expose the edge region of the active region adjacent to the isolation structure. Then, the additional doped region is formed under the mask of the patterned second mask layer. In this way, the patterned second mask layer can be made using a photomask that defines the active region. That is, forming the additional doped region does not require the introduction of a new photomask, which helps to save costs. Attached Figure Description

[0016] Figure 1 For existing MOS devices I d -V g Line graph.

[0017] Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0018] Figure 3This is a cross-sectional view of a patterned second mask layer formed on a gate material layer according to an embodiment of the present invention.

[0019] Figure 4 This is a cross-sectional view of the patterned second mask layer after modification in one embodiment of the present invention.

[0020] Figure 5 This is a top view of the patterned second mask layer after modification in one embodiment of the present invention.

[0021] Figure 6 This is a cross-sectional view of an embodiment of the present invention after a supplementary doped region is formed in the active region.

[0022] Figure 7 This is a top view of an embodiment of the present invention after a supplementary doped region has been formed in the active region.

[0023] Figure 8 This is a cross-sectional view after removing the patterned second mask layer in one embodiment of the present invention.

[0024] Figure 9 This is a cross-sectional view of a patterned third mask layer formed on a gate material layer according to an embodiment of the present invention.

[0025] Figure 10 This is a cross-sectional view of a semiconductor substrate after a gate electrode has been formed in one embodiment of the present invention.

[0026] Figure 11 This is a cross-sectional view of the active region after the source / drain region is formed in an embodiment of the present invention.

[0027] Figure 12 This is a planar schematic diagram of a semiconductor device provided in an embodiment of the present invention.

[0028] Explanation of reference numerals in the attached figures: 100-Semiconductor substrate; 101-Active region; 102-Isolation structure; 102a-Shallow trench; 102b-Isolation material; 103-Gate oxide layer; 104-Gate material layer; 105-Patterned second mask layer; 106-Supplemental doped region; 107-Patterned third mask layer; 108-Gate electrode; 109-Source / drain region; 110-Channel region. Detailed Implementation

[0029] The semiconductor device and its fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0030] Figure 2This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, the method for fabricating a semiconductor device provided in this embodiment includes:

[0031] Step S1, providing a semiconductor substrate, the semiconductor substrate including an isolation structure and an active region defined by the isolation structure;

[0032] Step S2: Well region implantation is performed on the semiconductor substrate to form a well region in the active region;

[0033] Step S3: A gate material layer is formed on the semiconductor substrate, and the gate material layer covers the semiconductor substrate;

[0034] Step S4: A patterned second mask layer is generated on the gate material layer, the patterned second mask layer covering the active region but not covering the isolation structure;

[0035] Step S5: Trim the patterned second mask layer to expose the edge region of the active region adjacent to the isolation structure;

[0036] Step S6: Under the cover of the patterned second mask layer, a supplementary doped region is formed on top of the edge region of the active region by ion implantation.

[0037] Step S7: The gate material layer is patterned to form a gate electrode, which extends in the first direction and covers part of the supplementary doped region.

[0038] Step S8: Source and drain regions are formed in the active regions on both sides of the gate electrode in the second direction; wherein the conductivity type of the supplementary doped region is the same as that of the active region adjacent to the supplementary doped region and located below the gate electrode.

[0039] Figures 3 to 12 This is a schematic diagram illustrating the fabrication process of a semiconductor device according to an embodiment of the present invention. It should be noted that... Figure 5 , Figure 7 and Figure 12 It is a top view, and Figure 5 and Figure 7 Gate material layer not shown. Figure 3 , Figure 4 , Figure 6 and Figure 8 This is a sectional view of the location indicated by line AB in the top view (i.e., a sectional view in the direction of the channel width). Figure 9 , Figure 10 and Figure 11 This is a sectional view (i.e., a sectional view along the length of the channel) at the location indicated by line CD in the top view. The following is combined with... Figure 2 , Figures 3 to 12 The method for fabricating the semiconductor device provided in this application is described.

[0040] like Figure 3 As shown, the semiconductor substrate 100 provided in step S1 includes an isolation structure 102 and an active region 101 defined by the isolation structure 102.

[0041] For example, the semiconductor substrate 100 can be a silicon substrate, a germanium substrate, a silicon-germanium substrate, silicon-on-insulator (SOI) or germanium-on-insulator (GOI), etc. The semiconductor substrate 100 can also be implanted with certain dopant ions to change the electrical parameters according to design requirements.

[0042] In this embodiment, the isolation structure 102 is a shallow trench isolation (STI) structure. In other embodiments, the isolation structure 102 can also be a silicon local oxide (LOCOS) isolation structure.

[0043] For example, a method of forming an isolation structure 102 in a semiconductor substrate 100 may include: referring to Figure 3 As shown, a patterned first mask layer (not shown) is formed on a semiconductor substrate 100, and the semiconductor substrate 100 is etched under the mask of the patterned first mask layer to form a shallow trench 102a; and an isolation material 102b is formed in the shallow trench 102a to form an isolation structure 102. The isolation material 102b includes, but is not limited to, silicon oxide.

[0044] refer to Figure 3 As shown, step S2 is performed to implant a well region into the semiconductor substrate 100, forming a well region 101a in the active region 101. The well region 101a can extend from the top surface of the active region 101 toward the bottom surface of the semiconductor substrate 100. The well region 101a can be partially located in the active region 101 and intersect with the isolation structure 102, but is not limited thereto.

[0045] For example, when the semiconductor device is an NMOS device, the well region 101a is P-type; when the semiconductor device is a PMOS device, the well region 101a is N-type.

[0046] Continue to refer to Figure 3 Step S3 is executed to generate a gate material layer 104 on the semiconductor substrate 100, the gate material layer 104 covering the semiconductor substrate 100.

[0047] For example, the material of the gate material layer 104 includes, but is not limited to, polysilicon.

[0048] In this embodiment, as Figure 3As shown, before forming the gate material layer 104 on the semiconductor substrate 100, a gate oxide layer 103 is formed on the semiconductor substrate 100, and the gate oxide layer 103 covers the active region 101. Exemplarily, the material of the gate oxide layer 103 can be silicon oxide. The gate oxide layer 103 can be formed by a chemical vapor deposition process or a thermal oxidation process, etc. The gate material layer 104 covers the gate oxide layer 103.

[0049] In this embodiment, the gate oxide layer 103 and the isolation material 102b in the isolation structure 102 are made of the same material, so the boundary line between the gate oxide layer 103 and the isolation material 102b is not shown in the figure.

[0050] Execute step S4 and continue referring to... Figure 3 As shown, a patterned second mask layer 105 is generated on the gate material layer 104. The patterned second mask layer 105 covers the active region 101 but does not cover the isolation structure 102.

[0051] For example, the patterned second mask layer 105 can be formed using a photomask that defines the active region 101. In this way, the fabrication of the patterned second mask layer 105, or the formation of the supplementary doped region, does not require the introduction of a new photomask, which helps to save costs.

[0052] Specifically, the patterned first mask layer is used to define the formation location of the isolation structure, that is, to define the formation location of the active region 101. In this embodiment, the patterned first mask layer and the patterned second mask layer 105 are formed using the same photomask. For example, both the patterned first mask layer and the patterned second mask layer 105 are photoresist layers, and both are formed by exposure using the same photomask.

[0053] Perform step S5, such as Figure 4 and Figure 5 As shown, the patterned second mask layer 105 is trimmed to expose the edge region of the active region 101 adjacent to the isolation structure 102.

[0054] For example, a method for trimming the patterned second mask layer 105 may include: using a plasma etching process to remove part of the patterned second mask layer 105, thereby enlarging the opening of the patterned second mask layer 105 to expose the edge region of the active region 101 adjacent to the isolation structure 102.

[0055] In this embodiment, the patterned second mask layer 105 is a photoresist layer, and the plasma used in the plasma etching process includes, but is not limited to, oxygen plasma. In other embodiments, the plasma used in the plasma etching process can be adjusted according to the material of the patterned second mask layer 105.

[0056] For example, such as Figure 4 As shown, by controlling the etching time of the plasma etching process, the width of the window widening in the patterned second mask layer 105 can be precisely controlled, that is, the width W1 of the active region 101 exposed at the edge of the isolation structure 102 can be controlled; the width of the window widening in the patterned second mask layer 105 can be adjusted according to the degree of the bimodal effect of the device to control the size of the supplementary doping region.

[0057] like Figure 6 and Figure 7 As shown, in step S6, under the masking of the patterned second mask layer 105, a supplementary doped region 106 is formed on top of the edge region of the active region 101 by an ion implantation process.

[0058] The conductivity type of the supplementary doped region 106 is the same as that of the well region 101a located adjacent to the supplementary doped region 106 and below the gate electrode.

[0059] For example, refer to Figure 6 As shown, the supplementary doped region 106 is located at the edge of the well region 101a near the isolation structure 102. The conductivity type of the supplementary doped region 106 is the same as that of the well region 101a, meaning that the type of ions implanted in the supplementary doped region 106 is the same as that implanted in the well region 101a. For example, the semiconductor device is an NMOS device, the well region 101a is a P-type well region, and the dopant in the supplementary doped region 106 includes P-type dopant such as boron or indium; or, the semiconductor device is a PMOS device, the well region 101a is an N-type well region, and the dopant in the supplementary doped region 106 includes N-type dopant such as phosphorus.

[0060] In this embodiment, a supplementary doped region 106 is formed on the surface layer of the edge region of the active region 101, with reference to... Figure 12 As shown, the ion concentration near the edge of the isolation structure 102 in the channel region 110 below the gate electrode 108 can be compensated by the dopant in the doped region 106, and the threshold voltage of the parasitic tube near the top corner of the isolation structure 102 can be increased.

[0061] For example, the thickness of the gate material layer 104 can be greater than or equal to 80 nm and less than or equal to 200 nm, such as 175 nm, and the implantation energy used in the ion implantation process can be greater than or equal to 10 keV and less than or equal to 180 keV, such as 50 keV. This ensures that the supplementary doped region 106 is located on the surface of the active region 101 and the implantation depth is not too deep. In other embodiments, the implantation energy used in the ion implantation process to form the supplementary doped region 106 can be adjusted according to the thickness of the gate material layer 104.

[0062] It should be noted that during the formation of the supplementary doped region 106, the work function of the gate material layer 104 above the supplementary doped region 106 can also be adjusted. This part of the gate material layer 104 will be partially retained as part of the gate electrode in the future. That is, the ion implantation process can also adjust the work function of the gate electrode located above the supplementary doped region 106, which is beneficial to further improve the bimodal effect and improve the electrical performance of the semiconductor device.

[0063] like Figure 8 As shown, after forming the supplementary doped region 106, the patterned second mask layer 105 is removed.

[0064] like Figure 9 , Figure 10 and Figure 12 As shown, in step S7, the gate material layer 104 is patterned to form a gate electrode 108, which extends in the first direction X and covers a portion of the supplementary doped region 106.

[0065] For example, step S7 may specifically include: Figure 9 As shown, a patterned third mask layer 107 is formed on the gate material layer 104; as Figure 9 and Figure 10 As shown, the gate material layer 104 is etched to form the gate electrode 108 using the patterned third mask layer 107 as a mask; then the patterned third mask layer 107 is removed.

[0066] refer to Figure 12 As shown, the active region covered by the gate electrode 108 is the channel region 110 (i.e. Figure 12 (The area shown in the dashed box in the image) The gate electrode 108 covers the supplementary doped regions 106 at both ends of the first direction X of the channel region 110.

[0067] refer to Figure 11 and Figure 12 As shown, step S8 is performed to form source / drain regions 109 in the active regions on both sides of the gate electrode 108 in the second direction Y. The source / drain regions 109 can be formed by a self-aligned ion implantation process. The source / drain regions 109 can be self-aligned with the gate electrode 108.

[0068] In this embodiment, the conductivity type of the supplementary doped region 106 is opposite to that of the source / drain region 109.

[0069] It should be noted that the reference Figure 10 , Figure 11 and Figure 12As shown, the source / drain regions 109 will occupy the formation positions of the supplementary doped regions 106 located on both sides of the gate electrode 108 in the second direction Y. Thus, after the source / drain regions 109 are formed, the supplementary doped regions 106 on both sides of the gate electrode 108 in the second direction Y will be injected with source / drain compensation doping. In this way, the formation of the supplementary doped regions 106 will not have an adverse effect on the electrical parameters of the semiconductor device.

[0070] The present invention also provides a semiconductor device, which can be manufactured using the semiconductor device manufacturing method described above.

[0071] refer to Figure 11 and Figure 12 As shown, the semiconductor device provided in this application includes a semiconductor substrate 100 and a gate electrode 108 located on the semiconductor substrate 100. The semiconductor substrate 100 includes an isolation structure 102 and an active region 101 defined by the isolation structure 102, wherein the active region 101 has a well region 101a. The gate electrode 108 extends along a first direction X and spans across the active region 101. Supplementary doped regions 106 are provided at both ends of the active region 101 covered by the gate electrode 108 in the first direction X. The conductivity type of the supplementary doped regions 106 is the same as that of the well region 101a adjacent to the supplementary doped regions 106 and located below the gate electrode 108. Active drain regions 109 are formed in the active regions on both sides of the gate electrode 108 in the second direction Y.

[0072] In the semiconductor device and its fabrication method provided by the present invention, after forming a gate material layer 104 on a semiconductor substrate 100, a supplementary doped region 106 is formed on the top of the edge region of the active region 101 near the isolation structure 102 by an ion implantation process. Then, the gate material layer 104 is patterned to form a gate electrode 108. The gate electrode 108 extends in the first direction X and partially covers the supplementary doped region 106. The conductivity type of the supplementary doped region 106 is the same as that of the well region adjacent to the supplementary doped region 106 and located below the gate electrode 108. Thus, the edge of the channel region below the gate electrode 108 near the top corner of the isolation structure 102 can be supplemented with well region doping concentration through the supplementary doped region 106. This increases the threshold voltage of the parasitic transistor near the top corner of the isolation structure 102 to suppress premature turn-on of the parasitic transistor, thereby reducing leakage current in the semiconductor device, improving the double-peak effect, and enhancing the electrical performance of the semiconductor device. Performance: After forming the gate material layer 104, an additional doped region 106 is formed on top of the edge region of the active region 101 adjacent to the isolation structure 102 by an ion implantation process. In this way, the ion implantation process can also adjust the work function of the gate electrode part region, which is beneficial to further improve the bimodal effect and improve the electrical performance of the semiconductor device. After forming the gate material layer, a patterned second mask layer 105 is generated on the gate material layer 104. The patterned second mask layer 105 covers the active region 101 but does not cover the isolation structure 102. Then, the patterned second mask layer 105 is trimmed to expose the edge region of the active region 101 adjacent to the isolation structure 102. Then, the additional doped region 106 is formed under the mask of the patterned second mask layer 105. In this way, the patterned second mask layer 105 can be made using the photomask that defines the active region 101. That is, the formation of the additional doped region 106 does not require the introduction of a new photomask, which helps to save costs.

[0073] In the embodiments of this application, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0074] In the embodiments of this application, "upper", "lower", "left" and "right" are not limited to the orientation of the components in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0075] In the embodiments of this application, unless the context otherwise requires, the term "comprising" is interpreted as open and encompassing, i.e., "including, but not limited to," throughout the specification and claims. In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplarily," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0076] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including an isolation structure and an active region defined by the isolation structure; Well implantation is performed on the semiconductor substrate to form a well region in the active region; A gate material layer is formed on the semiconductor substrate, and the gate material layer covers the semiconductor substrate; A patterned second mask layer is formed on the gate material layer, the patterned second mask layer covering the active region but not covering the isolation structure; The patterned second mask layer is trimmed to expose the edge region of the active region adjacent to the isolation structure; Under the masking of the patterned second mask layer, an additional doped region is formed on top of the edge region of the active region by ion implantation, while the work function of the gate material layer above the additional doped region is adjusted. The gate material layer is patterned to form a gate electrode, which extends in a first direction and covers a portion of the supplementary doped region; as well as Source and drain regions are formed in the active regions on both sides of the gate electrode in the second direction; The conductivity type of the supplementary doped region is the same as that of the well region adjacent to the supplementary doped region and located below the gate electrode.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Methods for providing semiconductor substrates include: A patterned first mask layer is formed on a semiconductor substrate, and shallow trenches are formed by etching the semiconductor substrate under the masking of the patterned first mask layer; and An insulating material is generated within the shallow trench to form an insulating structure; The patterned first mask layer and the patterned second mask layer are formed using the same photomask.

3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The method for trimming the patterned second mask layer includes: removing a portion of the patterned second mask layer using a plasma etching process to enlarge the openings of the patterned second mask layer.

4. The method for fabricating a semiconductor device as described in claim 3, characterized in that, The material of the patterned second mask layer includes photoresist, and the plasma etching process uses oxygen plasma.

5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The supplemental doped region is located at the edge of the well region near the isolation structure.

6. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The conductivity type of the supplementary doped region is opposite to that of the source / drain region.

7. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The semiconductor device is an NMOS device, and the dopant in the supplementary doping region includes boron or indium; or, the semiconductor device is a PMOS device, and the dopant in the supplementary doping region includes phosphorus.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The thickness of the gate material layer is greater than or equal to 80 nm and less than or equal to 200 nm, and the implantation energy used in the ion implantation process is greater than or equal to 10 keV and less than or equal to 180 keV.

9. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Before forming a gate material layer on the semiconductor substrate, a gate oxide layer is formed on the semiconductor substrate, the gate oxide layer covering the active region.

10. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method of manufacturing a semiconductor device as described in any one of claims 1 to 9.

Images