Semiconductor device and method of manufacturing the same

Abstract

The present application provides a semiconductor device and a method for manufacturing the same. In the semiconductor device, an isolation structure in a substrate includes a first isolation structure and a plurality of second isolation structures connected to the first isolation structure, the plurality of second isolation structures being on the same side of the first isolation structure and extending into the substrate in a first direction; a gate structure is above the substrate on a side of the second isolation structure away from the first isolation structure and extends in the first direction to cover the plurality of second isolation structures and part of the first isolation structure; a source region is in the substrate on a side of the gate structure away from the isolation structure; and a drain region is in the substrate on a side of the isolation structure away from the gate structure. This reduces the edge electric field of the isolation structure and improves the hot carrier injection failure problem of the semiconductor device. The method for manufacturing the semiconductor device provided by the present application can be used to manufacture the semiconductor device described above.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] At present, laterally-diffused metal-oxide semiconductor (LDMOS) has an important position in integrated circuit design and manufacturing, and LDMOS devices are often used in high-voltage power integrated circuits to meet the requirements of high-voltage resistance and power control.

[0003] Figure 1 It is a structural schematic diagram of an LDMOS device. Figure 2 It is Figure 1 It is a layout schematic diagram of a substrate interface of the LDMOS device. As shown in Figure 1 and Figure 2 In the LDMOS device, an edge flush isolation structure 20 is formed in a substrate 10, a gate structure 30 is located on the substrate 10, the gate structure 30 covers part of the substrate 10 and extends to cover part of the isolation structure 20, a drain region 13 is formed in the substrate 10 away from the isolation structure 20 side of the gate structure 30, and a source region 12 is formed in the substrate 10 away from the isolation structure 20 side of the gate structure 30. However, the above-mentioned LDMOS device is prone to hot carrier injection (HCI) failure, which affects the reliability of the LDMOS device. Therefore, how to improve the problem of hot carrier injection failure of the semiconductor device needs to be solved urgently. SUMMARY

[0004] One of the purposes of the present application is to provide a semiconductor device and a manufacturing method thereof, which can improve the problem of hot carrier injection failure of the semiconductor device and improve the reliability of the semiconductor device.

[0005] In order to achieve the above-mentioned purpose, the present application provides a semiconductor device in one aspect. The semiconductor device comprises: a substrate; an isolation structure located in the substrate, comprising a first isolation structure and a plurality of second isolation structures connected with the first isolation structure, the plurality of second isolation structures being located on the same side of the first isolation structure and extending into the substrate in a first direction; a gate structure located above the substrate on the side of the second isolation structure away from the first isolation structure, and extending to cover the plurality of second isolation structures and part of the first isolation structure in the first direction; a source region located in the substrate on the side of the gate structure away from the isolation structure; and a drain region located in the substrate on the side of the isolation structure away from the gate structure.

[0006] Optionally, the gate structure comprises a first gate and a plurality of second gates connected to the first gate; the first gate is located above the substrate on the side of the second isolation structure away from the first isolation structure, and extends in the first direction to cover a plurality of the second isolation structures; the second gates extend outward from the first gate in the first direction towards the edge of the first isolation structure; a plurality of the second isolation structures and a plurality of the second gates are arranged alternately in the second direction, and the first direction and the second direction intersect.

[0007] Optionally, a groove is formed in the substrate, the groove comprises a main groove and a plurality of extension grooves in communication with the main groove, a plurality of the extension grooves are located on the same side of the main groove and extend into the substrate in the first direction; the first isolation structure fills the main groove, and a plurality of the second isolation structures respectively fill a plurality of the extension grooves.

[0008] Optionally, the second isolation structure fills the part of the corresponding extension groove close to the main groove; the gate structure comprises a first gate and a plurality of third gates connected to the first gate; the first gate is located above the substrate on the side of the second isolation structure away from the first isolation structure, and extends in the first direction to cover a plurality of the second isolation structures; a plurality of the third gates respectively fill the part of the corresponding extension groove away from the main groove.

[0009] Optionally, a gate oxide layer is arranged between the gate structure and the substrate, and the gate oxide layer is also located between the gate structure and the isolation structure.

[0010] Optionally, a drift region and a body region are formed in the substrate; the isolation structure and the drain region are arranged on the drift region; the source region is arranged on the body region; the gate structure covers part of the drift region and part of the body region.

[0011] Optionally, the cross section of the second isolation structure parallel to the top surface of the substrate is rectangular, triangular or a pattern comprising an arc line.

[0012] Another aspect of the present application provides a method for manufacturing a semiconductor device. The method includes: providing a substrate; forming an isolation structure in the substrate, the isolation structure including a first isolation structure and a plurality of second isolation structures connected to the first isolation structure, the plurality of second isolation structures being on the same side of the first isolation structure and extending into the substrate in a first direction; forming a gate structure on the substrate, the gate structure being above the substrate on a side of the second isolation structure away from the first isolation structure and extending in the first direction to cover the plurality of second isolation structures and part of the first isolation structure; and forming a source region in the substrate on a side of the gate structure away from the isolation structure and forming a drain region in the substrate on a side of the isolation structure away from the gate structure.

[0013] Optionally, the method for forming the isolation structure in the substrate includes: forming a trench in the substrate, the trench including a main trench and a plurality of extension trenches in communication with the main trench, the plurality of extension trenches being on the same side of the main trench and extending into the substrate in the first direction; and growing an isolation material in the trench to form the isolation structure, wherein the isolation material in the main trench is the first isolation structure and the isolation material in the plurality of extension trenches is the plurality of second isolation structures.

[0014] Optionally, after the trench is formed in the substrate and before the isolation material is grown in the trench, a sacrificial layer is filled in the end of the extension trench away from the main trench; and after the isolation material is grown in the trench, the sacrificial layer is removed and a gate structure is formed on the substrate, the gate structure being partially filled in the end of the extension trench away from the main trench.

[0015] In the semiconductor device and the method for manufacturing the semiconductor device provided by the present application, the isolation structure in the substrate includes a first isolation structure and a plurality of second isolation structures connected to the first isolation structure, the plurality of second isolation structures being on the same side of the first isolation structure and extending into the substrate in a first direction, and a gate structure being above the substrate on a side of the second isolation structure away from the first isolation structure and extending in the first direction to cover the plurality of second isolation structures and part of the first isolation structure. Thus, by optimizing the isolation structure, the edge electric field of the isolation structure under the gate structure can be reduced, the electric field distribution of the device is more uniform, and the problem of hot carrier injection failure (HCI fail) of the semiconductor device can be improved, and the reliability of the semiconductor device is improved.

[0016] Further, the gate structure includes a first gate and a plurality of second gates connected to the first gate; the second gates extend outward from the first gate along the first direction and close to the edge of the first isolation structure; the plurality of second gates and the plurality of second isolation structures are arranged alternately along the second direction, so that the effect of improving the hot carrier injection failure of the semiconductor device is better, that is, the probability of the hot carrier injection pass (HCI pass) of the semiconductor device is higher.

[0017] Further, the second isolation structure fills the part of the corresponding extension groove close to the main groove; the gate structure includes a plurality of third gates connected to the first gate, and the plurality of third gates respectively fill the part of the corresponding extension groove away from the main groove, so that the same trench can be used to improve the problem of the device hot carrier injection failure, and the channel width of the device can be increased, so that the semiconductor device has sufficient driving capability, and the reliability of the device is further improved. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 It is a structure schematic diagram of an LDMOS device.

[0019] Figure 2 It is a structure schematic diagram of an LDMOS device. Figure 1 It is a layout schematic diagram of the substrate interface of the LDMOS device shown in the figure.

[0020] Figure 3 It is a structure schematic diagram of a semiconductor device provided by an embodiment of the present application.

[0021] Figure 4 It is a layout schematic diagram of the substrate interface of a semiconductor device provided by an embodiment of the present application.

[0022] Figure 5 It is a top view structure schematic diagram of a semiconductor device provided by an embodiment of the present application.

[0023] Figure 6 It is a top view structure schematic diagram of a semiconductor device provided by another embodiment of the present application.

[0024] Figure 7 It is a layout schematic diagram of the substrate interface of a semiconductor device provided by another embodiment of the present application.

[0025] Figure 8 It is a sectional view schematic diagram of the position shown along the AB line. Figure 7

[0026] Figure 9 It is a flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present application.

[0027] Figure 10 It is a structure schematic diagram of a semiconductor device provided by an embodiment of the present application after forming a trench in a substrate. ​

[0028] Figure 11 Fig. 6 is a schematic view of a structure after forming a gate material layer on a substrate in an embodiment of the present application.

[0029] Reference signs: 10-substrate; 11-trench; 111-main trench; 112-extended trench; 12-source region; 13-drain region; 20-isolation structure; 21-first isolation structure; 22-second isolation structure; 30-gate structure; 31-first gate; 32-second gate; 33-third gate; 34-gate oxide layer; 30a-gate material layer; 34a-oxide material layer. DETAILED DESCRIPTION

[0030] Reference Figure 2 As shown in the figure, research found that the existing LDMOS device in Figure 2 The electric field at the position shown by the dotted line is too large, which is easy to cause device hot carrier injection failure.

[0031] Therefore, the present application sets the isolation structure in the substrate to include a first isolation structure and a plurality of second isolation structures connected with the first isolation structure, the plurality of second isolation structures are located on the same side of the first isolation structure and extend into the substrate along the first direction, the gate structure is located above the substrate on the side of the second isolation structure away from the first isolation structure, and the gate structure extends in the first direction to cover the plurality of second isolation structures and part of the first isolation structure. In this way, the optimization of the isolation structure can reduce the edge electric field of the isolation structure located below the gate structure, so that the electric field distribution of the device is more uniform, thereby improving the problem of hot carrier injection failure (HCI fail) of the semiconductor device and improving the reliability of the semiconductor device.

[0032] The semiconductor device and the manufacturing method thereof proposed by the present application will be further described in detail below in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present application will be more apparent. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly assisting the description of the embodiments of the present application.

[0033] As used in the present application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. The term "or" is generally employed in its sense of "and / or" unless the content clearly dictates otherwise. The term "at least one" is generally employed in its sense of "one or more of" unless the content clearly dictates otherwise. The term "plurality" is generally employed in its sense of "two or more" unless the content clearly dictates otherwise. In addition, the terms "first," "second," "third," etc. are used only to describe a particular object and do not imply or suggest relative importance or an implied indication of the number of the technical features indicated. Thus, features qualified with "first," "second," "third," etc. can expressly or implicitly include one or at least two of the features unless the context clearly dictates otherwise.

[0034] Figure 3 A structure schematic diagram of a semiconductor device provided by an embodiment of the present application. Figure 4 A layout schematic diagram of a substrate interface of a semiconductor device provided by an embodiment of the present application. Referring to Figure 3 and Figure 4 As shown in the drawings, the semiconductor device provided by the embodiment includes a substrate 10, an isolation structure 20, a gate structure 30, a source region 12 and a drain region 13. The isolation structure 20 is located in the substrate 10 and includes a first isolation structure 21 and a plurality of second isolation structures 22 connected to the first isolation structure 21, the plurality of second isolation structures 22 being located on the same side of the first isolation structure 21 and extending into the substrate 10 along a first direction X. The gate structure 30 is located above the substrate on the side of the second isolation structure 22 away from the first isolation structure 21 and extends in the first direction X to cover the plurality of second isolation structures 22 and part of the first isolation structure 21. The source region 12 is located in the substrate on the side of the gate structure 30 away from the isolation structure 20. The drain region 13 is located in the substrate on the side of the isolation structure 20 away from the gate structure 30.

[0035] Specifically, the substrate 10 can be any semiconductor substrate. The material of the substrate 10 can include silicon, and the material of the substrate 10 can also include a wide bandgap material, which can include silicon carbide (SiC), gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium oxide (Ga2O3), diamond, etc. The substrate 10 can also be silicon-on-insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon-on-silicon germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or can also be double side polished wafers (DSP), etc.

[0036] Referring to Figure 4As shown, a groove 11 may be formed in the substrate 10. The groove 11 may include a main groove 111 and a plurality of extension grooves 112 communicating with the main groove 111. The plurality of extension grooves 112 are located on the same side of the main groove 111 and extend into the substrate 10 in a first direction X, that is, the plurality of extension grooves 112 protrude from the same side edge of the main groove 111 toward the substrate 10.

[0037] like Figure 4 As shown, the first isolation structure 21 fills the main groove 111, and the multiple second isolation structures 22 respectively fill the multiple extension grooves 112. The multiple second isolation structures 22 protrude from the same side edge of the first isolation structure 21 toward the base 10.

[0038] The first isolation structure 21 and the second isolation structure 22 include the same isolation material, such as silicon oxide. In this embodiment, the first isolation structure 21 and the second isolation structure 22 are formed through the same process step, and they are an integral structure.

[0039] refer to Figure 4 As shown, in this embodiment, the cross section of the second isolation structure 22 parallel to the top surface of the base 10 (i.e., the cross section parallel to the XY plane) is rectangular. In other embodiments, the cross section of the second isolation structure 22 parallel to the top surface of the base 10 can also be triangular or include arcs, etc., and the arcs include, for example, convex peaks.

[0040] Multiple second isolation structures 22 can be spaced apart or arranged consecutively in the second direction Y. (See reference) Figure 4 As shown, in this embodiment, multiple second isolation structures 22 can be spaced apart in the second direction Y, and the contour of one side of the isolation structure 20 where the second isolation structure 22 is located can be rectangular wavy. In another embodiment, the cross-section of the multiple second isolation structures 22 parallel to the top surface of the base 10 is triangular, the multiple second isolation structures 22 are continuously arranged in the second direction Y, and the outer contours of the multiple second isolation structures 22 are connected in a triangular sawtooth shape. In another embodiment, the cross-section of the second isolation structure 22 parallel to the top surface of the base 10 is convex peak-shaped, the multiple second isolation structures 22 can be continuously arranged in the second direction Y, and the contour of one side of the isolation structure 20 where the second isolation structure 22 is located can be sinusoidal wave-shaped, but is not limited to this.

[0041] refer to Figure 3 and Figure 4 As shown, the gate structure 30 is located above the substrate 10 on the side of the second isolation structure 22 away from the first isolation structure 21, and extends to cover the plurality of second isolation structures 22 and a portion of the first isolation structure 21. The gate structure 30 covers the plurality of second isolation structures 22 and at least also covers the portion of the first isolation structure 21 adjacent to the substrate 10.

[0042] Figure 5This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention. In this embodiment, as shown... Figure 3 and Figure 5 As shown, the gate structure 30 includes a first gate 31 and a plurality of second gates 32 connected to the first gate 31. The first gate 31 is located above the substrate on the side of the second isolation structure 22 away from the first isolation structure 21, and extends in the first direction X, covering the plurality of second isolation structures 22. The second gates 32 extend outward from the edge of the first gate 31 near the first isolation structure 21 along the first direction X. The plurality of second isolation structures 22 and the plurality of second gates 32 are alternately arranged in the second direction Y, and the first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular. The plurality of second gates 32 and the plurality of second isolation structures 22 intersect in the second direction Y to form an interdigitated structure, so that the electric field distribution of the device is more uniform and the effect of improving the hot carrier injection failure of the semiconductor device is better.

[0043] It should be noted that the reference Figure 4 and Figure 5 As shown, multiple extension slots 112, or multiple second isolation structures 22, define multiple protruding active regions, and multiple second gates 32 can correspond to the positions of the protruding active regions between the multiple second isolation structures 22. The extension of the second gate 32, the second isolation structure 22, or the extension slot 112 in the first direction X can be understood as extending in the positive or negative direction of X.

[0044] refer to Figure 5 As shown, in this embodiment, the boundary of the first gate 31 near the isolation structure 20 extends above the first isolation structure 21. The first gate 31 covers multiple second isolation structures 22 and further extends in the first direction X to cover the edge portion of the first isolation structure 21 near the second isolation structure 22. In other words, the boundary of the first gate 31 extends beyond the boundary of the protruding active region located between the second isolation structures 22. This helps to ensure that the gate structure 30 continuously covers the active region below it in the channel width direction (i.e., the second direction Y), which helps to ensure the control capability of the gate structure 30 and improve the reliability of the device.

[0045] Figure 6 This is a top view of a semiconductor device provided according to another embodiment of the present invention. In another embodiment of this application, as shown... Figure 6 As shown, the gate structure 30 may not have a protruding gate, and the boundary of the gate structure 30 near the isolation structure 20 extends above the first isolation structure 21 in the first direction X, that is, with... Figure 5 Compared to the gate structure, the gate structure 30 does not have a protruding second gate 32 but only has a first gate 31.

[0046] Figure 7This is a schematic diagram of the layout of the substrate interface of a semiconductor device provided in another embodiment of the present invention. Figure 8 For along Figure 7 A cross-sectional view of the location indicated by line AB.

[0047] refer to Figure 7 and Figure 8 As shown, the first isolation structure 21 fills the main trench 111, and the second isolation structure 22 fills the portion of the corresponding extension trench 112 near the main trench 111 but does not fill the extension trench 112 completely. The gate structure 30 may also include a plurality of third gates 33 connected to the first gate 31. The plurality of third gates 33 extend along the third direction Z and respectively fill the portion of the corresponding extension trench 112 away from the main trench 111. In this way, the use of the same trench 11 can improve the problem of hot carrier injection failure of the device. At the same time, the channel width of the gate structure 30 can extend with the sidewall of the extension trench 112, that is, increase the channel width of the device, so that the semiconductor device has sufficient driving capability and further improves the reliability of the device.

[0048] When the gate structure 30 is partially filled in the extension trench 112, the boundary of the gate structure 30 away from the first isolation structure 21 can be flush with the boundary of the extension trench 112 away from the first isolation structure 21; or, the boundary of the gate structure 30 away from the first isolation structure 21 can extend outward beyond the boundary of the extension trench 112 away from the first isolation structure 21, that is, part of the gate structure 30 is located above the substrate on the side of the extension trench 112 away from the main trench 111.

[0049] For example, the materials of the first gate 31, the second gate 32 and the third gate 33 are including but not limited to this polysilicon.

[0050] refer to Figure 3 and Figure 8 As shown, a gate oxide layer 34 is disposed between the gate structure 30 and the substrate 10, and the gate oxide layer 34 also isolates the gate structure 30 and the isolation structure 20. The material of the gate oxide layer 34 includes, but is not limited to, silicon oxide.

[0051] Continue to refer to Figure 3 As shown, source region 12 is located in the substrate on the side of gate structure 30 away from isolation structure 20; drain region 13 is located in the substrate on the side of isolation structure 20 away from gate structure 30. Source region 12 and drain region 13 can have the same conductivity type, i.e., both can be N-type or both can be P-type.

[0052] In this embodiment, the semiconductor device can be an LDMOS device, but is not limited to this.

[0053] The substrate 10 may also form a drift region (not shown) and a body region (not shown), the drift region and the body region having opposite conductivity types; the isolation structure 20 and the drain region 13 are disposed on the drift region; the source region 12 is disposed on the body region; the gate structure 30 covers part of the drift region and part of the body region.

[0054] Multiple contact holes can also be formed on the substrate 10, and the multiple contact holes contact the gate structure 30, the source region 12 and the drain region 13 respectively to lead out the gate structure 30, the source region 12 and the drain region 13.

[0055] The present invention also provides a method for manufacturing a semiconductor device, which can be manufactured using the above-mentioned method.

[0056] Figure 9 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 9 As shown, the method for fabricating a semiconductor device provided in this embodiment includes:

[0057] Step S1, provide the substrate;

[0058] Step S2: An isolation structure is formed in the substrate. The isolation structure includes a first isolation structure and a plurality of second isolation structures connected to the first isolation structure. The plurality of second isolation structures are all located on the same side of the first isolation structure and extend into the substrate along a first direction.

[0059] Step S3: A gate structure is formed on the substrate. The gate structure is located above the substrate on the side of the second isolation structure away from the first isolation structure, and the gate structure extends in a first direction to cover multiple second isolation structures and part of the first isolation structure.

[0060] Step S4: A source region is formed in the substrate on the side of the gate structure away from the isolation structure, and a drain region is formed in the substrate on the side of the isolation structure away from the gate structure.

[0061] Specifically, the material of the substrate 10 provided in step S1 includes, but is not limited to, silicon.

[0062] Execute step S2, refer to Figure 4 As shown, an isolation structure 20 is formed in the substrate 10. The isolation structure 20 includes a first isolation structure 21 and a plurality of second isolation structures 22 connected to the first isolation structure 21. The plurality of second isolation structures 22 are all located on the same side of the first isolation structure 21 and extend into the substrate 10 along a first direction X.

[0063] Figure 10 This is a schematic diagram of the structure after forming trenches in the substrate according to an embodiment of the present invention. Specifically, the method for forming the isolation structure 20 in the substrate 10 may include: as followsFigure 10 As shown, a trench 11 is formed in the substrate 10. The trench 11 includes a main trench 111 and a plurality of extending trenches 112 communicating with the main trench 111. The plurality of extending trenches 112 are located on the same side of the main trench 111 and extend into the substrate 10 in a first direction X. Reference Figure 4 As shown, an isolation material is grown in the trench 11 to form an isolation structure 20, wherein the isolation material in the main trench 111 serves as a first isolation structure 21, and the isolation material in the multiple extension trenches 112 serves as multiple second isolation structures 22.

[0064] The insulating material may be made of, but is not limited to, silicon oxide. The insulating material may be formed using chemical vapor deposition (CVD) processes, but is not limited to these. After the insulating material is grown within the trench 11, a planarization process may be performed to remove the insulating material located above the substrate 10.

[0065] In this embodiment, the isolation structure 20 is a shallow trench isolation structure (STI). In other embodiments, the isolation structure 20 may also be a local oxidation of silicon (LOCOS) isolation structure.

[0066] Execute step S3, refer to Figure 3 and Figure 4 As shown, a gate structure 30 is formed on the substrate 10. The gate structure 30 is located above the substrate 10 on the side of the second isolation structure 22 away from the first isolation structure 21, and extends in the first direction X to cover a plurality of second isolation structures 22 and a portion of the first isolation structure 21.

[0067] Methods for forming a gate structure 30 on the substrate 10 may include: Figure 11 As shown, an oxide material layer 34a and a gate material layer 30a are formed on the substrate 10, and the oxide material layer 34a and the gate material layer 30a can cover the substrate 10 and the isolation structure 20; Reference Figure 11 and Figure 3 As shown, etching removes part of the gate material layer 30a and part of the oxide material layer 34a to form the gate structure 30 and the gate oxide layer 34.

[0068] In this embodiment, reference Figure 3 As shown, the gate structure 30 may include a first gate 31 and a plurality of second gates 32 connected to the first gate 31; the first gate 31 is located above the substrate on the side of the second isolation structure 22 away from the first isolation structure 21, and extends in the first direction X to cover the plurality of second isolation structures 22; the second gates 32 extend outward from the edge of the first gate 31 near the first isolation structure 21 along the first direction X; the plurality of second isolation structures 22 and the plurality of second gates 32 are alternately arranged in the second direction Y.

[0069] In one embodiment of this application, reference is made to... Figure 10 , Figure 7 and Figure 8 As shown, after forming trench 11 in substrate 10 and before growing isolation material in trench 11, a sacrificial layer (not shown) is filled at the end of extension trench 112 away from main trench 111. Then, isolation material is grown in trench 11, and the sacrificial layer is removed. A gate structure 30 is then formed on substrate 10. The gate structure 30 partially fills the end of extension trench 112 away from main trench 111. The portion of gate structure 30 filling extension trench 112 is the third gate 33. Exemplarily, the sacrificial layer can be a photoresist layer or amorphous silicon, etc. Of course, the third gate 33 can also be formed by other methods. In this embodiment, extension trench 112 serves as both the extension trench for gate structure 30 and isolation structure 20, which can save process time and reduce costs.

[0070] In step S4, a source region 12 is formed in the substrate on the side of the gate structure 30 away from the isolation structure 20, and a drain region 13 is formed in the substrate on the side of the isolation structure 20 away from the gate structure 30. The source region 12 and the drain region 13 can be formed by the same ion implantation process, but are not limited thereto.

[0071] In the semiconductor device and its fabrication method provided by the present invention, the isolation structure 20 located in the substrate 10 includes a first isolation structure 21 and a plurality of second isolation structures 22 connected to the first isolation structure 21. The plurality of second isolation structures 22 are located on the same side of the first isolation structure 21 and extend into the substrate 10 along a first direction X. The gate structure 30 is located above the substrate on the side of the second isolation structures 22 away from the first isolation structure 21, and the gate structure 30 extends in the first direction X to cover the plurality of second isolation structures 22 and part of the first isolation structure 21. In this way, the edge electric field of the isolation structure 20 located below the gate structure 30 can be reduced by optimizing the isolation structure 20, for example, by using... Figure 2 The original electric field spike line became Figure 4 The two electric field spikes make the electric field distribution of the device more uniform, which can improve the problem of hot carrier injection failure (HCI fail) in semiconductor devices and improve the reliability of semiconductor devices.

[0072] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Base; An isolation structure, located in the substrate, includes a first isolation structure and a plurality of second isolation structures connected to the first isolation structure, wherein the plurality of second isolation structures are located on the same side of the first isolation structure and extend into the substrate in a first direction; A gate structure is located above the substrate on the side of the second isolation structure away from the first isolation structure, and extends in the first direction to cover a plurality of second isolation structures and a portion of the first isolation structure; the gate structure includes a first gate and a plurality of second gates connected to the first gate; the first gate is located above the substrate on the side of the second isolation structure away from the first isolation structure, and extends in the first direction to cover a plurality of second isolation structures; the second gate extends outward from the edge of the first gate near the first isolation structure along the first direction; A plurality of second isolation structures and a plurality of second gates are alternately arranged in a second direction, wherein the first direction and the second direction intersect; The source region is located in the substrate on the side of the gate structure away from the isolation structure; as well as The drain region is located in the substrate on the side of the isolation structure away from the gate structure.

2. The semiconductor device as claimed in claim 1, characterized in that, A trench is formed in the substrate, the trench including a main trench and a plurality of extension trenches communicating with the main trench, the plurality of extension trenches being located on the same side of the main trench and extending into the substrate in a first direction; a first isolation structure fills the main trench, and a plurality of second isolation structures respectively fill the plurality of extension trenches.

3. The semiconductor device as described in claim 2, characterized in that, The second isolation structure fills the portion of the corresponding extension trench near the main trench; the gate structure also includes a plurality of third gates connected to the first gate; the plurality of third gates respectively fill the portion of the corresponding extension trench away from the main trench.

4. The semiconductor device as claimed in claim 1, characterized in that, A gate oxide layer is disposed between the gate structure and the substrate, and the gate oxide layer is also located between the gate structure and the isolation structure.

5. The semiconductor device as claimed in claim 1, characterized in that, A drift region and a body region are formed in the substrate; the isolation structure and the drain region are disposed on the drift region; the source region is disposed on the body region; and the gate structure covers a portion of the drift region and a portion of the body region.

6. The semiconductor device as claimed in claim 1, characterized in that, The second isolation structure has a rectangular, triangular, or curved shape in cross-section parallel to the top surface of the base.

7. A method for fabricating a semiconductor device, characterized in that, include: Provide a base; An isolation structure is formed in the substrate, the isolation structure including a first isolation structure and a plurality of second isolation structures connected to the first isolation structure, the plurality of second isolation structures being located on the same side of the first isolation structure and extending into the substrate along a first direction; A gate structure is formed on the substrate, the gate structure being located above the substrate on the side of the second isolation structure away from the first isolation structure, and extending in the first direction to cover a plurality of second isolation structures and a portion of the first isolation structure; the gate structure includes a first gate and a plurality of second gates connected to the first gate; the first gate is located above the substrate on the side of the second isolation structure away from the first isolation structure, and extends in the first direction to cover a plurality of second isolation structures; the second gate extends outward from the edge of the first gate near the first isolation structure along the first direction; A plurality of second isolation structures and a plurality of second gates are alternately arranged in a second direction, wherein the first direction and the second direction intersect; as well as A source region is formed in the substrate on the side of the gate structure away from the isolation structure, and a drain region is formed in the substrate on the side of the isolation structure away from the gate structure.

8. The method for fabricating a semiconductor device as described in claim 7, characterized in that, The method for forming the isolation structure in the substrate includes: A trench is formed in the substrate, the trench including a main trench and a plurality of extension trenches communicating with the main trench, the plurality of extension trenches being located on the same side of the main trench and extending into the substrate in a first direction; An insulating material is grown within the trench to form an insulating structure, wherein the insulating material in the main trench serves as the first insulating structure, and the insulating materials in the plurality of extension trenches serve as a plurality of second insulating structures.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, After the trench is formed in the substrate and before the isolation material is grown in the trench, a sacrificial layer is filled at the end of the extension trench away from the main trench. After growing the isolation material in the trench, the sacrificial layer is removed, and a gate structure is formed on the substrate, the gate structure partially filling the end of the extension trench away from the main trench.

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