A silicon carbide semiconductor device with a p-well layer and a method of fabricating the same

Abstract

The application relates to the field of MOS semiconductor technology, and discloses a silicon carbide semiconductor device with a P-well layer and a preparation method thereof. The silicon carbide semiconductor device comprises a plurality of parallel MOS cells. A single MOS cell comprises a drain, a semiconductor epitaxial layer, a source, a gate and a gate oxide layer covering the surface of the gate. The semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P+ layer, an N well layer and a P well layer. A doping layer and a plurality of mutually non-contacting doping strips are formed by ion implantation in the inside of the N diffusion layer of a single MOS cell and below the region between the P well layer and the gate. The application introduces a specific doping layer and doping strip combination in the region below the P well and the gate of a traditional MOS cell. The structure design can significantly modulate the current path of the JFET region when the device is turned on, reduce the specific on-resistance, and improve the distribution of the lateral electric field in the blocking state, so that the on-state performance of the device is improved as a whole without sacrificing the breakdown voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MOS semiconductor technology, and in particular to a silicon carbide semiconductor device with a P-well layer and a preparation method thereof. BACKGROUND

[0002] Although silicon carbide (SiC) material has great potential in high-temperature, high-frequency and high-power application fields due to its excellent characteristics such as wide band gap, high critical breakdown field and high thermal conductivity, traditional SiC MOS devices, especially MOSFETs, still face the inherent contradiction between on-resistance (Rsp) and breakdown voltage (BV). In high-voltage applications, in order to obtain sufficient breakdown voltage, it is usually necessary to increase the thickness of the drift region and reduce its doping concentration, but this will significantly increase the specific on-resistance of the device, resulting in an increase in conduction loss. In the blocking state, the JFET region of the traditional structure is prone to electric field crowding, which limits the further improvement of the breakdown voltage, and the short-circuit resistance and surge resistance reliability of the device are also difficult to meet the increasingly stringent application requirements. The existing technology has limited ability to regulate the electric field and current through the conventional ion implantation formed well region and terminal structure, and it is difficult to comprehensively optimize other key parameters without sacrificing one performance, which has become the main technical bottleneck restricting the development of high-performance SiC power devices.

[0003] The existing patent discloses a silicon carbide semiconductor device (CN217468441U), which comprises: a silicon carbide epitaxial layer having opposite first and second surfaces, the first surface comprising a gate region and source regions located on both sides of the gate region; the surface of the gate region has a first trench; a first voltage-resistant masking structure formed in the silicon carbide epitaxial layer based on the first trench. In the technology disclosed in the existing patent, there are problems of gate oxide easy breakdown caused by high electric field concentrated in the corner region at the bottom of the gate trench, limited ion implantation depth, difficulty in achieving effective deep junction protection and surge resistance design, and insufficient thickness of the oxide layer formed at the bottom of the trench by the conventional high-temperature oxidation process, resulting in reduced voltage resistance and reliability. SUMMARY

[0004] The present application provides a silicon carbide semiconductor device with a P-well layer and a preparation method thereof to solve the existing technical problems, solving the problem of gate oxide layer easy to be broken down caused by high electric field concentrated in the corner region at the bottom of the gate trench.

[0005] To solve the above technical problems, according to one aspect of the present application, more specifically, a silicon carbide semiconductor device with P-well layer, comprising a plurality of parallel MOS cells, each of the MOS cells comprises a drain, a semiconductor epitaxial layer, a source, a gate and a gate oxide layer covering the surface of the gate, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P+ layer, an N well layer and a P well layer, the inside of the N diffusion layer of each of the MOS cells and the region below the P well layer and the gate are formed with a doping layer and a plurality of non-contacting doping strips by ion implantation.

[0006] Further, the doping layer is an N+ doping layer, the top end of the N+ doping layer directly contacts the P well layer and the gate oxide layer.

[0007] Further, the doping strip is an N-type doping strip, the N-type doping strip is located in the inside of the N diffusion layer between the N substrate layer and the N+ doping layer, and the length of the cross-sectional profile of each N-type doping strip is equal.

[0008] Further, the doping strip is a reduced doping strip, the reduced doping strip is located in the inside of the N diffusion layer between the N substrate layer and the N+ doping layer, and the length of the cross-sectional profile of each reduced doping strip is reduced from top to bottom.

[0009] Further, the doping layer is a through doping layer, the top end of the through doping layer directly contacts the P well layer and the gate oxide layer, and the bottom end of the through doping layer directly contacts the N substrate layer.

[0010] The doping strip is an inner doping strip, and the inner doping strip is located in the inside of the through doping layer.

[0011] Further, the through doping layer further comprises a contact doping layer, and the contact doping layers between adjacent MOS cells are integrated.

[0012] Further, the doping layer is a P well doping layer, the top end of the P well doping layer directly contacts the P well layer and the gate oxide layer, and the inside of the P well doping layer is formed with an N well doping layer by ion implantation.

[0013] The N well layer further comprises a through N well layer, and the bottom end of the through N well layer penetrates to the lower side of the P well layer and directly contacts the N well doping layer.

[0014] Further, the doping strip is a P-type doping strip, the P-type doping strip is located in the inside of the N diffusion layer between the N substrate layer and the P well doping layer, and the length of the cross-sectional profile of each P-type doping strip is equal.

[0015] A preparation method of a silicon carbide semiconductor device with P-well layer, specifically comprising:

[0016] S1, forming an N diffusion layer by N-type epitaxial growth on the surface of the N substrate layer;

[0017] S2, forming a P well layer and an N well layer in the N diffusion layer by ion implantation;

[0018] S3, forming a P+ layer above the P well layer by ion implantation;

[0019] S4, forming a doped layer and a plurality of mutually non-contacting doped strips below the region between the P well layer and the subsequently formed gate in the N diffusion layer by ion implantation;

[0020] S5, performing a high-temperature annealing process to activate the implanted ions, growing a gate oxide layer on the surface of the device, and depositing polysilicon to form a gate;

[0021] S6, forming a source and a drain by a metal vapor deposition method to complete the preparation of the device.

[0022] The present application provides a silicon carbide semiconductor device with a P-well layer and a preparation method thereof, compared with the prior art, the effects obtained by the present application are:

[0023] 1. The present application introduces a specific combination of a doped layer and a doped strip in the region below the P well and the gate of the traditional MOS cell, which can significantly modulate the current path of the JFET region when the device is turned on, reduce the specific on-resistance, and improve the distribution of the lateral electric field in the blocking state, thereby improving the on-state performance of the device without sacrificing the breakdown voltage.

[0024] 2. The present application realizes more precise control of the resistance and electric field distribution of the JFET region in the vertical direction by using a gradually changing doped strip with a cross-sectional profile that gradually decreases from top to bottom, which helps to alleviate the electric field crowding phenomenon that easily occurs under high blocking voltage, so that the device can withstand higher voltage stress, thereby obtaining higher breakdown voltage and more stable long-term reliability.

[0025] 3. The present application constructs a low-resistance vertical conduction channel from the top of the cell to the substrate by introducing a doped layer, which greatly optimizes the transport path of the carriers, and this structure not only significantly reduces the overall on-resistance of the device, but also helps to disperse and alleviate the electric field strength under high voltage, thereby improving the comprehensive performance of the device in high-voltage application scenarios.

[0026] 4. The present application connects the contact doped layers between adjacent cells to form a shared structure, which enhances the electrical connection and current spreading capability of the cells in the lateral direction, effectively reduces the parasitic resistance between the cells, and promotes the uniform distribution of current, thereby improving the overall on-state characteristics, operating robustness and reliability of the device.

[0027] 5、The application forms a local and deep-extended charge coupling and electric field modulation region in the device by adopting the composite structure of nesting the N-well doped layer in the P-well doped layer and connecting through the well layer, which can greatly enhance the energy absorption capacity and resistance of the device under abnormal working conditions, significantly improve the reliability against surge impact, and is very suitable for power applications with extremely high robustness requirements. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a schematic diagram of example one in the application;

[0029] Figure 2 is a schematic diagram of example two in the application;

[0030] Figure 3 is a schematic diagram of example three in the application;

[0031] Figure 4 is a schematic diagram of example four in the application;

[0032] Figure 5 is a schematic diagram of example five in the application;

[0033] Figure 6 is a MOS cell distribution diagram of example four in the application.

[0034] In the figure: 1, drain; 2, source; 3, gate; 4, N substrate layer; 5, N diffusion layer; 6, P+ layer; 7, N well layer; 8, P well layer; 9, N+ doped layer; 10, N-type doped band; 11, P-well doped layer; 12, N-well doped layer; 13, P-type doped band; 701, through N-well layer; 901, through doped layer; 902, contact doped layer; 101, reduced doped band; 102, inner doped band. DETAILED DESCRIPTION

[0035] In order to make the technical solutions of the application clearer, the application will be further described in detail below in combination with the drawings and specific examples.

[0036] As shown in Figure 1 , a preparation method of a silicon carbide semiconductor device with a P-well layer, specifically comprising:

[0037] Step one, form an N diffusion layer 5 by performing N-type epitaxial growth on the surface of the N substrate layer 4; precisely epitaxially grow the N diffusion layer on the N substrate to provide a high-quality crystal material basis for the intrinsic JFET zone and subsequent ion implantation. This step can precisely control the thickness and doping concentration of the N diffusion layer, lay a solid foundation for providing stable blocking voltage and on-resistance characteristics of the device, and ensure the consistency and repeatability of the device performance.

[0038] Step two, form P-well layer 8 and N-well layer 7 in N diffusion layer 5 by ion implantation; the P-well layer and N-well layer are formed synchronously by high-energy ion implantation technology, which realizes the accurate control of the junction depth and lateral diffusion of the well region. This step ensures that the P-well and N-well have clear boundaries and ideal doping distribution, providing a guarantee for the formation of stable channel and effective depletion region, thereby improving the threshold voltage stability and blocking characteristics of the device.

[0039] Step three, form P+ layer 6 above P-well layer 8 by ion implantation; form P+ layer by selective high-concentration P-type ion implantation above the P-well layer, which significantly reduces the contact resistance between the source and the P-body. This step ensures the good formation of ohmic contact, effectively avoids the opening of the parasitic bipolar transistor, and at the same time enhances the anti-latch-up capability and switching reliability of the device.

[0040] Step four, in N diffusion layer 5, below the region between P-well layer 8 and subsequently formed gate 3, form a doped layer and several non-contact doped bands by ion implantation; this core step forms various doped layers (such as N+ layer, through layer, P-well doped layer) and doped bands (such as N-type band, reduced band, P-type band) claimed in the claims by customized ion implantation in a specific area, once or in several times. The advantage is that it can flexibly realize various device structure variations, accurately modulate the resistance and electric field distribution of the JFET region, and fundamentally optimize key performance parameters such as on-resistance, breakdown voltage, and reliability of the device.

[0041] Step five, perform high-temperature annealing process to activate the implanted ions, grow gate oxide layer on the device surface, and deposit polysilicon to form gate 3; high-temperature annealing process effectively activates all implanted ions and repairs lattice damage, ensuring the accuracy and electrical activity of the doping distribution. The subsequently grown gate oxide layer has excellent interface quality and insulation characteristics, reducing the interface state density, thereby improving the channel mobility and gate reliability. This step integrates the key processes of annealing, gate oxide growth, and polysilicon deposition, ultimately forming a stable and reliable MOS gate structure.

[0042] Step six, form source 2 and drain 1 by metal vapor deposition method to complete the preparation of the device.

[0043] Example 1

[0044] As Figure 1As shown, a silicon carbide semiconductor device with a P-well layer includes several parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, a gate 3, and a gate oxide layer covering the surface of the gate 3. The semiconductor epitaxial layer includes an N-substrate layer 4, an N-diffusion layer 5, a P+ layer 6, an N-well layer 7, and a P-well layer 8. Inside the N-diffusion layer 5 of a single MOS cell, and below the region between the P-well layer 8 and the gate 3, a doped layer and several non-contacting doped bands are formed by ion implantation. The doped layer is an N+ doped layer 9, and the top of the N+ doped layer 9 is in direct contact with the P-well layer 8 and the gate oxide layer.

[0045] The doped bands are N-type doped bands 10, located inside the N-diffusion layer 5 between the N-substrate layer 4 and the N+ doped layer 9, with each N-type doped band 10 having an equal cross-sectional profile length. Within the N-diffusion layer 5 below the P-well layer 8 and the gate 3, an N+ doped layer with its top contacting the P-well and gate oxide, along with a series of equal-length N-type doped bands 10, are simultaneously formed. The implementation principle is that by doping these N-type regions (N+ doped layer 9 and N-type doped bands 10), the current path from source 2 to drain 1 during device turn-on (JFET region) is optimized, reducing the specific on-resistance (Rsp). Simultaneously, this structure effectively modulates the lateral electric field distribution in the device's off-state, improving the breakdown voltage. Its advantage is that it significantly improves the device's conduction performance without sacrificing breakdown voltage.

[0046] Example 2

[0047] like Figure 2 As shown, a silicon carbide semiconductor device with a P-well layer includes several parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, a gate 3, and a gate oxide layer covering the surface of the gate 3. The semiconductor epitaxial layer includes an N substrate layer 4, an N diffusion layer 5, a P+ layer 6, an N well layer 7, and a P well layer 8. Inside the N diffusion layer 5 of a single MOS cell, and below the region between the P well layer 8 and the gate 3, a doped layer and several non-contacting doped bands are formed by ion implantation.

[0048] The doping band is a reduced doping band 101, located inside the N-diffusion layer 5 between the N-substrate layer 4 and the N+ doped layer 9. The length of the cross-sectional profile of each reduced doping band 101 decreases sequentially from top to bottom. The equal-length N-type doped band 10 is replaced with a reduced doping band 101 whose cross-sectional length decreases sequentially from top to bottom. The principle behind this gradient doping distribution is to more precisely control the resistance and electric field distribution in the vertical direction of the JFET region, achieving a better balance between breakdown voltage and conduction capability. Its advantage is that it can further suppress the electric field crowding effect under high blocking voltage, thereby obtaining higher breakdown voltage and better reliability.

[0049] Example 3

[0050] like Figure 3 As shown, a silicon carbide semiconductor device with a P-well layer includes several parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, a gate 3, and a gate oxide layer covering the surface of the gate 3. The semiconductor epitaxial layer includes an N substrate layer 4, an N diffusion layer 5, a P+ layer 6, an N well layer 7, and a P well layer 8. Inside the N diffusion layer 5 of a single MOS cell, and below the region between the P well layer 8 and the gate 3, a doped layer and several non-contacting doped bands are formed by ion implantation.

[0051] The doped layer is a through-doped layer 901, with its top end in direct contact with the P-well layer 8 and the gate oxide layer, and its bottom end in direct contact with the N-substrate layer 4. The doped band is an inner doped band 102, located inside the through-doped layer 901. The through-doped layer 901 extends from the lower surface of the P-well 8 / gate oxide layer to the N-substrate 4, and an inner doped band 102 is formed within it. The principle behind this is the creation of a low-resistance vertical conductive channel from the top of the cell directly to the substrate 4, significantly optimizing the electron path from the source to the drain. The advantages include a significant reduction in the overall on-resistance of the device, and its unique vertical doping structure also helps to disperse the electric field, improving performance under high-voltage applications.

[0052] Example 4

[0053] like Figure 4 , 6 As shown, a silicon carbide semiconductor device with a P-well layer includes several parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, a gate 3, and a gate oxide layer covering the surface of the gate 3. The semiconductor epitaxial layer includes an N substrate layer 4, an N diffusion layer 5, a P+ layer 6, an N well layer 7, and a P well layer 8. Inside the N diffusion layer 5 of a single MOS cell, and below the region between the P well layer 8 and the gate 3, a doped layer and several non-contacting doped bands are formed by ion implantation.

[0054] The through-doped layer 901 also includes a contact doped layer 902, with the contact doped layers 902 between adjacent MOS cells being integrated. Similarly, the internal doped band 102 is also located inside the contact doped layer 902, thus connecting the portions (contact doped layers) between adjacent cells. The principle behind this is that multiple cells are physically and electrically connected through the shared contact doped layer 902, enhancing the device's lateral conductivity and current uniformity. The advantages include effectively reducing the on-resistance between cells, improving current spread, and enhancing the overall performance, robustness, and reliability of the device.

[0055] Embodiment 5

[0056] As Figure 5 shown, a silicon carbide semiconductor device with a P-well layer includes a plurality of parallel MOS cells, a single MOS cell including a drain 1, a semiconductor epitaxial layer, a source 2, a gate 3, and a gate oxide layer covering the surface of the gate 3, the semiconductor epitaxial layer including an N substrate layer 4, an N diffusion layer 5, a P+ layer 6, an N well layer 7, and a P well layer 8, the inside of the N diffusion layer 5 of a single MOS cell, and below the region between the P well layer 8 and the gate 3 are formed by ion implantation to form a doped layer and a plurality of non-contact doped strips.

[0057] The doped layer is a P well doped layer 11, the top end of the P well doped layer 11 directly contacts the P well layer 8 and the gate oxide layer, and the inside of the P well doped layer 11 is formed by ion implantation to form an N well doped layer 12; the N well layer 7 further includes a through N well layer 701, the bottom end of the through N well layer 701 penetrates below the P well layer 8 and directly contacts the N well doped layer 12. The doped strip is a P type doped strip 13, the P type doped strip 13 is located in the inside of the N diffusion layer 5 between the N substrate layer 4 and the P well doped layer 11, and the length of the cross-sectional profile of each P type doped strip 13 is equal. The N well doped layer 12 is nested in the inside of the P well doped layer 11 and connected to the N well doped layer 12 through the through N well layer 701. The implementation principle is to construct a local, deep PNPN parasitic thyristor structure or an electrically equivalent structure, aiming to achieve stronger charge coupling and electric field modulation. The advantage is that it can greatly enhance the short circuit withstand capability (SCWT) and surge reliability of the device, and is particularly suitable for power application scenarios with high reliability requirements.

[0058] The above embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it cannot be understood as a limitation on the scope of the present application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the present application patent should be subject to the appended claims.

Claims

1. A silicon carbide semiconductor device with a P-well layer, comprising a plurality of MOS cells arranged side by side, a single MOS cell comprising a drain (1), a semiconductor epitaxial layer, a source (2), a gate (3) and a gate oxide layer covering the surface of the gate (3), the semiconductor epitaxial layer comprising an N substrate layer (4), an N diffusion layer (5), a P+ layer (6), an N well layer (7) and a P well layer (8), characterized in that: The inside of the N diffusion layer (5) of the single MOS cell and the region below the P well layer (8) and the gate (3) are formed by ion implantation with a doping layer and a plurality of non-contact doping strips; The doping layer is an N+ doping layer (9), and the top end of the N+ doping layer (9) is in direct contact with the P well layer (8) and the gate oxide layer.

2. The silicon carbide semiconductor device with a P-well layer according to claim 1, characterized by: The doping strip is an N-type doping strip (10), which is located in the N diffusion layer (5) between the N substrate layer (4) and the N+ doping layer (9), and the length of the cross-sectional profile of each N-type doping strip (10) is equal.

3. The silicon carbide semiconductor device with a P-well layer of claim 1, wherein: The doping strip is a reduced doping strip (101), which is located in the N diffusion layer (5) between the N substrate layer (4) and the N+ doping layer (9), and the length of the cross-sectional profile of each reduced doping strip (101) is reduced from top to bottom.

4. A silicon carbide semiconductor device with a P-well layer, comprising a plurality of MOS cells arranged side by side, a single MOS cell comprising a drain (1), a semiconductor epitaxial layer, a source (2), a gate (3), and a gate oxide layer covering the surface of the gate (3), the semiconductor epitaxial layer comprising an N substrate layer (4), an N diffusion layer (5), a P+ layer (6), an N well layer (7), and a P well layer (8), characterized in that: The inside of the N diffusion layer (5) of the single MOS cell and the region below the P well layer (8) and the gate (3) are formed by ion implantation with a doping layer and a plurality of non-contact doping strips; The doping layer is a through doping layer (901), and the top end of the through doping layer (901) is in direct contact with the P well layer (8) and the gate oxide layer, and the bottom end of the through doping layer (901) is in direct contact with the N substrate layer (4); The doping strip is an internal doping strip (102), which is located in the through doping layer (901).

5. The silicon carbide semiconductor device with a P-well layer according to claim 4, wherein: The through doping layer (901) is a contact doping layer (902), and the contact doping layers (902) between adjacent MOS cells are integrated.

6. A silicon carbide semiconductor device with a P-well layer, comprising a plurality of MOS cells arranged side by side, a single MOS cell comprising a drain (1), a semiconductor epitaxial layer, a source (2), a gate (3), and a gate oxide layer covering the surface of the gate (3), the semiconductor epitaxial layer comprising an N substrate layer (4), an N diffusion layer (5), a P+ layer (6), an N well layer (7), and a P well layer (8), characterized in that: The inside of the N diffusion layer (5) of the single MOS cell and the region below the P well layer (8) and the gate (3) are formed by ion implantation with a doping layer and a plurality of non-contact doping strips; The doping layer is a P well doping layer (11), and the top end of the P well doping layer (11) is in direct contact with the P well layer (8) and the gate oxide layer, and the inside of the P well doping layer (11) is formed by ion implantation with an N well doping layer (12); The N well layer (7) is a through N well layer (701), and the bottom end of the through N well layer (701) penetrates to the lower side of the P well layer (8) and is in direct contact with the N well doping layer (12).

7. The silicon carbide semiconductor device with a P-well layer of claim 6, wherein: The doping strip is a P-type doping strip (13), which is located in the N diffusion layer (5) between the N substrate layer (4) and the P well doping layer (11), and the length of the cross-sectional profile of each P-type doping strip (13) is equal.

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