Symmetrical current-sharing power module

Abstract

The invention discloses a symmetrical current-sharing power module, and relates to the technical field of power electronic devices. By changing the traditional chip layout, an upper bridge chip and a lower bridge chip are arranged left and right, the upper bridge chip is located on a left substrate, the lower bridge chip is located on a right substrate, the chips with the same bridge arm are symmetrically arranged relative to a ceramic substrate, and the distance difference between the chips and a main electrode is reduced; the problem of current imbalance when multiple chips are connected in parallel is solved; the embedded conductive copper sheet design enables the current in the module to circulate in two branches, and the vertically overlapped metal connecting wire design enables magnetic field offset to be formed between main loops, so that the parasitic inductance of the power module can be effectively reduced, the switching and conduction loss can be reduced, and the reliability of the module can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, in particular to a symmetrical current-sharing power module. BACKGROUND

[0002] Power semiconductor devices, as the core components of controlling and converting electric energy, are widely used in power management, automotive electronics, industrial control, wastewater treatment and renewable energy, etc. and play an indispensable role in various occasions and working conditions.

[0003] Silicon carbide, as a representative of the third generation of semiconductor materials, has the advantages of high temperature, high speed, high efficiency and high reliability, etc. Figure 1 As shown in FIG. 1, it is a schematic diagram of the packaging structure of a traditional silicon carbide power module, which includes a positive electrode A1, a negative electrode A2, output poles A31 and A32, an upper bridge chip A41, a lower bridge chip A42 and two pieces of substrates; the two pieces of substrates are symmetrically placed and connected by metal wires or metal strips; the upper bridge chip A41 and the positive electrode A1 are located in the upper bridge copper skin area A51 and connected to the lower bridge copper skin area A52 where the lower bridge chip A42 and the output poles A31 and A32 are located by metal wires or metal strips; the lower bridge chip A42 is connected to the copper skin area A53 where the negative electrode A2 is located by metal wires or metal strips; the main loop distance between the positive electrode A1 and the negative electrode A2 of the module is relatively long, so the parasitic inductance is large, and the distances from the chips of the upper bridge and the lower bridge to the positive and negative electrodes are not equal, so the current flowing through each chip is not uniform, the generated loss and current stress difference are large, and it has a certain impact on the reliability of the module. SUMMARY

[0004] In order to solve the above technical problems, the present application provides a symmetrical current-sharing power module, which includes a substrate including an upper bridge ceramic substrate and a lower bridge ceramic substrate symmetrically arranged along the length direction of the substrate and connected to each other by metal wires, and a positive electrode and a negative electrode are respectively arranged on one side of the substrate length direction close to the lower bridge ceramic substrate, and a first output electrode and a second output electrode are respectively arranged on the other side; The upper surface of the upper bridge ceramic substrate is provided with an upper bridge upper conductive copper skin, which is divided into a first conductive copper skin, a second conductive copper skin and an output pole conductive copper skin by a groove; the first conductive copper skin and the second conductive copper skin are respectively provided with an upper bridge chip group symmetrically arranged along the width direction of the substrate; the upper bridge chip group includes a plurality of rows of upper bridge chips symmetrically and spaced apart along the width direction of the substrate, and each row of upper bridge chips is arranged at equal intervals; the regions of the upper bridge chip group on the first conductive copper skin and the second conductive copper skin are symmetrically arranged with respect to each other along the width direction of the upper bridge ceramic substrate; The upper surface of the lower bridge ceramic substrate is provided with a lower bridge upper conductive copper sheet, the lower bridge upper conductive copper sheet is divided into a third conductive copper sheet, a fourth conductive copper sheet, a positive electrode conductive copper sheet and a negative electrode conductive copper sheet by a groove, the third conductive copper sheet and the first conductive copper sheet are arranged on the same side in the substrate width direction; the third conductive copper sheet and the fourth conductive copper sheet are respectively provided with a lower bridge chip group symmetrical along the substrate width direction, the lower bridge chip group comprises a plurality of rows of lower bridge chips arranged at intervals and symmetrically in the substrate width direction, and each row of lower bridge chips is arranged at equal intervals; the regions of the third conductive copper sheet and the fourth conductive copper sheet provided with the lower bridge chip group are mutually symmetrical in the lower bridge ceramic substrate width direction. The positive electrode conductive copper sheet is connected with the first conductive copper sheet and the second conductive copper sheet through metal wires respectively, the output electrode conductive copper sheet is connected with the third conductive copper sheet and the fourth conductive copper sheet through metal wires respectively; the upper bridge chip group is connected with the output electrode conductive copper sheet through metal wires, the lower bridge chip group is connected with the negative electrode conductive copper sheet through metal wires; the positive electrode and the positive electrode conductive copper sheet are connected through metal wires, the negative electrode and the negative electrode conductive copper sheet are also connected through metal wires, and the two metal wires partially overlap in the vertical direction to form a magnetic field offset; the first output electrode and the second output electrode are connected with the output electrode conductive copper sheet through metal wires.

[0005] The further defined technical solution of the present application is: Further, the position of the first conductive copper sheet on one side in the substrate width direction is respectively provided with an upper bridge gate terminal, an upper bridge source terminal and an upper bridge drain terminal connected with the first conductive copper sheet through a metal wire, and the position of the fourth conductive copper sheet on the other side is respectively provided with a lower bridge gate terminal and a lower bridge source terminal.

[0006] As described above, the symmetrical current-sharing power module, the upper bridge upper conductive copper sheet is also divided into an upper bridge gate conductive copper sheet connected with the upper bridge gate terminal through a metal wire and an upper bridge source conductive copper sheet connected with the upper bridge source terminal through a metal wire by a groove, the upper bridge gate conductive copper sheet and the upper bridge source conductive copper sheet are both arranged in an L shape composed of two mutually perpendicular strip-shaped copper sheets, one of the strip-shaped copper sheets is arranged between the first conductive copper sheet and the second conductive copper sheet, and the other strip-shaped copper sheet is arranged between the first conductive copper sheet and the third conductive copper sheet. The lower bridge upper conductive copper sheet is also divided into a lower bridge gate conductive copper sheet connected with the lower bridge gate terminal through a metal wire and a lower bridge source conductive copper sheet connected with the lower bridge source terminal through a metal wire by a groove, the lower bridge gate conductive copper sheet and the lower bridge source conductive copper sheet are both arranged in an L shape composed of two mutually perpendicular strip-shaped copper sheets, one of the strip-shaped copper sheets is arranged between the third conductive copper sheet and the fourth conductive copper sheet, and the other strip-shaped copper sheet is arranged between the second conductive copper sheet and the fourth conductive copper sheet.

[0007] As described above, in a symmetrical current sharing power module, the upper bridge gate conductive copper foil and the upper bridge source conductive copper foil are arranged symmetrically along the width direction of the substrate between the first conductive copper foil and the second conductive copper foil.

[0008] As described above, in a symmetrical current sharing power module, the upper bridge gate conductive copper foil and the lower bridge gate conductive copper foil are symmetrical about the center of the substrate, and the upper bridge source conductive copper foil and the lower bridge source conductive copper foil are symmetrical about the center of the substrate.

[0009] As described above, in a symmetrical current sharing power module, each row of upper bridge chips in the upper bridge chipset is connected in series via metal lines and then connected to the upper bridge gate conductive copper foil; each row of lower bridge chips in the lower bridge chipset is connected in series via metal lines and then connected to the lower bridge gate conductive copper foil.

[0010] As described above, in a symmetrical current sharing power module, the upper bridge gate conductive copper foil and the upper bridge source conductive copper foil are respectively connected to the upper bridge chip on the first conductive copper foil and the second conductive copper foil via metal wires or metal strips, and the lower bridge gate conductive copper foil and the lower bridge source conductive copper foil are respectively connected to the lower bridge chip on the third conductive copper foil and the fourth conductive copper foil via metal wires or metal strips.

[0011] As described above, a symmetrical current-sharing power module has an upper bridge gate resistor group and a lower bridge gate resistor group respectively on the upper bridge gate conductive copper foil and the lower bridge gate conductive copper foil. The number of resistors in the upper bridge gate resistor group and the lower bridge gate resistor group is the same as the number of chips in the upper bridge chip group and the lower bridge chip group, and the spacing between adjacent chips in the same row is equal to the spacing between adjacent resistors. The chips in the upper bridge chip group correspond one-to-one with the resistors in the upper bridge gate resistor group and are connected by metal wires. The chips in the lower bridge chip group correspond one-to-one with the resistors in the lower bridge gate resistor group and are connected by metal wires.

[0012] As described above, in a symmetrical current sharing power module, the metal wire is made of any one of gold, silver, copper, and aluminum.

[0013] As described above, a symmetrical current sharing power module has a first lower conductive copper foil and a second lower conductive copper foil at the bottom of the upper bridge ceramic substrate and the lower bridge ceramic substrate, respectively. The first lower conductive copper foil and the second lower conductive copper foil are also symmetrically arranged along the length of the substrate.

[0014] The beneficial effects of this invention are: (1) In this invention, the “left-right” arrangement of the chips shortens the main power circuit of the module under the same current level, and the internal current of the module circulates in two branches, forming magnetic field cancellation and reducing the parasitic inductance of the module. (2) In this invention, some of the metal connection lines between the positive and negative electrodes of the power module and the ceramic substrate are arranged in an overlapping manner to form magnetic field cancellation and reduce the parasitic inductance of the module. (3) In this invention, the distance difference between the chip in the same bridge arm and the main electrode is reduced, the current imbalance between chips is improved, and the current sharing effect under the parallel connection of multiple chips is achieved; (4) In this invention, the upper bridge and lower bridge chips are distributed at equal intervals on the upper bridge and lower bridge substrates, respectively. The chip and substrate layout is symmetrically arranged along the X-axis midline of the substrate, which enhances the balance of the module. Furthermore, the number of chips can be increased symmetrically according to the current level to adapt to more application scenarios. (5) In this invention, the upper and lower bridge drive circuits are distributed on a single substrate, reducing the drive difference between the same bridge arm; (6) In this invention, the upper and lower bridge drive circuits are symmetrical about the center point of the substrate, ensuring the consistency of the upper and lower bridge drive circuits and avoiding inconsistent switching speeds of the upper and lower bridges; (7) In this invention, the chip and the gate resistor are in one-to-one correspondence, and the chip is symmetrically distributed with respect to the position of the resistor. This can effectively adjust the switching speed, suppress gate oscillation, balance switching losses, and improve the reliability of the power module. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the internal structure of a conventional power module in the background art of this invention; Figure 2 This is a schematic diagram of the overall structure of the present invention; Figure 3 This is a bottom view of the internal structure of the present invention; Figure 4 This is a side view of the internal structure of the present invention; Figure 5 This is a schematic diagram showing the division of each conductive copper sheet in an embodiment of the present invention; Figure 6 This is a top view of a power module structure with only one row of chips in an embodiment of the present invention; Figure 7 This is a three-dimensional structural diagram of a power module with only one row of chips in an embodiment of the present invention. Figure 8 This is a schematic diagram showing the position of the gate resistor group in an embodiment of the present invention.

[0016] Among them, 1. Substrate; 101. Upper bridge ceramic substrate; 102. Lower bridge ceramic substrate; 2. Upper bridge upper conductive copper foil; 201. First conductive copper foil; 202. Second conductive copper foil; 203. Output electrode conductive copper foil; 204. Upper bridge gate conductive copper foil; 205. Upper bridge source conductive copper foil; 3. Upper bridge chipset; 301. Upper bridge chip; 4. Lower bridge upper conductive copper foil; 401. Third conductive copper foil; 402. Fourth conductive copper foil; 403. Positive electrode conductive copper foil; 404. Negative electrode conductive copper foil. 405. Lower bridge gate conductive copper foil; 406. Lower bridge source conductive copper foil; 5. Lower bridge chipset; 501. Lower bridge chip; 6. Positive electrode; 7. Negative electrode; 8. First output electrode; 9. Second output electrode; 10. Upper bridge gate terminal; 11. Upper bridge source terminal; 12. Upper bridge drain terminal; 13. Lower bridge gate terminal; 14. Lower bridge source terminal; 15. Upper bridge gate resistor group; 16. Lower bridge gate resistor group; 17. First lower conductive copper foil; 18. Second lower conductive copper foil. Detailed Implementation

[0017] This embodiment provides a symmetrical current sharing power module, such as... Figures 2 to 4 As shown, the substrate includes a substrate 1, which includes an upper bridge ceramic substrate 101 and a lower bridge ceramic substrate 102 that are symmetrically arranged along their own length direction and interconnected by metal wires. A positive electrode 6 and a negative electrode 7 are respectively provided on one side of the substrate 1 along the length direction near the lower bridge ceramic substrate 102, and a first output electrode 8 and a second output electrode 9 are respectively provided on the other side.

[0018] The upper surfaces of the upper bridge ceramic substrate 101 and the lower bridge ceramic substrate 102 are directly connected to corresponding upper bridge upper conductive copper foil 2 and lower bridge upper conductive copper foil 4, respectively. The bottom of the upper bridge ceramic substrate 101 and the lower bridge ceramic substrate 102 are also respectively provided with a first lower conductive copper foil 17 and a second lower conductive copper foil 18. The first lower conductive copper foil 17 and the second lower conductive copper foil 18 are also symmetrically arranged along the length direction of the substrate 1. All the lower conductive copper foils, the ceramic substrate 1, and all the upper conductive copper foils form a DBC structure. The lower conductive copper foils are used to improve thermal conductivity and reduce contact resistance. The ceramic substrate 1 is used to provide insulation performance, with good reliability and stability, and plays a role in protecting the chip. All the upper conductive copper foils are used to improve thermal conductivity and provide electrical connection.

[0019] like Figure 5As shown, the upper bridge conductive copper foil 2 is divided by trenches into a first conductive copper foil 201, a second conductive copper foil 202, an output electrode conductive copper foil 203, an upper bridge gate conductive copper foil 204, and an upper bridge source conductive copper foil 205; the first conductive copper foil 201 and the second conductive copper foil 202 are respectively provided with upper bridge chip groups 3 symmetrically arranged along the width direction of the substrate 1. The upper bridge chip group 3 includes a plurality of rows of upper bridge chips 301 symmetrically spaced along the width direction of the substrate 1, and each row of upper bridge chips 301 is equally spaced.

[0020] The areas on the first conductive copper foil 201 and the second conductive copper foil 202 where the upper bridge chip group 3 is located are symmetrical to each other along the width direction of the upper bridge ceramic substrate 101; the upper bridge gate conductive copper foil 204 and the upper bridge source conductive copper foil 205 are both set as L-shaped by two mutually perpendicular strip copper foils, one of which is located between the first conductive copper foil 201 and the second conductive copper foil 202, and the other is located between the first conductive copper foil 201 and the third conductive copper foil 401.

[0021] The upper conductive copper foil 4 of the lower bridge is divided by trenches into a third conductive copper foil 401, a fourth conductive copper foil 402, a positive conductive copper foil 403, a negative conductive copper foil 404, a lower bridge gate conductive copper foil 405, and a lower bridge source conductive copper foil 406. The third conductive copper foil 401 and the first conductive copper foil 201 are located on the same side of the substrate 1 in the width direction. The third conductive copper foil 401 and the fourth conductive copper foil 402 are respectively provided with lower bridge chip groups 5 symmetrically arranged along the width direction of the substrate 1. The lower bridge chip group 5 includes several rows of lower bridge chips 501 symmetrically spaced along the width direction of the substrate 1, with each row of lower bridge chips 501 equally spaced. The number of chips in the upper bridge chip group 3 and the lower bridge chip group 5 can be increased according to the current level, such as... Figures 6 to 7 as well as Figure 2 As shown, the number of chips can be set to one row, two rows, or more rows to adapt to more application scenarios.

[0022] The areas on the third conductive copper foil 401 and the fourth conductive copper foil 402 where the lower bridge chip group 5 is located are symmetrical to each other along the width direction of the lower bridge ceramic substrate 102; the lower bridge gate conductive copper foil 405 and the lower bridge source conductive copper foil 406 are both set as L-shaped by two mutually perpendicular strip copper foils, one of which is located between the third conductive copper foil 401 and the fourth conductive copper foil 402, and the other is located between the second conductive copper foil 202 and the fourth conductive copper foil 402.

[0023] The upper bridge gate conductive copper foil 204 and the upper bridge source conductive copper foil 205 are strip copper foils located between the first conductive copper foil 201 and the second conductive copper foil 202, and are symmetrically arranged along the width direction of the substrate 1. The upper bridge gate conductive copper foil 204 and the lower bridge gate conductive copper foil 405 are symmetrical about the center of the substrate 1, and the upper bridge source conductive copper foil 205 and the lower bridge source conductive copper foil 406 are symmetrical about the center of the substrate 1.

[0024] On one side of the substrate 1, near the first conductive copper sheet 201, there are an upper bridge gate terminal 10, an upper bridge source terminal 11, and an upper bridge drain terminal 12 connected to the first conductive copper sheet 201 via a metal wire. On the other side, near the fourth conductive copper sheet 402, there are a lower bridge gate terminal 13 and a lower bridge source terminal 14.

[0025] The positive conductive copper foil 403 serves as the connection layer for the DC+ electrode of the silicon carbide chip, the negative conductive copper foil 404 serves as the connection layer for the DC- electrode of the silicon carbide chip, the output conductive copper foil 203 serves as the connection layer for the AC electrode of the silicon carbide chip, the gate conductive copper foil serves as the connection layer for the G electrode of the silicon carbide chip, and the source conductive copper foil serves as the connection layer for the S electrode of the silicon carbide chip.

[0026] The output conductive copper layer 203 is located on the left side of the upper bridge ceramic substrate 101 in a U-shape, and is nested with the first conductive copper layer 201, the second conductive copper layer 202, the upper bridge gate conductive copper layer 204, and the upper bridge source conductive copper layer 205. Similarly, the positive conductive copper layer is located on one side of the lower bridge ceramic substrate 102 in a U-shape, and is nested with the third conductive copper layer 401, the fourth conductive copper layer 402, the negative conductive copper layer 404, the lower bridge gate conductive copper layer 405, and the lower bridge source conductive copper layer 406. That is, all the copper layers are designed with a concave and convex shape, with the protruding and concave parts interlocking to form a tenon and mortise structure. The copper layers are nested and arranged crosswise. The current flowing through the upper bridge chipset 3 and the current flowing through the lower bridge chipset 5 are equal in magnitude and opposite in direction, forming a magnetic field cancellation loop. This effectively reduces the parasitic inductance of the loop, reduces switching and conduction losses, improves the output efficiency of the power module, and increases working efficiency.

[0027] The power terminals are connected to the conductive copper foil via metal wires. The positive electrode 6 is connected to the positive electrode 6 conductive copper foil. The first output electrode 8 and the second output electrode 9 are respectively connected to the output electrode conductive copper foil 203. The negative electrode 7 is connected to the negative electrode 7 conductive copper foil. The upper bridge gate terminal 10 is connected to the upper bridge gate conductive copper foil 204. The lower bridge gate terminal 13 is connected to the lower bridge gate conductive copper foil 405. The upper bridge source terminal 11 is connected to the upper bridge source conductive copper foil 205. The lower bridge source terminal 14 is connected to the lower bridge source conductive copper foil 406. The upper bridge drain terminal 12 is connected to the first conductive copper foil 201.

[0028] The positive conductive copper foil 403 is connected to the first conductive copper foil 201 and the second conductive copper foil 202 respectively via metal wires. The output conductive copper foil 203 is connected to the third conductive copper foil 401 and the fourth conductive copper foil 402 respectively via metal wires. The positive electrode 6 is connected to the positive conductive copper foil 403 via metal wires. The negative electrode 7 is also connected to the negative conductive copper foil 404 via metal wires. The two metal wires partially overlap in the vertical direction to form magnetic field cancellation. The first output electrode 8 and the second output electrode 9 are connected to the output conductive copper foil 203 via metal wires.

[0029] The upper bridge chip group 3 is connected to the output electrode conductive copper foil 203 via a metal wire. Each row of upper bridge chips 301 in the upper bridge chip group 3 is connected in series via a metal wire and then connected to the upper bridge gate conductive copper foil 204. The lower bridge chip group 5 is connected to the negative electrode conductive copper foil 404 via a metal wire. Each row of lower bridge chips 501 in the lower bridge chip group 5 is connected in series via a metal wire and then connected to the lower bridge gate conductive copper foil 405.

[0030] The upper bridge gate conductive copper foil 204 and the upper bridge source conductive copper foil 205 are connected to the upper bridge chip 301 on the first conductive copper foil 201 and the second conductive copper foil 202 respectively through metal wires or metal strips. The lower bridge gate conductive copper foil 405 and the lower bridge source conductive copper foil 406 are connected to the lower bridge chip 501 on the third conductive copper foil 401 and the fourth conductive copper foil 402 respectively through metal wires or metal strips.

[0031] The interconnection methods between the upper bridge gate conductive copper foil 204 and the lower bridge gate conductive copper foil 405 and the chip include, but are not limited to, direct connection or indirect connection, such as... Figure 8 As shown, for example, upper bridge gate conductive copper foil 204 and lower bridge gate conductive copper foil 405 are respectively provided with upper bridge gate resistor group 15 and lower bridge gate resistor group 16. The number of resistors in upper bridge gate resistor group 15 and lower bridge gate resistor group 16 is the same as the number of chips in upper bridge chip group 3 and lower bridge chip group 5, and the spacing between adjacent chips in the same row is equal to the spacing between adjacent resistors. The chips in upper bridge chip group 3 correspond one-to-one with the resistors in upper bridge gate resistor group 15 and are connected by metal wires. The chips in lower bridge chip group 5 correspond one-to-one with the resistors in lower bridge gate resistor group 16 and are connected by metal wires.

[0032] Metal wires are used to achieve electrical connections between conductive copper foils, while also withstanding certain external mechanical stresses and thermal stresses caused by temperature changes, maintaining the stability of the connected circuit. The materials of metal wires include, but are not limited to, gold, silver, copper, and aluminum.

[0033] The connection layer between the chip and the upper conductive copper foil has good conductivity, which can ensure a good electrical connection between the chip and the conductive copper foil, while improving heat dissipation efficiency and reducing the thermal resistance of the power module. The interconnection methods between the chip and the copper foil include, but are not limited to, silver sintering, copper sintering, and brazing.

[0034] To address the problem of existing traditional silicon carbide power modules struggling to achieve effective current sharing among multiple parallel chips, this embodiment proposes a symmetrical current-sharing power module. This module breaks away from the traditional "top-bottom" chip arrangement, changing it to a "left-right" arrangement. Through a rational layout design, a low-inductance main current loop is formed. This loop, on one hand, uses nested conductive copper foil and overlapping metal wires to ensure that the current flowing through the upper bridge chip 301 and the lower bridge chip 501 is equal in magnitude and opposite in direction, generating a magnetic field cancellation effect, thereby reducing the module's parasitic inductance. On the other hand, the rational chip layout balances and reduces switching and conduction losses, suppressing current imbalance. In power modules with multiple parallel chips or other complex and variable application conditions, this results in better current sharing, improving the power module's output efficiency and lifespan.

[0035] In addition to the embodiments described above, the present invention may have other implementations. All technical solutions formed by equivalent substitution or equivalent transformation fall within the protection scope claimed by the present invention.

Claims

1. A symmetrical current sharing power module, comprising a substrate (1), characterized in that: The substrate (1) includes an upper bridge ceramic substrate (101) and a lower bridge ceramic substrate (102) symmetrically arranged along its own length direction and connected to each other by metal wires. A positive electrode (6) and a negative electrode (7) are respectively provided on one side of the substrate (1) along the length direction of the lower bridge ceramic substrate (102), and a first output electrode (8) and a second output electrode (9) are respectively provided on the other side. The upper surface of the upper bridge ceramic substrate (101) is provided with an upper bridge upper conductive copper sheet (2), which is divided by trenches into a first conductive copper sheet (201), a second conductive copper sheet (202) and an output electrode conductive copper sheet (203); the first conductive copper sheet (201) and the second conductive copper sheet (202) are respectively provided with upper bridge chip groups (3) symmetrically arranged along the width direction of the substrate (1), the upper bridge chip group (3) includes several rows of upper bridge chips (301) symmetrically spaced along the width direction of the substrate (1), and each row of upper bridge chips (301) is equally spaced; the areas on the first conductive copper sheet (201) and the second conductive copper sheet (202) where the upper bridge chip group (3) is provided are symmetrical to each other along the width direction of the upper bridge ceramic substrate (101). The upper surface of the lower bridge ceramic substrate (102) is provided with a lower bridge upper conductive copper foil (4). The lower bridge upper conductive copper foil (4) is divided by trenches into a third conductive copper foil (401), a fourth conductive copper foil (402), a positive electrode conductive copper foil (403), and a negative electrode conductive copper foil (404). The third conductive copper foil (401) and the first conductive copper foil (201) are located on the same side of the width direction of the substrate (1). The third conductive copper foil (401) and the fourth conductive copper foil (402) are respectively provided with lower bridge chip groups (5) symmetrically arranged along the width direction of the substrate (1). The lower bridge chip group (5) includes several rows of lower bridge chips (501) symmetrically spaced along the width direction of the substrate (1). Each row of lower bridge chips (501) is equally spaced. The areas on the third conductive copper foil (401) and the fourth conductive copper foil (402) where the lower bridge chip group (5) is provided are symmetrical to each other along the width direction of the lower bridge ceramic substrate (102). The positive conductive copper foil (403) is connected to the first conductive copper foil (201) and the second conductive copper foil (202) respectively through metal wires. The output conductive copper foil (203) is connected to the third conductive copper foil (401) and the fourth conductive copper foil (402) respectively through metal wires. The upper bridge chip group (3) is connected to the output conductive copper foil (203) through metal wires. The lower bridge chip group (5) is connected to the negative conductive copper foil (404) through metal wires. The positive electrode (6) is connected to the positive conductive copper foil (403) through metal wires. The negative electrode (7) is also connected to the negative conductive copper foil (404) through metal wires. The two metal wires partially overlap in the vertical direction to form a magnetic field cancellation. The first output electrode (8) and the second output electrode (9) are connected to the output conductive copper foil (203) through metal wires.

2. The symmetrical current sharing power module according to claim 1, characterized in that: The substrate (1) has an upper bridge gate terminal (10), an upper bridge source terminal (11), and an upper bridge drain terminal (12) connected to the first conductive copper sheet (201) on one side of the width direction. On the other side, a lower bridge gate terminal (13) and a lower bridge source terminal (14) are provided on the fourth conductive copper sheet (402).

3. A symmetrical current sharing power module according to claim 2, characterized in that: The upper bridge conductive copper foil (2) is further divided by the trench into an upper bridge gate conductive copper foil (204) connected to the upper bridge gate terminal (10) by a metal wire and an upper bridge source conductive copper foil (205) connected to the upper bridge source terminal (11) by a metal wire. The upper bridge gate conductive copper foil (204) and the upper bridge source conductive copper foil (205) are both set as L-shaped by two mutually perpendicular strip copper foils, one of which is located between the first conductive copper foil (201) and the second conductive copper foil (202), and the other is located between the first conductive copper foil (201) and the third conductive copper foil (401). The lower bridge upper conductive copper foil (4) is further divided by the trench into a lower bridge gate conductive copper foil (405) connected to the lower bridge gate terminal (13) by a metal wire and a lower bridge source conductive copper foil (406) connected to the lower bridge source terminal (14) by a metal wire. Both the lower bridge gate conductive copper foil (405) and the lower bridge source conductive copper foil (406) are configured as an L-shape composed of two mutually perpendicular strip copper foils. One strip copper foil is located between the third conductive copper foil (401) and the fourth conductive copper foil (402), and the other strip copper foil is located between the second conductive copper foil (202) and the fourth conductive copper foil (402).

4. A symmetrical current sharing power module according to claim 3, characterized in that: The upper bridge gate conductive copper foil (204) and the upper bridge source conductive copper foil (205) are strip copper foils located between the first conductive copper foil (201) and the second conductive copper foil (202) and are symmetrically arranged along the width direction of the substrate (1).

5. A symmetrical current sharing power module according to claim 4, characterized in that: The upper bridge gate conductive copper foil (204) and the lower bridge gate conductive copper foil (405) are symmetrical about the center of the substrate (1), and the upper bridge source conductive copper foil (205) and the lower bridge source conductive copper foil (406) are symmetrical about the center of the substrate (1).

6. A symmetrical current sharing power module according to claim 3, characterized in that: Each row of upper bridge chips (301) in the upper bridge chip group (3) is connected in series by metal lines and then connected to the upper bridge gate conductive copper foil (204); each row of lower bridge chips (501) in the lower bridge chip group (5) is connected in series by metal lines and then connected to the lower bridge gate conductive copper foil (405).

7. A symmetrical current sharing power module according to claim 6, characterized in that: The upper bridge gate conductive copper foil (204) and the upper bridge source conductive copper foil (205) are connected to the upper bridge chip (301) on the first conductive copper foil (201) and the second conductive copper foil (202) respectively through metal wires or metal strips. The lower bridge gate conductive copper foil (405) and the lower bridge source conductive copper foil (406) are connected to the lower bridge chip (501) on the third conductive copper foil (401) and the fourth conductive copper foil (402) respectively through metal wires or metal strips.

8. A symmetrical current sharing power module according to claim 6, characterized in that: The upper bridge gate conductive copper foil (204) and the lower bridge gate conductive copper foil (405) are respectively provided with an upper bridge gate resistor group (15) and a lower bridge gate resistor group (16). The number of resistors of the upper bridge gate resistor group (15) and the lower bridge gate resistor group (16) is the same as the number of chips of the upper bridge chip group (3) and the lower bridge chip group (5), and the spacing between adjacent chips in the same row is equal to the spacing between adjacent resistors. The chips in the upper bridge chip group (3) correspond one-to-one with the resistors in the upper bridge gate resistor group (15) and are connected by metal wires. The chips in the lower bridge chip group (5) correspond one-to-one with the resistors in the lower bridge gate resistor group (16) and are connected by metal wires.

9. A symmetrical current sharing power module according to claim 8, characterized in that: The metal wire is made of any one of gold, silver, copper, and aluminum.

10. A symmetrical current sharing power module according to claim 1, characterized in that: The bottom of the upper bridge ceramic substrate (101) and the lower bridge ceramic substrate (102) are respectively provided with a first lower conductive copper foil (17) and a second lower conductive copper foil (18), and the first lower conductive copper foil (17) and the second lower conductive copper foil (18) are also symmetrically arranged along the length direction of the substrate (1).

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