Semiconductor device manufacturing methods and semiconductor process equipment

Abstract

This invention relates to the field of semiconductor technology, and more specifically, to a method for manufacturing a semiconductor device and semiconductor process equipment. The method for manufacturing a semiconductor device includes: providing a substrate having a plurality of stacked structures, the stacked structures including a semiconductor channel layer, a gate dielectric layer, a first work function layer, and a second work function layer disposed from the inside out; forming a first fill layer to cover each stacked structure; removing a portion of the first fill layer corresponding to a first partition; a portion of the stacked structure existing within the first partition; etching the second work function layer within the first partition under first process conditions to expose the first work function layer within the first partition; and removing the remaining first fill layer. The semiconductor device manufacturing method provided by this invention can obtain at least two gate structures with different threshold voltages, eliminating the need to separately fabricate gate structures with different threshold voltages, thus significantly reducing process complexity and cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a method for manufacturing a semiconductor device and semiconductor process equipment. Background Technology

[0002] AI chips, smartphones, tablets, desktop computers, laptops, and other types of electronic devices all face a continuous need for increased computing power. Since these devices utilize integrated circuits (ICs) to provide computing power, improving the computing power of ICs enhances the computing power of these devices. One method to improve the computing power of ICs is to increase the number of transistors and other IC components in a given area of ​​a semiconductor substrate. The ever-increasing demand for device miniaturization means a continuous need to increase transistor density, driving IC technology towards smaller technology nodes.

[0003] One way to increase transistor density is to form multiple gate structures with different threshold voltages in a semiconductor device. In related manufacturing technologies, to form multiple gate structures with different threshold voltages, it is generally achieved by forming material layers of varying work function thicknesses. Each thickness requires corresponding thin film deposition, photolithography, dry etching, and wet etching processes, resulting in high process complexity and cost. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor device and semiconductor process equipment to alleviate the technical problems of high process complexity and high cost in related technologies for forming multiple gate structures with different threshold voltages in semiconductor devices.

[0005] The method for manufacturing a semiconductor device provided by the present invention includes:

[0006] A substrate is provided, the substrate having a plurality of stacked structures, the stacked structures including a semiconductor channel layer, a gate dielectric layer, a first work function layer and a second work function layer disposed from the inside out;

[0007] The first filling step involves forming a first filling layer to cover each of the said stacked structures;

[0008] The first part of the removal step involves removing a portion of the first filling layer corresponding to the first partition; wherein, a portion of the stacked structure exists within the first partition;

[0009] In the first etching step, under the first process conditions, the second work function layer in the first partition is etched to expose the first work function layer in the first partition;

[0010] The first residual removal step removes the remaining first fill layer.

[0011] Preferably, as one possible implementation, the method further includes:

[0012] The second filling step involves forming a second filling layer to cover each of the said stacked structures;

[0013] The second part, the removal step, removes the portion of the second fill layer corresponding to the second partition;

[0014] In the second etching step, under the second process conditions, the second work function layer in the second partition is etched to expose the first work function layer in the second partition.

[0015] The second residual removal step removes the remaining portion of the second filler layer;

[0016] Wherein, the second work function layer contains W; in the first etching step, a portion of W in the second work function layer can diffuse to the first work function layer, and the concentration of W in the first work function layer exposed in the first etching step is a first concentration; in the second etching step, a portion of W in the second work function layer can diffuse to the first work function layer, and the concentration of W in the first work function layer exposed in the second etching step is a second concentration, and the second concentration is greater than the first concentration.

[0017] Preferably, as one possible implementation, the method further includes:

[0018] The third filling step involves forming a third filling layer to cover each of the aforementioned stacked structures;

[0019] The third step is the removal step, which removes the portion of the third fill layer corresponding to the third partition.

[0020] In the deposition step, a third work function layer is deposited on the outermost layer of the stacked structure within the third partition;

[0021] The third residual removal step removes the remaining third fill layer.

[0022] Preferably, as one possible implementation, before the third filling step, the method further includes:

[0023] The fourth filling step involves forming a fourth filling layer to cover each of the aforementioned stacked structures;

[0024] The fourth step is a removal step, in which the portion of the fourth fill layer corresponding to the fourth partition is removed; wherein the fourth partition is located within the third partition;

[0025] In the fourth etching step, under the third process conditions, the second work function layer and the first work function layer in the fourth partition are etched to expose the gate dielectric layer in the fourth partition.

[0026] The first residual removal step removes the remaining fourth filler layer.

[0027] Preferably, as one possible implementation, the first work function layer comprises TiN, and the second work function layer comprises WCN.

[0028] Preferably, as one possible implementation, the first process conditions include: injecting 20-40 ppm of O3 water or 4-8 M of hydrochloric acid into the process chamber where the substrate is placed, and setting the process temperature to 30-60°C;

[0029] And / or, the second process conditions include: injecting 0.1 to 20 ppm of O3 water or 0.1 to 4 M of hydrochloric acid into the process chamber in which the substrate is placed, and setting the process temperature to 20 to 30°C;

[0030] And / or, the third process conditions include: injecting 40-60 ppm of O3 water or 8-12 M of hydrochloric acid into the process chamber where the substrate is placed, and setting the process temperature to 60-90°C.

[0031] Preferably, as one possible implementation, the first partition, the second partition, and the fourth partition are arranged side by side in a horizontal direction;

[0032] And / or, the third partition includes the first partition, the second partition, and the fourth partition.

[0033] Preferably, as one possible implementation, a fifth partition is provided below the third partition, and the fifth partition contains several of the aforementioned stacked structures.

[0034] Preferably, as one possible implementation, the first work function layer and the second work function layer are both P-type work function layers, and the third work function layer is an N-type work function layer.

[0035] Preferably, as one possible implementation, the first part removal step includes: forming a patterned first mask layer on top of the first filler layer, the mask opening of the first mask layer facing the first partition; and patterning the first filler layer until the portion of the first filler layer corresponding to the first partition is completely removed.

[0036] And / or, the second part removal step includes: forming a patterned second mask layer on top of the second fill layer, the mask opening of the second mask layer facing the second partition; and patterning the second fill layer until the portion of the second fill layer corresponding to the second partition is completely removed;

[0037] And / or, the third part removal step includes: etching the third fill layer until the portion of the third fill layer corresponding to the third partition is completely removed;

[0038] And / or, the fourth part removal step includes: forming a patterned fourth mask layer on top of the fourth filler layer, the mask opening of the fourth mask layer facing the fourth partition; and patterning the fourth filler layer until the portion of the fourth filler layer corresponding to the fourth partition is completely removed.

[0039] The semiconductor process equipment provided by the present invention includes a process chamber, an air inlet assembly, a liquid inlet assembly, an upper electrode assembly, a lower electrode assembly, and a controller. The controller is characterized in that it includes at least one processor and at least one memory, wherein the memory stores a computer program, and the computer program is executed by the processor to implement the above-mentioned semiconductor device manufacturing method.

[0040] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0041] Since the work function value is related to the material composition of the work function layer, and after etching, the stacked structure in the first partition lacks a second work function layer compared to the stacked structures in other regions, the material composition of the work function layer in the stacked structure in the first partition is different from that in the stacked structures in other regions. This achieves the adjustment of the work function value of the stacked structure in the first partition, making the work function value of the stacked structure in the first partition different from that in the stacked structures in other regions. Therefore, the threshold voltage of the first gate structure (including the stacked structure and the metal gate) subsequently formed in the first partition is different from the threshold voltage of the gate structure in other regions. Thus, at least two gate structures with different threshold voltages Vt can be formed in the resulting semiconductor device.

[0042] Therefore, the semiconductor device manufacturing method provided by the present invention first prepares all the stacked structures, and then adjusts some of the stacked structures to obtain at least two gate structures with different threshold voltages; it eliminates the need to prepare gate structures with different threshold voltages separately, which can significantly reduce process complexity and cost. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0044] Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of the substrate structure before the formation of the power function layer, provided in an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of the substrate structure after the formation of the function layer, provided in an embodiment of the present invention;

[0047] Figures 4a-4d A first process flow diagram of a method for manufacturing a semiconductor device provided in an embodiment of the present invention;

[0048] Figures 5a-5b A second process flow diagram of a semiconductor device manufacturing method provided in an embodiment of the present invention;

[0049] Figures 6a-6b A third process flow diagram of a semiconductor device manufacturing method provided in an embodiment of the present invention;

[0050] Figures 7a-7c A fourth process flow diagram of a semiconductor device manufacturing method provided in an embodiment of the present invention;

[0051] Figure 8 This is a schematic diagram of the substrate after the gate structure is formed, provided in an embodiment of the present invention;

[0052] Figure 9 This is a schematic diagram of the structure of a semiconductor process equipment provided in an embodiment of the present invention. Detailed Implementation

[0053] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings.

[0055] Figure 1This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. The method includes:

[0056] S102, providing a substrate, the substrate having a plurality of stacked structures, the stacked structures including a semiconductor channel layer, a gate dielectric layer, a first work function layer and a second work function layer disposed from the inside out;

[0057] like Figure 3 As shown, the innermost layer of the stacked structure 10 is a semiconductor channel layer 11, a gate dielectric layer 12 covers the semiconductor channel layer 11, a first work function layer 13 covers the gate dielectric layer 12, and a second work function layer 14 covers the first work function layer 13.

[0058] S104, First filling step, forming a first filling layer to cover each stacked structure;

[0059] S106, First part removal step, remove the part of the first fill layer corresponding to the first partition; wherein, there is a partial stacked structure in the first partition;

[0060] See Figure 6a After the portion of the first filling layer 21 corresponding to the first partition P1 is removed, the stacked structure 10 located in the first partition P1 will be exposed, while the stacked structure 10 in other areas will still be covered and protected by the first filling layer 21.

[0061] S108, First etching step, under the first process conditions, the second work function layer in the first partition is etched to expose the first work function layer in the first partition;

[0062] After etching the second work function layer within the first partition, the stacked structure within the first partition is as follows: Figure 6a As shown.

[0063] S110, First Residual Removal Step: Remove the remaining first fill layer.

[0064] See Figure 8 After removing the remaining filler layer, a metal gate can be formed so that the metal gate and the stacked structure form a gate structure.

[0065] Since the work function value is related to the material composition of the work function layer, after etching, the stacked structure 10 in the first partition P1 lacks the second work function layer 14 compared to the stacked structure 10 in other regions. Therefore, the material composition of the work function layer of the stacked structure 10 in the first partition P1 is different from that of the stacked structure 10 in other regions. This achieves the adjustment of the work function value of the stacked structure 10 in the first partition P1, making the work function value of the stacked structure 10 in the first partition P1 different from that of the stacked structure 10 in other regions. Therefore, the threshold voltage of the first gate structure 41 (including the stacked structure 10 and the metal gate) subsequently formed in the first partition P1 is different from the threshold voltage of the gate structure in other regions. Thus, at least two gate structures with different threshold voltages Vt can be formed in the obtained semiconductor device.

[0066] Therefore, the semiconductor device manufacturing method provided in this embodiment first prepares all the stacked structures 10, and then adjusts some of the stacked structures 10 to obtain at least two gate structures with different threshold voltages; it is not necessary to prepare gate structures with different threshold voltages separately, which can significantly reduce process complexity and cost.

[0067] A, see Figure 5a and Figure 5b The above method may further include the step of adjusting the work function value of the stacked structure 10 of the second partition P2, which includes: a second filling step, forming a second filling layer 22 to cover each stacked structure 10; a second part removal step, removing the portion of the second filling layer 22 corresponding to the second partition P2; and a second etching step, etching the second work function layer 14 in the second partition P2 under second process conditions to expose the first work function layer 13 in the second partition P2 (e.g., ...). Figure 5a (as shown); the second residual removal step removes the remaining second fill layer 22 (as shown). Figure 5b (As shown). After the portion of the second fill layer 22 corresponding to the second partition P2 is removed, the stacked structure 10 located in the second partition P2 will be exposed, while the stacked structure 10 in other areas will still be covered and protected by the second fill layer 22.

[0068] The second work function layer 14 contains W (tungsten). In the first etching step, a portion of the W in the second work function layer 14 can diffuse to the first work function layer 13, resulting in the presence of W originating from the second work function layer 14 in the first work function layer 13. The concentration of W in the first work function layer 13 exposed in the first etching step is defined as the first concentration. In the second etching step, a portion of the W in the second work function layer 14 can diffuse to the first work function layer 13, resulting in the presence of W originating from the second work function layer 14 in the first work function layer 13. The concentration of W in the first work function layer 13 exposed in the second etching step is defined as the second concentration, and the second concentration is set to be greater than the first concentration.

[0069] It should be noted that by etching the second work function layer 14 of the stacked structure 10 under different process conditions (first process condition and second process condition), the amount of W diffusing from the second work function layer 14 to the first work function layer 13 can be different. This results in first work function layers 13 with different W concentrations, thus adjusting the work function value of the stacked structure 10 within the second partition P2. Although both the stacked structure 10 in the first partition P1 and the stacked structure 10 in the second partition P2 contain only the first work function layer 13, the material composition of the first work function layer 13 in the stacked structure 10 in the first partition P1 differs from that in the stacked structure 10 in the second partition P2. Consequently, the work function value of the stacked structure 10 in the first partition P1 differs from that in the stacked structure 10 in the second partition P2. Therefore, the threshold voltage of the first gate structure 41 formed in the first partition P1 is different from the threshold voltage of the second gate structure 42 formed in the second partition P2, thereby enabling at least two gate structures with different threshold voltages Vt to be formed in the resulting semiconductor device.

[0070] B, see also Figures 7a-7c The method may further include the step of adjusting the work function value of the stacked structure 10 in the third partition P3, which includes: a third filling step, forming a third filling layer 23 to cover each stacked structure 10; a third part removal step, removing the portion of the third filling layer 23 corresponding to the third partition P3; a deposition step, depositing a third work function layer 15 on the outermost layer of the stacked structure 10 in the third partition P3; and a third remaining removal step, removing the remaining portion of the third filling layer 23. After the portion of the third filling layer 23 corresponding to the third partition P3 is removed, the stacked structure 10 located in the third partition P3 will be exposed, while the stacked structures 10 in other areas will still be covered and protected by the third filling layer 23.

[0071] If both the first partition P1 and the second partition P2 are located within the third partition P3, then after the deposition of the third work function layer 15 is completed, the work function values ​​of the stacked structures 10 in the first partition P1 and the second partition P2 can be adjusted, thereby enabling the adjustment of the threshold voltage of the first gate structure 41, the threshold voltage of the second gate structure 42, and the threshold voltage of the third gate structure 43.

[0072] If the third partition P3 is located in a different region from the first partition P1 and the second partition P2, then after the deposition of the third work function layer 15, the stacked structure 10 in the third partition P3 has an additional third work function layer 15 compared to the stacked structures 10 in the first partition P1 and the second partition P2. Therefore, the work function material combination of the stacked structure 10 in the third partition P3 is different from the work function layer material combination of the stacked structure 10 in the first partition P1 and the second partition P2. Consequently, the work function value of the stacked structure 10 in the third partition P3 is different from the work function value of the stacked structure 10 in the first partition P1 and the second partition P2, and all three are different from the work function values ​​of the stacked structures 10 in other regions. Therefore, any two of the threshold voltage of the first gate structure 41, the threshold voltage of the second gate structure 42, and the threshold voltage of the gate structure in the third partition P3 are different. Thus, at least three gate structures with different threshold voltages Vt can be formed in the fabricated semiconductor device.

[0073] C, see also Figures 4a-4d The above method may further include the step of adjusting the work function value of the stacked structure 10 of the fourth partition P4, which includes: a fourth filling step, forming a fourth filling layer 34 to cover each stacked structure 10 (e.g., Figure 4a (As shown); The fourth step is the removal step, which removes the portion of the fourth fill layer 34 corresponding to the fourth partition P4 (as shown). Figure 4b (as shown); wherein, the fourth partition P4 is located within the third partition P3; in the fourth etching step, under the third process conditions, the second work function layer 14 and the first work function layer 13 within the fourth partition P4 are etched to expose the gate dielectric layer 12 within the fourth partition P4 (as shown). Figure 4c (as shown); First residual removal step, remove the remaining fourth fill layer 34 (as shown). Figure 4d (As shown). After the portion of the fourth fill layer 24 corresponding to the fourth partition P4 is removed, the stacked structure 10 located in the fourth partition P4 will be exposed, while the stacked structures 10 in other areas will still be covered and protected by the fourth fill layer 34.

[0074] It should be noted that, under the third process conditions, the first work function layer 13 and the second work function layer 14 of the stacked structure 10 in the fourth partition P4 are removed by etching. After etching, the gate dielectric layer 12 of the stacked structure 10 in the fourth partition P4 is exposed. Subsequently, a third work function layer 15 can be deposited outside the gate dielectric layer 12 of the stacked structure 10 in the fourth partition P4. Thus, the work function values ​​of the stacked structure 10 in the first partition P1, the second partition P2, and the fourth partition P4 are all different. Subsequently, a third gate structure 43 can be formed in the fourth partition P4. Therefore, any two of the threshold voltages of the first gate structure 41, the second gate structure 42, and the third gate structure 43 are different, thereby enabling the formation of at least three gate structures with different threshold voltages Vt in the fabricated semiconductor device.

[0075] Specifically, TiN (titanium nitride) can be set in the composition of the first work function layer 13, and WCN (dicarbonitride) can be set in the composition of the second work function layer 14.

[0076] The aforementioned first process conditions may include: injecting 20-40 ppm of O3 water or 4-8 M of hydrochloric acid into the process chamber where the substrate is placed, and setting the process temperature to 30-60°C; under these conditions, the second work function layer 14 of the stacked structure 10 located in the first partition P1 can be successfully etched away, and at the same time, a small amount of W in the second work function layer 14 can diffuse into the first work function layer 13.

[0077] The aforementioned second process conditions may include: injecting 0.1–20 ppm of O3 water or 0.1–4 M of hydrochloric acid into the process chamber containing the substrate, and setting the process temperature to 20–30°C; under these conditions, the second work function layer 14 of the stacked structure 10 located in the second partition P2 can also be successfully etched away. At the same time, a relatively large amount of W in the second work function layer 14 can diffuse into the first work function layer 13, making the concentration of W in the first work function layer 13 of the stacked structure 10 in the second partition P2 greater than the concentration of W in the first work function layer 13 of the stacked structure 10 in the first partition P1.

[0078] The aforementioned third process conditions may include: injecting 40-60 ppm of O3 water or 8-12 M of hydrochloric acid into the process chamber containing the substrate, and setting the process temperature to 60-90°C; under these conditions, the second work function layer 14 and the first work function layer 13 of the stacked structure 10 located in the fourth partition P4 can be successfully etched away.

[0079] Specifically, see Figure 8The first partition P1, the second partition P2, and the fourth partition P4 are arranged side by side in a horizontal direction. This allows the first, second, and third process conditions to be applied to different regions of the substrate stacked structure 10 without interfering with each other, facilitating control. Specifically, the fourth partition P4 and the first partition P1 are located on opposite sides of the second partition P2.

[0080] Furthermore, the third partition P3 is configured to include the first partition P1, the second partition P2 and the fourth partition P4. After the process is completed, the stacked structure 10 in the first partition P1 has a first work function layer 13 and a third work function layer 15 containing a first concentration W, the stacked structure 10 in the second partition P2 has a first work function layer 13 and a third work function layer 15 containing a second concentration W, and the stacked structure 10 in the fourth partition P4 has a third work function layer 15.

[0081] In addition, see Figure 8 Below the third partition P3, a fifth partition P5 can also be set. Several of the above-mentioned stacked structures 10 also exist in the fifth partition P5. Since the work function layer of the stacked structure 10 in the fifth partition P5 is not adjusted, the stacked structure 10 in the fifth partition P5 has the original first work function layer 13 and second work function layer 14. Its work function value is different from the work function value of the stacked structure 10 in the third partition P3. Therefore, the threshold voltage of the fourth gate structure 44 subsequently formed in the fifth partition P5 is different from the threshold voltage of the gate structure in the third partition P3. Thus, at least four gate structures with different threshold voltages Vt can be formed in the semiconductor device.

[0082] Preferably, the first work function layer 13 and the second work function layer 14 can both be set as P-type work function layers, and the third work function layer 15 can be set as an N-type work function layer. In this way, a complementary field-effect transistor (CFET) can be formed. The third partition P3 corresponds to the P-type transistor, and the fifth partition P5 corresponds to the N-type transistor. The two are stacked vertically, which can further increase the transistor density in the integrated circuit. In the CFET, all sides of the channel are surrounded by the gate electrode, and the gate electrodes of the N-type and P-type transistors can be electrically short-circuited together. This allows for more complete depletion in the channel and has the advantages of less short-channel effect and better gate control.

[0083] The first gate structure 41 includes a relatively lightly doped P-type work function layer, and thus can correspond to a mixture of N-type and P-type threshold voltages (e.g., having an effective work function of about 4.25 to 4.5 eV); the second gate structure 42 includes a relatively heavily doped P-type work function layer, and thus can correspond to a mixture of N-type and P-type threshold voltages (e.g., having an effective work function of about 4.5 to 4.75 eV); the third gate structure 43 does not include a P-type work function layer, and thus can correspond to more N-type threshold voltages (e.g., having an effective work function of about 4.0 to 4.25 eV); the fourth gate structure 44 does not include an N-type work function layer, and thus can correspond to more P-type threshold voltages (e.g., having an effective work function of about 4.7 to 5.0 eV).

[0084] A bonding structure can be provided between the third partition P3 and the fifth partition P5. The bonding structure can separate the P-type transistor and the N-type transistor to form a combined complementary FET (cCFET).

[0085] The first removal step described above may include: forming a patterned first mask layer 31 on top of the first filler layer 21, setting the mask opening of the first mask layer 31 to face the first partition P1; performing patterned etching on the first filler layer 21 to remove the first partition P1 of the first filler layer 21, until the portion of the first filler layer 21 corresponding to the first partition P1 is completely removed. The first mask layer 31 may be a first hard mask layer, which can be formed using photolithography and etching processes.

[0086] The second removal step described above may include: forming a patterned second mask layer 32 on top of the second filler layer 22, setting the mask opening of the second mask layer 32 to face the second partition P2; performing patterned etching on the second filler layer 22 to remove the second partition P2 of the second filler layer 22, until the portion of the second filler layer 22 corresponding to the second partition P2 is completely removed. The second mask layer 32 may be a second hard mask layer, which can be formed using photolithography and etching processes.

[0087] The third removal step mentioned above may include: etching the third filling layer 23 to remove the third partition P3 of the third filling layer 23 until the corresponding third partition P3 of the third filling layer 23 is completely removed.

[0088] The fourth removal step mentioned above includes: forming a patterned fourth mask layer 34 on top of the fourth filler layer 24, setting the mask opening of the fourth mask layer 34 to face the fourth partition P4; performing patterned etching on the fourth filler layer 24 to remove the fourth partition P4 of the fourth filler layer 24, until the portion of the fourth filler layer 24 corresponding to the fourth partition P4 is completely removed. The fourth mask layer 34 can be a fourth hard mask layer, which can be formed using photolithography and etching processes.

[0089] The process methods for the first work function layer 13, the second work function layer 14, and the third work function layer 15 may include chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0090] The composition of the semiconductor channel layer 11 may include any or more of Si, Ge, SiGe, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and GaInAsP. The fabrication method for the semiconductor channel layer 11 may include metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, and / or other suitable epitaxial growth processes.

[0091] The dielectric constant of the gate dielectric layer 12 is greater than 3.5. The composition of the gate dielectric layer 12 may include metal oxides or silicates, and the metal ions of the silicates may include any one or more of Hf, Al, Zr, La, Mg, Ba, Ti, and Pb. The processing method of the gate dielectric layer 12 may include molecular beam deposition, atomic layer deposition, or plasma-enhanced chemical vapor deposition.

[0092] The components of the first filling layer 21, the second filling layer 22, the third filling layer 23, and the fourth filling layer 24 may all include a conductive metal material or a photoresist coating. The conductive metal material may include Al, W, or Cu. The components of the first filling layer 21, the second filling layer 22, the third filling layer 23, and the fourth filling layer 24 may be the same or different. The processing method for the first filling layer 21 may include spin coating, chemical vapor deposition, or physical vapor deposition.

[0093] After the third residual removal step described above, a metal gate can be formed. The composition of the metal gate may include any or more of W, Cu, Au, and Co, and the processing method for the metal gate may include chemical vapor deposition, physical vapor deposition, electroplating, or electroless plating.

[0094] Another embodiment of the present invention provides a method for manufacturing a semiconductor device comprising:

[0095] A substrate is provided, and a plurality of semiconductor channel layers 11 are grown on the substrate using an epitaxial process; a gate dielectric layer 12 is deposited outside the semiconductor channel layers 11 (see...). Figure 2 (Structure shown); A first work function layer 13 and a second work function layer 14 are sequentially deposited outside the gate dielectric layer 12 to form a stacked structure (see...). Figure 3 (Structure shown);

[0096] Forming the fourth filler layer 24 (see Figure 4a (Structure shown); using photolithography and etching processes, a fourth hard mask layer 34 is formed; using the fourth hard mask layer 34, the morphology is etched in the fourth fill layer 24, exposing the two stacked structures located in the fourth partition P4 on the left (see...). Figure 4b (Structure shown); Under the third process conditions, the first work function layer 13 and the second work function layer 14 of the two stacked structures in the fourth partition P4 are removed by etching (see...). Figure 4c (Structure shown); the fourth hard mask layer 34 and the fourth filler layer 24 are removed using an etching process (see...). Figure 4d (Structure shown);

[0097] A second filling layer 22 is formed; a second hard mask layer 32 is formed using photolithography and etching processes; using the second hard mask layer 32, the morphology is etched into the second filling layer 22 to expose the two stacked structures located in the middle of the second partition P2; under the second process conditions, the second work function layer 14 of the two stacked structures in the second partition P2 is removed by etching, while the first work function layer 13 is retained (see...). Figure 5a (Structure shown); the second hard mask layer 32 and the second filler layer 22 are removed using an etching process (see...). Figure 5b (Structure shown);

[0098] A first filling layer 21 is formed; a first hard mask layer 31 is formed using photolithography and etching processes; using the first hard mask layer 31, the morphology is etched into the first filling layer 21 to expose the two stacked structures located in the first partition P1 on the right; under the first process conditions, the second work function layer 14 of the two stacked structures in the first partition P1 is removed by etching, while the first work function layer 13 is retained (see...). Figure 6a (Structure shown); the first hard mask layer 31 and the first filler layer 21 are removed using an etching process (see...). Figure 6b (Structure shown);

[0099] Forming a third filler layer 23 (see Figure 7a (Structure shown); Part of the third filler layer 23 was removed using an etching process, exposing the six stacked structures within the upper third partition P3 (see...). Figure 7b (Structure shown); the outermost layer of the stacked structure in the third partition P3 is the third work function layer 15 (see...). Figure 7c(Structure shown); The third filler layer 23 is removed using an etching process;

[0100] Forming a metal gate (see) Figure 8 (Structure shown).

[0101] Figure 9 A semiconductor process apparatus provided in one embodiment of the present invention includes a process chamber 50, an inlet assembly 60, a liquid inlet assembly 70, an upper electrode assembly 80, a lower electrode assembly 90, and a controller (not shown in FIG. 5). The controller includes at least one processor and at least one memory, the memory storing a computer program that, when executed by the processor, implements the method of any of the above embodiments.

[0102] For example, the controller can be a host computer or a slave computer. The controller can open the valve of the air inlet assembly 60 to introduce the corresponding process gas into the process chamber 50; the controller can also control the opening and closing degree of the valve of the air inlet assembly 60 to control the flow rate of the process gas. The controller can also control the evacuation assembly (not shown in Figure 5) to evacuate the interior of the process chamber 50, thereby controlling the gas pressure inside the process chamber 50 and removing reaction byproducts.

[0103] The controller can open the valve of the liquid inlet assembly 70 to introduce the corresponding process liquid (such as O3 water or hydrochloric acid) into the process chamber 50.

[0104] The upper electrode assembly 80 includes an RF coil 81, an upper RF power supply 82, and an upper matching unit 83. The controller is also used to control the upper RF power supply 82 to provide upper electrode power to the RF coil 81 through the upper matching unit 83, so that the RF coil 81 excites the process gas inside the process chamber 50 to generate plasma.

[0105] The lower electrode assembly 90 includes a wafer carrier 91, a lower RF power supply 92, and a lower matching unit 93. The controller further controls the lower RF power supply 92 to provide lower electrode power to the lower electrode of the wafer carrier 91 through the lower matching unit 93, thereby providing an RF bias voltage to the lower electrode of the wafer carrier 91 to attract plasma above the substrate and bombard the target area. The wafer carrier 91 includes an electrostatic chuck.

[0106] The semiconductor process equipment in this application embodiment can be either inductively coupled plasma (ICP) etching equipment or capacitively coupled plasma (CCP) etching equipment. This application embodiment does not limit the type of semiconductor process equipment.

[0107] The semiconductor process equipment provided in this embodiment of the invention has the same technical features as the semiconductor device manufacturing method provided in the above embodiments, so it can also solve the same technical problems and achieve the same technical effects.

[0108] This embodiment also provides a machine-readable storage medium storing machine-executable instructions. When the machine-executable instructions are invoked and executed by a processor, the machine-executable instructions cause the processor to implement the above-described method for manufacturing the semiconductor device.

[0109] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described equipment and apparatus can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0110] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0111] In the description of this invention, it should be noted that the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A substrate is provided, the substrate having a plurality of stacked structures, the stacked structures including a semiconductor channel layer, a gate dielectric layer, a first work function layer and a second work function layer disposed from the inside out; The second filling step involves forming a second filling layer to cover each of the said stacked structures; The second part, the removal step, removes the portion of the second fill layer corresponding to the second partition; In the second etching step, under the second process conditions, the second work function layer in the second partition is etched to expose the first work function layer in the second partition. The second residual removal step removes the remaining portion of the second filler layer; The first filling step involves forming a first filling layer to cover each of the said stacked structures; The first part of the removal step involves removing a portion of the first filling layer corresponding to the first partition; wherein, a portion of the stacked structure exists within the first partition; In the first etching step, under the first process conditions, the second work function layer in the first partition is etched to expose the first work function layer in the first partition; The first residual removal step removes the remaining first fill layer; Wherein, the second work function layer contains W; in the first etching step, a portion of W in the second work function layer can diffuse to the first work function layer, and the concentration of W in the first work function layer exposed in the first etching step is a first concentration; in the second etching step, a portion of W in the second work function layer can diffuse to the first work function layer, and the concentration of W in the first work function layer exposed in the second etching step is a second concentration, and the second concentration is greater than the first concentration.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The method further includes: The third filling step involves forming a third filling layer to cover each of the aforementioned stacked structures; The third step is the removal step, which removes the portion of the third fill layer corresponding to the third partition. In the deposition step, a third work function layer is deposited on the outermost layer of the stacked structure within the third partition; The third residual removal step removes the remaining third fill layer.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, Prior to the third filling step, the method further includes: The fourth filling step involves forming a fourth filling layer to cover each of the aforementioned stacked structures; The fourth step is a removal step, in which the portion of the fourth fill layer corresponding to the fourth partition is removed; wherein the fourth partition is located within the third partition; In the fourth etching step, under the third process conditions, the second work function layer and the first work function layer in the fourth partition are etched to expose the gate dielectric layer in the fourth partition. The first residual removal step removes the remaining fourth filler layer.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The first work function layer consists of TiN, and the second work function layer consists of WCN.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The first process conditions include: injecting 20-40 ppm of O3 water or 4-8 M of hydrochloric acid into the process chamber in which the substrate is placed, and setting the process temperature to 30-60°C; And / or, the second process conditions include: injecting 0.1~20ppm of O3 water or 0.1~4M of hydrochloric acid into the process chamber in which the substrate is placed, and setting the process temperature to 20~30°C; And / or, the third process conditions include: injecting 40-60 ppm of O3 water or 8-12 M of hydrochloric acid into the process chamber where the substrate is placed, and setting the process temperature to 60-90°C.

6. The method for manufacturing a semiconductor device according to any one of claims 3-5, characterized in that, The first partition, the second partition, and the fourth partition are arranged side by side in a horizontal direction; And / or, the third partition includes the first partition, the second partition, and the fourth partition.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, Below the third partition is a fifth partition, and within the fifth partition are several of the aforementioned stacked structures.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The first work function layer and the second work function layer are both P-type work function layers, and the third work function layer is an N-type work function layer.

9. The method for manufacturing a semiconductor device according to any one of claims 3-5, characterized in that, The first removal step includes: forming a patterned first mask layer on top of the first filler layer, the mask opening of the first mask layer facing the first partition; and patterning the first filler layer until the portion of the first filler layer corresponding to the first partition is completely removed. And / or, the second part removal step includes: forming a patterned second mask layer on top of the second fill layer, the mask opening of the second mask layer facing the second partition; and patterning the second fill layer until the portion of the second fill layer corresponding to the second partition is completely removed; And / or, the third part removal step includes: etching the third fill layer until the portion of the third fill layer corresponding to the third partition is completely removed; And / or, the fourth part removal step includes: forming a patterned fourth mask layer on top of the fourth filler layer, the mask opening of the fourth mask layer facing the fourth partition; and patterning the fourth filler layer until the portion of the fourth filler layer corresponding to the fourth partition is completely removed.

10. A semiconductor process apparatus, comprising a process chamber, a gas inlet assembly, a liquid inlet assembly, an upper electrode assembly, a lower electrode assembly, and a controller, characterized in that, The controller includes at least one processor and at least one memory, the memory storing a computer program that, when executed by the processor, implements the method for manufacturing a semiconductor device as described in any one of claims 1-9.

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