Laminated tunneling structure, solar cell and preparation method

Abstract

The invention provides a laminated tunneling structure, a solar cell and a preparation method. The laminated tunneling structure comprises a first tunneling layer and a second tunneling layer which are arranged in a laminated mode, the first tunneling layer and the second tunneling layer are both made of silicon oxide, and the total thickness of the first tunneling layer and the second tunneling layer is smaller than or equal to 3 nm. And the density of silicon oxide in the first tunneling layer is greater than that of silicon oxide in the second tunneling layer. According to the laminated tunneling structure, the electron transmission performance can be improved while a relatively good passivation effect is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of photovoltaic technology, and in particular to a laminated tunneling structure, a solar cell and a preparation method. BACKGROUND

[0002] A tunnel oxide passivated contact (TOPcon) solar cell is a solar cell using an ultrathin tunnel oxide layer as a passivation structure. The tunnel oxide layer has the characteristics of allowing electron tunneling and blocking holes, which can effectively reduce the recombination loss of photo-generated carriers in the solar cell, so that the tunnel oxide passivated contact solar cell can have a higher conversion efficiency and has a higher application potential. However, the actual production process of the tunnel oxide passivated contact solar cell is not mature, and the passivation effect of the tunnel oxide layer and the transmission efficiency of electrons often restrict each other, which limits the further improvement of the efficiency of the tunnel oxide passivated contact solar cell. SUMMARY

[0003] Therefore, it is necessary to provide a laminated tunneling structure capable of simultaneously improving the passivation effect and the electron transmission efficiency in view of the problems in the background art.

[0004] The present disclosure provides a laminated tunneling structure, which comprises a first tunneling layer and a second tunneling layer arranged in layers, the materials of the first tunneling layer and the second tunneling layer both comprise silicon oxide, the total thickness of the first tunneling layer and the second tunneling layer is ≤3nm, and the density of silicon oxide in the first tunneling layer is greater than the density of silicon oxide in the second tunneling layer.

[0005] In some embodiments of the present disclosure, the refractive index of the first tunneling layer is greater than the refractive index of the second tunneling layer, and the refractive index of the first tunneling layer is 1.46-1.47.

[0006] In some embodiments of the present disclosure, the refractive index of the second tunneling layer is 1.45-1.46.

[0007] In some embodiments of the present disclosure, the thickness of the first tunneling layer is less than the thickness of the second tunneling layer.

[0008] In some embodiments of the present disclosure, the thickness of the first tunneling layer is 0.2-1nm.

[0009] In some embodiments of the present disclosure, the thickness of the second tunneling layer is 1.3-1.8nm.

[0010] Further, the present disclosure also provides a solar cell, which comprises a semiconductor substrate and a stack tunnel structure as described in any of the above embodiments, the stack tunnel structure being arranged on the semiconductor substrate.

[0011] In some embodiments of the present disclosure, the material of the semiconductor substrate comprises silicon, and the solar cell further comprises a doped silicon material layer arranged on a side of the stack tunnel structure away from the semiconductor substrate.

[0012] In some embodiments of the present disclosure, the first tunnel layer and the second tunnel layer are arranged in sequence in a direction away from the semiconductor substrate.

[0013] Further, the present disclosure also provides a preparation method of a solar cell as described in any of the above embodiments, which comprises the following steps:

[0014] providing a semiconductor substrate comprising silicon;

[0015] performing an oxidizing acid washing treatment on the semiconductor substrate, and then performing an oxidation treatment on silicon in the semiconductor substrate to form a first tunnel layer comprising silicon oxide;

[0016] forming a second tunnel layer comprising silicon oxide on a side of the first tunnel layer away from the semiconductor substrate by vapor deposition, the density of silicon oxide in the first tunnel layer being greater than the density of silicon oxide in the second tunnel layer.

[0017] In some embodiments of the present disclosure, the step of performing an oxidation treatment on silicon in the semiconductor substrate comprises: placing the semiconductor substrate in an atmosphere of an oxidizing gas, and heating the semiconductor substrate to perform an oxidation treatment on silicon in the semiconductor substrate; or,

[0018] The step of performing an oxidation treatment on silicon in the semiconductor substrate comprises: performing an oxidation treatment on silicon in the semiconductor substrate by using an oxidizing solution, the oxidizing solution comprising one or more of hydrogen peroxide and nitric acid.

[0019] In some embodiments of the present disclosure, in the step of heating the semiconductor substrate, the heating temperature is controlled to be 900-1200℃.

[0020] In the step of performing an oxidation treatment on silicon in the semiconductor substrate by using an oxidizing solution, the oxidizing solution comprises hydrogen peroxide, and the molar concentration of hydrogen peroxide is 0.09-1 mol / L.

[0021] In some embodiments of this disclosure, the step of forming the second tunneling layer includes: placing the semiconductor substrate in a coating chamber, introducing a gas including a silicon source and an oxygen source into the coating chamber, and forming the second tunneling layer by reacting the silicon source and the oxygen source; optionally, the flow rate of the silicon source is 100 sccm to 1000 sccm, and the flow rate of the oxygen source is 7 slm to 12 slm.

[0022] In some embodiments of this disclosure, the cleaning solution for deoxidizing and acid-washing the silicon in the semiconductor substrate includes hydrofluoric acid; and / or,

[0023] Before cleaning the silicon in the semiconductor substrate, the process includes an alkaline polishing step on the semiconductor.

[0024] At least one embodiment of this disclosure provides a stacked tunneling structure comprising a first tunneling layer and a second tunneling layer stacked together. The total thickness of the first and second tunneling layers is ≤3 nm, enabling the stacked tunneling structure to exhibit good electron tunneling capability. Both the first and second tunneling layers are made of silicon oxide, with the first tunneling layer having a higher density than the second tunneling layer. In this stacked tunneling structure, the higher density of the first tunneling layer provides better passivation. The lower density of the second tunneling layer facilitates electron tunneling, thereby improving the electron transport performance of the stacked tunneling structure. Therefore, this stacked tunneling structure can improve electron transport performance while maintaining good passivation. Experimental verification shows that the open-circuit voltage and fill factor of solar cells using this stacked tunneling structure can be effectively improved, and the efficiency of the solar cells can also be effectively improved.

[0025] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of the cross-sectional structure of a layered tunnel structure;

[0028] Figure 2 This is a schematic diagram of the cross-sectional structure of a solar cell;

[0029] Figure 3 This is a schematic diagram illustrating the steps of a method for fabricating a solar cell according to an embodiment.

[0030] The reference numerals and their meanings in the accompanying drawings are as follows:

[0031] 110, First tunneling layer; 120, Second tunneling layer; 200, Semiconductor substrate; 210, Doped silicon material layer; 220, Emitter layer; 230, First electrode; 240, Second electrode. Detailed Implementation

[0032] To facilitate understanding of this document, a more comprehensive description will be provided below. Preferred embodiments are given herein. However, this document can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the content of this document more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this applies. The terminology used herein in the specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the document.

[0034] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part.

[0035] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship of one element or feature to other elements or features. It should be understood that spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then the element or feature described as “below,” “below,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Devices may be oriented in other ways (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used will be interpreted accordingly.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0037] This disclosure provides a stacked tunneling structure, comprising a first tunneling layer and a second tunneling layer stacked together. Both the first and second tunneling layers are made of silicon oxide, the total thickness of the first and second tunneling layers is ≤3 nm, and the density of silicon oxide in the first tunneling layer is greater than the density of silicon oxide in the second tunneling layer.

[0038] This stacked tunneling structure comprises a first tunneling layer and a second tunneling layer stacked together. The total thickness of the first and second tunneling layers is ≤3 nm, giving the stacked tunneling structure good electron tunneling capability. Both the first and second tunneling layers are made of silicon oxide, with the silicon oxide density in the first tunneling layer being greater than that in the second tunneling layer. In this stacked tunneling structure, the higher density silicon oxide provides better passivation. The lower density silicon oxide is more conducive to electron tunneling, thereby improving the electron transport performance of the stacked tunneling structure. Therefore, this stacked tunneling structure can improve electron transport performance while maintaining good passivation. Experimental results show that the open-circuit voltage and fill factor of solar cells using this stacked tunneling structure are effectively improved, as is the efficiency of the solar cells.

[0039] Figure 1 This is a schematic cross-sectional view of a stacked tunnel structure disclosed herein. (Refer to...)Figure 1 As shown, the stacked tunneling structure includes a first tunneling layer 110 and a second tunneling layer 120 stacked together. The materials of the first tunneling layer 110 and the second tunneling layer 120 both include silicon oxide. The total thickness of the first tunneling layer 110 and the second tunneling layer 120 is ≤3nm. The density of silicon oxide in the first tunneling layer 110 is greater than the density of silicon oxide in the second tunneling layer 120.

[0040] It is understood that density is used to describe the compactness of the material inside a thin film. The higher the density of the film, the more tightly packed the atoms are arranged inside the film, and the fewer the pores. In this embodiment, the first tunneling layer 110 has a higher density, meaning that the silicon and oxygen atoms inside the first tunneling layer 110 are more tightly packed, while the second tunneling layer 120 has a lower density, meaning that the silicon and oxygen atoms inside the second tunneling layer 120 are more loosely packed.

[0041] The inventors of this disclosure discovered during their research that denser silicon oxide has a better passivation effect, but it is prone to cracking under high-temperature conditions during production, and its thickness is also detrimental to electron transport. More porous silicon oxide has a poorer passivation effect but is beneficial for electron transport. Based on this, this disclosure proposes a stacked tunneling structure in this embodiment, which stacks a first tunneling layer 110 and a second tunneling layer 120 with different densities, improving passivation while ensuring good electron transport performance. Furthermore, the second tunneling layer 120 can buffer the internal stress in the first tunneling layer 110, mitigating cracking. Therefore, this stacked tunneling structure improves solar cell performance while maintaining a high yield.

[0042] Density can usually be characterized by refractive index testing or infrared spectroscopy. Specifically, for the same material, a higher density generally means a higher refractive index for light.

[0043] As some examples of this embodiment, the total thickness of the first tunneling layer and the second tunneling layer can be 1.5nm, 1.7nm, 2nm, 2.2nm, 2.5nm, 2.7nm, or 3nm, or the total thickness of the first tunneling layer and the second tunneling layer can be between any two of the above thicknesses.

[0044] As examples of this embodiment, the refractive index of the first tunneling layer 110 is greater than that of the second tunneling layer 120, and the refractive index of the first tunneling layer 110 is 1.46~1.47. The silicon oxide material in the first tunneling layer 110 with a refractive index of 1.46~1.47 is relatively dense, providing better passivation performance. Furthermore, the first tunneling layer 110 has a stronger barrier effect against atoms such as dopants, preventing component diffusion across the stacked tunneling structure.

[0045] In this example, optionally, the refractive index of the first tunneling layer 110 is 1.461, 1.462, 1.463, 1.464, 1.465, 1.466, 1.467, 1.468, 1.469, or 1.47, or the refractive index of the first tunneling layer 110 may be between any two of the above refractive indices.

[0046] As an example of this embodiment, the refractive index of the second tunneling layer 120 is 1.45 to 1.46. The silicon oxide material in the second tunneling layer 120 with a refractive index of 1.45 to 1.46 is relatively porous, making it easier to form tiny pinholes inside, which is more conducive to electron transport and further improves the electron transport capability of the stacked tunneling structure.

[0047] In this example, optionally, the refractive index of the second tunneling layer 120 is 1.451, 1.452, 1.453, 1.454, 1.455, 1.456, 1.457, 1.458, 1.459, or 1.46, or the refractive index of the second tunneling layer 120 may be between any two of the above refractive indices.

[0048] As examples of this embodiment, the thickness of the first tunneling layer 110 is less than the thickness of the second tunneling layer 120. The first tunneling layer 110 is mainly used to improve the passivation effect and block the diffusion of heteroatoms. Using a thinner first tunneling layer 110 can ensure a high passivation effect and blocking capability, and also helps to reduce the negative impact of a dense first tunneling layer 110 on electron transport performance. The second tunneling layer 120 is mainly used to ensure electron transport capability and to buffer the first tunneling layer 110. A thicker second tunneling layer 120 is more conducive to ensuring electron transport capability while playing a more effective buffering role, thereby improving the production yield of this stacked tunneling structure.

[0049] As an example of this embodiment, the thickness of the first tunneling layer 110 is 0.2 nm to 1 nm. This thickness of the first tunneling layer 110 can provide a good passivation effect and blocking ability, and is also conducive to electron tunneling.

[0050] In this example, optionally, the thickness of the first tunneling layer 110 is 0.2nm, 0.3nm, 0.4nm, 0.5nm, 0.6nm, 0.7nm, 0.8nm, 0.9nm, or 1nm, or the thickness of the first tunneling layer 110 may be between any two of the above thicknesses.

[0051] As some examples of this embodiment, the thickness of the second tunneling layer 120 is 1.3 nm to 1.8 nm. This thickness of the second tunneling layer 120 can provide good buffering capacity, and at the same time, it is beneficial to ensure that the overall stacked tunneling structure has strong electronic transport capability.

[0052] In this example, optionally, the thickness of the second tunneling layer 120 is 1.3nm, 1.35nm, 1.4nm, 1.45nm, 1.5nm, 1.55nm, 1.6nm, 1.65nm, 1.7nm, 1.75nm, or 1.8nm, or the thickness of the second tunneling layer 120 may be between any two of the above thicknesses.

[0053] In this embodiment, the thickness and refractive index of the first tunneling layer 110 and the second tunneling layer 120 are tested using an ellipsometer. For example, an SE850 ellipsometer can be used for testing, with a thickness measurement accuracy of 0.01nm~0.03nm and a refractive index measurement accuracy of 0.0005.

[0054] The stacked tunneling structure in this embodiment consists of a first tunneling layer 110 and a second tunneling layer 120. However, in other embodiments, the stacked tunneling structure may also include more silicon oxide-containing tunneling layers.

[0055] For example, in some embodiments, the stacked tunneling structure may have multiple second tunneling layers 120, which have the same density and are stacked sequentially on the first tunneling layer 110 in a direction away from the first tunneling layer 110.

[0056] Alternatively, in some other embodiments, the stacked tunneling structure may further include a supplementary tunneling layer, which may be stacked on the side of the second tunneling layer 120 away from the first tunneling layer 110, and the density of the supplementary tunneling layer is less than the density of the second tunneling layer 120.

[0057] Alternatively, in some other embodiments, the stacked tunneling structure may further include multiple supplementary tunneling layers, which may be stacked sequentially on the side of the second tunneling layer 120 away from the first tunneling layer 110, and the density of the multiple supplementary tunneling layers decreases sequentially along the direction away from the first tunneling layer 110.

[0058] The stacked tunneling structure in this embodiment can be used to form a solar cell. Another embodiment of this disclosure also provides a solar cell including a semiconductor substrate 200 and the stacked tunneling structure described in the above embodiment. The stacked tunneling structure is stacked on the semiconductor substrate 200.

[0059] Figure 2 This is a schematic diagram of the cross-sectional structure of a solar cell. (Refer to...) Figure 2 As shown, the solar cell in this embodiment of the present disclosure includes a semiconductor substrate 200 and, as shown in the figure, ... Figure 1The stacked tunneling structure is disposed on the semiconductor substrate 200. The semiconductor substrate 200 is used to receive light and generate photogenerated carriers, and the stacked tunneling structure is used to passivate the surface of the semiconductor substrate 200. Electrons in the semiconductor substrate 200 can tunnel through the stacked tunneling structure, thus the stacked tunneling structure can reduce the recombination loss of photogenerated carriers in the semiconductor substrate 200.

[0060] As some examples of this embodiment, the material of the semiconductor substrate 200 may include silicon. For example, the semiconductor substrate 200 may be a silicon wafer.

[0061] Reference Figure 2 As shown, as some examples of this embodiment, the solar cell further includes a silicon-doped layer 210, which is stacked on the side of the multilayer tunneling structure away from the semiconductor substrate 200. The silicon-doped layer 210 serves as a contact structure to reduce contact resistance and improve electron conductivity.

[0062] As examples of this embodiment, the doping type of the silicon material layer 210 can be N-type. Correspondingly, the doping type of the semiconductor substrate 200 can also be N-type. The doping concentration of the silicon material layer 210 can be higher than the doping concentration of the semiconductor substrate 200.

[0063] Reference Figure 2 As shown, as some examples of this embodiment, the solar cell may further include a first electrode 230. The first electrode 230 is disposed on the side of the doped silicon material layer 210 away from the semiconductor substrate 200, and the first electrode 230 is in ohmic contact with the doped silicon material layer 210. The first electrode 230 is used to conduct charge carriers in the doped silicon material layer 210 to an external circuit.

[0064] Reference Figure 2 As shown, as some examples of this embodiment, the solar cell may further include an emitter layer 220 disposed on the side of the semiconductor substrate 200 away from the stacked tunneling structure. The doping type of the emitter layer 220 is different from the doping type of the semiconductor substrate 200. For example, in this embodiment, the doping type of the emitter layer 220 is P-type.

[0065] Reference Figure 2 As shown, as some examples of this embodiment, the semiconductor substrate 200 may have a light-facing surface and a back-light surface disposed opposite to each other. The light-facing surface of the semiconductor substrate 200 has a textured structure, which is used to improve the light absorption performance of the semiconductor substrate 200. Furthermore, the emitter layer 220 may be disposed on the light-facing surface, and the stacked tunneling structure may be disposed on the back-light surface.

[0066] Reference Figure 2As shown, as some examples of this embodiment, the solar cell may further include a second electrode 240. The second electrode 240 is disposed on the side of the emitter layer 220 away from the semiconductor substrate 200, and the second electrode 240 is in ohmic contact with the emitter layer 220. The second electrode 240 is used to conduct charge carriers in the emitter layer 220 to an external circuit.

[0067] In this embodiment, a stacked tunneling structure is disposed on one side of the semiconductor substrate 200. This stacked tunneling structure includes a first tunneling layer 110 with high density and a second tunneling layer 120 with low density. The high-density first tunneling layer 110 ensures that the stacked tunneling structure as a whole has a good passivation effect and prevents the diffusion of dopant atoms into the semiconductor substrate 200, thereby reducing Auger recombination. As a result, this ensures that the solar cell has a high open-circuit voltage. The low-density second tunneling layer 120 ensures that the stacked tunneling structure has good electron transport performance. As a result, this ensures that the solar cell has a high fill factor.

[0068] Reference Figure 2 As shown, as examples of this embodiment, the first tunneling layer 110 and the second tunneling layer 120 are sequentially stacked along a direction away from the semiconductor substrate 200. Placing the denser first tunneling layer 110 closer to the semiconductor substrate 200 has the following advantages: firstly, the denser first tunneling layer 110 can be formed by chemical oxidation, which makes the fabrication process of the stacked tunneling structure more compatible with current processes and reduces process difficulty; secondly, the denser first tunneling layer 110 can directly contact the semiconductor substrate 200, providing a better passivation effect.

[0069] In another aspect, this disclosure also provides a method for preparing a solar cell. Figure 3 This is a schematic diagram illustrating the steps of a method for fabricating a solar cell according to an embodiment. (Refer to...) Figure 3 As shown, the method for preparing this solar cell includes steps S1 to S3.

[0070] Step S1, providing a semiconductor substrate 200 including silicon.

[0071] In this embodiment, the semiconductor substrate 200 may be a silicon wafer.

[0072] As some examples of this embodiment, the preparation method may further include: performing a pre-acid pickling treatment on the semiconductor substrate 200. The pre-acid pickling treatment may be performed using a chain-type equipment, and the cleaning solution used in the pre-acid pickling treatment includes hydrofluoric acid. The pre-acid pickling treatment is used to remove contaminants from the surface of the semiconductor substrate 200, ensuring that the surface of the semiconductor substrate 200 is relatively clean.

[0073] In this example, after the semiconductor substrate 200 is pre-washed, it can also be washed with water and dried for use in subsequent processes.

[0074] As some examples of this embodiment, the preparation method may further include: pre-cleaning the semiconductor substrate 200. The pre-cleaning process may be performed using a tank-type apparatus. The cleaning solution used in the pre-cleaning process includes alkali and hydrogen peroxide. The pre-cleaning process is used to further remove oil and impurities from the surface of the semiconductor substrate 200.

[0075] In this example, after the semiconductor substrate 200 is pre-cleaned, it can also be washed with water to remove the cleaning solution remaining on the surface of the semiconductor substrate 200.

[0076] As some examples of this embodiment, the preparation method may further include: performing an alkaline polishing treatment on the semiconductor substrate 200. The alkaline polishing treatment may be performed using a tank-type equipment. The cleaning solution used in the alkaline polishing treatment includes alkali, and the alkali concentration in the cleaning solution used in the alkaline polishing treatment is higher than the alkali concentration in the cleaning solution used in the pre-cleaning treatment. The alkaline polishing treatment is used to remove the oxide layer on the surface of the semiconductor substrate 200.

[0077] In this example, after the semiconductor substrate 200 is subjected to alkaline polishing, it can also be washed with water to remove the cleaning solution remaining on the surface of the semiconductor substrate 200.

[0078] As some examples of this embodiment, the preparation method may further include: performing a post-cleaning treatment on the semiconductor substrate 200. The post-cleaning treatment may be performed using a tank-type apparatus. The cleaning solution used in the post-cleaning treatment includes an alkali, and the cleaning solution used in the post-cleaning treatment may be the same as the cleaning solution used in the pre-cleaning treatment.

[0079] In this example, after the semiconductor substrate 200 is post-cleaned, it can also be washed with water to remove the cleaning solution remaining on the surface of the semiconductor substrate 200.

[0080] Step S2 involves performing an oxidation-removing acid wash on the semiconductor substrate 200, followed by an oxidation treatment on the silicon therein to form a first tunneling layer 110 including silicon oxide.

[0081] After a preliminary cleaning process, the surface of the semiconductor substrate 200 is typically exposed to air, forming a thin, uneven, and loose native oxide layer. In this embodiment, an oxidation-removing acid pickling process is used to remove this native oxide layer from the surface of the semiconductor substrate 200. This native oxide layer can affect and hinder the subsequent oxide layer fabrication process, thus impacting the quality of the stacked tunneling structure.

[0082] As examples of this embodiment, the deoxidation pickling process can be performed using a tank-type equipment, and the cleaning solution used in the deoxidation pickling process includes hydrofluoric acid. In addition to removing the natural oxide layer, hydrofluoric acid can also remove residual metal ions on the silicon wafer surface, including but not limited to sodium and potassium ions, thereby improving the efficiency of solar cells.

[0083] In this example, after the semiconductor substrate 200 is subjected to deoxidation acid pickling, it can also be washed with water to remove the cleaning solution remaining on the surface of the semiconductor substrate 200.

[0084] It is understood that oxidizing silicon in the semiconductor substrate 200 can form a controllable and dense silicon oxide layer on the surface of the semiconductor substrate 200, and the formed silicon oxide layer can serve as the first tunneling layer 110. In this embodiment, the first tunneling layer 110 can be an entire film layer, and the first tunneling layer 110 can cover the entire surface of the semiconductor substrate 200.

[0085] In this embodiment, the step of oxidizing the silicon in the semiconductor substrate 200 can be performed immediately after the deoxidation and acid washing process. The deoxidation and acid washing process can remove the original oxide layer on the surface of the semiconductor substrate 200, exposing the relatively unstable silicon atoms on the surface of the semiconductor substrate 200. These silicon atoms are more easily oxidized during the oxidation process, thereby forming dense silicon oxide.

[0086] As examples of this embodiment, the silicon in the semiconductor substrate 200 can be oxidized using an oxidizing solution, including one or more of hydrogen peroxide and nitric acid. Hydrogen peroxide and nitric acid have strong oxidizing properties and can react with silicon atoms to form a dense silicon oxide film. It is understood that oxidation using an oxidizing solution can be carried out in a tank-type equipment, making this oxidation process easier to integrate into existing cleaning processes, thereby simplifying the production flow. Nitric acid is advantageous for forming a denser silicon oxide film. However, nitric acid is volatile and the reaction products contain polluting gases such as nitrogen oxides, which is detrimental to practical production applications.

[0087] As some examples of this embodiment, the step of oxidizing silicon in semiconductor substrate 200 includes: placing semiconductor substrate 200 in an oxidizing solution containing hydrogen peroxide to oxidize silicon in semiconductor substrate 200.

[0088] In this example, during the oxidation process of silicon in the semiconductor substrate 200, the molar concentration of hydrogen peroxide in the oxidizing solution is 0.09 mol / L to 1 mol / L. For example, the molar concentration of hydrogen peroxide can be 0.09 mol / L, 0.1 mol / L, 0.2 mol / L, 0.3 mol / L, 0.4 mol / L, 0.5 mol / L, 0.7 mol / L, 0.9 mol / L, or 1 mol / L, or it can be between any two of these concentrations. Using this concentration of hydrogen peroxide is beneficial for controlling the reaction process and forming a dense and uniformly thick silicon oxide film. Using a relatively low concentration of hydrogen peroxide is beneficial for forming a relatively dense silicon oxide film, but its formation rate is slower. Using a relatively high concentration of hydrogen peroxide results in a faster silicon oxide film formation rate, but the density is relatively low, and there may be problems with poor uniformity.

[0089] In this example, during the step of oxidizing the silicon in the semiconductor substrate 200, the temperature of the oxidizing solution is controlled to be between 40°C and 65°C. For example, the temperature of the oxidizing solution can be controlled to be 40°C, 45°C, 50°C, 55°C, 60°C, or 65°C, or the temperature of the oxidizing solution can be between any two of the above temperatures.

[0090] In this example, during the step of oxidizing the silicon in the semiconductor substrate 200, the oxidation time is controlled to be between 30s and 300s. For example, the oxidation time can be controlled to be 30s, 50s, 70s, 100s, 120s, 150s, 180s, 200s, 250s, or 300s, or the oxidation time can be between any two of the above times. By controlling the oxidation time, the thickness of the formed first tunneling layer 110 can be controlled accordingly.

[0091] As some examples of this embodiment, the step of oxidizing silicon in semiconductor substrate 200 includes: placing semiconductor substrate 200 in an atmosphere of oxidizing gas and heating semiconductor substrate 200 to oxidize silicon in semiconductor substrate 200. A relatively dense silicon oxide film can also be formed on the silicon surface through thermal oxidation.

[0092] In this example, the oxidizing gas may include oxygen. The temperature at which the semiconductor substrate 200 is heated can be between 900°C and 1200°C. For example, the temperature at which the semiconductor substrate 200 is heated can be 900°C, 950°C, 1000°C, 1050°C, 1100°C, 1150°C, or 1200°C. Alternatively, the temperature at which the semiconductor substrate 200 is heated may be between any two of the above temperatures.

[0093] As some examples of this embodiment, when the semiconductor substrate 200 is placed in an atmosphere of oxidizing gas, the atmosphere of oxidizing gas may also include water vapor. Water vapor can promote the oxidation of silicon.

[0094] In this embodiment, the thickness of the first tunneling layer 110 is 0.2 nm to 1 nm. Optionally, the thickness of the first tunneling layer 110 is 0.2 nm, 0.3 nm, 0.4 nm, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, or 1 nm, or the thickness of the first tunneling layer 110 may be between any two of the above thicknesses.

[0095] In this embodiment, the refractive index of the first tunneling layer 110 is 1.46 to 1.47. Optionally, the refractive index of the first tunneling layer 110 is 1.461, 1.462, 1.463, 1.464, 1.465, 1.466, 1.467, 1.468, 1.469, or 1.47, or the refractive index of the first tunneling layer 110 may be between any two of the above refractive indices.

[0096] In step S3, a second tunneling layer 120 is formed on the side of the first tunneling layer 110 away from the semiconductor substrate 200 by vapor deposition.

[0097] The vapor deposition method can be either chemical vapor deposition (CVD) or physical vapor deposition (PVD). In this embodiment, CVD can be used to form the second tunneling layer 120. Further, plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) can be used to deposit silicon oxide material to form the second tunneling layer 120.

[0098] It is understandable that compared to silicon oxide formed by directly oxidizing the semiconductor substrate 200, silicon oxide formed by chemical vapor deposition has a relatively low density. Therefore, the deposited silicon oxide can be used as the second tunneling layer 120.

[0099] As some examples of this embodiment, the step of forming the second tunneling layer 120 includes: placing the semiconductor substrate 200 in a coating chamber, introducing a gas including a silicon source and an oxygen source into the coating chamber, and forming the second tunneling layer 120 by reacting the silicon source and the oxygen source.

[0100] As examples of this embodiment, in the step of forming the second tunneling layer 120, the silicon source flow rate is 100 sccm to 1000 sccm, and the oxygen source flow rate is 7 slm to 12 slm. Using silicon and oxygen source flow rates at these levels is beneficial for forming a silicon oxide film with good film quality. Specifically, when the silicon and oxygen source flow rates are relatively low, the density of the silicon oxide film is relatively high, but the deposition rate is slow. When the silicon and oxygen source flow rates are relatively high, the formation rate of the silicon oxide film is fast, but the density is relatively low.

[0101] In this example, the silicon source can be selected from hydrides, such as silanes. The oxygen source can be selected from nitrogen oxides, such as nitrous oxide.

[0102] As some examples of this embodiment, the refractive index of the second tunneling layer 120 is 1.45 to 1.46. Optionally, the refractive index of the second tunneling layer 120 is 1.451, 1.452, 1.453, 1.454, 1.455, 1.456, 1.457, 1.458, 1.459, or 1.46, or the refractive index of the second tunneling layer 120 may be between any two of the above refractive indices.

[0103] As some examples of this embodiment, the thickness of the second tunneling layer 120 is 1.3 nm to 1.8 nm. Optionally, the thickness of the second tunneling layer 120 is 1.3 nm, 1.35 nm, 1.4 nm, 1.45 nm, 1.5 nm, 1.55 nm, 1.6 nm, 1.65 nm, 1.7 nm, 1.75 nm, or 1.8 nm, or the thickness of the second tunneling layer 120 may be between any two of the above thicknesses.

[0104] In this example, the deposition time can be controlled to be 80s to 100s when forming the second tunneling layer 120. Optionally, the deposition time can be 80s, 82s, 85s, 88s, 90s, 92s, 95s, 98s, or 100s, or the deposition time can be between any two of the above times.

[0105] As some examples of this embodiment, after forming the second tunneling layer 120, the following steps are also included: depositing a doped silicon material layer 210 on the side of the second tunneling layer 120 away from the semiconductor substrate 200.

[0106] In this example, the doped silicon material layer 210 can be deposited using chemical vapor deposition. The doped silicon material layer 210 and the second tunneling layer 120 can be formed sequentially in the same deposition chamber, so that the doped silicon material layer 210 is in direct contact with the second tunneling layer 120.

[0107] In traditional processes, silicon wafers are alkali-polished and acid-washed before being transferred to a coating chamber to deposit silicon oxide as a tunneling oxide layer. The applicant's research has revealed that acid washing exposes silicon atoms on the wafer surface, making them susceptible to oxidation in air. This results in the formation of a non-dense, uneven, and incomplete oxide layer. This oxide affects the quality of the subsequently deposited tunneling oxide layer, ultimately impacting the efficiency of the solar cell.

[0108] In the solar cell fabrication method disclosed herein, a relatively dense and uniform silicon oxide layer 110 is pre-formed as a first tunneling layer 110 through chemical oxidation, and then a second tunneling layer 120 is formed on top of the first tunneling layer 110 by deposition, which improves the deposition quality of the second tunneling layer 120. Furthermore, the high density of the first tunneling layer 110 ensures that the stacked tunneling structure has a good passivation effect and prevents the diffusion of dopant atoms into the semiconductor substrate 200, thereby reducing Auger recombination. As a result, this ensures that the solar cell has a high open-circuit voltage. The lower density of the second tunneling layer 120 ensures that the stacked tunneling structure has good electron transport performance. As a result, this ensures that the solar cell has a high fill factor.

[0109] Furthermore, in this embodiment, the step of forming the first tunneling layer 110 is performed after the deoxidation and acid washing treatment. After the formation of the first tunneling layer 110, the second tunneling layer 120 is subsequently deposited in the coating chamber. This process can be well integrated with the cleaning process in conventional technology, without requiring excessive transfer of the semiconductor substrate 200, nor requiring additional equipment or production lines. Therefore, this preparation method is relatively simple.

[0110] As some examples of this embodiment, the method for fabricating the solar cell may further include the step of forming an emitter layer 220 on the light-facing surface of the semiconductor substrate 200. The method may also include the step of forming a first electrode 230 and a second electrode 240 on opposite side surfaces of the semiconductor substrate 200, respectively.

[0111] Through the above steps S1 to S3, the following can be prepared: Figure 2 The solar cell shown.

[0112] This disclosure also provides the following more specific embodiments and comparative examples to further demonstrate the advantages of the stacked tunneling structure and corresponding solar cells in this disclosure.

[0113] Example 1

[0114] An N-type silicon wafer with a thickness of 130 μm is provided as the semiconductor substrate.

[0115] The semiconductor substrate is cleaned according to the following process: pre-acid pickling, water rinsing, drying, pre-cleaning, water rinsing, alkaline polishing, water rinsing, post-cleaning, water rinsing, deoxidation acid pickling, and water rinsing. The pre-acid pickling and deoxidation acid pickling processes use cleaning solutions containing hydrofluoric acid, while the pre-cleaning, alkaline polishing, and post-cleaning processes use cleaning solutions containing sodium hydroxide.

[0116] The semiconductor substrate, after deoxidation and acid washing, is placed in an oxidizing solution, which is an aqueous solution of hydrogen peroxide with a concentration of 0.4 mol / L. The oxidation temperature is 50°C and the oxidation time is 120 s, forming silicon oxide on the back surface of the semiconductor substrate as the first tunneling layer. Then, it is sequentially washed with water, slowly pulled, and dried for later use.

[0117] The oxidized semiconductor substrate is transferred to the coating chamber, and silane and nitrous oxide are introduced into the coating chamber. The silane flow rate is controlled at 200 sccm and the nitrous oxide flow rate is controlled at 8.5 slm. Silicon oxide is deposited on the back surface of the semiconductor substrate as a second tunneling layer for 90 s.

[0118] Stop the nitrous oxide flow, adjust the silane flow rate to 2.5 slm, and introduce phosphine at a flow rate of 600 sccm. Deposit an N-type doped silicon material layer on the back surface of the semiconductor substrate for 300 s.

[0119] A P-type doped silicon material layer is deposited on the light-facing surface of a semiconductor substrate as an emitter.

[0120] Antireflection films and passivation films are fabricated on the light-facing and back-facing surfaces of a semiconductor substrate, respectively, and gate electrodes are screen-printed.

[0121] Example 2

[0122] Example 2 is basically the same as Example 1, the main difference being that: the oxidation time is 50s when placed in an oxidizing solution for oxidation treatment, and the deposition time is 110s when silicon oxide is deposited in the coating chamber, forming a first tunneling layer with a thickness of 0.2nm and a second tunneling layer with a thickness of 1.8nm respectively.

[0123] Example 3

[0124] Example 3 is basically the same as Example 1, the main difference being that: the oxidation time is 190s when placed in an oxidizing solution for oxidation treatment, and the deposition time is 70s when silicon oxide is deposited in the coating chamber, forming a first tunneling layer with a thickness of 0.8nm and a second tunneling layer with a thickness of 1.2nm respectively.

[0125] Example 4

[0126] Example 4 is basically the same as Example 1, except that when it is placed in an oxidizing solution for oxidation treatment, the concentration of hydrogen peroxide is 1.2 mol / L and the oxidation time is shortened to 30 s.

[0127] Example 5

[0128] Example 5 is basically the same as Example 1, the main difference being that when depositing silicon oxide in the coating chamber, the silane flow rate is 100 sccm, the nitrous oxide flow rate is controlled at 4.25 slm, and the deposition time is 200 s.

[0129] Example 6

[0130] Example 6 is basically the same as Example 1, the main difference being that when the semiconductor substrate after deoxidation and acid washing is placed in an oxidizing solution for oxidation treatment, the oxidizing solution is an aqueous solution of nitric acid, wherein the mass concentration of nitric acid is 10%, the oxidation time is 60s, and the thickness of the first tunneling layer remains unchanged.

[0131] Example 7

[0132] Example 7 is basically the same as Example 1, the main difference being that after deoxidation and acid washing, the semiconductor substrate is placed in an oxygen atmosphere and heated to 960°C for 300 seconds, while the thickness of the first tunneling layer remains unchanged.

[0133] Comparative Example 1

[0134] Comparative Example 1 is basically the same as Example 1, except that: Comparative Example 1 forms a first tunneling layer with a thickness of 2 nm during oxidation treatment, and does not prepare a second tunneling layer.

[0135] Comparative Example 2

[0136] Comparative Example 2 is basically the same as Example 1, except that: Comparative Example 2 does not prepare a first tunneling layer, but prepares a second tunneling layer with a thickness of 2nm when depositing silicon oxide.

[0137] Experiment 1: The thickness and refractive index of the first tunneling layer and the thickness and refractive index of the second tunneling layer in each embodiment and comparative example were tested, and the results are shown in Table 1.

[0138] Experiment 2: The efficiency, open-circuit voltage, short-circuit current, and fill factor of the solar cells prepared in each embodiment and comparative example were tested. The results are shown in Table 2.

[0139] Table 1

[0140]

[0141] Table 2

[0142]

[0143] Based on the information presented in Tables 1 and 2, Comparative Example 1 used only a first tunneling layer with high density as the tunneling dielectric layer, while Comparative Example 2 used only a second tunneling layer with low density. Specifically, Comparative Example 1 exhibited a significantly lower short-circuit current, indicating poor electron transport capability, while Comparative Example 2 showed a significantly lower open-circuit voltage, indicating poor passivation performance. Compared to Comparative Examples 1 and 2, Examples 1 through 7 all employed a stacked design of first and second tunneling layers. Furthermore, the fill factor and efficiency of Examples 1 through 7 were significantly higher than those of Comparative Examples 1 and 2, demonstrating that the solar cells of Examples 1 through 7 can improve passivation performance while maintaining electron transport performance, ultimately resulting in improved fill factor and conversion efficiency.

[0144] Compared to Example 1, Example 2 uses a thinner first tunneling layer and a thicker second tunneling layer, resulting in a lower fill factor. This is mainly due to a reduced passivation effect, leading to a lower open-circuit voltage, while the short-circuit current remains essentially unchanged. Example 3 uses a thicker first tunneling layer and a thinner second tunneling layer, also resulting in a lower fill factor, primarily due to reduced electron transport performance. In Example 5, the higher refractive index (density) of the second tunneling layer also leads to a decrease in short-circuit current.

[0145] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this document.

[0146] It should be understood that, unless otherwise expressly stated herein, there is no strict order in which the steps are performed, and these steps may be performed in other orders. Moreover, at least some steps in the preparation process may include multiple sub-steps or multiple stages, which are not necessarily completed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0147] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0148] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A stacked tunneling structure, characterized in that, The device includes a first tunneling layer and a second tunneling layer stacked together. Both the first tunneling layer and the second tunneling layer are made of silicon oxide. The total thickness of the first tunneling layer and the second tunneling layer is ≤3nm. The density of silicon oxide in the first tunneling layer is greater than the density of silicon oxide in the second tunneling layer.

2. The stacked tunneling structure according to claim 1, characterized in that, The refractive index of the first tunneling layer is greater than that of the second tunneling layer, and the refractive index of the first tunneling layer is 1.46~1.

47.

3. The stacked tunneling structure according to claim 2, characterized in that, The refractive index of the second tunneling layer is 1.45~1.

46.

4. The stacked tunneling structure according to any one of claims 1 to 3, characterized in that, The thickness of the first tunneling layer is less than the thickness of the second tunneling layer.

5. The stacked tunneling structure according to claim 4, characterized in that, The thickness of the first tunneling layer is 0.2 nm to 1 nm.

6. The stacked tunneling structure according to claim 5, characterized in that, The thickness of the second tunneling layer is 1.3 nm to 1.8 nm.

7. A solar cell, characterized in that, It includes a semiconductor substrate and a stacked tunneling structure as described in any one of claims 1 to 6, wherein the stacked tunneling structure is stacked on the semiconductor substrate.

8. The solar cell according to claim 7, characterized in that, The semiconductor substrate is made of silicon, and the solar cell further includes a silicon-doped material layer, which is stacked on the side of the stacked tunneling structure away from the semiconductor substrate.

9. The solar cell according to any one of claims 7 to 8, characterized in that, The first tunneling layer and the second tunneling layer are stacked sequentially along a direction away from the semiconductor substrate.

10. A method for preparing a solar cell, characterized in that, Includes the following steps: Provides semiconductor substrates including silicon; The semiconductor substrate is subjected to an oxidation-removing acid pickling process, and then the silicon therein is oxidized to form a first tunneling layer including silicon oxide. A second tunneling layer comprising silicon oxide is formed on the side of the first tunneling layer away from the semiconductor substrate by vapor deposition, wherein the density of silicon oxide in the first tunneling layer is greater than the density of silicon oxide in the second tunneling layer.

11. The method for preparing a solar cell according to claim 10, characterized in that, The step of oxidizing silicon in the semiconductor substrate includes: placing the semiconductor substrate in an atmosphere of oxidizing gas, and heating the semiconductor substrate to oxidize the silicon in the semiconductor substrate; or, The step of oxidizing silicon in the semiconductor substrate includes: oxidizing silicon in the semiconductor substrate with an oxidizing solution, wherein the oxidizing solution includes one or more of hydrogen peroxide and nitric acid.

12. The method for preparing a solar cell according to claim 11, characterized in that, In the step of heating the semiconductor substrate, the heating temperature is controlled to be 900℃~1200℃; In the step of oxidizing the silicon in the semiconductor substrate with an oxidizing solution, the oxidizing solution includes hydrogen peroxide, and the molar concentration of hydrogen peroxide is 0.09 mol / L to 1 mol / L.

13. The method for preparing a solar cell according to any one of claims 10 to 12, characterized in that, The step of forming the second tunneling layer includes: placing the semiconductor substrate in a coating chamber, introducing a gas including a silicon source and an oxygen source into the coating chamber, and forming the second tunneling layer by reacting the silicon source and the oxygen source; optionally, the flow rate of the silicon source is 100 sccm to 1000 sccm, and the flow rate of the oxygen source is 7 slm to 12 slm.

14. The method for preparing a solar cell according to any one of claims 10 to 12, characterized in that, The cleaning solution for deoxidizing and acid-washing silicon in the semiconductor substrate includes hydrofluoric acid; and / or, Before cleaning the silicon in the semiconductor substrate, the process includes an alkaline polishing step on the semiconductor.

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