Anode capable of reducing non-uniform spin coating and preparation method thereof

Abstract

The invention discloses an anode capable of reducing non-uniform spin coating and a preparation method thereof, and belongs to the technical field of Micro OLED display, the anode capable of reducing non-uniform spin coating comprises a CMOS substrate, an insulating dielectric layer, a conductive adhesive and an anode; a tungsten hole is formed in the CMOS substrate; the insulating dielectric layer is deposited on the CMOS substrate and covers the tungsten hole; a first pit and a second pit located above the first pit are sequentially formed in the portion, above the tungsten hole, of the insulating medium layer. The opening area of the second pit is larger than that of the first pit; the conductive adhesive is filled in the first pit and is used for realizing electrical connection between the first pit and the tungsten hole; the anode is deposited and completely filled in the second pit and is electrically connected with the tungsten hole through the conductive adhesive, and the morphology of the second pit is suitable for reducing the non-uniformity of the adhesive in the subsequent spin-coating process; according to the design, the anode and the surface of the CMOS substrate can be horizontal, the influence of non-uniform spin coating in a subsequent process section on the appearance of a product is reduced, and the competitiveness of the product is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of Micro OLED display, and particularly relates to an anode for reducing spin coating unevenness and a preparation method thereof. BACKGROUND

[0002] Micro OLED display technology has become the core solution in high-end fields such as AR / VR near-eye display and special military equipment, due to its ultra-high resolution (PPI≥2000), fast response and miniaturization. In the preparation process, the spin coating process is used to form the organic light-emitting layer and the encapsulation layer, and the uniformity of the coating layer directly determines the display quality. Even a nanoscale thickness deviation may cause Mura (uneven brightness / color), which seriously affects the product yield. The prior art such as patent comparison document CN116249420A discloses an anode for reducing spin coating unevenness and a preparation method thereof, which proposes to etch a pit and deposit an anode to improve the flatness of the substrate surface. Although this scheme reduces the surface undulation to a certain extent, it still has the following technical defects:

[0003] The pit and the anode thickness matching precision is insufficient: in the comparison document, the pit depth is controlled by single etching, while the anode deposition thickness has a ±5nm deviation affected by PVD process (such as target material consumption and sputtering power fluctuation), which makes it difficult for the anode surface to be truly flush with the insulating layer (SIO / SIN), and flow field disturbance still exists during spin coating;

[0004] The tungsten hole connection reliability is poor: in the comparison document, the electrical connection between the tungsten hole and the anode relies on direct contact, and no transition structure is designed for the insulating layer step around the tungsten hole, which leads to large fluctuation of the conductive contact resistance and affects the pixel driving consistency;

[0005] Process compatibility is limited: the existing patent uses single etching to form a pit, and for SIO / SIN composite film layers with a thickness of ≥2μm, the film layer stress is easily concentrated due to excessive etching depth, and cracks are easily generated;

[0006] In view of the deficiencies of the prior art, the application provides an anode for reducing spin coating unevenness and a preparation method thereof, aiming to solve the above problems. SUMMARY

[0007] The application aims to overcome the deficiencies in the prior art, and provides an anode for reducing spin coating unevenness and a preparation method thereof, which can make the anode and the surface of the CMOS substrate level, reduce the influence of spin coating unevenness in the subsequent process section on the appearance of the product, and improve the competitiveness of the product.

[0008] To achieve the above-mentioned purpose, in a first aspect, the application provides an anode for reducing spin coating unevenness, comprising:

[0009] A CMOS substrate provided with a tungsten hole;

[0010] An insulating medium layer deposited on the CMOS substrate and covering the tungsten hole; the insulating medium layer is provided with a first recess and a second recess above the first recess in sequence above the tungsten hole; and the opening area of the second recess is greater than that of the first recess;

[0011] A conductive glue filled in the first recess for electrically connecting the first recess with the tungsten hole;

[0012] and an anode deposited and completely filled in the second recess and electrically connected with the tungsten hole through the conductive glue, wherein the topography of the second recess is suitable for reducing the non-uniformity of the glue in a subsequent spin coating process.

[0013] In combination with the first aspect, the insulating medium layer includes but is not limited to SIO / SIN film layers.

[0014] In combination with the first aspect, after chemical mechanical polishing, the anode is still conformally filled in the second recess, and the upper surface thereof is flush with the upper surface of the insulating medium layer.

[0015] In combination with the first aspect, the depth of the second recess is 50-200 nm, and after chemical mechanical polishing, the difference between the remaining thickness of the anode and the depth is ≤5 nm.

[0016] In combination with the first aspect, the material of the anode is ITO, AZO or Ag nanowire conductive layer, and the light transmittance under a visible light band and a wavelength of 550 nm is ≥85%.

[0017] The second aspect provides a preparation method of an anode for reducing spin coating non-uniformity, applied to the anode for reducing spin coating non-uniformity of the first aspect, and the preparation method includes the following steps:

[0018] S1: providing a CMOS substrate provided with a tungsten hole;

[0019] S2: depositing an insulating medium layer on the CMOS substrate to cover the tungsten hole;

[0020] S3: etching a first recess above the tungsten hole of the insulating medium layer;

[0021] S4: filling a conductive glue into the first recess to electrically connect the conductive glue with the tungsten hole;

[0022] S5: etching a second recess on the insulating medium layer, the opening area of the second recess is greater than that of the first recess, and the depth thereof matches the thickness of the anode to be deposited;

[0023] S6: depositing an anode material in the second recess by a PVD method;

[0024] S7: removing the excess anode material outside the second recess by etching, and then performing a CMP treatment to make the surface of the anode flush with the surface of the insulating medium layer;

[0025] S8: after the CMP treatment, continuing to perform subsequent processes, including deposition of an organic light-emitting layer, formation of a thin film encapsulation (TFE) layer, a first organic planarization layer (OC1), a color filter (CF) layer, a second organic planarization layer (OC2), an adhesion layer (OCR), a cover plate (CG), and cutting to obtain a display module.

[0026] In combination with the second aspect, the insulating medium layer includes but is not limited to an SIO / SIN film layer; the deposition method of the SIO / SIN film layer includes but is not limited to ALD, PECVD or PVD, wherein the thickness of the SiO2 layer is 0.5-2 μm, and the thickness of the SiN layer is 0.5-3 μm.

[0027] In combination with the second aspect, the etching method in S3 and S5 includes but is not limited to dry etching, and the depth of the second recess is 50-200 nm.

[0028] In combination with the second aspect, the filling method of the conductive adhesive in S4 is inkjet printing or etching filling, and the conductive adhesive is baked and solidified at 100-150 °C after filling.

[0029] In combination with the second aspect, after the CMP treatment, the height difference between the upper surface of the anode and the upper surface of the insulating medium layer is ≤5 nm.

[0030] Compared with the prior art, the present application has the following beneficial effects:

[0031] 1. The present application realizes precise matching by the combined process of "two etching + CMP polishing", first etches a second recess (depth error ≤5 nm) corresponding to the thickness of the anode in the SIO / SIN film layer, then deposits an anode material by a PVD method, and finally removes the excess part by etching and performs a CMP treatment to ensure that the surface of the anode is flush with the surface of the SIO / SIN film layer, and the actual flatness is ≤5 nm, thus eliminating the cause of spin-coating flow field disturbance from the root.

[0032] 2. The present application designs an independent "tungsten hole connection structure", etches a first recess in the SIO / SIN film layer above the tungsten hole, fills conductive adhesive to realize the electrical connection between the tungsten hole and the anode, and the fluidity of the conductive adhesive can adapt to the step structure around the tungsten hole to form stable ohmic contact, which significantly improves the consistency of pixel driving.

[0033] 3. The application improves compatibility through layered design and step-by-step process: the SIO / SIN film layer adopts a SiO2 and SiN composite structure, and two etchings are respectively for tungsten hole areas and anode areas to avoid stress concentration caused by single deep etching, the etching precision of the second recess can adapt to high-resolution scenarios with pixel spacing <5um, and through fine photolithography and dry etching process, the processing needs of high-density pixels of Micro OLED are met. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a structure diagram of preparing an insulating dielectric layer (SIO / SIN film layer) in S2 of the application.

[0035] Figure 2 is a structure diagram of preparing a first recess in S3 of the application.

[0036] Figure 3 is a structure diagram of injecting conductive glue in S4 of the application.

[0037] Figure 4 is a structure diagram of etching a second recess in S5 of the application.

[0038] Figure 5 is a structure diagram of depositing an anode in S6 of the application.

[0039] Figure 6 is a structure diagram of continuing to perform subsequent processes after completing CMP processing in S8 of the application.

[0040] Among them:

[0041] 1, CMOS substrate; 2, tungsten hole; 3, insulating dielectric layer; 4, first recess; 5, conductive glue; 6, second recess; 7, anode; 8, evaporated organic light-emitting layer; 9, thin film encapsulation layer TFE; 10, first organic planarization layer OC1; 11, color filter layer CF; 12, second organic planarization layer OC2; 13, adhesive layer OCR; 14, cover plate CG. DETAILED DESCRIPTION

[0042] The application will be further described below in conjunction with the drawings. The following examples are only used to more clearly illustrate the technical solutions of the application, and cannot be used to limit the protection scope of the application.

[0043] In the description of the present application, it is to be understood by those skilled in the art that the terms "middle", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, in the description of the present application, unless otherwise specified and limited, the term "a plurality of" means two or more.

[0044] In the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0045] Invention concept: In OLED products, uneven process spin coating is easy to cause Mura (screen brightness or color unevenness), affecting the appearance of the product; in this patent, etching technology is used to keep the product surface level and consistent, reduce the influence of uneven spin coating in subsequent process sections, and reduce the influence on the appearance of the product.

[0046] Embodiment one

[0047] Reference Figures 1-5 The embodiment provides an anode 7 for reducing spin coating unevenness, comprising:

[0048] A CMOS substrate 1, wherein a tungsten hole 2 is arranged on the CMOS substrate 1;

[0049] An insulating medium layer 3 is deposited on the CMOS substrate 1 and covers the tungsten hole 2; the insulating medium layer 3 is sequentially provided with a first pit 4 and a second pit 6 located above the first pit 4 above the tungsten hole 2; and the opening area of the second pit 6 is greater than that of the first pit 4;

[0050] A conductive glue 5 is filled in the first pit 4, and is used to realize electrical connection with the tungsten hole 2;

[0051] And an anode 7 is deposited and completely filled in the second pit 6, and is electrically connected with the tungsten hole 2 through the conductive glue 5, wherein the topography of the second pit 6 is suitable for reducing the unevenness of the glue in the subsequent spin coating process.

[0052] It should be noted that in the embodiment, the insulating medium layer 3 includes but is not limited to an SIO / SIN film layer.

[0053] It should be noted that in the embodiment, after chemical mechanical polishing, the anode 7 is still conformally filled in the second recess 6, and the upper surface thereof is flush with the upper surface of the insulating medium layer 3.

[0054] It should be noted that in the embodiment, the depth of the first recess 4 is 0.5-2um, the depth of the second recess 6 is 50-200nm, and after chemical mechanical polishing, the difference between the remaining thickness of the anode 7 and the depth is ≤5nm.

[0055] It should be noted that in the embodiment, the material of the anode 7 is an ITO, AZO or Ag nanowire conductive layer, and the light transmittance at a wavelength of 550nm in a visible light band is ≥85%.

[0056] In the embodiment, the present application first realizes precise matching through a combination process of "two etching+CMP polishing", etches a second recess 6 (depth error ≤5nm) corresponding to the thickness of the anode 7 in the SIO / SIN film layer, then deposits anode 7 material through a PVD method, and finally removes the excess part through etching and performs CMP processing to ensure that the surface of the anode 7 is flush with the surface of the SIO / SIN film layer, and the actual flatness is ≤5nm, thereby eliminating the cause of spin coating flow field disturbance from the root; secondly, through the design of an independent "tungsten hole 2 connection structure", a first recess 4 is specially etched in the SIO / SIN film layer above the tungsten hole 2, and the tungsten hole 2 is electrically connected with the anode 7 by filling the conductive adhesive 5, the flowability of the conductive adhesive 5 can adapt to the step structure around the tungsten hole 2, forming a stable ohmic contact, and significantly improving the consistency of pixel driving.

[0057] Embodiment two

[0058] Reference Figures 1-5 On the basis of embodiment one, the present embodiment provides a preparation method of an anode 7 for reducing spin coating unevenness, which is applied to the anode 7 for reducing spin coating unevenness in embodiment one, and the preparation method comprises the following steps:

[0059] S1: providing a CMOS substrate 1, wherein the CMOS substrate 1 is provided with a tungsten hole 2;

[0060] S2: depositing an insulating medium layer 3 on the CMOS substrate 1 to cover the tungsten hole 2;

[0061] S3: etching a first recess 4 above the tungsten hole 2 of the insulating medium layer 3;

[0062] S4: filling conductive adhesive 5 into the first recess 4 to electrically connect the conductive adhesive 5 with the tungsten hole 2;

[0063] S5: etching a second recess 6 on the insulating medium layer 3, the opening area of the second recess 6 is larger than that of the first recess 4, and the depth matches the thickness of the anode 7 to be deposited;

[0064] S6: depositing anode 7 material in the second recess 6 by PVD method;

[0065] S7: removing excess anode 7 material outside the second recess 6 by etching, and then flattening the surface of the anode 7 with the surface of the insulating medium layer 3 by CMP treatment.

[0066] Further, referring to Figure 6 , in order to embody the practical application scenario of the anode 7 design in the entire Micro OLED device manufacturing process, it is proved that it is not an isolated structural improvement, but a practical technology that can directly serve the final product. In this embodiment, after the CMP treatment is completed, subsequent processes are continued, which include deposition of an organic light-emitting layer 8, formation of a thin film encapsulation layer TFE 9, a first organic planarization layer OC1 10, a color filter layer CF 11, a second organic planarization layer OC2 12, an adhesive layer OCR 13, a cover plate CG 14, and cutting to obtain a display module.

[0067] In this embodiment, the insulating medium layer 3 includes but is not limited to SIO / SIN film layer; the deposition method of the SIO / SIN film layer includes but is not limited to ALD, PECVD or PVD, wherein the thickness of the SiO2 layer is 0.5-2 μm, and the thickness of the SiN layer is 0.5-3 μm.

[0068] In this embodiment, the etching method in S3 and S5 includes but is not limited to dry etching, and the depth of the second recess 6 is 50-200 nm.

[0069] In this embodiment, the filling method of the conductive adhesive 5 in S4 is inkjet printing or etching filling, and after filling, it is baked and cured at 100-150°C.

[0070] In this embodiment, after the CMP treatment, the height difference between the upper surface of the anode 7 and the upper surface of the insulating medium layer 3 is ≤5 nm.

[0071] In the embodiment, the application improves the compatibility by layered design and step-by-step process: the SIO / SIN film layer adopts a SiO2 and SiN composite structure, two etchings are respectively for the tungsten hole 2 area and the anode 7 area, so as to avoid stress concentration caused by single deep etching, the etching precision of the second recess 6 can be adapted to high-resolution scenarios with a pixel pitch < 5 μm, through fine photoetching and dry etching process, the processing demand of high-density pixels of MicroOLED is met.

[0072] To sum up, the application designs an anode 7 reducing spin coating unevenness and a preparation method thereof, a layer of SIO / SIN film layer is deposited on the CMOS substrate 1, a first recess 4 with a certain width is etched above the tungsten hole 2, the tungsten hole 2 is connected by filling the conductive glue 5 in the first recess 4, the second recess 6 with a corresponding thickness is etched in the SIO / SIN film layer, corresponding to the thickness of the anode 7, and the anode 7 is deposited in the second recess 6, so that the surface of the anode 7 and the CMOS substrate 1 are horizontal, the influence of subsequent process segment spin coating unevenness on product appearance is reduced, and the competitiveness of the product is improved.

[0073] The above only describes the preferred embodiments of the application, and it should be noted that, for ordinary skilled in the art, without departing from the technical principles of the application, a number of improvements and modifications can be made, and these improvements and modifications should be considered as the protection scope of the application.

Claims

1. An anode with reduced spin uniformity, characterized in that, The application relates to a CMOS substrate (1) provided with a tungsten hole (2), an insulating medium layer (3) deposited on the CMOS substrate (1) and covering the tungsten hole (2), a conductive glue (5) filled in the first recess (4) and used for electrically connecting the tungsten hole (2), and an anode (7) deposited in and completely filling the second recess (6) and electrically connected with the tungsten hole (2) through the conductive glue (5). The insulating medium layer (3) comprises but is not limited to an SIO / SIN film layer. After chemical mechanical polishing, the anode (7) is still conformally filled in the second recess (6), and the upper surface of the anode (7) is flush with the upper surface of the insulating medium layer (3). The depth of the second recess (6) is 50-200 nm, and the difference between the remaining thickness of the anode (7) and the depth is less than or equal to 5 nm after chemical mechanical polishing. The material of the anode (7) is ITO, AZO or a Ag nanowire conductive layer, and the light transmittance of the anode (7) is greater than or equal to 85% at a wavelength of 550 nm in a visible light band.

2. The spin uniformity reducing anode of claim 1, wherein The preparation method comprises the following steps:

3. The spin uniformity reducing anode of claim 1, wherein S1: providing a CMOS substrate (1) provided with a tungsten hole (2); 4. The spin uniformity reducing anode of claim 3, wherein S2: depositing an insulating medium layer (3) on the CMOS substrate (1) to cover the tungsten hole (2); 5. The spin uniformity reducing anode of claim 1, wherein S3: etching a first recess (4) above the tungsten hole (2) of the insulating medium layer (3); 6. A method for producing a spin-coating non-uniformity reducing anode, applied to the spin-coating non-uniformity reducing anode (7) according to any one of claims 1 to 5, characterized by, S4: filling conductive glue (5) in the first recess (4) to electrically connect the conductive glue (5) with the tungsten hole (2); S5: etching a second recess (6) on the insulating medium layer (3), wherein the opening area of the second recess (6) is greater than that of the first recess (4), and the depth of the second recess (6) matches the thickness of the anode (7) to be deposited; S6: depositing anode (7) material in the second recess (6) by using a PVD method; S7: removing the excess anode (7) material outside the second recess (6) by etching, and then performing CMP treatment to make the surface of the anode (7) flush with the surface of the insulating medium layer (3). The insulating medium layer (3) comprises but is not limited to an SIO / SIN film layer; the deposition method of the SIO / SIN film layer comprises but is not limited to ALD, PECVD or PVD, wherein the thickness of the SiO2 layer is 0.5-2 mu m, and the thickness of the SiN layer is 0.5-3 mu m. The etching method in S3 and S5 comprises but is not limited to dry etching, and the depth of the second recess (6) is 50-200 nm. The filling method of the conductive glue (5) in S4 is inkjet printing or etching filling, and the conductive glue (5) is baked and solidified at 100-150 DEG C after filling. After the CMP treatment, the height difference between the upper surface of the anode (7) and the upper surface of the insulating medium layer (3) is less than or equal to 5 nm.

7. The method of claim 6, wherein the spin coating is performed at a rotation speed of 1,000 rpm to 3,000 rpm. ​ 8. The method of claim 6, wherein the spin coating is performed at a temperature of 20 to 30°C. ​ 9. The method of claim 6, wherein the spin coating is performed at a rotation speed of 1,000 rpm to 3,000 rpm. ​ 10. The method of claim 6, wherein the spin coating is performed at a temperature of 20 to 30°C. ​

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