Compensating voltage offset in memory

Abstract

The present disclosure includes apparatuses, methods, and systems for compensating for voltage offsets in memory. Embodiments include a memory having an array of memory cells, and circuitry configured to sense a data state of memory cells of the array by applying a voltage to data lines coupled to the memory cells and to plates of the memory cells, wherein the voltage applied to the plate electrode is delayed with respect to the voltage applied to the data line.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more specifically, to compensating for voltage offsets in memories. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits and / or external removable devices in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, read-only memory (ROM), ferroelectric random access memory (FeRAM), resistive variable memory such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and programmable conductive memory, etc.

[0003] Memory devices can be used as volatile and non-volatile memory for a wide range of electronic applications requiring high memory density, high reliability, and low power consumption. Non-volatile memory can be used in, for example, personal computers, Memory Sticks, solid-state drives (SSDs), digital cameras, cellular phones, portable music players such as MP3 players, movie players, and other electronic devices.

[0004] Memory devices may include memory cells that can store data based on the charge level of storage elements (e.g., capacitors). Such memory cells can be programmed to store data corresponding to a target data state by changing the charge level of the storage elements (e.g., different charge levels of a capacitor can represent different data states). For example, a source of electric field or energy (e.g., positive or negative electrical pulses (e.g., positive or negative voltage or current pulses)) can be applied to the memory cell (e.g., applied to the storage element of the cell) for a specific duration to program the cell to a target data state.

[0005] Memory cells can be programmed into one of several data states. For example, a single-level memory cell (SLC) can be programmed into two different data states, which can be represented by binary units 1 or 0 and can depend on whether the cell's capacitor is charged or uncharged. As an additional example, some memory cells can be programmed into more than two data states (e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110). Such cells can be called multi-state memory cells, multi-unit cells, or multi-level cells (MLCs). MLCs can provide higher density memory without increasing the number of memory cells because each cell can represent more than one digit (e.g., more than one bit). Attached Figure Description

[0006] Figure 1A Examples of memory arrays according to embodiments of the present disclosure are described.

[0007] Figure 1B Examples of memory cells according to embodiments of the present disclosure are described.

[0008] Figure 2 Examples of hysteresis curves associated with memory cells according to embodiments of the present disclosure are illustrated.

[0009] Figures 3A to 3B Examples of circuit systems for compensating voltage offsets in a memory according to embodiments of the present disclosure are described.

[0010] Figure 4 Examples of timing diagrams associated with voltage offsets in a compensated memory according to embodiments of the present disclosure are illustrated.

[0011] Figure 5 Examples of circuit systems for compensating voltage offsets in a memory according to embodiments of the present disclosure are described.

[0012] Figure 6 Examples of timing diagrams associated with voltage offsets in a compensated memory according to embodiments of the present disclosure are illustrated. Detailed Implementation

[0013] This disclosure includes apparatus, methods, and systems for compensating for voltage offsets in a memory. Embodiments include a memory having an array of memory cells and circuitry configured to sense the data state of the memory cells in the array by applying voltages to data lines coupled to the memory cells and to plates of the memory cells, wherein the voltage applied to the plates is delayed relative to the voltage applied to the data lines.

[0014] During sensing of a memory cell (e.g., a FeRAM cell), a voltage may be applied to the data (e.g., digital) line coupled to the memory cell (which may be referred to herein as a “selected” digital line) and the plate of the memory cell to determine the data state of the cell. After the memory cell has been sensed, the voltage applied to the plate may be reduced (e.g., ramped down), and the cell may be precharged (e.g., the data state may be written back to the memory cell).

[0015] When the voltage applied to the plate of the sensed memory cell decreases, the voltage on the digital lines must also decrease (e.g., the digital line voltage must follow the plate voltage) to prevent voltage interference on the access (e.g., word) lines coupled to the selected cell (which may be referred to herein as “selected” word lines) and the digital lines not coupled to the sensed memory cell (which may be referred to herein as “unselected” digital lines). However, due to the different electrical characteristics of the plate and digital lines (e.g., different inherent resistances and / or capacitances), the digital line voltage may not follow the plate voltage without delay. This delay (which may be referred to herein as voltage offset between the plate and the digital lines) can cause voltage interference on both the selected and unselected digital lines. For example, the greater the distance (e.g., physical and / or electrical distance) between the unselected digital lines and the plate of the sensed memory cell, the greater the potential for voltage interference. For instance, voltage interference of 100 millivolts (mV) or higher may occur on the unselected digital lines positioned furthest from the cell plate. This voltage interference can adversely affect the performance and / or reliability of the memory.

[0016] However, embodiments of this disclosure can compensate for voltage offsets between the board and digital lines (e.g., mitigating voltage delays between the board and digital lines) by controlling the board voltage slew rate (e.g., slowing down the board voltage ramp). For example, embodiments of this disclosure can control the board voltage slew rate by delaying the voltage applied to the board relative to the voltage applied to the selected digital line when sensing a memory cell, and / or by applying the voltage to the selected digital line faster when sensing the memory cell than applying the voltage to the board. By controlling the board voltage slew rate (e.g., ramp rate) in this way, and thereby compensating for voltage offsets between the board and digital lines, embodiments of this disclosure can reduce and / or prevent voltage interference on selected word lines and unselected digital lines, which can improve memory performance and / or reliability.

[0017] As used herein, “a” or “an” can refer to one or more of something, and “a plurality of” can refer to more than one such thing. For example, a memory cell can refer to one or more memory cells, and a plurality of memory cells can refer to two or more memory cells. Additionally, the indicators “M” and “N” (especially with respect to reference numerals in the accompanying drawings) as used herein indicate that embodiments of this disclosure may include one or more of the specific features so indicated.

[0018] The figures in this document follow a numbering convention, where the first one or the first few digits correspond to the figure number and the remaining digits identify the elements or components in the figure. Similar elements or components between different figures can be identified by using similar numbers.

[0019] Figure 1A An example of a memory array 106 according to an embodiment of the present disclosure is described. The memory array 106 may be, for example, a ferroelectric memory (e.g., FeRAM) array.

[0020] like Figure 1A As shown, memory array 106 may include memory cells 108 programmable to store different states. Memory cells 108 may be, for example, FeRAM cells. Memory cells (e.g., FeRAM cells) 108 may include capacitors for storing charges representing programmable states. For example, charged and uncharged capacitors may represent two logic states (e.g., 0 and 1). Memory cells 108 may include capacitors having ferroelectric materials, in some instances of which are, for example, oxide materials such as lead zirconium titanate (PZT). Additional examples of ferroelectric materials may include barium titanate (BaTiO3), lead titanate (PbTiO3), and strontium bismuth tantalate (SBT). For example, ferroelectric materials may have a nonlinear relationship between the applied electric field and the stored charge (e.g., in the form of a hysteresis loop, as combined with...). Figure 2 (To be further described), and may have spontaneous polarization (e.g., non-zero polarization in the absence of an electric field). For example, different charge levels of a ferroelectric capacitor can represent different logic states.

[0021] like Figure 1A As shown, memory cell 108 can be coupled to a corresponding access line (e.g., one of access lines 110-1 to 110-M) and a corresponding data (e.g., digital) line (e.g., one of data lines 115-1 to 115-N). For example, memory cell 108 can be coupled between access line 110 and data line 115. In this example, access line 110 may also be referred to as a word line, and data line 115 may also be referred to as a bit line. For example, access line 110 and data line 115 may be made of a conductive material, such as copper, aluminum, gold, tungsten, metal alloys, other conductive materials, or the like.

[0022] In this example, the memory cell 108 commonly coupled to access line 110 may be referred to as a row memory cell. For instance, access line 110 may be coupled to a row decoder ( Figure 1A (Not shown in the image), and data line 115 can be coupled to the column decoder ( Figure 1A (Not shown in the image). Operations such as programming (e.g., writing) and sensing (e.g., reading) can be performed on memory cells 108 by activating or selecting appropriate access lines 110 and data lines 115 (e.g., by applying voltage to the access lines). Activating access line 110 electrically couples the corresponding row memory cell 108 to its corresponding data line 115.

[0023] Although for clarity and to avoid obscuring the embodiments of this disclosure Figure 1A Not shown, but memory array 106 may be included in a device in the form of a memory device. As used herein, “device” may mean, but is not limited to, any of a variety of structures or combinations thereof, such as (for example) a circuit or circuit system, one or more dies, one or more modules, one or more devices, or one or more systems. Additionally, a device (e.g., a memory device) may include an additional memory array similar to array 106.

[0024] Figure 1B This describes an example circuit 120 including a memory unit 108 according to an embodiment of the present disclosure. For example... Figure 1B As shown, circuit 120 may include memory (e.g., FeRAM) cell 108, access line 110, and data line 115, which may respectively... Figure 1A Examples of memory cell 108, access line 110 and data line 115 shown in the figure.

[0025] like Figure 1B As shown, memory cell 108 may include storage elements, such as capacitor 122, which may have a first plate (e.g., cell plate 124) and a second plate (e.g., cell bottom 126). Cell plate 124 and cell bottom 126 may be capacitively coupled via ferroelectric material 128 positioned between them. The orientation of cell plate 124 and cell bottom 126 may be flipped without altering the operation of memory cell 108.

[0026] like Figure 1B As shown, circuit 120 may include selection device 130, such as a selection transistor. For example, the control gate 112 of selection device 130 may be coupled to access line 110. Figure 1BIn this example, cell plate 124 can be accessed via plate line 132, and cell bottom 126 can be accessed via data line 115. For example, selection device 130 can be used to selectively couple data line 115 to cell bottom 126 in response to activation of selection device 130 by access line 110. For example, when selection device 130 is deactivated, capacitor 122 can be electrically isolated from data line 115, and when selection device 130 is activated, capacitor 122 can be electrically coupled to data line 115. For example, activating selection device 130 may be referred to as selecting memory cell 108.

[0027] In this example, a source of electric field or energy (e.g., positive or negative electric pulses, such as positive or negative voltage or current pulses) can be applied to the storage elements of memory cell 108 (e.g., applied to capacitor 122) for a specific duration to program the cell to a target data state. For example, when an electric field (e.g., an electric pulse) is applied across the ferroelectric material 128 of capacitor 122, the dipoles of the ferroelectric material 128 can align in the direction of the applied electric field. The dipoles can maintain their alignment (e.g., polarization state) after the electric field is removed, and different logic states (e.g., 0 and 1) can be stored as different polarization states of the ferroelectric material 128. Thus, memory cell 108 can be programmed by charging cell plate poles 124 and cell bottom 126, which applies an electric field across the ferroelectric material 128 and places the ferroelectric material in a specific polarization state (e.g., depending on the polarity of the applied field) that corresponds to a specific data (e.g., logic) state. The data state of the memory cell can then be determined (e.g., sensed) by determining which polarization state the ferroelectric material is in. This article will further describe examples of programming and sensing memory cells.

[0028] Figure 2 Examples of hysteresis curves (e.g., loops) 200-A and 200-B associated with memory cells according to embodiments of the present disclosure are illustrated. The memory cells may be, for example, ferroelectric memory (e.g., FeRAM) cells, such as those previously associated with... Figures 1A to 1B The memory unit 108 described.

[0029] Hysteresis curves 200-A and 200-B illustrate the write and read processes of the example ferroelectric memory cell, respectively. Hysteresis curves 200-A and 200-B depict the voltage difference (V) stored in the ferroelectric capacitor (e.g., previously combined) according to the voltage difference (V). Figure 1B The charge (Q) on the capacitor 122 described.

[0030] The hysteresis curves 200-A and 200-B can be understood from the perspective of a single terminal of the capacitor. For example, if the ferroelectric material has negative polarization, then positive charge accumulates at the terminal, and if the ferroelectric material has positive polarization, then negative charge accumulates at the terminal. Furthermore, it should be understood that the voltage in the hysteresis curves 200-A and 200-B represents the voltage difference across the capacitor and is directional. For example, this can be achieved by applying a positive voltage to the terminals in question (e.g., previously combined...). Figure 1B The described unit plate pole 124) and the second terminal (e.g., previously combined) Figure 1B A positive voltage is achieved by keeping the bottom 126 of the described unit grounded (e.g., at approximately 0 volts). A negative voltage can be applied by keeping the terminal in question grounded and applying a positive voltage to a second terminal (e.g., a positive voltage can be applied to negatively polarize the terminal in question). Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages can be applied to the appropriate capacitor terminals to produce the voltage difference shown in hysteresis curves 200-A and 200-B.

[0031] As shown in hysteresis curve 200-A, ferroelectric materials can maintain positive or negative polarization using zero voltage difference, thus generating two possible charging states: charge state 205 and charge state 211. Figure 2 In the examples described, charge state 205 represents logic 0 and charge state 211 represents logic 1. In some instances, the logic values ​​of the corresponding charge states can be inverted.

[0032] Logic 0 or 1 can be written to a memory cell by controlling the polarization of the ferroelectric material and thus the charge on the capacitor terminals. For example, applying a net positive voltage 216 across the capacitor causes charge to accumulate until a charge state 205-1 is reached. After removing voltage 216, charge state 205-1 follows path 221 until it reaches charge state 205 at zero voltage. Similarly, writing charge state 211 by applying a net negative voltage 225 results in charge state 211-1. After removing negative voltage 225, charge state 211-1 follows path 231 until it reaches charge state 211 at zero voltage. Charge states 205-1 and 211-1 may be referred to as residual polarization (Pr) values ​​(e.g., the polarization (or charge) retained after the removal of an external bias voltage). Coercive voltage is the voltage at which the charge (or polarization) is zero.

[0033] To sense (e.g., read) the stored state of a ferroelectric capacitor, a voltage can be applied across the capacitor. In response, the stored charge (Q) changes, and the extent of the change depends on the initial charge state (e.g., the final stored charge (Q) depends on whether the initial stored charge state was 205-2 or 211-2). For example, hysteresis curve 200-B illustrates two possible stored charge states 205-2 and 211-2. A voltage 235 can be applied across the capacitor. In other cases, a fixed voltage can be applied to the cell plates, and although depicted as a positive voltage, voltage 235 can be negative. In response to voltage 235, charge state 205-2 can follow path 233. Similarly, if the initial stored charge state was 211-2, then it follows path 237. The final positions of charge states 205-3 and 211-3 depend on several factors, including, for example, the specific sensing scheme and circuitry.

[0034] The initial state of the capacitor can be determined by comparing the voltage on the digital line coupled to the memory cell (e.g., as measured by a sensing component) with a reference voltage. The digital line voltage can be the difference between voltage 235 and the final voltage across the capacitor (voltage 238 or voltage 239) (e.g., (voltage 235 - voltage 238) or (voltage 235 - voltage 239)). A reference voltage can be generated such that its magnitude lies between two possible digital line voltages to determine the stored logic state (e.g., whether the digital line voltage is higher or lower than the reference voltage). For example, the reference voltage can be the average of two quantities (voltage 235 - voltage 238 and voltage 235 - voltage 239). After comparison by the sensing component, the sensed digital line voltage can be determined to be higher or lower than the reference voltage, and the stored logic value (e.g., logic 0 or 1) of the ferroelectric memory cell can be determined.

[0035] Figures 3A to 3B This section describes an example of a circuit system 340 for compensating for voltage offsets in a memory according to embodiments of the present disclosure. The circuit system 340 may be coupled to previously associated... Figures 1A to 1B The memory array 106 described herein is the same device (e.g., a memory device) and is contained therein. For example, circuitry 340 may be coupled to include devices similar to those previously described. Figures 1A to 1B The array of memory cells of the described memory cell 108.

[0036] Additionally, although for simplicity and to avoid obscuring the embodiments of this disclosure... Figure 3A and 3BNot shown, but circuitry 340 may be coupled to a controller. The controller may include, for example, control circuitry and / or logic (e.g., hardware and / or firmware), and may be contained on the same physical device (e.g., the same die) as the memory array, or may be contained on a separate physical device communicatively coupled to the physical device containing the memory array. In embodiments, components of the controller may be distributed across multiple physical devices (e.g., some components are located on the same die as the array, and some components are located on different dies, modules, or boards).

[0037] The controller-operable circuitry 340 compensates for voltage shifts that may occur when sensing the data state of the memory cells in the array. For example, when sensing the data state of the memory cells in the array, the controller-operable circuitry 340 applies a power supply voltage to the data (e.g., digital) lines coupled to the memory cells and the plates of the memory cells, wherein the voltage applied to the plates is delayed relative to the voltage applied to the data lines. The data lines may be, for example, previously coupled... Figures 1A to 1B The described data line 115, and the board may be, for example, the previously combined Figure 1B The described unit plate pole 124.

[0038] For example, in Figure 3A In the example described herein, circuit system 340 includes a single driver (e.g., a plate driver) 344 that applies power supply voltage to data lines and the plate. As... Figure 3A As shown, driver 344 includes transistors 346-1, 346-2, and 346-3, which can be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., n-type MOSFETs). After providing a first voltage (e.g., VPL) to the drain of transistor 346-1, a second voltage (e.g., VIBIAS) to the gate of transistor 346-3, a third voltage (e.g., VSS) to the source of transistor 346-3, and selection signals (e.g., PLSelH and PLSelL) to the gates of transistors 346-1 and 346-2, the power supply voltage can be output from driver 344 to the data lines and plate, as shown. Figure 3A As explained in the text.

[0039] exist Figure 3A In the example illustrated, circuit system 340 includes a single delay component 342 coupled to the output and plate of driver 344 (e.g., in series with it) (e.g., but not coupled to a data line) to delay the voltage applied to the plate. Delay component 342 may be, for example, a resistor-capacitor (RC) assembly (e.g., an RC circuit). As an additional example, delay component 432 may be a switch.

[0040] exist Figure 3BIn the example described herein, circuit system 340 includes a first driver (e.g., a plate driver) 344-1 that applies a power supply voltage to a data line, and a second driver 344-2 that applies a power supply voltage to a plate. Figure 3B As shown, driver 344-1 includes transistors 346-1A, 346-2A and 346-3A, and driver 344-2 includes transistors 346-1B, 346-2B and 346-3B, which may be, for example, MOSFETs (e.g., n-type MOSFETs). After providing a first voltage (e.g., VPL) to the drains of transistors 346-1A and 346-1B, a second voltage (e.g., VIBIAS) to the gates of transistors 346-3A and 346-3B, a third voltage (e.g., VSS) to the sources of transistors 346-3A and 346-3B, a first selection signal (e.g., PLSelH) to the gate of transistor 346-1A, and a second selection signal (e.g., PLSelL) to the gates of transistors 346-2A, 346-1B, and 346-2B, the power supply voltage can be output from driver 344-1 to the data line and from driver 344-2 to the plate, as follows. Figure 3B As explained in the text.

[0041] exist Figure 3B In the example described herein, circuit system 340 includes a first delay component 342-1 coupled to the second selection signal and the gate of transistor 346-1B (e.g., in series therewith), and a second delay component 342-2 coupled to the second selection signal and the gate of transistor 346-2B (e.g., in series therewith) to delay the voltage applied to the plates. Delay components 342-1 and 342-2 may be, for example, RC components (e.g., RC circuits) or switches.

[0042] During the sensing of the data state of a memory cell, additional voltage can be applied to the access (e.g., word) lines coupled to the memory cell, while a power supply voltage is applied to the data lines and the plate. The access lines can be, for example, previously coupled... Figures 1A to 1B Access line 110 is described. The magnitude of the additional voltage may be greater than the magnitude of the supply voltage. For example, the magnitude of the additional voltage may be 3.0 volts (V) (for example, the magnitude of the supply voltage may be less than 3.0 V).

[0043] The data state of a memory cell can be determined (e.g., sensed) based on the voltage on the data lines coupled to the memory cell in response to an applied supply voltage and additional voltage, as previously described herein. For example, a sensing component (e.g., a sensing amplifier; for simplicity and to avoid obscuring embodiments of this disclosure) may be used. Figure 3A and 3B(Not shown in the text) can be coupled to the array and used to determine the data state of memory cells, as previously described in this document.

[0044] After the data state of the memory cell has been sensed, the voltage applied to the plate of the cell can be reduced (e.g., slopped). Because the power supply voltage applied to the plate is delayed relative to the voltage applied through circuit system 340 to the data line coupled to the memory cell, the plate voltage can be reduced at a slower rate than in previous memory cell sensing methods (e.g., methods where the power supply voltage applied to the plate is not delayed), which compensates for the voltage offset between the plate and the digital line. (As will be used herein, e.g., in conjunction with...) Figure 4 Further description and illustration of an example of this voltage offset compensation.

[0045] After the voltage applied to the plate of the cell has decreased, the memory cell can be precharged by applying an additional voltage to the access line coupled to the memory cell (e.g., the sensed data state can be written back to the cell). The additional voltage can be, for example, an additional voltage applied to the access line when sensing the data state of the memory cell (e.g., the additional voltage applied to the access line when sensing the data state of the cell can continue to be applied to the access line to precharge the cell after the data state has been sensed).

[0046] Figure 4 This illustration shows an example of a timing diagram 450 associated with a voltage offset in a compensated memory according to an embodiment of the present disclosure. The memory may include, for example, previously combined... Figures 1A to 1B The described memory cell array 108.

[0047] like Figure 4 As shown, timing diagram 450 includes waveforms 452, 454, 456, 458, and 460. Waveform 452 represents the plate pole applied to the memory cell sensing its data state during sensing operation (e.g., previously combined with...). Figure 1B The voltage signal (e.g., pulse) of the plate 124 described herein, and waveform 454 represents the access (e.g., word) line (e.g., previously coupled) applied to the memory cell during the sensing operation. Figures 1A to 1B The voltage signal applied to the access line 110 (e.g., a selected access line) is described. The voltage signal applied to the plate may be delayed, as previously described herein. The voltage signal applied to the selected access line may have a value of, for example, 3.0 V, and may have a value greater than that applied to the plate, such as... Figure 4 As explained in the document. Additionally, the plate voltage signal can be applied to the plate before the access line voltage signal is applied to the selected access line, and the plate voltage signal can continue to be applied to the plate while the access line voltage signal is applied to the selected access line, as... Figure 4 As explained in the text.

[0048] Waveform 456 represents the data (e.g., digital) line (e.g., previously coupled) to the memory cell in response to a voltage signal being applied to the plate and the selected access line. Figures 1A to 1B The voltage signal described is on the data line 115 (e.g., a selected data line). The voltage signal on the selected data line can be used to determine (e.g., sense) the data state of a memory cell, as previously described herein. For example, in Figure 4 In the example described, if the data state of the memory cell is logic 1, then waveform 456-1 represents the voltage signal on the selected data line, and if the data state of the memory cell is logic 0, then waveform 456-2 represents the voltage signal on the selected data line.

[0049] Waveforms 458 and 460 represent voltage signals on data lines (e.g., data line 115) (e.g., unselected data lines) of the array that are not coupled to memory cells that sense their data state during sensing operations. For example, waveform 458 represents a voltage signal on an unselected data line that is close to (e.g., physically and / or electrically close to) a memory cell, and waveform 460 represents a voltage signal on an unselected data line that is far from (e.g., physically and / or electrically far from) a memory cell.

[0050] After the data state of a memory cell has been sensed, the voltage signal applied to the cell plate can be reduced (e.g., sloped down), and the voltage signal on unselected data lines can also be reduced (e.g., sloped down), such as Figure 4 As explained in the document, because the voltage signal applied to the cell plate is delayed, as previously described herein, the cell plate voltage signal slopes between the voltage signals on the near and far unselected data lines during its sag (e.g., waveform 452 is between waveforms 458 and 460 during its sag), as... Figure 4 As explained in the document. Therefore, voltage interference on unselected data lines can be balanced (e.g., voltage interference on near and far unselected data lines can be approximately the same), which reduces voltage interference that may occur on far unselected data lines. For example, voltage interference on far unselected data lines can be below 100 mV.

[0051] In contrast, if the voltage signal is not delayed, then the dashed waveform 462 represents the voltage signal applied to the plate of the memory cell. This undelayed voltage signal will increase (rise) and decrease (e.g., fall) at a faster rate than the delayed voltage signal represented by waveform 452, such as... Figure 4 As explained in the text. For example, this undelayed voltage signal will slope down faster than the voltage signals on the near and far unselected data lines (e.g., when it slopes down, waveform 462 is to the left of both waveforms 458 and 460), as... Figure 4As explained in [the document], this undelayed voltage signal will cause an imbalance in voltage interference on the unselected data lines (e.g., voltage interference on the far unselected data lines will be greater than voltage interference on the near unselected data lines), which will result in even greater voltage interference on the far unselected data lines. For example, the voltage interference on the far unselected data lines caused by this undelayed voltage signal can be greater than 100 mV.

[0052] like Figure 4 As shown, after the cell plate voltage signal has ramped down, the access line voltage signal can continue to be applied to the selected access line. Continuing to apply the access line voltage signal to the selected access line can precharge the memory cell, as previously described herein.

[0053] Figure 5 This section describes an example of a circuit system 570 for compensating for voltage offsets in a memory according to embodiments of the present disclosure. The circuit system 570 may be coupled to previously associated... Figures 1A to 1B The memory array 106 described herein is the same device (e.g., a memory device) and is contained therein. For example, circuitry 570 may be coupled to include devices similar to those previously described. Figures 1A to 1B The array of memory cells of the described memory cell 108.

[0054] Additionally, although for simplicity and to avoid obscuring the embodiments of this disclosure... Figure 5 Not shown, but circuitry 570 may be coupled to a controller. The controller may include, for example, control circuitry and / or logic (e.g., hardware and / or firmware), and may be contained on the same physical device (e.g., the same die) as the memory array, or may be contained on a separate physical device communicatively coupled to the physical device containing the memory array. In embodiments, components of the controller may be distributed across multiple physical devices (e.g., some components are located on the same die as the array, and some components are located on different dies, modules, or boards).

[0055] The controller-operable circuitry 570 compensates for voltage shifts that may occur when sensing the data state of the memory cells in the array. For example, when sensing the data state of the memory cells in the array, the controller-operable circuitry 570 applies a power supply voltage to the data (e.g., digital) lines coupled to the memory cells and the plates of the memory cells, wherein the power supply voltage is applied to the data lines faster than the power supply voltage is applied to the plates. The data lines may be, for example, previously coupled... Figures 1A to 1B The described data line 115, and the board may be, for example, the previously combined Figure 1B The described unit plate pole 124.

[0056] For example, in Figure 5In the example described herein, circuit system 570 includes a first driver (e.g., a plate driver) 572-1 that applies a power supply voltage to a data line, and a second driver 572-2 that applies a power supply voltage to a plate. Figure 5 As shown, driver 572-1 includes transistors 578-1A, 578-2A, and 578-3A, and driver 572-2 includes transistors 578-1B, 578-2B, and 578-3B, which may be, for example, MOSFETs (e.g., n-type MOSFETs). After providing a voltage (e.g., VPL) to the drains of transistors 578-1A and 578-1B, a voltage (e.g., VIBIAS) to the gates of transistors 578-3A and 578-3B, a voltage (e.g., VSS) to the sources of transistors 578-3A and 578-3B, a first selection signal (e.g., PLSelH) to the gates of transistors 578-1A and 578-1B, and a second selection signal (e.g., PLSelL) to the gates of transistors 578-2A and 578-2B, the power supply voltage can be output from driver 572-1 to the data line and from driver 572-2 to the plate, as shown. Figure 5 As explained in the text.

[0057] For example, in Figure 5 In the example described herein, circuit system 570 includes a first voltage buffer 574-1 coupled to the data line and the output of driver 572-1, and a second voltage buffer 574-2 coupled to the plate and the output of driver 572-2. Power supply voltage can be output from driver 572-1 to the data line via voltage buffer 574-1, and power supply voltage can be output from driver 572-2 to the plate via voltage buffer 574-2, as... Figure 5 As described in the diagram. Additionally, circuit system 570 includes a first capacitor 576-1 coupled to the input terminal (e.g., non-inverting input terminal) of voltage buffer 574-1 and the output terminal of driver 572-1, and a second capacitor 576-2 coupled to the input terminal (e.g., non-inverting input terminal) of voltage buffer 574-1 and the output terminal of driver 572-2, as described in the diagram. Figure 5 As explained in the document. Capacitors 576-1 and 576-2 can be charged by applying a voltage (e.g., VSS), as... Figure 5 As explained in the text.

[0058] In this example, the voltage (e.g., VIBIAS) supplied to the gate of transistor 578-3A in driver 572-1 may be greater than the voltage (e.g., VIBIAS) supplied to the gate of transistor 578-3B in driver 572-2 to apply the power supply voltage to the data line faster than applying the power supply voltage to the plate. For example, the voltage supplied to the gate of transistor 578-3A may be 1.2 times the voltage supplied to the gate of transistor 578-3B. However, the embodiment is not limited to this example.

[0059] In this example, the capacitance of capacitor 576-1 may be smaller than that of capacitor 576-2 to apply the power supply voltage to the data lines faster than applying the power supply voltage to the plates. For example, the capacitance of capacitor 576-1 may be 0.7 times that of capacitor 576-2. However, the embodiments are not limited to this example.

[0060] In this example, the voltage (e.g., VSS) supplied to the source of transistor 578-3A in driver 572-1 may be less than the voltage (e.g., VSS) supplied to the source of transistor 578-3B in driver 572-2 to apply the power supply voltage to the data line faster than applying the power supply voltage to the plate. For example, the voltage supplied to the source of transistor 578-3A may be negative, and the voltage supplied to the source of transistor 578-3B may be positive. However, the embodiment is not limited to this example.

[0061] During the sensing of the data state of the memory cell, additional voltage may be applied to the access (e.g., word) lines coupled to the memory cell, while a power supply voltage is applied to the data lines and the plate, as previously described herein (e.g., in conjunction with...). Figures 3A to 3B As described herein. The data state of a memory cell can be determined (e.g., sensed) based on the voltage on the data lines coupled to the memory cell in response to an applied supply voltage and additional voltage, as previously described herein. For example, a sensing component (e.g., a sensing amplifier; for simplicity and to avoid obscuring embodiments of this disclosure) may be used. Figure 5 (Not shown in the text) can be coupled to the array and used to determine the data state of memory cells, as previously described in this document.

[0062] After the data state of the memory cell has been sensed, the voltage applied to the plate of the cell can be reduced (e.g., slopped). Since the power supply voltage is applied to the plate of the memory cell faster than the power supply voltage is applied to the data lines coupled to the memory cell via circuitry 340, the plate voltage can be reduced at a slower rate than in previous memory cell sensing methods (e.g., methods where the power supply voltage is applied to both the plate and the data lines at the same rate), which compensates for the voltage offset between the plate and the digital lines. (As will be used herein, e.g., in conjunction with...) Figure 6Further description illustrates an example of this voltage offset compensation. After the voltage applied to the plate of the cell has decreased, the memory cell can be precharged by applying an additional voltage to the access line coupled to the memory cell, as previously described herein (e.g., in conjunction with...). Figures 3A to 3B As described in ).

[0063] Figure 6 This illustration shows an example of timing diagram 680 associated with a voltage offset in a compensated memory according to an embodiment of the present disclosure. The memory may include, for example, previously combined... Figures 1A to 1B The described memory cell array 108.

[0064] like Figure 6 As shown, timing diagram 680 includes waveforms 682, 684, 686, 688, and 690. Waveform 682 represents the plate pole applied to the memory cell sensing its data state during sensing operation (e.g., previously combined with...). Figure 1B The voltage signal (e.g., pulse) of the plate 124 described herein, and waveform 684 represents the access (e.g., word) line (e.g., previously coupled) applied to the memory cell during the sensing operation. Figures 1A to 1B The voltage signal described is for the access line 110 (e.g., a selected access line). The voltage signal may be applied to the plate at a slower rate than the voltage applied to the data (e.g., digital) lines coupled to the memory cells (e.g., the voltage may be applied to the data lines faster than the voltage applied to the plate), as previously described herein. The voltage signal applied to the selected access line may have a value of, for example, 3.0 V, and may have a value greater than the voltage signal applied to the plate, such as... Figure 6 As explained in the document. Additionally, the plate voltage signal can be applied to the plate before the access line voltage signal is applied to the selected access line, and the plate voltage signal can continue to be applied to the plate while the access line voltage signal is applied to the selected access line, as... Figure 6 As explained in the text.

[0065] Waveform 686 represents a data line (e.g., previously coupled) that is coupled to a memory cell (e.g., a selected data line) in response to a voltage signal being applied to the plate and the selected access line. Figures 1A to 1B The voltage signal on the data line 115 described herein. The voltage signal on the selected data line can be used to determine (e.g., sense) the data state of a memory cell, as previously described herein. For example, in Figure 6 In the example described, if the data state of the memory cell is logic 1, then waveform 686-1 represents the voltage signal on the selected data line, and if the data state of the memory cell is logic 0, then waveform 686-2 represents the voltage signal on the selected data line.

[0066] Waveforms 668 and 690 represent voltage signals on data lines (e.g., data line 115) (e.g., unselected data lines) of the array that are not coupled to the memory cells that sense their data state during sensing operations. For example, waveform 668 represents a voltage signal on an unselected data line that is close to (e.g., physically and / or electrically close to) the memory cells, and waveform 690 represents a voltage signal on an unselected data line that is far from (e.g., physically and / or electrically far from) the memory cells.

[0067] After the data state of a memory cell has been sensed, the voltage signal applied to the cell plate can be reduced (e.g., sloped down), and the voltage signal on unselected data lines can also be reduced (e.g., sloped down), such as Figure 6 As explained in the document, because the voltage signal applied to the cell plate is slower than the voltage applied to the selected data line, as previously described herein, the cell plate voltage signal slopes between the voltage signals near and far from the unselected data line during its sag (e.g., when it slopes, waveform 682 is between waveforms 688 and 690), as... Figure 6 As explained in the document. Therefore, voltage interference on unselected data lines can be balanced (e.g., voltage interference on near and far unselected data lines can be approximately the same), which reduces voltage interference that may occur on far unselected data lines. For example, voltage interference on far unselected data lines can be below 100 mV.

[0068] In contrast, if the applied voltage signal is no slower than the voltage applied to the selected data line, then the dashed waveform 692 represents the voltage signal applied to the plate of the memory cell. This voltage signal will decrease (e.g., slope) at a faster rate than the voltage signal represented by waveform 682, such as... Figure 6 As explained in the text. For example, this voltage signal will slope down faster than the voltage signals on the near and far unselected data lines (e.g., when it slopes down, waveform 692 is to the left of both waveforms 688 and 690), as... Figure 6 As explained in [the document]. Therefore, this voltage signal will cause an imbalance in voltage interference on the unselected data lines (e.g., voltage interference on the far unselected data lines will be greater than voltage interference on the near unselected data lines), which will result in even greater voltage interference on the far unselected data lines. For example, the voltage interference on the far unselected data lines caused by this undelayed voltage signal can be greater than 100 mV.

[0069] like Figure 6 As shown, after the cell plate voltage signal has ramped down, the access line voltage signal can continue to be applied to the selected access line. Continuing to apply the access line voltage signal to the selected access line can precharge the memory cell, as previously described herein.

[0070] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of several embodiments of this disclosure. It should be understood that the foregoing description has been carried out in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon reviewing the foregoing description, combinations of the foregoing embodiments and other embodiments not explicitly described herein. The scope of several embodiments of this disclosure includes other applications in which the foregoing structures and methods are used. Therefore, the scope of several embodiments of this disclosure should be determined with reference to the appended claims and the full scope of the equivalents entitled to by such claims.

[0071] In the foregoing detailed embodiments, for the purpose of simplifying this disclosure, some features are grouped together in a single embodiment. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments of the disclosure must use more features than expressly stated in each claim. Rather, as reflected in the appended claims, the subject matter of the invention exists in fewer than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is an independent, separate embodiment.

Claims

1. An apparatus comprising: A memory, which has an array of memory cells; and A circuit system configured to sense the data state of the memory cells of the array by applying a voltage to a data line coupled to the memory cell and a plate of the memory cell, wherein the voltage applied to the plate is delayed relative to the voltage applied to the data line.

2. The device of claim 1, wherein the circuit system comprises a resistor-capacitor (RC) assembly for delaying the voltage applied to the plates.

3. The device of claim 1, wherein the circuit system includes a switch for delaying the voltage applied to the plate.

4. The device of claim 1, wherein the circuit system includes a driver for applying the voltage to the data line and the plate.

5. The device of claim 4, wherein the circuit system includes a delay component coupled to the plate and the output of the driver to delay the voltage applied to the plate.

6. The device of claim 1, wherein the circuit system comprises: A first driver is used to apply the voltage to the data line; A second driver is used to apply the voltage to the plate electrode; A first delay component, which is coupled to a first transistor of the second driver; and A second delay component, which is coupled to a second transistor of the second driver; The first delay component and the second delay component are configured to delay the voltage applied to the plate electrode.

7. A method of operating a memory, comprising: The data state of the ferroelectric memory cell is sensed by applying a voltage to a data line coupled to the ferroelectric memory cell and the plate of the ferroelectric memory cell, wherein the voltage applied to the plate is delayed relative to the voltage applied to the data line; and After sensing the data state of the ferroelectric memory cell, the voltage applied to the plate is reduced.

8. The method of claim 7, wherein the method comprises pre-charging the ferroelectric memory cell after reducing the voltage applied to the plate.

9. The method of claim 8, wherein precharging the ferroelectric memory cell comprises applying an additional voltage to an access line coupled to the ferroelectric memory cell.

10. The method of claim 7, wherein the method comprises sensing the data state of the ferroelectric memory cell by applying an additional voltage to an access line coupled to the ferroelectric memory cell while the voltage is applied to the data line and the plate.

11. The method of claim 10, wherein the magnitude of the additional voltage is greater than the magnitude of the voltage.

12. An apparatus comprising: A memory, which has an array of memory cells; and A circuit system configured to sense the data state of the memory cells of the array by applying voltage to data lines coupled to the memory cells and the plates of the memory cells, wherein the voltage is applied to the data lines faster than the voltage is applied to the plates.

13. The device of claim 12, wherein the memory cell of the array is a ferroelectric memory cell.

14. The device according to any one of claims 12 to 13, wherein the circuitry is configured to reduce the voltage applied to the plate after sensing the data state of the memory cell.

15. The device according to any one of claims 12 to 13, wherein the circuit system comprises: A first driver is used to apply the voltage to the data line; A second driver is used to apply the voltage to the plate electrode.

16. The device of claim 15, wherein the circuit system comprises: A first buffer, coupled to the data line and the output of the first driver; and The second buffer is coupled to the plate pole and the output of the second driver.

17. The device of claim 16, wherein the circuit system comprises: A first capacitor, coupled to the input of the first buffer and the output of the first driver; and A second capacitor is coupled to the input of the second buffer and the output of the second driver; The capacitance of the first capacitor is less than the capacitance of the second capacitor.

18. The apparatus according to claim 15, wherein: A first voltage is provided to the transistor of the first driver to apply the voltage to the data line; A second voltage is provided to the transistor of the second driver to apply the voltage to the plate. and The magnitude of the first voltage is greater than the magnitude of the second voltage.

19. The apparatus according to claim 15, wherein: A first voltage is provided to the first driver to apply the voltage to the data line; A second voltage is provided to the second driver to apply the voltage to the plate electrode; and The first voltage is less than the second voltage.

20. The apparatus according to claim 19, wherein: The first voltage is a negative voltage; and The second voltage is a positive voltage.

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