SPAD array control circuit and control method

Abstract

Embodiments of the present application provide a SPAD array control circuit and a control method. The SPAD array control circuit comprises a pixel unit array and a bias adjustment circuit located outside the pixel unit array. The bias adjustment circuit comprises a reference voltage source and a plurality of driving enhancement circuits. The reference voltage source provides a plurality of reference voltages. An input end of each driving enhancement circuit receives one reference voltage and outputs the reference voltage to the pixel unit array. The pixel unit array comprises a plurality of pixel units. A first voltage end of each pixel unit selectively receives a reference voltage output by one driving enhancement circuit. A second voltage end of each pixel unit is connected to a fixed voltage. Embodiments of the present application can reduce the area occupied by the driving enhancement circuit and improve the integration of the SPAD array.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a SPAD array control circuit and a control method. BACKGROUND

[0002] Single photon avalanche diodes (SPADs) may have different breakdown voltages due to temperature and process effects, so that even if the same operating voltage is provided to each SPAD in a SPAD array, the over-bias of each SPAD may not be the same.

[0003] Different over-biases of SPADs result in different detection characteristics (including time characteristics, pulse characteristics, detection probability / sensitivity characteristics, etc.) of the SPADs. Inappropriate over-biases also cause the SPADs to have working reliability problems or even not work, for example, too high over-biases cause the quenching circuit to bear too high a voltage, which exceeds the working voltage of the circuit and causes the circuit to burn out; too low over-biases cause the SPADs to be unable to sense photons to generate pulses. SUMMARY

[0004] Embodiments of the present application provide a SPAD array control circuit and a control method.

[0005] In a first aspect, embodiments of the present application provide a SPAD array control circuit, comprising a pixel unit array and a bias voltage adjustment circuit located outside the pixel unit array;

[0006] The bias voltage adjustment circuit comprises a reference voltage source and a plurality of drive enhancement circuits, the reference voltage source provides a plurality of reference voltages, and the input end of each drive enhancement circuit receives one reference voltage and outputs to the pixel unit array;

[0007] The pixel unit array comprises a plurality of pixel units, the first voltage end of the pixel unit selectively receives the reference voltage output by one of the drive enhancement circuits, and the second voltage end of the pixel unit is connected to a fixed voltage.

[0008] In a second aspect, embodiments of the present application provide a control method applied to a SPAD array control circuit, the SPAD array control circuit comprising a pixel unit array and a bias voltage adjustment circuit located outside the pixel unit array, the bias voltage adjustment circuit comprising a reference voltage source and a plurality of drive enhancement circuits, the input end of each drive enhancement circuit receiving one reference voltage and outputting to the pixel unit array; the pixel unit array comprising a plurality of pixel units, the first voltage end of the pixel unit selectively receiving the reference voltage output by one of the drive enhancement circuits, and the second voltage end of the pixel unit being connected to a fixed voltage.

[0009] The control method includes:

[0010] A fixed voltage is provided to the second voltage terminal of each pixel unit in the pixel unit array, and the ideal reference voltage required for the first voltage terminal of each pixel unit is obtained;

[0011] Based on the ideal reference voltage required by each pixel unit, determine the reference voltages that the reference voltage source needs to output;

[0012] Based on the reference voltages that the reference voltage source needs to output, the number of pixel units that each reference voltage needs to drive, and the specifications of each driving enhancement circuit, the correspondence between each reference voltage, the driving enhancement circuit, and the pixel unit is determined, and the circuit connection is turned on.

[0013] This application provides a SPAD array control circuit and control method. The control circuit integrates the drive enhancement circuit within the bias voltage regulation circuit, eliminating the need for the drive enhancement circuit in each pixel unit. This significantly reduces the trace resource requirements of the drive enhancement circuit in the SPAD array. Furthermore, in this application, the drive enhancement circuit directly enhances the reference voltage output from the reference voltage source in the bias voltage regulation circuit before providing it to the SPAD array. This allows a single reference voltage, after its load-carrying capacity is increased by the drive enhancement circuit, to be used to drive multiple SPADs. The number of drive enhancement circuits can be consistent with the number of reference voltages and is much smaller than the number of pixel units in the SPAD array, thus greatly reducing the trace resource requirements of the bias voltage regulation circuit. In summary, this application not only significantly reduces the trace resource requirements in the SPAD array but also effectively overcomes the problem of a substantial increase in trace resource requirements caused by integrating the drive enhancement circuit into the bias voltage regulation circuit. Therefore, it can be widely applied in large-area SPAD arrays. Attached Figure Description

[0014] Figure 1 A schematic diagram of the structure of a SPAD array control circuit provided in this application embodiment. Figure 1 ;

[0015] Figure 2 A schematic diagram of the structure of a SPAD array control circuit provided in this application embodiment. Figure 2 ;

[0016] Figure 3 A schematic diagram of the structure of a SPAD array control circuit provided in this application embodiment. Figure 3 ;

[0017] Figure 4 A schematic diagram of the structure of a SPAD array control circuit provided in this application embodiment.Figure 4 ;

[0018] Figure 5 A structure schematic of a SPAD array control circuit provided for an embodiment of the present application Figure 5 ;

[0019] Figure 6 A structure schematic of a SPAD array control circuit provided for an embodiment of the present application Figure 6 ;

[0020] Figure 7 A flowchart of a control method provided for an embodiment of the present application

[0021] Figure 8 A component structure schematic of a pixel unit provided for an embodiment of the present application DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, it should be noted that only the parts related to the application are shown in the drawings for the convenience of description.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing the embodiments of the present application only, and is not intended to limit the present application.

[0024] In the following description, “some embodiments” are described, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0025] It should be noted that the terms “first\second\third” involved in the embodiments of the present application are only to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that “first\second\third” can be interchanged with a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0026] SPAD is a semiconductor detector based on Geiger mode, which realizes high sensitivity detection at single photon level through avalanche multiplication effect. Its core materials include indium gallium arsenide (InGaAs) and other semiconductors, which have the characteristics of short-wave infrared response, low power consumption and small size, and are suitable for quantum communication, laser radar and 3D imaging technology fields.

[0027] A SPAD can be considered as a PN junction diode in nature, and the SPAD uses avalanche breakdown effect to realize single photon detection. Similar to other diodes, the SPAD includes a cathode and an anode. When a reverse bias voltage is applied, the cathode is connected to a positive voltage (or a positive voltage relative to the anode), and the anode is connected to a negative voltage (or a negative voltage relative to the cathode). The reverse bias voltage refers to the voltage applied to the PN junction. For the SPAD, working in the reverse bias state is a necessary condition for generating avalanche breakdown.

[0028] The breakdown voltage is the critical voltage value at which the SPAD occurs avalanche breakdown under a certain reverse bias voltage. When the reverse bias voltage is high enough, the electric field strength in the depletion region becomes very large. At this time, the carriers (electrons or holes) accelerated by the electric field in the depletion region obtain sufficient kinetic energy. When they collide with lattice atoms, they can knock valence band electrons into the conduction band to generate new electron-hole pairs. The newly generated carriers are also accelerated by the strong electric field, and continue to collide and ionize to generate more carriers. This process grows exponentially, forming an "avalanche" effect, which causes the reverse current to increase sharply. This phenomenon is called avalanche breakdown.

[0029] The overvoltage is the part of the working voltage (reverse bias voltage) of the SPAD that exceeds its breakdown voltage, that is, the overvoltage is the difference between the reverse bias voltage and the breakdown voltage. The overvoltage is the most core and important parameter in the design and application of the SPAD, which directly determines the key performance of the device, such as photon detection efficiency, avalanche rise time, etc.

[0030] Due to the influence of temperature, process and other factors, the breakdown voltages of SPADs of the same specification may not be the same, so even if the same working voltage is provided to each SPAD in the SPAD array, the overvoltages of the SPADs may not be the same. The reverse bias voltage of the SPAD, also known as the working voltage, is the difference between the cathode voltage and the anode voltage of the SPAD. Assuming that the anode is connected to ground, the working voltage of the SPAD in the standby state is equal to the cathode voltage, and the overvoltage = working voltage - breakdown voltage.

[0031] Different overvoltages of SPADs will result in different detection characteristics (such as time characteristics, pulse characteristics, detection probability / sensitivity characteristics, etc.) of the SPADs. Inappropriate overvoltage will also cause reliability problems or even no work of the SPAD, for example: too high overvoltage will cause the quenching circuit to bear too high voltage, which exceeds the working voltage of the circuit and causes the circuit to burn out; too low overvoltage will cause the SPAD to be unable to sense photons to generate pulses. The influence of inconsistent breakdown voltages is more serious in large arrays, which may cause some detectors to be unable to avalanche or even directly breakdown.

[0032] In order to solve the problem of different over-bias and inappropriate bias of each SPAD in the SPAD array, the over-bias of the SPAD is adjusted by the bias adjustment circuit outside the pixel unit. Referring to Figure 1 , a circuit diagram for adjusting the over-bias of the SPAD is shown, as Figure 1 shown, the SPAD array control circuit 10 in the present application includes a pixel unit array 30 and a bias adjustment circuit 20 outside the pixel unit array 30, the pixel unit array 30 includes a plurality of pixel units 40, each pixel unit 40 (or referred to as SPAD pixel unit) can be composed of at least a SPAD (also referred to as SPAD pixel), a quenching circuit and a second voltage selection circuit. It is assumed that the pixel unit array includes n pixel units, and n is a positive integer.

[0033] As shown in Figure 1 , the bias adjustment circuit can include a reference voltage source 201 and a plurality of drive enhancement circuits 202, the reference voltage source 201 provides m different reference voltages V ref1 ~V refm , each reference voltage is transmitted to the pixel unit array 30 after being enhanced by a drive enhancement circuit 202. The second voltage selection circuit in each pixel unit 40 in the pixel unit array 30 selects a suitable reference voltage from the plurality of reference voltages transmitted to the pixel unit array 30 and transmits it to one electrode end of the SPAD. The other electrode end of all SPADs in the pixel unit array 30 uniformly receives a fixed voltage, so that the over-bias of all SPADs (the difference between the voltage difference of the two ends of the SPAD and the breakdown voltage of the SPAD) tends to be consistent or / and maintains a suitable level, and each SPAD in the pixel unit array 30 has higher detection consistency and better working performance.

[0034] It can be understood that, in the present application, the bias adjustment circuit 20 is a circuit module arranged outside the pixel unit array 30, that is, the reference voltage source 201 and the plurality of drive enhancement circuits 202 and the circuit connection wires therebetween are arranged outside the pixel unit array 30. Compared with the traditional way of directly arranging the drive enhancement circuit 202 in each pixel unit 40, the present application embodiment does not occupy the wire resource inside the pixel unit array 30, and the number of the drive enhancement circuit 202 does not have to match the number of the pixel units 40 in the pixel unit array 30, which can greatly reduce the number of the drive enhancement circuit 202, thereby further reducing the circuit wire resource occupation required by the bias adjustment circuit 20 outside the pixel unit array 30. As can be seen, the present application can reduce the circuit resource occupation in two aspects. On the one hand, the wire resource occupation inside the pixel unit array 30 can be reduced, which is beneficial to reducing the area of the pixel unit 40, so that the pixel unit array 30 can be widely applied to large array detectors. On the other hand, the present application can also effectively overcome the problem of excessive circuit wire resource occupation outside the SPAD array caused by moving the drive enhancement circuit originally arranged inside the SPAD pixel unit out of the SPAD array in the traditional technology, thereby realizing the high integration of the detector chip.

[0035] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0036] In an embodiment of the present application, referring to Figure 1 , a constituent structure schematic diagram of a SPAD array control circuit 10 provided by the embodiment of the present application is shown. As Figure 1 indicated, the SPAD array control circuit 10 comprises a pixel unit array 30 and a bias adjustment circuit 20 located outside the pixel unit array 30.

[0037] The bias adjustment circuit 20 comprises a reference voltage source 201 and a plurality of drive enhancement circuits 202, and the reference voltage source 201 provides a plurality of reference voltages V ref , and the input end of each drive enhancement circuit 202 respectively receives one reference voltage V ref to improve the load capacity of the reference voltage V ref and output to the pixel unit array 30.

[0038] The pixel unit array 30 comprises a plurality of pixel units 40, and the first voltage end of the pixel unit 40 selectively receives the reference voltage V ref output by one of the drive enhancement circuits 202, and the second voltage end of the pixel unit 40 is connected to a fixed voltage.

[0039] It should be noted that the accompanying drawings in the embodiments of the present application only exemplarily show the constituent structure of the circuit, and do not represent the actual arrangement manner of the circuit, etc.

[0040] like Figure 1 As shown, the reference voltage source 201 includes m reference voltage output terminals, which output m reference voltages, denoted as V. ref1 ~V refm Wherein, the reference voltage V refj The corresponding drive enhancement circuit j, j=1, 2, ..., m, is provided. The bias adjustment circuit 20 includes m drive enhancement circuits 202, denoted as: drive enhancement circuit 1 to drive enhancement circuit m, with only one label 202 shown in the figure. In the embodiment of this application, the drive enhancement circuit 202 is used to adjust the reference voltage V. ref Drive enhancement is performed to improve its load-carrying capacity, but the reference voltage V is not changed. ref The voltage value is essentially a buffer or voltage follower. In addition, as a buffer, it can provide a certain degree of isolation between the input and the output. Specifically, the buffer can isolate the bias regulation circuit 20 located at the input end and the pixel unit array 30 located at the output end, so that the instantaneous large current (avalanche current) generated by the pixel unit array 30 in the working state is less likely to affect the stability of the front-end bias regulation circuit 20, and avoid mutual interference between the two.

[0041] In this embodiment, the input terminal of the drive enhancement circuit j is connected to the reference voltage source 201, which provides the reference voltage V. refj The reference voltage output terminal is connected via a signal line, thereby driving the enhancement circuit j to receive the reference voltage V through the corresponding signal line. refj .

[0042] like Figure 1 As shown, the pixel unit array 30 includes a plurality of pixel units 40 (only one 40 is shown in the figure). Pixel units 40 can be SPAD pixel units, wherein at least a SPAD is included. For example, as... Figure 2 As shown, pixel unit 40 may include SPAD 401, second voltage selection circuit 402, and quenching circuit 403. Figure 2 Only labels 401, 402, and 403 are shown in the diagram. The second voltage selection circuit 402 is connected to the outputs of m drive enhancement circuits 202, selecting the reference voltage V output by one of the drive enhancement circuits 202. refThe first voltage end of the pixel unit 40 is equivalent to an input end of the second voltage selection circuit 402 inside the pixel unit 40 for receiving a reference voltage, and can also be regarded as an electrode end of the SPAD 401 inside the pixel unit 40 for receiving the reference voltage through the quenching circuit 403. For ease of description, the second voltage end of the pixel unit 40 is described as the second voltage end of the SPAD 401 below, and correspondingly, the first voltage end of the pixel unit 40 can be regarded as another electrode end of the SPAD 401 for receiving a fixed voltage, and thus the first voltage end of the pixel unit 40 can be described as the first voltage end of the SPAD 401.

[0043] In the embodiment of the present application, as shown in Figure 2 , the SPAD 401 includes an anode end and a cathode end, the anode end of the SPAD 401 receives a reference voltage V ref through the quenching circuit 403, and the cathode end of the SPAD 401 receives a fixed voltage V power .

[0044] As shown in Figure 2 , since the anode end of the SPAD 401 is connected to the reference voltage V ref through the quenching circuit 403, the anode end of the SPAD 401 is equivalent to the first voltage end of the pixel unit 40, and the cathode end of the SPAD 401 is equivalent to the second voltage end of the pixel unit 40.

[0045] In other embodiments, the cathode end of the SPAD 401 can also receive the reference voltage V ref , and the anode end of the SPAD 401 receives the fixed voltage. The quenching circuit 403 can be arranged at the anode end or the cathode end of the SPAD 401, and the anode end or the cathode end of the SPAD 401 receives the reference voltage V ref or the fixed voltage through the quenching circuit 403.

[0046] In the embodiment of the present application, if the cathode end of the SPAD 401 is set as the second voltage end of the pixel unit 40, as shown in Figure 2 , the cathode end of the SPAD 401 is connected to the first fixed voltage V power as the second voltage end of the pixel unit 40, where the first fixed voltage V power may be a power supply voltage. The anode end of the SPAD 401 is connected to the second voltage selection circuit 402 through the quenching circuit 403 as the first voltage end of the pixel unit 40, for receiving the reference voltage V ref selected and output by the second voltage selection circuit 402.

[0047] In other embodiments, if the cathode end of the SPAD 401 is set as the first voltage end of the pixel unit 40, as shown in Figure 3As shown, the cathode end of the SPAD 401 is connected with the second voltage selection circuit 402 as the first voltage end of the pixel unit 40, for receiving the reference voltage V ref selected by the second voltage selection circuit 402.

[0048] In this way, in the embodiment of the present application, the bias adjustment circuit 20 is a circuit module arranged outside the pixel unit array 30, that is, the reference voltage source 201 and the plurality of driving enhancement circuits 202 and the circuit connection wires therebetween are arranged outside the pixel unit array 30. Compared with the traditional way of directly arranging the driving enhancement circuit 202 in each pixel unit 40, the embodiment of the present application does not occupy the wire resource inside the pixel unit array 30, and the number of the driving enhancement circuit 202 does not have to match the number of the pixel units 40 in the pixel unit array 30, which can greatly reduce the number of the driving enhancement circuit 202, thereby further reducing the circuit wire resource occupation required by the bias adjustment circuit 20 outside the pixel unit array 30. As can be seen, the present application can reduce the circuit resource occupation in two aspects. On the one hand, the wire resource occupation inside the pixel unit array 30 can be reduced, which is beneficial to reducing the area of the pixel unit 40, so that the pixel unit array 30 can be widely applied to large array detectors. On the other hand, the present application can also effectively overcome the problem of excessive circuit wire resource occupation outside the SPAD array caused by moving the driving enhancement circuit originally arranged inside the SPAD pixel unit out, thereby realizing the high integration of the detector chip.

[0049] In some embodiments, the number of the driving enhancement circuit 202 is the same as the number of the reference voltage V ref provided by the reference voltage source 201, and is less than the number of the pixel units 40 in the pixel unit array 30.

[0050] It should be noted that, as Figures 1-3 any of the embodiments shown, one reference voltage V ref corresponds to one driving enhancement circuit 202, and can correspond to a plurality of pixel units 40. The reference voltage V ref corresponds to one driving enhancement circuit 202, and each driving enhancement circuit 202 is used to drive and enhance the corresponding reference voltage V ref to enhance its load capacity. The number of the second voltage selection circuit 402 is consistent with the number of the SPAD 401 and is located inside the pixel unit 40, thereby selecting a suitable reference voltage V ref for the first voltage end of the SPAD 401.

[0051] For example, the number of driving enhancement circuits 202 = the number of reference voltages V ref , the number of pixel units 40 = n, and m < n. In this way, one driving enhancement circuit 202 can be connected to and drive multiple pixel units 40. Compared with the scheme in which the driving enhancement circuit is located inside the pixel unit, the number of driving enhancement circuits 202 is reduced, so that the overall area of the circuit is reduced, and the driving of the pixel units 40 is not affected. It can be understood that the voltage values of the m reference voltages V ref may be partially or completely the same, or partially or completely different. In the embodiments of the present application, the number m of reference voltages V ref is only related to the number of ports of the reference voltage source 201 that output the reference voltages.

[0052] In this way, the scheme provided by the embodiments of the present application can not only provide appropriate reference voltages V ref to the first voltage terminals of each SPAD 401 to make the over-bias of the SPADs consistent and appropriate, but also does not have to arrange the driving enhancement circuit 202 inside the pixel unit 40, reduces the wiring inside the pixel unit 40, and makes the size of the pixel unit 40 smaller, which can be applicable to large arrays.

[0053] In addition, moving the driving enhancement circuit 202 from inside the pixel unit 40 to the reference voltage output terminal of the bias adjustment circuit 20 can also concentrate the arrangement of a small number of driving enhancement circuits 202, so that the wiring arrangement of the multiple driving enhancement circuits 202 is more concentrated, thereby further reducing the chip wiring resource occupation outside the SPAD array.

[0054] In some embodiments, the numerical values of the multiple reference voltages V ref are set according to a preset rule, which can include but is not limited to at least one of an arithmetic progression, a geometric progression, and a stepped progression.

[0055] It should be noted that in the actual design of the circuit, the circuit with a certain regularity is usually easier to implement and control. Therefore, the embodiments of the present application can set each reference voltage in an arithmetic, geometric, stepped, or other manner that meets certain rules. However, the reference voltage can also be set in an increasing but non-arithmetic manner or a manner without obvious rules, which is not limited in detail.

[0056] For example Figure 4 , in some embodiments, the reference voltage source 201 includes a voltage dividing resistor string, and the voltage dividing resistor string includes multiple resistors R1-R m connected in series; the multiple reference voltages output by the resistor string can vary in an increasing sequence / decreasing sequence, or vary in a stepped manner, or the resistance values can be set according to the requirements to obtain the required reference voltages. The resistor string can be in the form of a fixed resistor, a variable resistor, a field effect transistor, or the like.

[0057] The first resistor R1 in the voltage divider resistor string is grounded (GND), and the last resistor R... m Connected to the power supply voltage VDD, the connection point between two adjacent resistors is a voltage node. Some or all of these voltage nodes are used to correspond to different output reference voltages V. ref .

[0058] like Figure 4 As shown, resistors R1 to R m The resistors form a voltage divider string, where in this example, each voltage node is used to output a reference voltage V. ref The grounding node of resistor R1 also outputs a reference voltage V. ref1 Assume resistors R1 to R2 are... m If all resistors are of the same specification, then m reference voltages V can be output in an arithmetic sequence. ref Assume resistor R1 ~ resistor R m If the resistance increases proportionally, then m reference voltages V can be output in a geometric sequence. ref Resistors R1 to R m The resistance value can also be of other magnitudes to output a reference voltage V that meets the requirements. ref Alternatively, the number of resistors in the voltage divider resistor string can be greater than m, so that multiple equal / unequal resistors connected in series are equivalent to forming a larger resistor, thereby obtaining a larger voltage to output a larger reference voltage.

[0059] In some embodiments, such as Figure 4 As shown, in addition to the voltage divider resistor string, the reference voltage source 201 may also include amplifier P1 and transistor T1, wherein the non-inverting input terminal (+) of amplifier P1 receives the input reference voltage V. in The output terminal is connected to the gate of transistor T1. The first terminal of transistor T1 is connected to the power supply voltage VDD, and the second terminal of transistor T1 is connected to resistor R. m And the inverting input terminal (-) of amplifier P1. Among them, amplifier P1 can be an error amplifier (EA), and transistor T1 can be an N-type metal-oxide-semiconductor field-effect transistor (NMOS transistor).

[0060] In other embodiments, such as Figure 5 As shown, the reference voltage source 201 includes at least one sub-source 2011 (one denoted by a number 2011 is shown in the figure), each sub-source 2011 being used to provide a corresponding reference voltage V. ref .

[0061] likeFigure 5 As shown, the m reference voltages V ref The reference voltage source 201 can include m sub-power sources 2011, respectively denoted as sub-power source 1 to sub-power source m, respectively corresponding to the output reference voltages V ref1 to V refm Here, each sub-power source 2011 is an independent power source, and can be set to output a suitable reference voltage V ref .

[0062] In the embodiments of the present application, the reference voltage source 201 can be a global voltage source circuit composed of multiple independent voltage sources, for example Figure 5 As shown, the independent voltage source, i.e. the sub-power source 2011, can be a digital-to-analog converter (DAC) that independently outputs a reference voltage.

[0063] In some embodiments, as shown in Figure 4 or Figure 5 The driving enhancement circuit 202 can be a voltage follower (Buffer). The voltage follower is a 1:1 amplifier connected by the output terminal and the inverting input terminal (-), which is used for driving enhancement processing of the input voltage, but does not change the resistance value of the input voltage. As shown in Figure 4 or Figure 5 The reference voltage output terminal of the reference voltage source 201 is connected to the non-inverting input terminal (+) of the corresponding voltage follower (Buffer), and the corresponding reference voltage V refj As the input voltage of the voltage follower, the driving enhancement circuit 202 outputs the reference voltage to the pixel unit 40 after driving enhancement.

[0064] In some embodiments, at least part of the driving enhancement circuits 202 have different driving enhancement capabilities, and the number of pixel units 40 corresponding to the driving enhancement circuit 202 with stronger driving enhancement capability is greater than the number of pixel units 40 corresponding to the driving enhancement circuit 202 with weaker driving enhancement capability; wherein the pixel unit 40 corresponding to the driving enhancement circuit 202 refers to the pixel unit 40 that selects to access the reference voltage V ref output by the driving enhancement circuit 202.

[0065] It should be noted that the driving enhancement capabilities of driving enhancement circuits 202 of different specifications are different, and the driving enhancement circuit 202 with larger specification and stronger driving enhancement capability can drive more pixel units 40, and the number of pixel units 40 that can be driven by the driving enhancement circuit 202 with smaller specification and weaker driving enhancement capability is smaller. Therefore, in the embodiments of the present application, the driving enhancement circuit 202 can drive the number of pixel units 40 that adapt to its own driving enhancement capability according to the strength of the driving enhancement capability of the driving enhancement circuit 202, so as to ensure that the efficient work of the circuit is not affected.

[0066] In some embodiments, as shown in Figure 6 The bias adjustment circuit 20 further includes a plurality of first voltage selection circuits 203, which are in one-to-one correspondence with the plurality of drive enhancement circuits 202. The first voltage selection circuit 203 is arranged between the reference voltage source 201 and the drive enhancement circuit 202, and is configured to receive a plurality of reference voltages V ref provided by the reference voltage source 201, and selectively output a reference voltage to the corresponding drive enhancement circuit 202.

[0067] Here, the reference voltage source 201 is taken as an example of a voltage division resistor string.

[0068] In Figure 4 the scheme shown, the voltage node between the drive enhancement circuit 202 and the voltage division resistor is directly connected, and the reference voltage V ref divided by the voltage division resistor is a fixed value (depending on the resistance value of the voltage division resistor), Figure 5 and the scheme shown is the same, that is, the drive enhancement circuit 202 and the reference voltage V ref at the input end thereof are in a fixed matching relationship. When there are a large number of pixel units 40 in the pixel unit array 30 that require the same or similar reference voltage V ref , these pixel units 40 need to be connected to the same drive enhancement circuit 202 to share the same reference voltage V ref , which requires the drive enhancement circuit 202 to have a large driving enhancement capability. The driving enhancement capability of the drive enhancement circuit 202 depends on its circuit specification, which has been determined by its circuit structure at the beginning of chip design and cannot be adjusted. In Figure 4 and Figure 5 the schemes shown, since the drive enhancement circuit 202 and the reference voltage V ref at the input end thereof are in a fixed matching relationship, there may be a mismatch between the reference voltage V ref , the drive enhancement circuit 202, and the pixel unit 40.

[0069] Therefore, the embodiment of the present application further provides a first voltage selection circuit 203 before each drive enhancement circuit 202, as shown in Figure 6 The input end of each first voltage selection circuit 203 receives all reference voltages V ref output from the reference voltage source 201, and selectively outputs a reference voltage to the corresponding drive enhancement circuit 202, which is driven by the drive enhancement circuit 202; and the input end of the second voltage selection circuit 402 in each pixel unit 40 receives all reference voltages V ref output by the drive enhancement circuit 202, and selectively outputs a reference voltage to the first voltage end of the corresponding SPAD 401.

[0070] In this way, the SPADs 401 requiring the same or similar reference voltages can be selected by the respective second voltage selection circuits 402 to select the same driving enhancement circuit 202 with matched specifications (driving promotion capability), and then the driving enhancement circuit 202 selects the appropriate reference voltage V ref according to the required reference voltages of the SPADs 401 through the corresponding first voltage selection circuit 203. ref The matching degree between the reference voltage V

[0071] In the embodiments of the present application, a plurality of pixel units 40 accessing the same reference voltage V ref may be referred to as the same type of pixel units, and in the pixel unit array 30, the first voltage ends of the same type of pixel units select the reference voltage V ref output by the same driving enhancement circuit 202; more specifically, the same type of pixel units refer to any two or more pixel units 40 with a difference in ideal reverse bias voltage less than or equal to a first preset threshold.

[0072] It should be noted that each pixel unit 40 in the pixel unit array 30 has the same specifications, but as described above, due to various factors, the breakdown voltage of the SPAD 401 in each pixel unit 40 can be different, resulting in different overvoltages of the pixel units 40 under the same reverse bias voltage, which affects the detection consistency of each pixel unit 40 in the pixel unit array 30 and affects the performance of the detector. Therefore, in the embodiments of the present application, the voltage at the second voltage end of each pixel unit 40 is set to a fixed voltage that does not change, and on this basis, the first voltage end of each pixel unit 40 is provided with a reference voltage that is not exactly the same, so that the reverse bias voltage of each pixel unit 40 is its ideal reverse bias voltage (or the closest to its ideal reverse bias voltage), and at this time, the overvoltage of the pixel unit 40 is its ideal overvoltage (or the closest to its ideal overvoltage). The ideal overvoltage is the overvoltage when the pixel unit 40 works in the best state. It can be understood that the reverse bias voltage of the pixel unit 40 is the reverse bias voltage of the internal SPAD 401, and similarly, the overvoltage and ideal overvoltage of the pixel unit 40 are the overvoltage and ideal overvoltage of the internal SPAD 401, respectively. It should be noted that the ideal overvoltage of the SPAD is one of the performance parameters of the SPAD, which can be designed during the manufacturing process of the SPAD device or obtained by testing after manufacturing, and is a known quantity.

[0073] As Figure 6 the reverse bias voltage of the SPAD is equal to the absolute value of the voltage difference between its two ends, and in the present application, the second voltage end of the SPAD 401 receives a fixed voltage Vpower (for example, Vpower), and the first voltage end receives a reference voltage Vref Therefore, the reverse bias voltage of the SPAD 401 = V power -V ref (absent the positive and negative signs). If the reverse bias voltage of the SPAD 401 is equal to its ideal reverse bias voltage, it means that the reference voltage at the first voltage terminal of the SPAD 401 is exactly its required ideal reference voltage, i.e., the over-bias voltage of the SPAD 401 is exactly equal to its ideal over-bias voltage.

[0074] It can be understood that, since the second voltage terminal of each pixel unit 40 receives the same fixed voltage V power If the difference value of the ideal reverse bias voltages of different pixel units 40 is less than or equal to the first preset threshold, it means that the difference value of the ideal reference voltages required by the first voltage terminals of the pixel units 40 is also less than or equal to the first preset threshold. The pixel units 40 meeting this feature are classified as the same type of pixel units in the embodiment of the present application. The first voltage terminals of these same type of pixel units select to access the reference voltage output by the same driving enhancement circuit 202, so as to achieve the purpose of sharing the driving enhancement circuit 202 and realizing good detection performance.

[0075] Here, the first preset threshold is the maximum critical value of the allowed difference range of the ideal reverse bias voltages. If the difference value of the ideal reverse bias voltages of a certain pixel unit 40 and the remaining pixel units 40 is greater than the first preset threshold, the pixel unit 40 itself is classified as a same type of pixel unit. At this time, the reference voltage selected to be received by the first voltage terminal of the pixel unit 40 is only used to drive the pixel unit 40.

[0076] In this way, in the circuit design stage, multiple driving enhancement circuits 202 with different driving capabilities can be designed (for example, according to the rules, they can be simply divided into large Buffer and small Buffer), or multiple grades of driving enhancement circuits 202 can be designed according to the different degrees of driving capability improvement. The larger the driving enhancement circuit 202 (the larger the circuit occupies area), the more pixel units 40 it can drive to improve the voltage.

[0077] In the embodiment of the present application, multiple pixel units 40 with the same or similar required reference voltages can be classified into one grade as the same type of pixel units. The pixel units 40 in the same grade can be driven by the same driving enhancement circuit 202 to improve the voltage and select the same reference voltage V ref The pixel units driven by the same driving enhancement circuit 202 to improve the voltage can also be regarded as being in one grade / channel. In this way, the grading correspondence among the reference voltages V ref , the driving enhancement circuit 202, and the pixel units 40 can be realized.

[0078] In this way, each pixel unit 40 can select a suitable driving enhancement circuit 202 through the second voltage selection circuit 402, so that the driving enhancement circuit 202 with strong driving capability drives more pixel units 40, and the driving enhancement circuit 202 with weak driving capability drives less pixel units 40, and the applicability is better.

[0079] It should be noted that the first voltage selection circuit 203 and the second voltage selection circuit 402 in the embodiments of the present application can be decoders or decoders (Decoder), for example, multiplexers, and the selected signal output is controlled by a corresponding control signal, which can be provided by a control unit such as a controller.

[0080] The embodiments of the present application provide a SPAD array control circuit 10, which moves the driving enhancement circuit 202 inside the pixel unit 40 to the bias adjustment circuit 20 outside the pixel unit 40, and provides different reference voltages to the first voltage ends of different pixel units 40, so that the bias adjustment circuit 20 can adjust the over-bias of each pixel unit 40 to be consistent or / and maintain a suitable level, which can not only make the detection performance of multiple pixel units 40 in the pixel unit array 30 similar and the reliability higher, but also reduce the circuit area occupation inside the pixel unit 40, thereby realizing large array application.

[0081] On the basis of the foregoing embodiments, the present application further provides a control method applied to the foregoing SPAD array control circuit 10. As shown in the figure, Figure 7 The control method can include:

[0082] S701: A fixed voltage is provided to the second voltage end of each pixel unit 40 in the pixel unit array 30, and an ideal reference voltage required by the first voltage end of each pixel unit 40 is obtained.

[0083] S702: According to the ideal reference voltage required by each pixel unit 40, determine each reference voltage required to be output by the reference voltage source 201;

[0084] S703: According to each reference voltage required to be output by the reference voltage source 201, the number of pixel units 40 corresponding to each reference voltage required to be driven, and the specifications of each driving enhancement circuit 202, determine the correspondence between each reference voltage, the driving enhancement circuit 202 and the pixel unit 40 and turn on the circuit connection.

[0085] It should be noted that the second voltage end of each pixel unit 40 in the pixel unit array 30 receives the same fixed voltage, and the ideal reference voltage required by the first voltage end of each pixel unit 40 can be different and needs to be determined respectively.

[0086] In step S701, obtaining the ideal reference voltage required for the first voltage terminal of each pixel unit 40 may include:

[0087] Determine the ideal reverse bias voltage for each pixel unit 40;

[0088] The ideal reference voltage required for the first voltage terminal of the pixel unit 40 is determined based on the ideal reverse bias voltage of each pixel unit 40 and the fixed voltage of the second voltage terminal.

[0089] It should be noted that the ideal reverse bias voltage is the reverse bias voltage that allows the SPAD 401 to operate at the ideal overbias voltage. Under the ideal overbias voltage, the SPAD 401 performs optimally. For the SPAD 401: reverse bias voltage = cathode voltage - anode voltage. Figure 6 For example, the cathode voltage (voltage at the second voltage terminal) of SPAD 401 is a fixed voltage V. power The anode voltage (voltage at the first voltage terminal) of SPAD401 is the reference voltage V connected through the quenching circuit 403. ref Then the reverse bias voltage of the SPAD = fixed voltage - reference voltage, where the fixed voltage is V. power Since the ideal reverse bias voltage is known, the ideal reference voltage required for the first voltage terminal can be calculated once the ideal reverse bias voltage is determined.

[0090] In other words, before providing the required ideal reference voltage to the first voltage terminal of each pixel unit 40 in the pixel unit array 30, the ideal reverse bias voltage of the pixel unit 40 must first be determined. In some embodiments, the pixel unit 40 may include a SPAD 401, a quenching circuit 403, and an inverter 404. The cathode or anode of the SPAD 401 serves as the first voltage terminal of the pixel unit 40 and is connected to the reference voltage V output by the drive enhancement circuit 202. ref The positive or negative terminal of SPAD 401 serves as the second voltage terminal of pixel unit 40 and is connected to a fixed voltage; the quenching circuit 403 is disposed on the negative or positive terminal of SPAD 401, and the input terminal of inverter 404 is connected to the intermediate node between SPAD 401 and quenching circuit 403.

[0091] For example, such as Figure 8 As shown, in the working state, the anode of SPAD 401 is connected to the reference voltage V through the quenching circuit 403 as the first voltage terminal. ref It is also connected to the input terminal of inverter 404 (the connection node is denoted as point Q). The input terminal (point Q) of inverter 404 is located between SPAD 401 and quenching circuit 403; the cathode of SPAD 401 is connected to a fixed voltage V as the second voltage terminal. power .

[0092] Exemplarily, the embodiment of the present application can determine the ideal reverse bias voltage of the pixel unit 40 based on the circuit as shown in the figure before the SPAD array enters the working state, which can specifically include the following steps: Figure 8 S1: obtaining the ideal over-bias voltage of the SPAD 401 in the pixel unit 40 and the threshold voltage of the inverter 404;

[0093] S1: obtaining the ideal over-bias voltage of the SPAD 401 in the pixel unit 40 and the threshold voltage of the inverter 404;

[0094] S2: providing the same fixed reference voltage to the first voltage end of each pixel unit 40 in the pixel unit array 30;

[0095] S3: adjusting the voltage of the second voltage end of each pixel unit 40 until the inverter 404 flips, and recording the voltage of the second voltage end of the pixel unit 40 when each inverter 404 starts to flip (the voltage can be recorded as the flip voltage);

[0096] S4: determining the ideal reverse bias voltage of the pixel unit 40 according to the flip voltage, the ideal over-bias voltage of the SPAD 401 in the pixel unit 40, the fixed reference voltage and the threshold voltage of the inverter 404.

[0097] It should be noted that the ideal over-bias voltage is the over-bias voltage when the SPAD 401 works in the best or better state, which is a known parameter; the threshold voltage of the inverter 404 is the critical value of the voltage at the input end of the inverter 404 when the output signal of the inverter 404 flips, which is also a known parameter, and the fixed reference voltage V ref-g is a voltage value provided to the first voltage end of the pixel unit 40 in the test environment, which is also a known parameter.

[0098] As shown in the figure, Figure 8 here, taking the anode end of the SPAD 401 connected with the quenching circuit 403 as the first voltage end of the pixel unit 40 and the cathode end of the SPAD 401 as the second voltage end of the pixel unit 40 as an example, the fixed reference voltage V ref-g of the anode end of the SPAD 401 can be set to 0, so that in the voltage adjustment process, the cathode end (second voltage end) voltage of the SPAD 401 is equal to the reverse bias voltage on the SPAD 401, assuming that the cathode end voltage of the SPAD 401 in this process is the reverse bias voltage, which is denoted as V op , then the cathode end voltage V op of the SPAD 401 = breakdown voltage V br + over-bias voltage V ov (taking the absolute value of the voltage without considering the positive and negative signs).

[0099] It should be noted that, as shown in the figure, Figure 8As shown, the pixel unit 40 can further include a digital circuit 405, and an output end of the inverter 404 is connected to the digital circuit 405, and the digital circuit 405 outputs a valid signal when the output signal of the inverter 404 is flipped.

[0100] In the pixel unit 40, the SPAD 401 is used to receive incident photons and generate a pulse signal after triggering an avalanche breakdown. The quenching circuit 403 is used to perform a quenching operation after the SPAD 401 enters an avalanche state, so as to terminate the avalanche breakdown. The inverter 404 is used to start flipping and output a rising edge or falling edge signal when the voltage at the anode end of the SPAD 401 reaches the threshold voltage of the inverter 404, and the digital circuit 405 acquires the rising edge or falling edge signal output by the inverter 404 and counts.

[0101] The specific transmission process of the photoelectric signal in the pixel unit 40 is as follows: under a large reverse bias voltage (exceeding the breakdown voltage) of the pixel unit 40, the SPAD 401 is in an unexcited state, when an incident photon enters the light-sensitive area of the SPAD 401 and triggers an avalanche, the SPAD 401 will generate a pulse signal, and then the SPAD 401 is restored to the state before the avalanche by the quenching circuit 403, and is ready to sense the next photon. The pulse signal output by the SPAD 401 causes the potential V Q at the anode end of the SPAD 401 (i.e., the Q point) to change, and the potential change reaches the threshold voltage V th of the inverter 404, so that the inverter 404 flips and generates a rising edge or falling edge signal, and the rising edge or falling edge signal is transmitted to the digital circuit 405, and the digital circuit 405 samples and counts the rising edge or falling edge signal by using a counter or the like. Figure 8 The quenching circuit 403 can be an active quenching circuit or a passive quenching circuit, for example, the passive quenching circuit shown in the figure, and the quenching circuit 403 is a resistor Rc.

[0102] However, if the reverse bias voltage V op at both ends of the pixel unit 40 is not greater than the breakdown voltage V br , even if a photon reaches the SPAD 401, the avalanche cannot be triggered to generate a pulse signal.

[0103] Therefore, by adjusting the voltage (i.e., the reverse bias voltage) at the second voltage end of the pixel unit 40, the reverse bias voltage V op at both ends of the pixel unit 40 is always changed until the SPAD 401 can sense the photon to output a pulse signal to make the inverter 404 flip, and the voltage at the second voltage end at this moment is recorded (denoted as the flipping voltage V op-ref ). At this moment, the SPAD 401 and the quenching circuit 403 form a series connection, and the flipping voltage Vop-ref The voltage shared by the SPAD 401 is just equal to its breakdown voltage V br The voltage shared by the quenching circuit 403 is also equal to the Q-point potential V Q , which is equal to the difference between the flip-over voltage V op-ref and the breakdown voltage V br Therefore, there is the following relationship:

[0104] (1).

[0105] In addition, according to the foregoing analysis, when the reverse bias voltage V op on the SPAD 401 is equal to its ideal reverse bias voltage V op-L , the over-bias voltage on the SPAD 401 is just equal to its ideal over-bias voltage V ov-L Therefore, there is the following relationship:

[0106] (2).

[0107] According to (1) and (2), we have:

[0108] (3).

[0109] In formula (3), the ideal over-bias voltage V ov-L and the threshold voltage V th are known parameters, and the flip-over voltage V op-ref can be determined by the foregoing method, so that the ideal reverse bias voltage V op-L can be calculated.

[0110] It should be further noted that the manner of adjusting the voltage of the second voltage terminal of the pixel unit 40 can be stepwise adjustment. For example, starting from an initial voltage and gradually increasing the voltage by a certain step value, or starting from an initial voltage and gradually decreasing the voltage by a certain step value. Meanwhile, coarse adjustment can be performed first and then fine adjustment can be performed. For example, the voltage value is gradually increased by a larger step value for coarse adjustment until the inverter 404 flips over, and then the voltage value is gradually decreased by a smaller step value for fine adjustment until the inverter 404 flips over, so that a more accurate flip-over voltage is obtained. Stepwise adjustment can also be performed in a decreasing and increasing manner from an initial voltage, so as to avoid incorrect adjustment direction. After the inverter 404 flips over in a certain step direction, fine adjustment can be performed in the opposite step direction.

[0111] It should be noted that in the foregoing examples, the fixed reference voltage is assumed to be 0, so in the calculation process, the fixed reference voltage is omitted, and if the fixed reference voltage is not 0, the corresponding calculation is substituted. The same applies to the case where the first voltage terminal is the cathode terminal of the SPAD 401 and the second voltage terminal is the anode terminal of the SPAD 401. Only the fixed voltage terminal changes, which will not be described here.

[0112] In some embodiments, in step S701, in the process of adjusting the voltage of the second voltage terminal of each pixel unit 40, the control method can further include:

[0113] providing the same initial voltage to the second voltage terminal of each pixel unit 40, and synchronously and uniformly adjusting the voltage of the second voltage terminal of each pixel unit 40;

[0114] For the pixel unit 40 that has output a pulse signal, in the process of continuing to adjust the voltage of the second voltage terminal of the pixel unit 40, the fixed reference voltage of the first voltage terminal of the pixel unit 40 is adjusted synchronously to make the voltage difference between the voltage of the second voltage terminal of the pixel unit 40 and the fixed reference voltage of the first voltage terminal always less than or equal to the second preset threshold.

[0115] It should be noted that the pixel unit array 30 usually contains a large number of pixel units 40, and if the voltage of the second voltage terminal of each pixel unit 40 is adjusted one by one, it will waste a lot of time and be difficult to implement in practice. Therefore, in the embodiments of the present application, in the process of determining the ideal reverse bias voltage of each pixel unit 40, the same voltage is provided to the second voltage terminal of multiple pixel units 40 in the pixel unit array 30, and in the adjustment process, the adjustment is performed synchronously. That is, no matter how much the voltage is adjusted, the voltage of the second voltage terminal of each pixel unit 40 is the same.

[0116] In this synchronous adjustment, there can be some pixel units 40 with a smaller breakdown voltage, and in the adjustment process, the reverse bias voltage across the two terminals of the pixel unit 40 exceeds the breakdown voltage earlier, so that the pixel unit 40 has output a pulse signal in the early stage of the adjustment process. If the voltage of the second voltage terminal of these pixel units 40 is further increased or decreased, it may cause the reverse bias voltage on the pixel unit 40 to be too large, and the quenching circuit 403 and / or the SPAD 401 on the SPAD 401 to be damaged when the avalanche current is generated by the avalanche of the sensed photons. Therefore, in the process of synchronously adjusting the voltage of the second voltage terminal of all pixel units 401, for the pixel units 40 that have output a pulse signal (i.e., the inverter 404 has flipped), the fixed reference voltage connected to the first voltage terminal of these pixel units 40 also needs to be adjusted synchronously to prevent the reverse bias voltage on these pixel units 40 from being too large, thereby achieving the effect of voltage withstand protection.

[0117] For example, the voltage difference (taking the absolute value) between the voltage of the second voltage terminal of these pixel units 40 and the fixed reference voltage of the first voltage terminal is always less than or equal to a second preset threshold. Wherein, the second preset threshold corresponding to each pixel unit 40 can be different. For example, the specific value of the second preset threshold can be determined according to the voltage withstand limit of the SPAD 401 and / or quenching circuit 403 in each pixel unit 40, to ensure that the voltage division on the SPAD 401 and / or quenching circuit 403 in each pixel unit 40 does not exceed its voltage withstand limit. Alternatively, the second preset threshold can be less than or equal to the flip voltage V op-ref , so as to determine the flip voltage V op-ref of each pixel unit 40. Afterwards, the reverse bias voltage on each pixel unit 40 is less than the critical value (i.e. the flip voltage V op-ref ) that can induce photons, which is equivalent to turning off the pixel units 40 that have previously output the pulse signal, avoiding unnecessary circuit loss.

[0118] For example, the voltage of the second voltage terminal is increased or decreased by a certain value, and the fixed reference voltage connected to the first voltage terminal of these pixel units 40 is also increased or decreased by the same value, so that the reverse bias voltage of these pixel units 40 remains unchanged, avoiding damage to the device during adjustment and achieving voltage withstand protection.

[0119] That is, in order to avoid the fact that some pixel units 40 with smaller breakdown voltage are burned out due to the excessive reverse bias voltage on the pixel units 40 caused by the voltage adjustment of the second voltage terminal during the scanning process of determining the ideal reverse bias voltage of the pixel units 40, the embodiment of the present application increases the fixed reference voltage of the first voltage terminal of the SPAD 401 (for example, by selecting a larger voltage through the second voltage selection circuit 402) after the SPAD 401 starts to output the pulse signal, which plays a role in voltage withstand protection.

[0120] After step S701, step S702 is performed: according to the ideal reference voltage required by each pixel unit 40, the reference voltage required to be output by the reference voltage source 201 is determined.

[0121] It should be noted that before selecting the reference voltage to be delivered to the first voltage terminal of the pixel unit 40, the ideal reverse bias voltage of the pixel unit 40 needs to be determined first through the foregoing step S701, and the ideal reference voltage required by the first voltage terminal of the pixel unit 40 is calculated according to the determined ideal reverse bias voltage and the known fixed voltage of the second voltage terminal.

[0122] That is, after the ideal reverse bias voltage of all pixel units 40 is determined, the voltage of the second voltage terminal of all pixel units 40 is uniformly adjusted to a fixed voltage Vpower For example, the ideal reference voltage V power is determined according to the ideal reverse bias voltage V op-L and the fixed voltage V power of each pixel unit 40. ref-L The ideal reference voltage V ref-L = V op-L - V power or V ref-L = V power - V op-L .

[0123] Thus, the ideal reference voltage required by each pixel unit 40 is obtained, and the reference voltage source 201 needs to output each reference voltage according to the ideal reference voltage required by these pixel units 40.

[0124] Specifically, since the number of ports through which the reference voltage source 201 can output reference voltages can be less than the number of ideal reference voltages required by the pixel units 40 in the pixel unit array 30, a number of suitable reference voltages can be selected according to the ideal reference voltage values required by the pixel units 40 in the pixel unit array 30 and output by the reference voltage source 201, so that the voltage intervals of the reference voltages output by the reference voltage source 201 can cover all the ideal reference voltage values required by the pixel units 40.

[0125] Further, each reference voltage value output by the reference voltage source 201 can be set near the ideal reference voltage value required by part / all of the pixel units 40, so that part / all of the pixel units 40 can share the reference voltage and ensure better working performance.

[0126] Finally, step S703 is performed: according to each reference voltage required to be output by the reference voltage source 201, the number of pixel units 40 that each reference voltage needs to drive, and the specifications of each driving enhancement circuit 202, the correspondence between each reference voltage, the driving enhancement circuit 202, and the pixel unit 40 is determined and the circuit connection is turned on.

[0127] It should be noted that a plurality of pixel units 40 close to the ideal reference voltage can be driven by the same reference voltage. That is, the number of reference voltages actually output by the reference voltage source 201 can be less than the number of pixel units 40.

[0128] In some embodiments, determining the correspondence between each reference voltage, the driving enhancement circuit 202, and the pixel unit 40 and turning on the circuit connection comprises:

[0129] According to the ideal reference voltage required by each pixel unit 40, determine the reference voltage corresponding to the pixel unit 40 to be driven; wherein the difference between the ideal reference voltage required by the pixel unit 40 to be driven and the reference voltage is less than or equal to a third preset threshold value;

[0130] Obtain the number of pixel units 40 to be driven corresponding to each reference voltage and the specifications of each driving enhancement circuit 202;

[0131] According to the number of pixel units 40 to be driven corresponding to each reference voltage, select the driving enhancement circuit 202 with matching specifications, and sequentially turn on the connection between the reference voltage, the driving enhancement circuit 202 with matching specifications, and the pixel unit 40 to be driven.

[0132] It should be noted that for a plurality of pixel units 40 driven by the same reference voltage, the difference between the ideal reference voltage of these pixel units 40 and the reference voltage (which can be the absolute value of the difference between the ideal reference voltage and the reference voltage) should be less than the third preset threshold value. The third preset threshold value is the allowable difference value for classifying a plurality of ideal reference voltages into one category.

[0133] In some embodiments, according to the ideal reference voltage required by each pixel unit 40, determining the reference voltage corresponding to the pixel unit 40 to be driven can include:

[0134] Classify each pixel unit 40 in the pixel unit array 30 to obtain a plurality of same type pixel units, and the difference between the ideal reference voltages required by the same type pixel units is less than or equal to a first preset threshold value;

[0135] According to the difference between the ideal reference voltage required by each same type pixel unit 40 and each reference voltage, determine the same type pixel unit to be driven corresponding to each reference voltage.

[0136] It should be noted that the first preset threshold value is the maximum difference threshold value allowed for the ideal reference voltages required by the same type pixel units. The difference between the ideal reference voltages is less than or equal to the first preset threshold value, which means that the ideal reference voltages of these pixel units 40 are close and can be classified into the same category, that is, in a group of same type pixel units, the difference between the ideal reference voltages required by any two pixel units 40 is less than or equal to the first preset threshold value. For pixel units 40 that cannot be classified into the same category as other pixel units 40, they themselves form a same type pixel unit. Here, the classification of pixel units 40 can be realized by software or algorithm with statistical and classification functions. At the same time, since the same type pixel units are driven by the same reference voltage, the total number of different categories of same type pixel units can be set to m, so that the same type pixel units of different categories and different reference voltages are one-to-one corresponding.

[0137] In some embodiments, the determination of the reference voltage corresponding to the pixel unit 40 to be driven according to the ideal reference voltage required by the pixel unit 40 can comprise:

[0138] comparing the ideal reference voltage required by the pixel unit 40 with the reference voltage output by the reference voltage source 201, and selecting the reference voltage V ref closest to the ideal reference voltage required by the pixel unit 40 as the reference voltage V ref .

[0139] It should be noted that in the embodiments of the present application, the ideal reference voltage required by the pixel unit 40 and each reference voltage V ref output by the reference voltage source 201 can be directly compared, and the closest one is selected as the reference voltage V ref for driving the pixel unit 40, so that the reference voltage V ref accessed by the pixel unit 40 is closest to the ideal reference voltage required by the pixel unit 40, and the best effect can be achieved. Here, a reference voltage V ref may correspond to several pixel units 40 of the same type to be driven as the same type of pixel unit.

[0140] In some embodiments, the n pixel units 40 can also be divided into m same type of pixel units, and a first ideal reference voltage can be determined from the ideal reference voltages of the pixel units 40 in each same type of pixel unit, which can be one of the maximum value, the minimum value, the average value, the median value, the weighted average value, etc. The first ideal reference voltage is used as the reference voltage shared by the same type of pixel units. Alternatively, statistical analysis is performed on the m ideal reference voltages, and the m reference voltages are adjusted according to the arithmetic progression, geometric progression or the number of steps as described above, and the corresponding reference voltage source 201 is designed to output the m reference voltages.

[0141] In some embodiments, the driving enhancement circuit 202 of the same specification is selected according to the number of pixel units 40 to be driven corresponding to each reference voltage, comprising:

[0142] determining the number of pixel units 40 in the same type of pixel units to be driven corresponding to each reference voltage;

[0143] arranging the pixel units according to the number of pixel units, and arranging the driving enhancement circuits 202 according to the specifications;

[0144] sequentially matching and connecting the same type of pixel units and the driving enhancement circuits 202 according to the same arrangement rule.

[0145] It should be noted that the m reference voltages correspond to the m driving enhancement circuits 202 one by one. The driving enhancement circuit 202 with large specification (usually large area) can carry more number of pixel units 40. Therefore, the pixel units of the same type can be sorted according to the number of pixel units 40 contained, and the driving enhancement circuits 202 are sorted according to the same sorting rule (from large to small or from small to large) according to the specification size, and then the driving enhancement circuits 202 and the pixel units 40 in the same type of pixel units are connected in the same order. That is, the driving enhancement circuit 202 with the largest specification connects the largest number of pixel units 40, and the driving enhancement circuit 202 with the smallest specification connects the smallest number of pixel units 40.

[0146] In this way, the embodiments of the present application can design a plurality of driving enhancement circuits 202 with different specifications (corresponding to different driving capabilities), and a plurality of pixel units 40 with the same or similar required reference voltage are classified into a category. The pixel units 40 in the same category select the same reference voltage and are driven by the same driving enhancement circuit 202. In this way, the reference voltage, the driving enhancement circuit 202 and the pixel unit 40 are classified and corresponded. The driving enhancement circuit 202 with strong driving capability drives more number of pixel units 40, and the driving enhancement circuit 202 with weak driving capability drives less number of pixel units 40, which is more suitable.

[0147] The above is only a preferred embodiment of the present application, and is not used to limit the protection scope of the present application.

[0148] It should be noted that in the present application, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0149] The above sequence number of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments.

[0150] The methods disclosed in the several method embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments.

[0151] The features disclosed in the several product embodiments provided by the present application can be combined arbitrarily without conflict to obtain new product embodiments.

[0152] The features disclosed in several method or device embodiments of the present application can be combined, without conflict, to form new method or device embodiments.

[0153] The above description is merely illustrative of the application and is not intended to limit the scope of the application. Any changes and modifications that can be made to the application in light of the teachings described herein are contemplated in the broad scope of the application.

Claims

1. A SPAD array control circuit, characterized in that, It includes a pixel unit array and a bias adjustment circuit located outside the pixel unit array; The bias voltage adjustment circuit includes a reference voltage source and multiple drive enhancement circuits. The reference voltage source provides multiple reference voltages, and the input terminal of each drive enhancement circuit receives one of the reference voltages and outputs it to the pixel unit array. The pixel unit array includes multiple pixel units, the first voltage terminal of the pixel unit selectively receives a reference voltage output by one of the driving enhancement circuits, and the second voltage terminal of the pixel unit is connected to a fixed voltage; The number of drive enhancement circuits is the same as the number of the plurality of reference voltages provided by the reference voltage source, and is less than the number of pixel units in the pixel unit array.

2. The SPAD array control circuit according to claim 1, characterized in that, The values ​​of the multiple reference voltages are set according to a preset rule, which includes at least one of an arithmetic sequence, a geometric sequence, and a step sequence.

3. The SPAD array control circuit according to claim 2, characterized in that, The bias voltage regulation circuit further includes a plurality of first voltage selection circuits, each of which corresponds one-to-one with a plurality of drive enhancement circuits. The first voltage selection circuit is disposed between the reference voltage source and the drive enhancement circuit, and is used to receive the plurality of reference voltages provided by the reference voltage source and select one to output to the corresponding drive enhancement circuit.

4. The SPAD array control circuit according to any one of claims 1-3, characterized in that, At least some of the drive enhancement circuits have different drive boosting capabilities, and the number of pixel units corresponding to the drive enhancement circuit with stronger drive boosting capability is greater than the number of pixel units corresponding to the drive enhancement circuit with weaker drive boosting capability; wherein, the pixel unit corresponding to the drive enhancement circuit refers to the pixel unit that is selected to connect to the reference voltage output by the drive enhancement circuit.

5. The SPAD array control circuit according to claim 4, characterized in that, In the pixel unit array, the first voltage terminals of pixel units of the same type are selected to be connected to the same reference voltage output by the driving enhancement circuit; Among them, the same type of pixel unit refers to any two or more pixel units whose difference in ideal reverse bias voltage is less than or equal to the first preset threshold.

6. A control method for a SPAD array control circuit, characterized in that, The SPAD array control circuit is applied to a SPAD array control circuit, which includes a pixel unit array and a bias voltage adjustment circuit located outside the pixel unit array. The bias voltage adjustment circuit includes a reference voltage source and multiple drive enhancement circuits. The input terminal of each drive enhancement circuit receives a reference voltage and outputs it to the pixel unit array. The pixel unit array includes multiple pixel units. The first voltage terminal of the pixel unit selectively receives a reference voltage output by one of the driving enhancement circuits, and the second voltage terminal of the pixel unit is connected to a fixed voltage. The number of driving enhancement circuits is the same as the number of multiple reference voltages provided by the reference voltage source, and is less than the number of pixel units in the pixel unit array. The control method includes: A fixed voltage is provided to the second voltage terminal of each pixel unit in the pixel unit array, and the ideal reference voltage required for the first voltage terminal of each pixel unit is obtained; Based on the ideal reference voltage required by each pixel unit, determine the reference voltages that the reference voltage source needs to output; Based on the reference voltages that the reference voltage source needs to output, the number of pixel units that each reference voltage needs to drive, and the specifications of each driving enhancement circuit, the correspondence between each reference voltage, the driving enhancement circuit, and the pixel unit is determined, and the circuit connection is turned on.

7. The control method according to claim 6, characterized in that, The process of obtaining the ideal reference voltage required for the first voltage terminal of each pixel unit includes: Determine the ideal reverse bias voltage for each pixel unit; The ideal reference voltage required for the first voltage terminal of each pixel unit is determined based on the ideal reverse bias voltage of each pixel unit and the fixed voltage of the second voltage terminal.

8. The control method according to claim 7, characterized in that, The pixel unit includes at least a SPAD, a quenching circuit, and an inverter. The cathode or anode of the SPAD serves as the first voltage terminal of the pixel unit and is connected to the reference voltage output by the drive enhancement circuit. The anode or cathode of the SPAD serves as the second voltage terminal of the pixel unit and is connected to a fixed voltage. The quenching circuit is disposed on the cathode or anode of the SPAD, and the input terminal of the inverter is connected to the intermediate node between the SPAD and the quenching circuit. Determining the ideal reverse bias voltage for each pixel unit includes: Obtain the ideal over-bias voltage of the SPAD within the pixel unit and the threshold voltage of the inverter; The same fixed reference voltage is provided to the first voltage terminal of each pixel unit in the pixel unit array; Adjust the voltage at the second voltage terminal of each pixel unit until the inverter flips, and record the voltage at the second voltage terminal of the pixel unit when each inverter starts to flip; The ideal reverse bias voltage of the pixel unit is determined based on the voltage at the second voltage terminal of the pixel unit when the inverter starts to flip, the ideal over bias voltage of the SPAD in the pixel unit, the fixed reference voltage, and the threshold voltage of the inverter.

9. The control method according to claim 8, characterized in that, In the process of adjusting the voltage at the second voltage terminal of each pixel unit, the control method further includes: The same initial voltage is provided to the second voltage terminal of each pixel unit, and the voltage of the second voltage terminal of each pixel unit is adjusted synchronously and uniformly. For the pixel unit that has already output a pulse signal, while continuing to adjust the voltage of the second voltage terminal of the pixel unit, the fixed reference voltage of the first voltage terminal of the pixel unit is adjusted synchronously so that the voltage difference between the second voltage terminal of the pixel unit and the fixed reference voltage of the first voltage terminal is always less than or equal to the second preset threshold.

10. The control method according to any one of claims 6 to 9, characterized in that, The step of determining the correspondence between each of the reference voltages, the driving enhancement circuit, and the pixel unit, and then connecting the circuits, includes: Based on the ideal reference voltage required by each pixel unit, determine the pixel unit that needs to be driven by each reference voltage; wherein, the difference between the ideal reference voltage required by the pixel unit that needs to be driven and the reference voltage is less than or equal to a third preset threshold. The number of pixel units to be driven corresponding to each of the reference voltages and the specifications of each of the driving enhancement circuits are obtained; Based on the number of pixel units that each reference voltage needs to drive, select the specification-matching drive enhancement circuit, and sequentially connect the reference voltage, the specification-matching drive enhancement circuit, and the corresponding driven pixel units.

11. The control method according to claim 10, characterized in that, The step of determining the pixel unit driven by each reference voltage according to the ideal reference voltage required by each pixel unit includes: The pixel units in the pixel unit array are classified to obtain multiple types of similar pixel units. The difference in the ideal reference voltage required by the similar pixel units is less than or equal to a first preset threshold. Based on the difference between the ideal reference voltage required by various types of pixel units and each of the reference voltages, the pixel units of the same type that each reference voltage should drive are determined.

12. The control method according to claim 11, characterized in that, The step of selecting the specification-matching drive enhancement circuit based on the number of pixel units to be driven according to each of the reference voltages includes: Determine the number of pixel units in the same type of pixel unit that each reference voltage needs to drive; Arrange various similar pixel units according to the number of pixel units, and arrange each driving enhancement circuit according to its size; Multiple pixel units of the same type and each driving enhancement circuit are sequentially matched and connected according to the same arrangement rule.

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