Material carrying table for chip testing and testing method
By combining a layered negative pressure adsorption architecture with an adaptive closed loop, zero-contact, non-destructive fixation is achieved during chip testing. This solves the problems of stress concentration caused by mechanical fixation and displacement caused by lack of fixation, thereby improving the safety and efficiency of chip testing.
Patent Information
- Application Number
- CN202511079119.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-02
- Publication Date
- 2025-11-28
AI Technical Summary
In existing technologies, mechanical fixing methods during chip testing can easily lead to stress concentration, which may damage thin chips. Furthermore, without a fixing method, chips are prone to displacement and misalignment, making it impossible to balance non-destructive constraints and disturbance resistance stability.
Employing a layered negative pressure adsorption architecture, the chip achieves zero-contact, non-destructive fixation through independent negative pressure chambers and an adaptive sealed ring. Combined with an intelligent control system that dynamically adjusts the negative pressure, the chip's airtight stability and positional accuracy are ensured during testing.
It significantly improves the safety and efficiency of testing high-value chips, avoids the risk of damage caused by mechanical fixation, and maintains the structural integrity and positional stability of the chip during the testing process.
Smart Images
Figure CN121027571A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of chip testing, and in particular to a chip testing carrier table and a testing method. BACKGROUND
[0002] In the field of semiconductor testing, reliable fixation of chips is a basic prerequisite for ensuring testing accuracy. The existing technology mainly has two schemes: one is mechanical fixation, which applies physical constraints to the chip through clamping or pressing blocks, but such methods are prone to stress concentration at the edges of microchips, especially for chips with exposed pads or very thin chips, mechanical contact may cause gold wire breakage or damage to the passivation layer; the second is the non-fixed method, which relies only on the weight of the chip or a simple positioning slot to maintain the position, and is prone to displacement when the test probe is contacted or the equipment is vibrated, causing the test point to be offset or even short-circuited. Both of these two schemes cannot balance the non-destructive constraint and the stability against disturbance.
[0003] In view of the above defects, although individual schemes attempt to introduce basic adsorption structures, they do not form a systematic solution: mechanical fixation still cannot avoid local stress, and the non-fixed scheme has a high failure rate in high-speed testing. More importantly, the existing technology lacks adaptability to chip deformation, when the chip has warping or uneven thickness, the fixation force cannot be dynamically adjusted, which may either cause test displacement due to insufficient pressure, or cause hidden cracks due to over-constraint. This results in a risk of damage and reliability bottleneck in the testing process of high-value chips.
[0004] Therefore, there is an urgent need for a chip testing carrier table and a testing method to solve the above problems. SUMMARY
[0005] The present application provides a chip testing carrier table and a testing method, which provides a zero-contact non-destructive fixation method for chip testing through a layered negative pressure adsorption architecture. The independent negative pressure chamber design avoids the stress damage risk caused by mechanical fixation, ensuring the structural integrity of the chip; the self-adaptive airtight ring ensures airtight stability without displacement throughout the test. This scheme significantly improves the safety and efficiency of high-value chip testing, and provides a reliable testing foundation for advanced semiconductor manufacturing.
[0006] In a first aspect, a chip testing carrier table is provided, which includes:
[0007] a base layer, a hollow structure is arranged in the middle of the base layer;
[0008] A negative pressure layer includes a negative pressure generator and a plurality of negative pressure chambers connected with the negative pressure generator through pipelines, the negative pressure layer is arranged above the base layer, the negative pressure generator is located at one side of the negative pressure layer close to the base layer, and the negative pressure generator is accommodated in the hollow structure; and a chip placement layer includes a plurality of chip placement areas corresponding to the negative pressure chambers.
[0009] It should be understood that the space utilization and structural stability of the carrier table are significantly optimized by embedding the negative pressure generator in the carrier base layer hollow structure; the one-to-one correspondence design of the independent negative pressure chamber and the chip placement area realizes independent and accurate control of the chip, avoids the risk of mechanical fixing damage, ensures the adsorption reliability and position accuracy in the whole test process, and provides an efficient and lossless test solution for high-value chips.
[0010] In combination with the first aspect, in some implementations of the first aspect, the chip placement area includes:
[0011] A base is provided with a plurality of adsorption holes, the base is connected with the negative pressure chamber through the adsorption holes, and the adsorption holes are made of elastic material.
[0012] An adaptive airtight ring can adaptively fix the chip and form an airtight environment according to the shape of the chip.
[0013] In combination with the first aspect, in some implementations of the first aspect, the ring wall of the adaptive airtight ring is filled with phase change material, and the adaptive airtight ring is provided with a heat-conducting graphite sheet in contact with the base.
[0014] It should be understood that the flexible connection of the chip and the negative pressure chamber is realized through the elastic adsorption hole structure, and the stress concentration risk caused by the traditional rigid contact is completely eliminated; in combination with the adaptive airtight ring filled with phase change material, the sealing interface is dynamically reshaped when the chip is heated and expanded or has inherent warping, the micro-gap is compensated in real time to ensure the air tightness, and the heat of the chip in the test process is synchronously discharged through the heat-conducting graphite sheet to effectively inhibit the thermal deformation.
[0015] In combination with the first aspect, in some implementations of the first aspect, a valve is arranged in the negative pressure chamber, and a sensor is arranged at one end of the negative pressure chamber close to the base.
[0016] In combination with the first aspect, in some implementations of the first aspect, a pressure relief device is arranged on the inner wall of the negative pressure chamber.
[0017] In combination with the first aspect, in some implementations of the first aspect, the negative pressure generator includes a control device, and the control device controls the opening and closing of the valve according to the data collected by the sensor.
[0018] It should be understood that by integrating the cooperative control architecture of the valve, the sensor and the pressure relief device in the negative pressure chamber, an intelligent adsorption closed-loop system with millisecond response is constructed: the sensor monitors the contact state of the chip in real time, the control device accurately adjusts the valve opening degree according to the pressure data, and realizes dynamic optimization from adsorption start to pressure maintenance; the pressure relief device as a redundant safety module releases the negative pressure instantaneously when the test is abnormal or power failure, which double guarantees the zero suction damage of the chip; this design solves the reliability risk caused by response lag and sudden working conditions in the traditional scheme.
[0019] In combination with the first aspect, in some implementations of the first aspect, the control logic of the control device includes: the control device judging whether the chip is placed on the base according to the data collected by the sensor; if the chip has been placed on the base, the control device controls the valve to open and performs negative pressure adsorption on the chip;
[0020] If the chip is not placed on the base, the control device controls the valve to close;
[0021] If the sensor detects abnormal data, the control device controls the pressure relief device to release pressure. The second aspect provides a chip testing method, characterized in that the method comprises:
[0022] S1: placing a to-be-tested chip on the loading table provided in any implementation of the first aspect;
[0023] S2: starting the negative pressure generator of the loading table to generate negative pressure and performing adsorption on the to-be-tested chip;
[0024] S3: testing the to-be-tested chip;
[0025] S4: after the to-be-tested chip is tested, the negative pressure generator stops generating negative pressure, and a worker takes away the to-be-tested chip.
[0026] It should be understood that the test method relies on the loading table provided in the first aspect, and the negative pressure adsorption is triggered when the chip is placed, realizing reliable fixation without contact; the dynamic pressure closed-loop control ensures that the chip has no displacement deviation during the whole test, and the built-in pressure relief device actively eliminates the risk of suction; after the test, the negative pressure system is intelligently released and assisted by pulse airflow to assist separation, so that the chip taking-off process has no physical damage, which significantly improves the test efficiency and safety of high-value chips, and reduces the operation complexity. BRIEF DESCRIPTION OF DRAWINGS
[0027] Figure 1 A loading table for chip testing provided by the embodiments of the present application is shown in the figure.
[0028] Figure 2A chip test carrier table negative pressure layer schematic diagram provided by an embodiment of the present application.
[0029] Figure 3 A chip test carrier table cross section schematic diagram provided by an embodiment of the present application.
[0030] Figure 4 A negative pressure chamber and negative pressure generator connection schematic diagram provided by an embodiment of the present application. DETAILED DESCRIPTION
[0031] The terms used in the following examples are for the purpose of describing particular embodiments and are not intended to be limiting of the present application. As used in this description and the appended claims, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding the syllables of a list of elements, modify the entire list of elements and do not change the meaning of the list.
[0032] Reference throughout this specification to “one embodiment” or “an embodiment” or “some embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases “in one embodiment,” “in some embodiments,” “in other embodiments,” “in additional embodiments,” and so on, in various places throughout this specification are not necessarily all referring to the same embodiment, unless otherwise specified. The terms “comprise,” “comprising,” “including,” “containing,” “have,” “having,” and “include” and their variations, mean “including but not limited to,” unless otherwise specified.
[0033] In the field of semiconductor testing, reliable fixation of chips is the key to ensuring testing accuracy. The existing technology mainly has two types of defect solutions: the mechanical fixation method is easy to cause stress concentration at the edge of the microchip, especially for thin chips with exposed pads, which may cause gold wire breakage or damage to the passivation layer; and the non-fixation method is easy to cause chip displacement offset in the test vibration, resulting in test point offset or even short circuit. Both solutions cannot balance the non-destructive constraint and anti-disturbance stability. Although individual solutions attempt to introduce basic adsorption structures, they have not been able to systematically solve the problems of stress residue of mechanical fixation and high failure rate of non-fixation.
[0034] The chip test carrier table and the test method provided by the embodiment of the application adopt a layered negative pressure suction structure, eliminate stress damage caused by mechanical fixation through independent negative pressure chambers, realize zero-contact lossless fixation of chips, and significantly improve the safety and efficiency of high-value chip testing, thereby building a reliable test platform for advanced chip manufacturing.
[0035] The technical solutions provided by the embodiment of the application will be described below with reference to the drawings.
[0036] Figure 1 A schematic diagram of a chip test carrier table provided by the embodiment of the application is shown in FIG. 1. Figure 2 A schematic diagram of a negative pressure layer of a chip test carrier table provided by the embodiment of the application is shown in FIG. 2. Figure 1 And Figure 2 In some examples, the carrier table includes:
[0037] A base layer 1, a hollow structure 11 is arranged in the middle of the base layer 1;
[0038] A negative pressure layer 2, the negative pressure layer includes a negative pressure generator 21 and a plurality of negative pressure chambers 22, the negative pressure chambers 22 are connected with the negative pressure generator 21 through a pipeline 23, the negative pressure layer 2 is arranged above the base layer 1, the negative pressure generator 21 is located on the side of the negative pressure layer 2 close to the base layer 1, and the negative pressure generator 21 is accommodated in the hollow structure 11;
[0039] A chip placement layer 3, the chip placement layer 3 includes a plurality of chip placement areas 31, and the chip placement areas 31 correspond to the negative pressure chambers 22 one by one.
[0040] In a possible implementation, the negative pressure generator 21 is located below the negative pressure layer 2, the plurality of negative pressure chambers 22 are independently connected with the negative pressure generator 21, and the negative pressure generator 21 is accommodated in the hollow structure 11 of the base layer 1, so as to reduce the overall occupied volume of the negative pressure layer 2, and make the whole carrier table structure more compact.
[0041] In a possible implementation, the distribution mode of the chip placement areas 31 on the chip placement layer 3 is that the chip placement areas 31 are distributed outward around the center point of the chip placement layer 3. The embodiment of the application does not limit this.
[0042] Figure 3 A schematic diagram of a cross section of a chip test carrier table provided by the embodiment of the application is shown in FIG. 3. Figure 2 In some examples, the chip placement area 31 includes:
[0043] A base 311, a plurality of suction holes 3111 are arranged in the base 311, the base 311 is connected with the negative pressure chamber 22 through the suction hole 3111, and the suction hole 3111 is made of elastic material.
[0044] An adaptive sealing ring 312 that can adaptively fix the chip according to its shape and form a sealed environment.
[0045] With reference to the foregoing Figure 3 In some examples, the ring wall of the adaptive sealing ring 312 is filled with a phase change material, and the adaptive sealing ring 312 is provided with a heat-conducting graphite sheet in contact with the base 311.
[0046] In a possible implementation, the chip placement area 31 of the carrier table adopts an elastic silica gel base, and flexible adsorption holes are distributed on the surface to achieve the buffered connection of the chip and the negative pressure chamber 22; a temperature-sensitive phase change composite material is encapsulated in the adaptive sealing ring 312, and an ultrathin graphite heat-conducting layer is integrated at the bottom of the ring body. When the chip is placed, the elastic adsorption hole absorbs the positioning deviation, and the sealing ring is adaptively attached to the chip contour; when the chip is heated during the test, the phase change material softens and flows to fill the micro gap to form a dynamic seal, and at the same time, the heat-conducting layer uniformly spreads the heat to the base, thereby achieving zero-damage fixation and effectively inhibiting the risk of thermal deformation.
[0047] Figure 4 A negative pressure chamber and a negative pressure generator are connected, and a schematic diagram is provided for the embodiments of the present application. With reference to the foregoing Figure 4 In some examples, a valve 24 is arranged in the negative pressure chamber 22, and a sensor 25 is arranged at one end of the negative pressure chamber 22 close to the base 311.
[0048] With reference to the foregoing Figure 4 In some examples, a pressure relief device 26 is arranged on the inner wall of the negative pressure chamber 22.
[0049] With reference to the foregoing Figure 4 In some examples, the negative pressure generator 21 comprises a control device 27, which controls the opening and closing of the valve 24 according to the data collected by the sensor 25.
[0050] In a possible implementation, a miniature electromagnetic valve and a contact pressure sensor are installed in each negative pressure chamber 22, and the sensor monitors the contact state of the chip and the base 311 in real time. When the chip is detected to be placed, the control device immediately drives the valve 24 to open, and the negative pressure generator 21 starts the adsorption process; during the test, the control device dynamically analyzes the pressure data and automatically adjusts the valve opening to maintain a constant and stable adsorption force. In particular, a mechanical pressure relief device is embedded in the inner wall of the chamber as an independent safety module. If abnormal pressure fluctuation or sudden power failure is detected, the pressure relief device is instantly connected to the atmospheric pressure to realize negative pressure zero, and at the same time, the control device synchronously closes the valve to cut off the air source. This design forms a double protection mechanism, which completes the full-process automatic control from precise adsorption to safe release on the premise of ensuring zero over-absorption damage.
[0051] In some examples, the control logic of the control device 27 comprises:
[0052] The control device 27 determines whether the chip is placed on the base 311 according to the data collected by the sensor 25;
[0053] If the chip has been placed on the base 311, the control device 27 controls the valve 24 to open and performs negative pressure adsorption on the chip;
[0054] If the chip is not placed on the base 311, the control device 27 controls the valve 24 to close;
[0055] If the sensor 25 detects abnormal data, the control device 27 controls the pressure relief device 26 to relieve pressure.
[0056] The embodiment of the present application also provides a chip testing method, which comprises:
[0057] S1: placing a chip to be tested on the loading table as described in any of the preceding examples;
[0058] S2: starting the negative pressure generator 21 of the loading table to generate negative pressure and adsorb the chip to be tested;
[0059] S3: testing the chip to be tested;
[0060] S4: after the chip to be tested is tested, the negative pressure generator 21 stops generating negative pressure, and a worker takes away the chip to be tested.
[0061] The above is only the preferred embodiment of the present application, and the protection scope of the present application is not limited to the above-mentioned embodiment, but any equivalent modification or change made by those skilled in the art according to the disclosed content of the present application shall be included in the protection scope recorded in the claims.
Claims
1. A carrier table for testing a chip, characterized by comprising: The loading platform includes: A base layer (1) with a hollow structure (11) in the middle; a negative pressure layer (2) including a negative pressure generator (21) and multiple negative pressure chambers (22), the negative pressure chambers (22) being connected to the negative pressure generator (21) via pipes (23), the negative pressure layer (2) being disposed on the base layer (1), the negative pressure generator (21) being located on the side of the negative pressure layer (2) close to the base layer (1), the negative pressure generator (21) being housed in the hollow structure (11); a chip placement layer (3) including multiple chip placement areas (31), the chip placement areas (31) corresponding one-to-one with the negative pressure chambers (22).
2. The material loading platform according to claim 1, characterized in that, The chip placement area (31) includes: a base (311) having multiple adsorption holes (3111) and being connected to the negative pressure chamber (22) through the adsorption holes (3111), wherein the adsorption holes (3111) are made of elastic material; and an adaptive sealing ring (312) which can adaptively fix the chip according to the shape of the chip and form a sealed environment.
3. The material loading platform according to claim 2, characterized in that, The adaptive closed ring (312) is filled with phase change material in its ring wall, and the adaptive closed ring (312) is provided with a thermally conductive graphite sheet that contacts the base (311).
4. The material loading platform according to claim 1, characterized in that, A valve (24) is provided in the negative pressure chamber (22), and a sensor (25) is provided at one end of the negative pressure chamber (22) near the base (311).
5. The material loading platform according to claim 4, characterized in that, The inner wall of the negative pressure chamber (22) is provided with a pressure relief device (26).
6. The material loading platform according to claim 5, characterized in that, The negative pressure generator (21) includes a control device (27), which controls the opening and closing of the valve (24) based on the data collected by the sensor (25).
7. The material loading platform according to claim 6, characterized in that, The control logic of the control device (27) includes: the control device (27) determines whether the chip is placed on the base (311) based on the data collected by the sensor (25); if the chip is already placed on the base (311), the control device (27) controls the valve (24) to open and perform negative pressure adsorption on the chip; If the chip is not placed on the base (311), the control device (27) controls the valve (24) to close; if the sensor (25) detects abnormal data, the control device (27) controls the pressure relief device (26) to relieve pressure.
8. A chip testing method, characterized in that, The method includes: S1: Place the chip under test onto the loading stage as described in any one of claims 1 to 7; S2: Start the negative pressure generator (21) of the loading stage to generate negative pressure and adsorb the chip to be tested; S3: Test the chip under test; S4: After the chip under test is completed, the negative pressure generator (21) stops generating negative pressure, and the staff removes the chip under test.