Chip testing method, device, equipment and medium

Abstract

The invention relates to the technical field of chip testing, and discloses a method, a device, equipment and a medium for chip testing, and the method comprises the following steps: based on configuration requirements of chip testing, executing write-in operation on registers in a plurality of chips to be tested; based on a comparison result of the state value of the target register among the plurality of to-be-tested chips before the write-in operation is executed, and / or based on a comparison result of the state value of the target register among the plurality of to-be-tested chips after the write-in operation is executed, the type of the target register is determined, and the type of the register comprises a static configuration register and a dynamic configuration register; and generating a test vector corresponding to the type of the register, and testing the plurality of to-be-tested chips based on the test vector. The test time and the mass production cost can be greatly reduced, and meanwhile, the time cost and the equipment occupation cost in the mass production stage can be remarkably reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, and in particular to a method, device, equipment and medium for chip testing. BACKGROUND

[0002] In the field of chip mass production testing, register configuration is the core link to realize all test functions. For example, serializer and deserializer (SerDes) rate configuration, power parameter calibration, and firmware program loading, etc. The essence of register configuration is to send control instructions to chip registers through test vectors, so as to drive the chip to enter the target test mode and feedback state data.

[0003] How to reduce test time and cost under the premise of ensuring test quality has become a problem to be solved in the field of automatic test equipment (ATE) testing. SUMMARY

[0004] The present application provides a method, device, equipment and medium for chip testing to solve the problem of high test time and test cost in ATE testing.

[0005] In a first aspect, the present application provides a method for chip testing, the method comprising: performing a write operation on a register in a plurality of chips to be tested based on configuration requirements of chip testing; determining a type of the target register based on a comparison result of a state value of the target register among the plurality of chips to be tested before the write operation is performed, and / or a comparison result of the state value of the target register among the plurality of chips to be tested after the write operation is performed, the type of the register including a static configuration register and a dynamic configuration register; generating a test vector corresponding to the type of the register, and testing the plurality of chips to be tested based on the test vector.

[0006] In an optional implementation, the write operation on the register in the plurality of chips to be tested based on the configuration requirements of chip testing comprises: reading, writing and re-reading operations on the register in the plurality of chips to be tested based on the configuration requirements of chip testing, to obtain an initial value, a modified value and a re-read value, the plurality of chips to be tested comprising a plurality of registers, and the plurality of chips to be tested being of the same model.

[0007] In an optional implementation, the determining the type of the register based on a comparison result of the state value of the target register among the plurality of chips to be tested before the write operation is performed and a comparison result of the state value of the target register among the plurality of chips to be tested after the write operation is performed comprises: determining that the target register is the static configuration register if each initial value of the target register in the plurality of chips to be tested is the same and each re-read value of the target register is the same; determining that a register other than the static configuration register in the chip to be tested is the dynamic configuration register; or determining that the target register is the dynamic configuration register if each initial value of the target register is the same and the re-read value of the target register has a difference among the plurality of chips to be tested.

[0008] In an optional implementation, the generating the test vector corresponding to the type of the register in the chip to be tested comprises: splicing the modified value of the static configuration register, the initial value of the dynamic configuration register and the modified value of the dynamic configuration register to generate a test vector based on a preset sequence of the chip test.

[0009] In an optional implementation, the performing the reading, the writing and the re-reading operations on the registers in the plurality of chips to be tested based on the configuration requirement of the chip test to obtain the initial value, the modified value and the re-read value comprises: reading an initial value of a target register in the plurality of chips to be tested; determining a modified value of the target register based on the configuration requirement of the chip test, writing the modified value into the target register; re-reading the target register to obtain a re-read value of the target register; performing the reading, the writing and the re-reading operations on a next register of the target register until the operations on all the registers in the plurality of chips to be tested are completed.

[0010] In an optional implementation, the testing the plurality of chips to be tested based on the test vector comprises: splicing the modified value of the static configuration register, the initial value of the dynamic configuration register and the modified value of the dynamic configuration register to generate a standard test interface language file; converting the standard test interface language file into a binary vector file; and testing the plurality of chips to be tested based on the binary vector file.

[0011] In an optional implementation, the type of the register is determined based on a comparison result of a state value of the target register among the plurality of chips to be tested before the write operation is performed, or based on a comparison result of the state value of the target register among the plurality of chips to be tested after the write operation is performed, and the type of the register includes a static configuration register and a dynamic configuration register.

[0012] In a second aspect, the present application provides a device for chip testing, the device comprising: a debugging module configured to perform a write operation on a register in a plurality of chips to be tested based on a configuration requirement of chip testing; a classification module configured to determine a type of a target register based on a comparison result of a state value of the target register among the plurality of chips to be tested before the write operation is performed, and / or based on a comparison result of the state value of the target register among the plurality of chips to be tested after the write operation is performed, the type of the register including a static configuration register and a dynamic configuration register; and a testing module configured to generate a test vector corresponding to the type of the register, and perform testing on the plurality of chips to be tested based on the test vector.

[0013] In a third aspect, the present application provides an electronic device, comprising a memory and a processor, the memory and the processor being communicatively connected, and the memory storing computer instructions, and the processor executing the computer instructions to perform the method for chip testing according to the first aspect or any one of the corresponding implementation forms thereof.

[0014] In a fourth aspect, the present application provides a computer readable storage medium, and the computer readable storage medium stores computer instructions, and the computer instructions are used to make a computer execute the method for chip testing according to the first aspect or any one of the corresponding implementation forms thereof.

[0015] In a fifth aspect, the present application provides a computer program product, and the computer program product comprises computer instructions, and the computer instructions are used to make a computer execute the method for chip testing according to the first aspect or any one of the corresponding implementation forms thereof.

[0016] Compared with a pure dynamic vector configuration scheme, the method, device, equipment and medium for chip testing provided in the embodiment can reduce the number of dynamic vectors by more than 80% by automatically screening static configuration registers, can reduce the time overhead of dynamic vector software modification, can shorten the single-chip test time by 95%, and can reduce the test time from 120 seconds to 6 seconds, thereby greatly reducing the test time and mass production cost; meanwhile, compared with the cross-field research and bit-by-bit verification scheme in the related art, the automatic classification of the test classification program can shorten the SerDes chip test development cycle from 7 months to 1 month, reduce the test time by 70%, and can significantly reduce the time cost and equipment occupation cost in the mass production stage. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the specific embodiments or the prior art, the drawings needed to be used in the specific embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] Figure 1 is a schematic diagram of an application scenario according to an embodiment of the present application; Figure 2 A register configuration flowchart in the related art is shown; Figure 3 A flowchart of configuring a dynamic configuration register in the related art is shown; Figure 4 A flowchart of configuring a static configuration register in the related art is shown; Figure 5 A flowchart of a method for chip testing according to an embodiment of the present application is shown; Figure 6 A data flow diagram of re-reading after a write operation in an embodiment of the present application is shown; Figure 7 A comparison result diagram of a plurality of chips to be tested in an embodiment of the present application is shown; Figure 8 A flowchart of a splicing process in an embodiment of the present application is shown; Figure 9 A structural diagram of a device for chip testing provided in an embodiment of the present application is shown; Figure 10 is a hardware structure diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0020] It can be understood that, before using the technical solutions disclosed in the embodiments of the present application, the type, use range, use scenario and the like of the personal information involved in the present application should be informed to the user and the authorization of the user should be obtained through appropriate means according to relevant laws and regulations.

[0021] The terms "first", "second" are only for descriptive purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more than two, unless otherwise specifically limited.

[0022] The concepts involved in the present application will be introduced below.

[0023] Automatic test equipment (ATE) testing is used for automatic function and performance verification in the chip mass production stage, and the core is to send configuration instructions to the chip through test vectors, and receive feedback to judge whether the chip is qualified.

[0024] Automatic test pattern generation (ATPG) testing is the core scenario of design for testability (DFT), and relies on static vectors to achieve efficient fault detection.

[0025] As an optional application scenario of the embodiments of the present application, Figure 1 The application scenario of the method for chip testing provided by the embodiments of the present application is shown, as shown in Figure 1 In the application scenario of the method for chip testing, at least one terminal device and at least one server can be included, Figure 1 The system includes a computer 101, a mobile terminal 102 and a server 103, and the terminal devices such as the computer 101 and the mobile terminal 102 are connected to the server 103 through a network 110.

[0026] Among them, the terminal device includes a computer 101 and a mobile terminal 102, which can be specifically a smart phone, a tablet computer, a notebook computer, a palm computer, and can also be a desktop computer, a game console, a smart television, a smart wearable device, a vehicle-mounted terminal, a VR (Virtual Reality) device, an AR (Augmented Reality) device, an ATE test machine, etc. The server 103 can be a standalone physical server, or a server cluster or distributed system, or a cloud server providing cloud services. The network 110 can be a wired network or a wireless network, and its examples include but are not limited to the Internet, an intranet, a local area network, a wide area network, a mobile communication network, and a combination thereof.

[0027] In the field of chip mass production testing, according to the difference of configuration logic and data characteristics, the test vector includes static test vector and dynamic test vector, and the two have significant differences in application scene and execution efficiency: On the one hand, the static test vector has extremely high test efficiency because it does not need to modify the data in real time, and has been widely used in ATPG test scenarios, such as normal scan test (DC Scan), at-speed scan (AC Scan), and register full field coverage write-in scenarios, which are key technical means to ensure test efficiency.

[0028] On the other hand, the dynamic test vector needs to read the original state value of the register by the tester, modify the target field through software, and then write the modified data back to the register, which is mainly used in scenarios of automatic configuration or adaptive adjustment of chip kernel, such as external impedance calibration or SerDes rate adaptation. However, the time overhead of the software modification link of this type of vector accounts for more than 90%, which becomes the core bottleneck restricting the efficiency of mass production testing.

[0029] With the continuous improvement of chip integration and functional complexity, a typical mass production functional test needs to involve configuration operations of tens of thousands of registers, and most of the registers only need to modify a few bit positions, such as adjusting only the 4-7 bit field of the register. Under this background, the following problems are faced: First, it is difficult to distinguish the type of register configuration.

[0030] The logic complexity of the test firmware is extremely high, and engineers from multiple fields such as architecture design, IP development, ATE testing, etc. need to cooperate to clarify the register configuration behavior; and third-party IP suppliers usually cannot provide complete register configuration logic documents, and engineers are prone to miss when manually distinguishing static or dynamic configuration registers, which may lead to test quality risks, such as misjudging dynamic configuration registers as static configuration, causing abnormal chip functions.

[0031] Second, there is a contradiction between test cost and configuration risk.

[0032] If all registers are uniformly configured according to dynamic vectors, the read-modify-write process of tens of thousands of registers will cause the single-chip test time to increase from seconds to minutes, and the production cost will rise sharply. If all registers are uniformly configured according to static vectors, it is easy to mismodify non-target fields of registers, causing configuration mismatch risk. In the later stage, register data needs to be exported (dumped), compared with laboratory debugging data, and then problems are located, and the debugging efficiency is significantly low.

[0033] In related technologies, the technical solutions for classifying register configuration vectors include: First, organization architects, IP engineers and ATE engineers discuss and preliminarily determine the range of static configuration registers; ATE engineers check the configuration correctness step by step and bit by bit to verify the feasibility of static vectors.

[0034] Second, all registers are uniformly configured according to dynamic vectors, that is, all registers perform the read-modify-write process without distinguishing static attributes and dynamic attributes.

[0035] Third, all registers are uniformly configured according to static vectors, that is, fixed values are directly written to registers, and all registers are assumed to be static.

[0036] The first technical solution in related technologies has the problems of large development workload, long cycle and high labor cost. In this solution, manual cooperation of engineers in multiple fields is needed, and tens of thousands of registers need to be verified bit by bit for configuration correctness, which will cause the ATE test development workload to grow exponentially. For example, in the test project of a certain SerDes IP chip, an engineer with 9 years of ATE test experience needs to invest 7 months of time to complete the division and verification of static and dynamic registers, which is significantly high in labor cost and time cost, and cannot meet the rapid development needs of large-scale chip production.

[0037] Figure 2 A register configuration flowchart in related technologies is shown. As Figure 2As shown, in the related art, the static and dynamic configuration requirements of the registers are artificially divided by the ATE test engineers to determine the static configuration registers and the dynamic configuration registers, which exemplarily include the first static configuration register 201, the second static configuration register 202, the first dynamic configuration register 211, and the third static configuration register 203. The test vectors are divided into two categories, namely, static test vectors and dynamic test vectors. For the dynamic configuration registers, the following steps are performed: step S21, reading, the time for performing this step is about 1.5 uS; step S22, modifying 4-7 bits, for example, the 4-7 bits are parameters obtained by the chip central processing unit (CPU) according to the chip running environment, and the external debugger or the mass production test equipment is not allowed to change, therefore, the external equipment needs to read the value in this register from the chip first, keep the 4-7 bits unchanged, and then write the data in the 0-3 and 8-31 bits into the chip after modification, the time for performing this step is about 1 Ms; and step S23, writing, the time for performing this step is about 1 uS. For the static configuration registers, the following step is performed: step S23, writing, the time for performing this step is about 1 uS. Under the premise of accurate positioning of the register type (dynamic and static), the test efficiency is high, but it is difficult to distinguish between static and dynamic registers, resulting in high development difficulty and long development cycle.

[0038] The second technical solution in the related art has the problem of uncontrolled test cost in a large-scale scenario. The core bottleneck of the dynamic test vector is the time overhead of the software modification link, which accounts for more than 90% of the total time of single register configuration. In a large-scale test scenario involving tens of thousands of registers, the single-chip test time will increase by more than 10 times, for example, from 10 seconds to 100 seconds. The test equipment occupancy cost and time cost in the mass production stage increase sharply, which is only suitable for small-scale test scenarios with fewer registers and cannot meet the mass production needs of complex chips.

[0039] Figure 3 A flowchart for configuring dynamic configuration registers in the related art is shown. As shown in the figure, Figure 3 In the related art, all registers are uniformly configured as dynamic configuration registers, and the following steps are performed for all registers: step S21, reading, the time for performing this step is about 1.5 uS; step S22, modifying 4-7 bits, the time for performing this step is about 1 Ms; and step S23, writing, the time for performing this step is about 1 uS. The test efficiency is low, but the development difficulty is small and the development cycle is short.

[0040] The third technical solution in the related art has the problems of high mismatch risk and low post-debugging efficiency. This solution directly configures all registers as static configuration registers. Figure 4A flowchart of configuring a static configuration register in the related art is shown. As shown in Figure 4 All registers are uniformly configured as static configuration registers, and steps S23, writing, are performed on all registers. The time for performing this step is about 1uS. Dynamic configuration registers are misjudged as static configuration registers, resulting in abnormal chip functions, such as impedance calibration failure or SerDes rate mismatch. In the later stage, register data needs to be dumped by a laboratory debugger, and compared with production test data field by field to locate the problem, which not only has a long debugging period, but also cannot guarantee that the mismatch risk is completely solved, seriously affecting the production progress and product yield. The test efficiency is high, but there are unknown risks and cannot be used.

[0041] There is also a method for determining dynamic parameters according to the number of running frames and environmental parameters in the related art, which is a dynamic vector or register configuration scheme, which can be used in scenarios where dynamic configuration is explicitly required. However, it requires researchers to analyze and obtain related dynamic register addresses, which has certain implementation difficulty, and requires a large amount of human resources when dealing with a large-scale dynamic configuration scheme.

[0042] To solve the problems of low development efficiency, high test cost and large mismatch risk in the related art, the embodiments of the present application start from the dual dimensions of methodological innovation and process optimization, take debugging risk-free, data-driven classification and automatic conversion as the core design concept, and propose a method, device, equipment and medium for chip testing.

[0043] According to the embodiments of the present application, a method for chip testing is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0044] A method for chip testing is provided in this embodiment, which can be used in the terminal device described above, Figure 5 A flowchart of the method for chip testing according to the embodiments of the present application is shown, as shown in Figure 5 The flowchart includes the following steps: Step S501, based on the configuration requirement of chip testing, performing a write operation on the registers in the plurality of chips to be tested.

[0045] In the implementation process of the embodiments of the present application, dynamic configuration is taken as the debugging basis to ensure no risk. All debugging and testing work is based on dynamic vector, and its configuration logic is consistent with that of the laboratory debugger, which can avoid chip function abnormalities caused by misjudgment of static configuration, and ensure the reliability of the debugging process.

[0046] The chips to be tested, used for characterizing the chips for which the method for chip testing provided by the embodiments of the present application is used to perform function verification, can be multiple chips of the same model, used for batch testing or consistency verification, etc. The register, used for characterizing a high-speed storage unit inside the chip, temporarily stores data, state or control signals. The write operation, used for characterizing the operation of writing specific data to the address space of the register by the test equipment, for example, ATE.

[0047] Based on the configuration requirements of the chip testing, for example, verifying whether the register can correctly receive data, the test tool can write preset data to all or part of the registers in the chip to be tested. For example, the field of four to seven bits of a certain register is modified, and the original value 0xAAAA is modified to 0xAAFA. The write data can be used for register configuration.

[0048] Step S502, based on the comparison results of the state values of the target register among the multiple chips to be tested before the write operation is executed, and / or the comparison results of the state values of the target register among the multiple chips to be tested after the write operation is executed, the type of the register is determined, and the type of the register includes a static configuration register and a dynamic configuration register.

[0049] In this step, the state value of the register is used to represent the specific value stored by the register at a certain time, which can reflect the current state of the register. The comparison result is used to represent the difference in the state value of the target register among the multiple chips to be tested before the write operation is executed, and the difference in the state value of the target register among the multiple chips to be tested after the write operation is executed. The static configuration register is used to represent the register that can be configured by a static vector. The dynamic configuration register is used to represent the register that can only be configured by a dynamic vector.

[0050] The initial value of the register state can be read before writing, and the re-reading value of the register state can be read after writing. Based on the comparison result of the state value of the target register among the plurality of chips to be tested before the writing operation is performed, and / or based on the comparison result of the state value of the target register among the plurality of chips to be tested after the writing operation is performed, the type of the register is determined, including: determining the type of the register based on the comparison result of the state value of the target register among the plurality of chips to be tested before the writing operation is performed; or determining the type of the register based on the comparison result of the state value of the target register among the plurality of chips to be tested after the writing operation is performed; or determining the type of the register based on the state value of the target register that is not written bit before and after the writing operation is performed, for example, the 3-31 bits are externally modified, and the 0-2 bits before and after writing are compared to determine whether the 0-2 bits are dynamic configuration registers; or determining the type of the register based on the comparison result of the state value of the target register among the plurality of chips to be tested before the writing operation is performed, and the comparison result of the state value of the target register among the plurality of chips to be tested after the writing operation is performed.

[0051] Specifically, the static configuration register, before the writing operation is performed, the initial value of the state is consistent among the plurality of chips to be tested, and after the writing operation is performed, the re-reading value of the state is consistent among the plurality of chips to be tested; without real-time modification, the test time can be greatly reduced.

[0052] The dynamic configuration register, before the writing operation is performed, the initial value of the state may be different among the plurality of chips to be tested; before the writing operation is performed, the initial value of the state may be consistent among the plurality of chips to be tested, and after the writing operation is performed, the re-reading value of the state may be different among the plurality of chips to be tested; after the writing operation is performed, the re-reading value of the state may be different among the plurality of chips to be tested. The foregoing features of the dynamic configuration register may be caused by the self-adaptation of the chip kernel.

[0053] Step S503, generating a test vector corresponding to the type of the register, and testing the plurality of chips to be tested based on the test vector.

[0054] In this step, the test vector is used to represent the input data sequence of the register in the test chip and the corresponding expected output, which is the basis for chip testing. Based on the type of the register determined in step S502, a specific test vector is designed, and the plurality of chips to be tested are tested based on these test vectors to verify whether the register function in the chip to be tested meets the design requirements.

[0055] The static test vector corresponding to the static configuration register is used to represent a vector that remains unchanged during the test process and does not need to be modified in real time. The static test vector can be used in an ATPG test scenario, for example, a DC Scan or an AC Scan, and a scenario in which the functional test logic configuration is completely determined, for example, a test scenario in which all fields of the register are overwritten, and the test efficiency is high.

[0056] The dynamic test vector corresponding to the dynamic configuration register is used to represent a vector that needs to be dynamically modified and changed in real time during the test process. The dynamic test vector can be used in a kernel automatic configuration or an adaptive test scenario during chip operation. For example, only part of the fields of the register is modified. The test machine software and hardware need to be cooperatively completed.

[0057] Compared with a pure dynamic vector configuration scheme, the method for chip testing provided in the embodiment can reduce the number of dynamic vectors by more than 80% by automatically screening static configuration registers, can reduce the time overhead of dynamic vector software modification, can shorten the single-chip test time by 95%, and can reduce the test time from 120 seconds to 6 seconds, thereby greatly reducing the test time and production cost. At the same time, compared with the scheme of cross-field research and bit-by-bit verification in the related art, the method can shorten the SerDes chip test development cycle from 7 months to 1 month, reduce the test time by 70%, and can significantly reduce the time cost and equipment occupation cost in the production stage.

[0058] In some optional embodiments, based on the configuration requirement of chip testing, a write operation is performed on the registers in the plurality of chips to be tested, including: based on the configuration requirement of chip testing, performing a read, write and re-read operation on the registers in the plurality of chips to be tested, to obtain an initial value, a modified value and a re-read value. The chip to be tested includes a plurality of registers, and the plurality of chips to be tested are of the same model.

[0059] In the embodiment, Figure 6 A data flow diagram of re-reading after a write operation in the embodiment of the application is shown in FIG. 6. Figure 6 As shown in FIG. 6, a re-reading operation is added in the dynamic configuration process of each register in the chip to be tested, that is, the re-reading operation is performed after the read and write operations.

[0060] Specifically, in the related art, as shown in 601, the registers in the plurality of to-be-tested chips are all dynamically configured, and the debug data flow determined based on the configuration requirement of chip testing is: reading reg1, writing reg1, reading reg2, writing reg2, reading reg3, writing reg3,..., reading regN, and writing regN. That is, reading the state value of register 1, modifying the state value of register 1, reading the state value of register 2, modifying the state value of register 2,..., reading the state value of register N, and modifying the state value of register N.

[0061] In the embodiment, for a single register, the register state is first read to obtain an initial value, then the modified data is written according to the configuration requirement of chip testing, the modified value is recorded, and finally the current state value of the register is immediately re-read to obtain a re-read value.

[0062] As shown in 602, the debug data flow determined based on the configuration requirement of chip testing includes a read data flow, a write data flow, and a re-read data flow, and specifically includes: reading reg1, writing reg1, re-reading reg1, reading reg2, writing reg2, re-reading reg2, reading reg3, writing reg3, re-reading reg3,..., reading regN, writing regN, and re-reading regN. That is, reading the state value of register 1, modifying the state value of register 1, re-reading the state value of register 1, reading the state value of register 2, modifying the state value of register 2, re-reading the state value of register 2,..., reading the state value of register N, modifying the state value of register N, and re-reading the state value of register N.

[0063] The debug data flow can be saved to a configuration file to provide a data basis for subsequent register classification. The saving format of the debug data flow can be adjusted. Specifically, the file format for saving the debug data flow can be TXT format, Excel format, or JSON format. The Excel format is convenient for engineers to intuitively view the correspondence between the register address and the data, and the JSON format is convenient for automatic script analysis. Both formats can completely save the data flow information and do not affect the subsequent vector conversion logic.

[0064] The number of to-be-tested chips can be a first number, specifically, a small batch of to-be-tested chips, for example, 10 to 12 chips. The to-be-tested chips include chips of different production batches and different process angles.

[0065] In this way, the re-reading operation is added in the data stream collection mechanism, the debug data stream of reading, writing and re-reading is generated, the data is obtained through the actual hardware behavior, which is more objective and reliable, can provide accurate data basis for subsequent register classification; meanwhile, the complete data record of reading, writing and re-reading can facilitate subsequent problem tracing, and enhance the traceability of the scheme.

[0066] In some optional embodiments, based on the comparison result of the state value of the target register among the plurality of to-be-tested chips before the write operation is performed and the comparison result of the state value of the target register among the plurality of to-be-tested chips after the write operation is performed, the type of the register is determined, including: if each initial value of the target register in the plurality of to-be-tested chips is the same, and each re-reading value of the target register is the same, it is determined that the target register is a static configuration register; it is determined that the register in the to-be-tested chip except the static configuration register is a dynamic configuration register; or, if each initial value of the target register in the plurality of to-be-tested chips is the same, and the re-reading value of the target register exists difference among the plurality of to-be-tested chips, it is determined that the target register is a dynamic configuration register.

[0067] In the embodiment, the debug scheme is performed to collect the full-flow data stream of each chip. The initial value obtained by reading and the re-reading value obtained by re-reading can be compared through software for the same operation step and the same address register. If the data stream of the target register in the plurality of to-be-tested chips is completely consistent among the plurality of to-be-tested chips, it is determined that the target register is a static configuration register; if the data stream of the target register in the plurality of to-be-tested chips exists difference among the plurality of to-be-tested chips, it is determined that the target register is a dynamic configuration register.

[0068] Figure 7 The comparison result of the plurality of to-be-tested chips in the embodiment of the application is shown. As shown in Figure 7 The plurality of to-be-tested chips are of the same model, and the number is 12. The plurality of to-be-tested chips include chip 1, chip 2, chip 3, …, chip 12. The initial value of reg1 in each to-be-tested chip is the same, and the re-reading value of reg1 is the same, and it is determined that reg1 is a static configuration register. Similarly, reg3 and regN are static configuration registers. After all the static configuration registers are screened out, the register except the static configuration register is a dynamic configuration register, and it can be determined that reg2 is a dynamic configuration register. Or, based on the initial value or the re-reading value of reg2, there exists difference among the plurality of to-be-tested chips, and it is determined that reg2 is a dynamic configuration register.

[0069] In this way, the automatic distinction of the register type can replace manual judgment, the problem of missing dynamic configuration registers caused by insufficient experience of engineers can be avoided, more than 90% of manual operation errors can be reduced, meanwhile, repeated alignment of register configuration logic by cross-domain engineers is not needed, more than 80% of communication costs can be reduced, and in addition, the vector generation logic is based on data flow comparison, the technical principle is transparent and traceable, the code reading workload is reduced by 80%, and the later maintenance and version iteration are facilitated.

[0070] In some optional embodiments, the test vector corresponding to the type of the register in the chip to be tested is generated by splicing the modified value of the static configuration register, the initial value of the dynamic configuration register and the modified value of the dynamic configuration register based on a preset sequence of chip testing.

[0071] In the embodiment, the preset sequence is used to represent the sequence of the chip testing process. The write data flow of the static configuration register, i.e., the modified value of the static configuration register, can be automatically extracted from the debug data flow to generate a static test vector segment, the read and write data flow of the dynamic configuration register, i.e., the initial value and the modified value of the dynamic configuration register, can be extracted to generate a dynamic test vector segment, and the static test vector segment and the dynamic test vector segment can be combined based on the sequence of the chip testing process to generate the test vector.

[0072] Figure 8 A flowchart of a splicing process in the embodiment of the application is shown. As shown in Figure 8 , it is determined that reg2 is a dynamic configuration register based on the foregoing steps, and the remaining reg1, reg2, reg3 and regN are static configuration registers. The splicing process includes: in step S801, the modified value of the static configuration register, i.e., the write reg1, write reg3 and write regN in Figure 8 , can be extracted from the debug data flow of the chip to be tested; in step S802, the initial value and the modified value of the dynamic configuration register, i.e., the read reg2 and write reg2 in Figure 8 , can be extracted from the debug data flow of the chip to be tested; and in step S803, the vectors of steps S801 and S802 are spliced to generate the test vector.

[0073] Specifically, the automatic conversion of the debug data flow to the mass production vector is implemented, including: first, extracting the static test vector. The write data flow, i.e., the initial value, of the static configuration register is selected from the debug data flow, and the read data flow and the read-again data flow, i.e., the modified value and the read-again value, are removed, to generate a static test vector segment, because the static configuration register does not need to be read in real time for verification. For example, for the static register reg1, only the vector instruction of write reg1 (0xAAFA) is retained.

[0074] Second, the dynamic test vector is reserved. For the dynamic configuration register, the read data stream and the write data stream, i.e., the initial value and the modified value, are reserved, and the repeated read data stream, i.e., the repeated read value, is removed, so that the dynamic test vector segment is not generated for repeated verification in the mass production stage. For example, for the dynamic register reg2, the vector instruction of reading reg2 (0xBBBB) and writing reg2 (0xBBFB) is reserved.

[0075] In this way, by splicing the debugging data of the chips to be tested, for the static configuration register, real-time read verification is not required, only the modified value is reserved, the length of the test vector can be reduced, for the dynamic configuration register, the repeated read data stream is removed, and repeated verification is not required in the mass production stage of the chip, the total test time can be reduced, and the test throughput can be improved.

[0076] In some optional embodiments, based on the configuration requirement of chip testing, the read, write and re-read operations are performed on the registers in the plurality of chips to be tested, and the initial value, the modified value and the repeated read value are correspondingly obtained, including: reading the initial value of a target register in the plurality of chips to be tested; determining the modified value of the target register based on the configuration requirement of chip testing, writing the modified value into the target register; re-reading the target register to obtain the repeated read value of the target register; performing the read, write and re-read operations on a next register of the target register until the operations on all the registers in the plurality of chips to be tested are completed.

[0077] In the embodiment, first, the read operation is performed on the registers in the plurality of chips to be tested, including: sequentially reading the original state values of all the registers to be configured based on a preset order of chip testing, such as reg1-regN, to generate a read data stream. For example, the initial value of the register reg1 is 0xAAAA, which will be used as a reference for subsequent configuration.

[0078] Second, the write operation is performed on the registers in the plurality of chips to be tested, including: modifying the target field of each register according to the configuration requirement of the test function, for example, modifying the specific bit of the register, generating a write data stream, and inserting the write data stream after the read data stream of the corresponding register. For example, the 4-7 bit field of reg1 needs to be modified, and the initial value 0xAAAA can be overwritten as the modified value 0xAAFA, and the write data will be directly used for register configuration.

[0079] Third, the re-read operation is performed on the registers in the plurality of chips to be tested, including: immediately re-reading the current value of each register after the write data stream of the register is executed, generating a repeated read data stream and inserting the repeated read data stream into the flow, so as to verify the validity of the write data. For example, after reg1 is written as 0xAAFA, the value of reg1 is still 0xAAFA, which indicates that the write operation is valid.

[0080] Finally, save the debug data flow. The full flow data flow (including register address, read / write operation type, data value, waiting time parameter, such as 40 ms after reset) of read→write→reread is saved as a standardized configuration file, for example, MacroAndTXRelease.txt, to ensure the integrity and traceability of the data flow. A typical data flow process can be: read reg1 (0xAAAA)→write reg1 (0xAAFA)→reread reg1 (0xAAFA)→read reg2 (0xBBBB)→write reg2 (0xBBFB)→reread reg2 (0xBBFB)→…→read regN (0xFFFF)→write regN (0xFFF8)→reread regN (0xFFF8).

[0081] In this way, the read-write-reread full flow data flow record can be realized, and complete data support can be provided for subsequent classification; at the same time, the full flow data flow and its saving mechanism can provide complete data support for test problem tracing, further improve the reliability of production testing, and can significantly improve the reliability and maintainability of testing.

[0082] In some optional embodiments, testing a plurality of chips to be tested based on a test vector includes: splicing a modified value of a static configuration register, an initial value of a dynamic configuration register, and a modified value of the dynamic configuration register to generate a standard test interface language file; converting the standard test interface language file into a binary vector file; and testing the plurality of chips to be tested based on the binary vector file.

[0083] In the present embodiment, the standard test interface language file (STIL) is used to store the vector and timing configuration of ATE testing, and is an intermediate format for converting debug vectors and production vectors. The binary vector (Binl) file is used to represent a binary vector file that can be directly loaded by an ATE tester, which is converted from the STIL file and can be used for formal production testing.

[0084] The modified value of the static configuration register, the initial value of the dynamic configuration register, and the modified value of the dynamic configuration register can be spliced in sequence based on the sequence of the chip test process to generate an STIL file, which includes vector data and timing configuration. The STIL file is converted into a Binl file that can be directly loaded by an ATE tester by using a BinlGen special tool, so as to ensure that the vector can be recognized and executed by the tester. Testing a plurality of chips to be tested based on the Binl file can realize seamless connection from debugging to production without manual intervention.

[0085] In this way, in terms of cross-platform compatibility, the scheme can be adapted to almost all mainstream ATE test systems, such as Advantest V93000 or Teradyne J750, without the need to develop special codes for different test machines, and has high universality.

[0086] In some optional embodiments, the type of the register is determined based on a comparison result of the state value of the target register among the plurality of chips to be tested before the write operation is performed, or based on a comparison result of the state value of the target register among the plurality of chips to be tested after the write operation is performed, and the determining the type of the register comprises: if the initial value of the target register in the plurality of chips to be tested is different among the plurality of chips to be tested, determining that the target register is a dynamic configuration register; if the re-read value of the target register is different among the plurality of chips to be tested, determining that the target register is a dynamic configuration register; and determining that the register other than the dynamic configuration register in the chip to be tested is a static configuration register.

[0087] In the embodiment, the range of the static configuration register and the dynamic configuration register can be determined through multi-chip data flow comparison: first, batch collection of data flow. 10-12 chips of the same type can be selected to cover different production batches and different process angles to ensure that the sample is representative, and the test can be performed by using the foregoing debugging scheme to collect the complete read, write and re-read data flow of each chip.

[0088] Secondly, data flow comparison is performed. The data flow of a plurality of chips can be compared by using an automatic software tool, and the comparison rules are as follows: Firstly, if the read data, i.e. the initial value, of the register at the same address in the same step is different among a plurality of chips, for example, the read value of reg2 of chip 3 is different from those of other chips, it can be determined that the register is a dynamic configuration register; Secondly, if the initial value is consistent but the re-read value is different, for example, the re-read value of reg2 of chip 4 is different from those of other chips, it can be determined that the register is a dynamic configuration register; Thirdly, if the initial value of the target register is completely consistent among all chips, and the re-read value of the target register is completely consistent among all chips, it can be determined that the register is a static configuration register.

[0089] Thirdly, a classification result for distinguishing the types of registers is obtained. A register configuration classification table can be generated based on the classification result to clearly indicate the address, configuration type (static or dynamic) and classification basis of each register, for example, reg1 is a static configuration register because the read-re-read data of 12 chips are all 0xAAAA→0xAAFA, which can provide a clear basis for subsequent vector conversion.

[0090] In this way, data flow consistency verification of batch chips can be achieved; meanwhile, the multi-chip data flow comparison mechanism can greatly reduce the risk of configuration mismatch, avoid problem troubleshooting through export (dump) registers in the later stage, and further release debugging manpower.

[0091] In some optional embodiments, the foregoing method for chip testing further comprises: determining the number of chips to be tested based on the project scale and reliability requirements of chip testing.

[0092] In the present embodiment, the number of chips for data flow verification can be flexibly set according to the project scale and reliability requirements. Specifically, a second number of chips can be selected for a small-scale test project to balance verification efficiency and cost, and the second number can be determined as 5; a third number of chips can be selected for a project with high reliability requirements, such as a car chip, to improve the accuracy of data flow consistency determination, as long as the data flow consistency feature can be reflected through multi-chip data, the accurate classification of register configuration types can be realized, and the third number can be determined as 20. The second number is less than the first number, and the first number is less than the third number.

[0093] In this way, by optimizing resource allocation, over-testing and under-testing can be avoided.

[0094] In some optional embodiments, the foregoing standardized configuration file can be called in an ATE test graphical development interface, such as an SDS_New interface, to support parameter traversal, loop control, and conditional judgment, for example, file count control is realized through @FileCount>0, engineers do not need to manually write underlying test codes, and the development difficulty can be significantly reduced.

[0095] In some optional embodiments, the foregoing method for chip testing further comprises: automatically printing a full-process log of reading-writing-re-reading during the reading, writing, and re-reading operations, and after the engineer checks the log and confirms that there is no exception, the debugging data flow can be directly converted into a formal mass production vector, without the need for secondary development and debugging, to realize seamless connection between debugging and mass production.

[0096] The method for chip testing provided in the embodiments of the present application can be packaged as a common test public foundation module (CBB), which supports mainstream ATE test systems, such as Advantest V93000 or Teradyne J750, and can be adapted to any register configuration type test item, such as Double Data Rate (DDR) calibration test or Universal Serial Bus (USB) function test. Users do not need to understand the underlying code logic of the ATE, and can directly call the module to write mass production test cases, realize the landing application of the debugging scheme to mass production, and realize the large-scale reuse of the technical scheme.

[0097] In some optional embodiments, the data stream comparison granularity can be optimized as needed. For different accuracy requirement test scenarios, different data stream comparison granularities can be selected: for high accuracy requirement scenarios such as power calibration registers, bit-level comparison can be used to ensure data accuracy; for low accuracy requirement scenarios such as firmware loading registers, byte-level comparison can be used to improve verification efficiency, and both comparison methods do not affect the final classification result.

[0098] In some optional embodiments, the graphical tool for vector development, such as SDS_New, can be replaced by other graphical tools provided by the ATE test system, as long as the tool supports configuration file calling, vector fragment combination and basic logic control (such as loop, judgment), the same vector development function can be realized.

[0099] The method, device, equipment and storage medium for chip testing provided in the embodiments of the present application have been verified in a SerDes chip mass production project, and compared with the related art, can greatly reduce the test time and mass production cost; at the same time, the technical threshold of ATE test development is reduced, compared with the related art in which a 9-year experienced engineer needs to invest 7 months of time, an ATE engineer with 2 years of work experience can complete the debugging and mass production development of the SerDes chip within 1 month, which can significantly reduce the development difficulty and release human resources; in addition, in terms of scheme reusability, the packaged CBB module can be directly applied to various register configuration projects such as DDR calibration and USB function test, without the need for secondary development; in terms of process standardization, the present scheme unifies the whole process technical specification of debugging→data acquisition→vector conversion→mass production, supports large-scale popularization and application of the team, and the script automation rate is more than 90% (such as configuration file generation, STIL→Binl format conversion), which can further improve the development efficiency.

[0100] An apparatus for chip testing is also provided in the embodiments, which is configured to implement the above-described embodiments and preferred embodiments, and details of which have been described above. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0101] An apparatus for chip testing is provided in the embodiments, Figure 9 A structure diagram of the apparatus for chip testing provided by the embodiments of the present application is shown in FIG. 1, which includes: Figure 9 The debugging module 901 is configured to perform a write operation on the registers in the plurality of chips to be tested based on the configuration requirement of the chip testing.

[0102] The classification module 902 is configured to determine the type of the target register based on a comparison result of the state value of the target register among the plurality of chips to be tested before the write operation is performed, and / or based on a comparison result of the state value of the target register among the plurality of chips to be tested after the write operation is performed, wherein the type of the register includes a static configuration register and a dynamic configuration register.

[0103] The testing module 903 is configured to generate a test vector corresponding to the type of the register, and perform testing on the plurality of chips to be tested based on the test vector.

[0104] In some optional embodiments, the debugging module 901 includes: The debugging module first unit is configured to perform a read, write and re-read operation on the registers in the plurality of chips to be tested based on the configuration requirement of the chip testing, to obtain an initial value, a modified value and a re-read value, wherein the plurality of chips to be tested include a plurality of registers, and the plurality of chips to be tested are of the same type.

[0105] In some optional embodiments, the classification module 902 includes: The classification module first unit is configured to determine that the target register is a static configuration register if each initial value of the target register in the plurality of chips to be tested is the same and each re-read value of the target register is the same, and determine that the registers other than the static configuration register in the chips to be tested are dynamic configuration registers, or determine that the target register is a dynamic configuration register if each initial value of the target register is the same and the re-read value of the target register is different among the plurality of chips to be tested.

[0106] In some optional embodiments, the testing module 903 includes: ​The test module first unit is configured to splice the modified value of the static configuration register, the initial value of the dynamic configuration register and the modified value of the dynamic configuration register to generate a test vector based on a preset order of chip testing.

[0107] In some optional embodiments, the debugging module first unit comprises: The debugging module first unit first sub-unit is configured to read an initial value of a target register in the plurality of chips to be tested, determine a modified value of the target register based on a configuration requirement of chip testing, write the modified value into the target register, re-read the target register to obtain a re-read value of the target register, and perform the reading, writing and re-reading operations on a next register of the target register until the operations on all registers in the plurality of chips to be tested are completed.

[0108] In some optional embodiments, the test module 903 further comprises: The test module second unit is configured to splice the modified value of the static configuration register, the initial value of the dynamic configuration register and the modified value of the dynamic configuration register to generate a standard test interface language file, convert the standard test interface language file into a binary vector file, and test the plurality of chips to be tested based on the binary vector file.

[0109] In some optional embodiments, the debugging module first unit further comprises: The debugging module first unit second sub-unit is configured to determine that the target register is a dynamic configuration register if the initial value of the target register in the plurality of chips to be tested is different among the plurality of chips to be tested, determine that the target register is a dynamic configuration register if the re-read value of the target register is different among the plurality of chips to be tested, and determine that a register in the chip to be tested other than the dynamic configuration register is a static configuration register.

[0110] The apparatus for chip testing provided by the embodiments of the present application can perform the method for chip testing provided by any of the embodiments of the present application, and has the corresponding function modules and beneficial effects of performing the method. The further function description of each of the above modules and units is the same as that of the corresponding embodiments, which will not be repeated here.

[0111] Figure 10 A structural schematic diagram of an electronic device provided by the embodiments of the present application.

[0112] The following will be specifically described with reference to Figure 10which shows a structural schematic diagram suitable for use to implement an electronic device in embodiments of the present application. The electronic device can include a processor (e.g., a central processing unit, a graphics processing unit, etc.) 1001, which can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 1002 or programs loaded from a storage 1008 into a random access memory (RAM) 1003. In the RAM 1003, various programs and data required for operation of the electronic device are also stored. The processor 1001, the ROM 1002, and the RAM 1003 are connected to each other through a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0113] Generally, the following devices can be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage 1008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009 such as a debugger, an ATE tester, etc. The communication device 1009 can allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. Although Figure 10 The electronic device is shown with various devices, but it should be understood that all of the shown devices are not required, and more or less devices can alternatively be implemented.

[0114] In particular, the processes described above with reference to the flowcharts can be implemented as a computer software program according to embodiments of the present application. For example, embodiments of the present application include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network through the communication device 1009, or installed from the storage 1008, or installed from the ROM 1002. When the computer program is executed by the processor 1001, the above-described functions defined in the methods for chip testing of embodiments of the present application are performed.

[0115] Figure 10 The electronic device shown is merely an example and should not impose any limitation on the functions and scope of use of embodiments of the present application.

[0116] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded to a local storage medium through network, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method for chip testing shown in the above embodiments is implemented.

[0117] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, the operation of the computer can invoke or provide the method and / or technical solutions according to the present application. Those skilled in the art should understand that the form of computer program instructions in computer readable medium includes but is not limited to source file, executable file, installation package file, etc. Correspondingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0118] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A method for chip testing, characterized in that, The method includes: Based on the configuration requirements for chip testing, write operations are performed on the registers of multiple chips under test; Based on the comparison results of the target register's state value among the multiple chips under test before the write operation is executed, and / or based on the comparison results of the target register's state value among the multiple chips under test after the write operation is executed, the type of the target register is determined, and the type of the register includes static configuration registers and dynamic configuration registers; A test vector corresponding to the type of the register is generated, and the plurality of chips to be tested are tested based on the test vector.

2. The method according to claim 1, characterized in that, The configuration requirements based on chip testing include performing write operations on registers in multiple chips under test, including: Based on the configuration requirements for chip testing, the registers in the multiple chips under test are read, written, and reread, respectively, to obtain initial values, modified values, and reread values. The chips under test include multiple registers, and the multiple chips under test are of the same model.

3. The method according to claim 2, characterized in that, Based on the comparison results of the target register's state value among the multiple chips under test before the write operation is executed, and based on the comparison results of the target register's state value among the multiple chips under test after the write operation is executed, the type of the register is determined, including: If the initial values ​​of the target registers in the plurality of chips under test are all the same, and the repeated values ​​of the target registers are all the same, the target register is determined to be the static configuration register; The registers in the chip under test other than the static configuration register are determined to be the dynamic configuration registers; or, if all the initial values ​​of the target registers are the same, and the repeated values ​​of the target registers differ among the multiple chips under test, the target register is determined to be the dynamic configuration register.

4. The method according to claim 2, characterized in that, The generation of test vectors corresponding to the types of registers in the chip under test includes: Based on the preset order of chip testing, the modified value of the static configuration register, the initial value of the dynamic configuration register, and the modified value of the dynamic configuration register are concatenated to generate a test vector.

5. The method according to claim 2, characterized in that, Based on the configuration requirements for chip testing, the registers in the multiple chips under test are read, written, and reread, corresponding to initial values, modified values, and reread values, including: Read the initial values ​​of the target registers in the plurality of chips under test; Based on the configuration requirements of the chip test, determine the modified value of the target register and write the modified value into the target register; The target register is read again to obtain the repeated value of the target register; The read, write, and reread operations are performed on the next register of the target register until all register operations in the plurality of chips under test are completed.

6. The method according to claim 4, characterized in that, The testing of the plurality of chips under test based on the test vector includes: By concatenating the modified value of the static configuration register, the initial value of the dynamic configuration register, and the modified value of the dynamic configuration register, a standard test interface language file is generated. Convert the standard test interface language file into a binary vector file; The multiple chips to be tested are tested based on the binary vector file.

7. The method according to claim 2, characterized in that, Based on the comparison results of the target register's state value among the multiple chips under test before the write operation is executed, or based on the comparison results of the target register's state value among the multiple chips under test after the write operation is executed, the type of the register is determined, including: If the initial value of the target register differs among the multiple chips under test, the target register is determined to be the dynamic configuration register. If the repeated value of the target register differs among the multiple chips under test, the target register is determined to be the dynamic configuration register; The registers in the chip under test, excluding the dynamic configuration register, are determined to be static configuration registers.

8. An apparatus for chip testing, characterized in that, The device includes: The debugging module is used to perform write operations on registers in multiple chips under test based on the configuration requirements of chip testing. The classification module is used to determine the type of the target register based on the comparison results of the target register's state value among the multiple chips under test before the write operation is executed, and / or based on the comparison results of the target register's state value among the multiple chips under test after the write operation is executed. The type of the register includes static configuration registers and dynamic configuration registers. The testing module is used to generate test vectors corresponding to the type of the registers, and to test the plurality of chips to be tested based on the test vectors.

9. An electronic device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method for chip testing as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the method for chip testing as described in any one of claims 1 to 7.

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